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Patent 1045240 Summary

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Claims and Abstract availability

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(12) Patent: (11) CA 1045240
(21) Application Number: 245401
(54) English Title: HIGH DENSITY LOGIC PANEL BOARD FOR HIGH SPEED LOGIC CIRCUITRY
(54) French Title: TABLEAU DE DISTRIBUTION LOGIQUE A HAUTE DENSITE POUR CIRCUITS LOGIQUES A GRANDE VITESSE
Status: Expired
Bibliographic Data
(52) Canadian Patent Classification (CPC):
  • 347/35
(51) International Patent Classification (IPC):
  • H05K 7/08 (2006.01)
  • H05K 1/11 (2006.01)
  • H05K 1/16 (2006.01)
  • H05K 3/22 (2006.01)
  • H05K 1/00 (2006.01)
  • H01R 12/16 (2006.01)
(72) Inventors :
  • DOUCET, LEONARD A. (Not Available)
(73) Owners :
  • AUGAT INC. (United States of America)
(71) Applicants :
(74) Agent:
(74) Associate agent:
(45) Issued: 1978-12-26
(22) Filed Date:
Availability of licence: N/A
(25) Language of filing: English

Patent Cooperation Treaty (PCT): No

(30) Application Priority Data: None

Abstracts

English Abstract






A B S T R A C T

An improved logic panel board having three conductive
layers, the external layers both being ground planes while the
voltage plane is located between the ground planes. Socket
contacts with wire wrapping pins are mounted in the panel board
in dual-in-line arrays, one of the contacts in each array being
electrically connected to both ground planes and another contact
in each array being electrically connected to the voltage plane.


Claims

Note: Claims are shown in the official language in which they were submitted.




CLAIMS

What is claimed is:

1. A panel board comprising:
a first dielectric laminate;
a second dielectric laminate in face-to-face confronting
relationship with said first dielectric laminate;
a first conductive plane located between said first and
second dielectric laminates;
a second conductive plane on the outside of said second
dielectric laminate;
a third conductive plane on the outside of said first
dielectric laminate;
said panel board being formed with a plurality of dual-in-
line arrays of holes therethrough, said arrays being arranged in
regular adjacent parallel and end-to-end relationship over the
surface of said panel board;
a socket contact mounted in each of said holes in said
dual-in-line arrays of holes, said socket contact having a
socket projecting into said panel board from one side of said
panel board and a contact pin extending from the opposite side
of said panel board; and
means for electrically connecting said second conductive
plane and said third conductive plane together.

- 9 -



2. The panel board recited in claim 1 wherein said means for
connecting said second and third conductive planes together com-
prises one of said socket contacts in each array projecting
through said board and being electrically connected to each of
said second and third conductive planes.


3. The panel board recited in claim 2 wherein another of said
socket contacts in each array is electrically isolated from said
second and third conductive planes and is electrically connected
to said first conductive plane.


4. The panel board recited in claim 1 and further comprising a
dual-in-line package having two parallel rows of leads extending
beyond one surface thereof, said leads being inserted into the
sockets of said socket contacts in one array on said panel board.


5. The panel board recited in claim 3 wherein said second
dielectric laminate has a hole therethrough to provide access for
soldering said another of said socket contacts to said first
conductive plane.

- 10 -



6. A panel board comprising:
a first dielectric laminate;
a second dielectric laminate in face-to-face confronting
relationship with said first dielectric laminate;
a first conductive plane located between said first and
second dielectric laminates, said first conductive plane being
in surface contact with said first and second dielectric lamin-
ates;
a second conductive plane on the outside of said second
dielectric laminate;
a third conductive plane on the outside of said first
dielectric laminate;
said panel board being formed with a plurality of dual-
in-line arrays of holes therethrough, said arrays being arranged
in regular adjacent parallel and end-to-end relationship over
the surface of said panel board;
a socket contact mounted in each of said holes in said
dual-in-line arrays of holes, said socket contact having a
socket projecting into said panel board from one side thereof
and a contact pin extending from the opposite side of said panel
board, one of said socket contacts in each array being electri-
cally connected to each of said second and third conductive
planes and another of said socket contacts in each array being
electrically isolated from said second and third conductive
planes and electrically connected to said first conductive plane.
- 11 -

Description

Note: Descriptions are shown in the official language in which they were submitted.



1~)45Z40
IELD OF THE INVENTION

1 This invention relates in general to electronic circuit
2 interconnecting means and more particularly concerns a panel
3 board having three voltage planes wlth a multiplicity of soc~et
4 ~ contacts extending therethrough for use in high speed switching ,
ll logic circuitry.
,


DISCUSSIOIl OF THE PRIOR ART
!l
6 ~' Panel boards having two voltage planes are in common use '
7 li for electronic interconnection. In many instances the use of
8 ll two-layer panel boards with printed circuitry for making the ', -~ -
9 ¦ necessary interconnections for high speed switching circuitry
1I has not been totally satisfactory due to a relatively high level ~
~ of high-frequency noise which often accompanies such logic -:`
12 ~I circuitry so constructed. Multi-layer panel boards with three
13 1l different voltage planes have also been used in high speed logic
14 ,~' and switching circuitry where three different voltage levels are ,
~i required.


SUMMARY OF THE INVENTION j .

16 j This invention provides an improved logic panel board
17 having three conductive layers but with the electronic equiva-
18 ~ lence of two voltage planes. The middle plane has a specified
19 voltage level while the two outer planes are both at ground

i



1045Z40
1 potential and are interconnected by a plurality of socket pins,
2 one în each of a plurality of dual-in-line (DIL) arrays of
3 socket pins. The conductive surfaces oE this panel board are
~ appropriately etched around the dual-in-line ar~rays of holes and
` there is inserted in each of the holes a socket contact having
6 ~ a wire wrapping extension protruding from the side of the board
7 ; opposite the socket. This panel configuration effectively -
8 increases the distributed capacitance between the voltage and
9 ~I ground planes by a factor of up to four over standard two-layer
l,l panel boards. High frequency noise on the voltage busing system ,
11 i' of this panel board is significantly reduced because of this in- ~
12 1' creased capacitance. By effectively doubling the conductive area t
13 1l of the ground bus between any two circuits, the series impedance ~ -
14 ¦1 of the ground network is greatly reduced, thereby increasing the
jl effectiveness of the ground plane and consequently the transmis-
16 1¦ sion characteristics of the panel. Through the means of directly
17 !I connecting socket contacts to the proper conductive planes, a t
1~ ¦ significantly lower impedance is realized, while at the same time¦19 ¦~ the need for wrapping these connections is eliminated.
¦! This panel board is often termed a Schottky panel.
21 1I Schottky logic is the fastest presently known form of saturating j
22 ~~ logic and is transistor-transistor couPled. It is also called
23 ii Schottky TTL logic. The panel of this invention helps to elim-
24 ¦1 inate noise that is associated with poor ground circuits which
i~ can occur in panels of the prior art when used for such high
26 Il speed logic, while providing good performance with wire wrapped
27 ~l interconnections.


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- 1045Z40

- 1 Provision for capacitive decoupling at each DIL array is
2 included in the panel, as are areas for electrolytic decoupling
3 capacitors at each power entry location.


', BRIEF DESCRIPTION OF THE DRAWING

4 i The advantages, features and objects of this invention
i I
5 li will be more clearly understood from the following detailed
6 1, description when taken in conjunction with the drawing in which: j
7 l¦ Fig. 1 is a perspective view of a portion of a panel ~ -~
8 ¦! board constructed in accordance with the present invention; and
9 il Fig. 2 is a greatly enlarged partial sectional view taken¦
¦¦ through cutting plane 2-2 of Fig. 1 showing a DIP mounted in the i
ll $1 socket contacts.
1~ . .

I DESCRIPTION OF THE PREFERRED EMBODIMENT

12 ~¦ With reference now to the drawing there is shown a panel
13 ¦I board 11 having dual-in-line arrays 12 of socket contacts 13,
14 ¦¦ each having wire wrapping pin extensions 14 projecting from the
15 ¦i opposite side of board 11. The board may comprise any number I -
16 ¦l of such arrays, normally being in groups of thirty in a five-by-
17 1l six matrix. Dual-in-line packages (DIP's) 15 may be mounted in
18 'I any one or more of arrays 12 and a panel board such as shown in
19 I the drawing will often have several dozen such DIP's which are
I normally integrated circuits used in some type of switching
21 logic circuitry.

" ~ .
I 1 .

- 4 -


~)4SZ40
1 Panel 11 is comprised of dielectric laminates 16 and 17
2 separated by a conductive layer 21 which is the voltage
3 plane Vcc. On the outside of laminate 16 is conductive layer 22 '
4 which is a ground plane and on the outside of laminate 17 is a
' conductive layer 23 which is also a ground plane. Inserted
6 ,, through panel board 11 are a multiplicity of socket contacts 13
7 ~ having a socket portion projecting into the panel board and wire
8 ~ wrapping pin extension 14 projecting from the opposite side of
9 , the board. The pins 14 are ty~ically interconnected by means of ,
,~i wire wrapping techniques as indicated by reference numeral 25 and
11 , may have a length sufficient for either two or three levels of
12 ~I wrap.
13 ,l The contact pins of a typical array 12 are numbered for
14 ,' electronic interconnect purposes such that contact 26 is
~I number 8 of the array while contact 27 is number 16 of the array,
16 1ll assuming a 16-pin configuration for the DIP. A dual-in-line
17 ¦l integrated circuit package having electrical leads 31 inserted
18 ~l into the socket contacts is sho~n by waY of example in Fig. 2. ~ .;19 ~ Contact 26 is connected to voltage planes 22 and 23 by solder
1~ connections 32 and 33 respectively and is isolated from internal
21 l, voltage plane 21 as shown in the drawing. Socket contact 27
22 1i does not make electrical contact with voltage ground planes 22
23 ,l and 23 but is electrically connected to voltage plane 21 through
24 `~ opening 34 in laminate 17 and is securely connected by solder 35.
!, This panel board functions as a two-layer board with a
26 ground plane and a voltage plane but has significant advantages
27 because of the doubling in size of the ground plane. The

~.



_ 5 _
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~()45Z40
1 impedance in the ground network is greatly reduced because the
2 cross section of the ground bus between any two circuits is
3 effectively doubled, thereby increasing the effec~iveness of the
4 ground plane. Not only is the electrical effectiveness of the
ground plane increased, but because the voltage plane is sand-
6 wiched between two ground planes the distributed capacitance
7 ~ between the voltage and ground planes is significantly increased,
8 by up to 400% over a conventional panel having two voltage planes.
9 ~~ This increase in distributed cap~citance reduces the high
, frequency noise on the voltage busing system of the panel board.
11 l Because transistor-transistor logic (TTL) and especially
12 ii Schottky TTL is a very fast saturating logic, this reduction of
13 '~ noise is a significant improvement where the switching signals
14 i1~ have small magnitude changes, in the vicinity of 5 volts, com-
~j pared with possible noise spikes which may have equivalent mag-
16 ~I nitudes By reducing the magnitude of the noise, the purity of
17 ~j the intelligence signal is improved, improving the performance
18 il of the entire system.
19 !~ Referring again to Fig. 1, there are shown at the end of
li each dual-in-line array 12 a pair of holes 36 and 37. A lead
21 1! inserted through hole 36 is electrically isolated from ground
22 ~ planes 22 and 23 because conductive plane 22 is etched away from
23 ~, the hole and a hole through conductive plane 23 and dielectric ~,
24 i! laminate 17 (not shown) removes both ground planes from the
!I vicinity of any such lead in the manner of hole 34 shown in
26 Fig. 2. The same lead is electrically connected to voltage
27 `I plane 21, access to the voltage plane being through the hole ,,

,:

,
-- 6 --


, .

.
.
. ~:


1045Z40
1 , just mentioned in dielectric laminate 17 and conductive plane 23.
2 ; A lead inserted ~hrough hole 37 is electrically connected by
3 means of solder to ground planes 22 and 23, there~y providing
4 ~ still another means of connecting these two layer~s together. The
!I pair of holes 36 and 37 may be used for connecting decoupling
6 1, capacitors which may be associated with each DIP as desired.
7 ,` This is another means of reducing noise where such reduction is
8 ¦I found to be necessary.
9 ¦i Another means of improving the transmission characteris- ,
l,~ tics of the panel board is by reducing the width of the etched
~ areas 41 from a conventional 0.160 inch wide to between approxi- i~
12 ~ mately 0.125 and 0.140 inch wide. This thereby further increasesl
13 ~ the total area of conductive material, normally copper, and adds I
14 ¦ to the increased overall effectiveness of the ground and voltage
! planes-
16 ~ By way of example, panel board 11 may be a 1/ 8 inch
17 ~ thick glass epoxy with three layers of 2 ounce copper circuitry
18 1 as shown in the drawing, the copper circuitry being tin plated.
19 l The relative thickness of the conductive planes is shown exag- !
gerated in the drawing for purposes of clarity. The terminal ~ .
21 j portion of socket contact 13 is preferably brass with gold over
22 nickel plated and the inside socket contact material is
23 1I beryllium copper, also gold over nickel plated. The space , -
24 1'l between the rows in which pins 26 and 27 reside is 0.300 inch.
1I The spacing between parallel adjacent DIP's or dual-in-line
26 ll arrays is 0.200 inch while the spacing between each socket con-
27 i, tact in a row is 0.100 inch. End-to-end spacing between DIP's




~, '.
.. ~, , . , , . .. ~ ,

!


104S240
1 is 0.300 inch. Note that spacings are multiples of 0.100 inch
2 which is the conventional modular spacing for DIP panel boards.
3 ,~ In vi~w of the above descri~tion, it is likely that
4 modifications and improvements will occur to those skilled i
the art which are within the scope of this invention.
,i i
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!i - 8 - '.

1~ ',

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Representative Drawing

Sorry, the representative drawing for patent document number 1045240 was not found.

Administrative Status

For a clearer understanding of the status of the application/patent presented on this page, the site Disclaimer , as well as the definitions for Patent , Administrative Status , Maintenance Fee  and Payment History  should be consulted.

Administrative Status

Title Date
Forecasted Issue Date 1978-12-26
(45) Issued 1978-12-26
Expired 1995-12-26

Abandonment History

There is no abandonment history.

Owners on Record

Note: Records showing the ownership history in alphabetical order.

Current Owners on Record
AUGAT INC.
Past Owners on Record
None
Past Owners that do not appear in the "Owners on Record" listing will appear in other documentation within the application.
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Document
Description 
Date
(yyyy-mm-dd) 
Number of pages   Size of Image (KB) 
Drawings 1994-05-28 1 36
Claims 1994-05-28 3 106
Abstract 1994-05-28 1 20
Cover Page 1994-05-28 1 15
Description 1994-05-28 7 289