Note: Descriptions are shown in the official language in which they were submitted.
-
iO~5;~48
; 1 BACKGROUND
; For many years, persons and firms in the data
processing field have sought a method and apparatus to reduce
the time necessary to transmit data between two given points.
The present invention provides such a method and such apparatus.
SUMMARY
A data compaction system and apparatus is disclosed
,;
` which, in the preferred embodiment, includes a high speed
controller utilizing both read-only storage and read-write
t
storage. A compaction device according to the present
invention could then be placed upon both ends of a transmission
line, the data received by a compaction unit at one end of the
line from whatever apparatus wished to transmit data on the
line, the data compacted within the compaction unit according
to the present invention, the data transmitted on the
line to a compaction unit on the other end of the line, the
data decompacted, and the data provided to whatever apparatus
wished to receive the data. Data received by the compaction
¦ device according to the present invention in a fixed length,
fixed number base, coded manner would then be compacted by
altering the expression of the data, as by altering the number
bases in which the data is expre~sed and by switching between
number bases. Thus, it has been found that expressing the data
- :
as a string of characters of varying lengths and varying number
25 bases, that is chara~ters not all expressed in the same number `~ ~
base, shortens the overall length of the data transmitted. ~ -
~ This is true even if the length of certain characters may be
i increased by the techniques according to the present invention.
.,~
- 2 -
'
, .. . . . .
. . . -
,, ., . , . , ~ ~,
iO4S~48
Also, the present invention continuously stores
the present character in the prior record mask and in the
prior character mask. It has then been found that a
comparison of the record to be compacted with both the
prior character mask and the prior record mask allows a
significantly shortened, coded representation which further
and significantly enhances the compaction ability of the
present invention.
It is thus an aim of the present invention
to provide novel, efficient, and heretofore considered
unavailab~e apparatus and methods for compacting data.
,, .
Accordingly, the invention provides, in its
; most general aspect, data compression apparatus for use
on a path of communication of groups of symbols where-
~symbols represent characters each having a fixed bit
length. The data compression apparatus includes: members
for storing characters; members for providing sequential,
real time, adaptive, open ended compaction of the symbols/
characters; members for providing an electrical connection
~ 20 between the members for storing and the compaction members;
;~ and members for providing an electrical connection between ~; -
the compaction members and communication path.
The present invention provides, in more specific
aspect, data compaction apparatus including compaction
2 apparatus inserted into the communication path at the
, transmission end and decompaction apparatus inserted into
the communication path at the reception end for compaciing
data to be transmitted and decompacting data to be received.
The compaction apparatus comprises: members for
~ - 3 -
, . ~ .
. ..
s ' - .
: . ~
~45248
1 accepting an input from the communication path; members for
controlling the compaction apparatus and causing
the compaction apparatus to perform a data dependent
- sequence of operations; members for storing, associated
j 5 with the compaction apparatus and including a portion
for storing selected data from the communication path ~ ~:
and a portion for storing preset coding including coding ~ :
.' 3
::~ for at least selected of the symbols from the communica-
.i, :
~ tion path; members for selectively causing the storage ~
.~ ,
~ 10 Of symbols from the communication path and for pro-
.~ .
1 viding sequential, real time, adaptive coding of symbols
., ; .
from the communication path by comparing the sym-
j~ bols received by the compaction device in a sequential ~ ~.
.. and serial fashion with prior symbols received and : ~:
stored in the members for storing and for causing a type of
compacted symbol to be transmitted if a symbol within
the coding members of the compaction apparatus con-
forms to a symbol of a prior symbol received and stored
in the members for storing, and for causing another type ~ :
20 f compacted symbol to be transmitted if the symbol
within the coding members of the compaction apparatus
~J iS not appropriately conforming to prior symbols received ~g
and stored in the members for storing but conforms to the
.~ preset coding within the members for storing, and for
''`'3~ 25 causing yet another type of compacted symbol to be :
: ~ .
;~3 transmitted if the symbol within the coding members of
~:
the compaction apparatus is not appropriately con-
, ..
.'i forming to prior symbols received and stored in the ~:
. members for storing and not appropriately conforming to
30 preset coding within the members for storing; and members for
.. ,~ ~ . .
providing the sequences of symbols from the coding
- 3a -
r~
lO~SZ48
1 members to the communication path in a sequential fashion
conforming to the sequence received. The
decompaction apparatus comprises: members for accept-
ing an input from the communication path; members for
` 5 controlling the decompaction apparatus and causing
the decompaction apparatus to perform compacted
data dependent sequence of operations; members for
storing, associated with the decompaction apparatus
and including a portion for storing selected data from
"t 10 the communication path and a portion for storing pre-
` set decoding including decoding for at least selected of
the symbols from the communication path conforming
~; to the selected symbols stored in the members for storing
associated with the compaction apparatus; members for ~ -
. 15 providing sequential, real time, adaptive decoding of ; -
symbols from the communication path by recognizing
the first mentioned type of compacted symbols, the
.'~ . .
another type of compacted symbols, and the yet an-
~ other type of compacted symbols, and for providing
- 20 appropriate decoded symbols from the members for stor-
ing conforming to the particular symbols received; and
members for providing the decoded sequences of symbols
from the decoding members to the communication path in
a sequential fashion conforming to the sequence re-
~' 25 ceived. Further provided are: members for providing electrical .
connection between the members for storing associated with the .
compaction apparatus and the members for controlling asso-
ciated with the compaction apparatus; members for pro-
viding electrical connection between the members for ~ -
30 storing associated with the compaction apparatus and
the coding members; members for providing electrical
connection between the members for storing associated with
.v. ~ - 3b -
.
:.... -
- - . . . .
~O~SZ~8
1 the decompaction apparatus and the mem~ers for control-
ling associated with the decompaction apparatus;
., .
members for providing electrical connection between the
members for storing associated with the decompaction
apparatus and the decoding members; members for provid- :
ing electrical connection between the members for con-
trolling associated with the compaction apparatus and
the coding members; and members for providing electrical con- ;
~ nection between the members for controlling associated
10 with the decompaction apparatus and the decoding
, members. ~ .
', In another aspect of the present invention, the ~ .
``~ coding members of the compaction apparatus
comprises members for comparing the symbols received
15 by the compaction device in a sequential and serial
fashion with prior symbols received and prior groups of
symbols received and stored in the members for storing '
: . .
:~ associated with the compaction apparatus and for caus-
ing a first type of first mentioned sequence of com-
pacted symbols to be transmitted if the symbol within
.,, ~ .
the coding members of the compaction apparatus con-
~ forms to a symbol of a prior group received and stored
J. in the members for storing associated with the compaction -
i, apparatus and for causing a second type of first men-
25 tioned sequence of compacted symbols to be transmit- ~ :
ted if the symbol within the coding members of the com-
~ paction apparatus conforms to a symbol of a current
`'. group received and stored in the members for storing
`~ associated with the compaction apparatus.
.,; .
..
,
"" . . : ,- : .
.. : . - : .
. ;. ::, . :
; . . : . . :
11)45Z48
In another aspect, the present invention provides a
method for data compaction for use in conjunction with a path of
transmission of groups of symbols/characters. The method com-
prises the steps of: intercepting data in the form of symbols/
characters upon the transmission path; comparing the intercepted
data with prior symbols received and stored; if a comparison is
` reached, encoding the intercepted data to reflect such a compari-
son; if no comparison is reached, encoding the intercepted data
`' in a present manner (whereby sequential, real time, adaptive,
open-ended compaction of the symbols/characters is effected); and
transmitting the results of the foregoing steps.
In another aspect of the present invention, the encoding ~ -
step if no comparison is reached comprises: encoding the inter-
~;~ cepted data by substituting a preset coding for selected of the
data for which a coding has been preset; and adding a transmission
, code to the intercepted data without further compaction for re-
maining of the intercepted data.
In another aspect of the present invention, the step of
comparing the intercepted data with prior symbols received and
stored comprises comparing the symbols of the data of the group
currently intercepted against symbols of the data of the group
previously intercepted and stored by first comparing the symbols
of the currently intercepted data with the symbols stored within
specific storage space allocated to storage of previously inter-
cepted symbols and (1) if no comparison is reached, storing the
symbols of the data of the group currently intercepted, and com- ~;
pared in the previous method step, within the specific storage
space allocated to storage of previously intercepted symbols and
(2) if a comparison is reached between the symbols of the data of
the group currently intercepted and symbols of the data of the
group previously intercepted and stored within the storage space
allocated to the storage of previously
- 3d -
.,. ', ' ' .
10~5Z48
1 intercepted symbols, skipping the previous step of stor-
ing the symbols of the data of the group currently inter-
cepted and compared, as the symbols of the data of the
group currently intercepted and the symbols of the data
of the group previously intercepted and stored are
identical and it is not necessary to restore identical
symbols. `~
In another aspect of the present invention, the step of
comparing the symbols of the data of the group cur-
10 rently intercepted against symbols of the data of thegroup previously intercepted and stored further com-
prises comparing the currently intercepted symbol with
the correspondingly situated symbol of the data of the
group of previously intercepted symbols received and
15 stored. Additionally, the encoding step if a comparison is
reached further comprises setting up a data indepen-
dent coding indicating only that the symbol currently
intercepted is identical to the correspondingly situated
symbol in the previously intercepted group of symbols -
20 received and stored. Furthermore, the step of comparing
the symbols of the data of the group currently inter-
cepted against the symbols of the data of the group
previously intercepted and stored further comprises
comparing the currently intercepted symbol with the
~ 25 immediately previously intercepted symbol received.
,~ Further, the encoding step if a comparison is reached
comprises setting up a data independent coding indi-
cating only that the symbol currently intercepted is
identical to the immediately previously intercepted
` 30 symbol.
- 3e -
.~- .
.: , . . : :
: : , '
.. ~ , .
109~5Z48 ~
. 1 In another aspect of the present invention, the encoding
. .
, step if a comparison is reached comprises encoding in
a data independent manner not reflective of data but
only reflective of the reaching of a comparison.
These and further aims and advantages of the
present invention will become clearer in light of the ~ -
following detailed description of an illustrative embodiment
of this invention described in connection with the drewings.
,
:`' ~.:
.,~ , ~ .
'
`'~ ` ' , :
'.
.~ . ;
.~ ~
;~ - 3f ~
,
.
` lO~SZ48
- DESCRIPTION OF THE DRAWINGS
Figure 1 shows a functional block diagram of an
exemplary system incorporating the present invention at
~ the terminal and computer ends of a transmission line. ,
-~ Figure 2 shows a block diagram of a system according
'~ to the present invention.
Figures 3 to 6 show block diagrams further explaining -~
the block diagram of Figure 2.
Figure 7 is a functional block diagram of a preferred
~` 10 system and apparatus according to the present invention.
Figure 8 shows a block diagram similar to Figure 2
. 1
of an alternate embodiment according to the present invention.
Figures 9 to 14 show block diagrams further explaining ~`the block diagrams of Figures 2 and 8.
Figures 15 to 26 show schematic representations of
preferred apparatus according to the present invention,
~ organized by the functional block diagrams shown in Figures
i 7 and 9 to 14, with Figures 15 and 16 referring to Figures 2,
7, 8, and 9, Figure 17 referring to Figures 2, 7, 8, and 10,
,~ 20 Figures 18 and 19 referring to Figures 2, 7, 8, and 11,
Figures 20, 21, and 22 referring to Figures 2, 7, 8, and 12,
~, Figures 23 and 24 referring to Figures 2, 7, 8, and 13, and
Figures 25 and 26 referring to Figures 2, 7, 8, and 14. -~
All of the figures are drawn for ease of explanation ~-
of the basic teachings of the present invention only; the ~ -
extension of the figures with respect to a particular application
of the present invention will be within the skill of a practitioner
of the art after the teachings of the present invention have been
~ read, followed, and understood.
i 30
., ~. .
.~, . . . , :.... , . . :
~5i~8
- DESCRIPTION
Turning now to Figure l, and for the moment
eliminating those portions of the block diagram designated
C and G, the present state of the art is disclosed. That
is, for example, a remote batch terminal transmission
system is disclosed in which the input is fed into the
reader at terminal A through means such as punched cards.
The data passes from terminal A in an eight bit parallel
mode into a line controller B where the data is translated
into a bit serial mode and applied in some instances to a
modem D which is commonly a modulator/demodulator. The modem
' conventionally translates the bit serial information into analog
signals such as audio tones. These tones are conventionally
applied to a voice grade telephone line E but it may also be
possible to eliminate the modem and use a digital transmission
line and transmit the data signals directly. Where a voice
` grade telephone line is used, the speed of data transfer is
! limited by the bandwidth of the line and the effectiveness
of the modem in utilizing the particular bandwidth. For
the purposes of description of o~eration of the presentinvention
the Bell system 201A modem and the Bell system dial up telephone
' line will be used, as these are the most widely used components.
At the far end of the line E there is another
interface to a second modem F where the analog signals are
conventionally translated to bit serial data and which is
connected to the line controller H which converts that
data into an eight bit parallel mode for storage in the
memory of computer I. After processing by the computer I,
the output data can then be transmitted to terminal A
where it may be printed or punched into cards for the
information retrieval.
-- 5 --
~ ~' ' ' ,,. '''
.
lO~SZ48 :
For the exemplary system described, the eight bits
of the character are gated to a line eontroller B in
parallel form, that is, all eight bits simultaneously. Line
controller B holds the character and releases one bit at
a time to the modem D, which in turn generates tone modulated
signals for the communication line. Depending upon the modem,
it may use frequency shifting, phase shifting, or amplitude
shifting to represent the different combinations of the bits.
The Bell 201A model, for example, uses dibit (two bits) phase
encoding and utilizes four phase shifts to represent the
four possible bit combinations. Each combination is held
for two cycles and in this way each bit is converted to one
cycle of bandwidth and each character to eight cycles of band- -
., .
width. Thus the usable bandwidth of a dial up line is
normally 2000 cycles per second, from 750Hz to 2750Hz. This
bandwidth provides a maximum transmission speed of 250 characters
per second for this combination. Inasmuch as all eharacters
are the same length and the transmission media delivers a
constant speed in bits per second, it is apparent that the
amount of data which may be transmitted in a given time is
strictly limited, and thus the speed at which a terminal
; device may operate is also so limited.
~3 In the exemplary system just described, while -;
no specific compaction device is used, eertain limited
eompaetion may be eonventionally performed by the eentral
.
-- 6 --
10~5Z48
.
computer at one end and by the terminal ~, which may be
a small computer, at the other end of the transmission line.
A first method previously utilized is the deletion of
trailing blanks from each record of data by inserting a
special character which signifies that no significant
; data exists beyond that point. This special coding is
commonly known as end compression. Another method utilized
for compression is the detection of strings of identical
data, usually blanks, which is found in the record or text.
Conventionally, this string is deleted and one to three
special characters are inserted, depending upon the
character which is deleted, the number deleted, and the
system being used.
The particular compaction methods described above,
however, and others currently in use have a number
of characteristics in common. Generally, all characters
are of fixed length, and this length may be 6, 7, 8, 10,
or other binary bit lengths, but the character length is
consistent for a given system. That is, all characters
20 are given in the same number base and require the same
number of bits for expression of that character. For
; example, all characters are generally eight bits long and
are expressed in the number base 256, thus allowing
a maximum of 256 characters to be expre ed.
;':
- 7 -
-.:
.,
.,, . ~ ':
.. . .
~04S248
Now considering the complete exemplary Figure 1,
;~ including the present invention, a compaction device C
,
would be inserted between line controller B and modem D,
and another compaction device G would be inserted between
modem F and line controller H. Compaction device C,
in relation to the exemplary system described, receives
the bit serial data and performs compaction of the record
received before passing the data of the record to modem D.
It should also be recognized that if digital lines are
used, compaction device C may be used without a modem.
As will be set out in more detail hereinafter,
specifically with respect to Figure 7, the compaction device
according to the present invention is made up of a small, high
speed compaction controller or coder/decoder utilizing both a
read-only storage and a read-write storage. Also, logic devices
for the system of the present invention, a preferred embodiment
of which is shown in Figures 2 through 6, are preferred to be in
the form of a diode matrix. The diode matrix is usually cast as
an integrated circuit chip and, in either case, the diode
matrix with its associated logic becomes the read-only
storage referred to previously. Thus the read-only storage
has the qualities of being nonchangeable and maintains its
state indefinitely. As such, it is ideally suited for use at
remote locations where service is not readily available. Since
the read-only storage is nonchangeable, it cannot be used to store
.~ .
~, '
`3, ::
~ 30
:1 .
-- 8 --
,
~ .
:~,,. . , ~ . .
~SZ~8
1 data and ther~fore.a read-write or buffer memory is also used
,, in the preferred embodiment. This read-write memory may be in ~'
the form of a magnetic core memory, where it is used for , ',
temporary retention of data and tables, or other conventional
5 types. A basic type diode matrix is shown and described on
pages 323 through 336 of a text entitled DIGITAL CC~PUTER
PRINCIPLES, publish~d by the McGraw-Hill Book Company, Inc. in
1962. The same text also describes a buffer memory in the
' form of â magnetic core memory on pages 397-410.
~ 10 In operation, the compaction device of the
-~ exemplary system continually receives and executes a
'~ microcode from the read-only storage mechanism and this
''i microcode in turn produces the control necessary to
~ operate the compaction device. In its preferred state of
1~ ' ' . - ::
5~sp,erat,i,on,,,,,t,h"e ,compaçtion device is running at an idle
-~ condition and accepts a signal from a modem to indicate
^~ that communications have been established. The compaction device
C then begins to read the input material from the terminal A.
As each amount, block, or byte of data is read in, the compaction
~; 20 device stores the data in the buffer memory and the ~ ~
compaction device performs the logical operations as ~ ,
encoded in the diode matrix forming the read-only storage.
~, This reduces the amount of data transmitted substantially.
' As each byte or group of bytes is compacted, it is then
25 transmitted across the communications line E. At the other end
;, of the line, the compaction device goes through the reverse
, procedure to expand the data to its original content.
. ~
. . .
~ _ g _
:,~
~,, : .
,;
.~ -
~Q4~2~
1 It shoulq also be recoynized that while the compaction
device is reading noncompacted data, it is simultaneously
compacting the prior data and also transmitting the data
prior to that.
S Because of the complexity of the present invention and its
significant departure from the art, the remaining d~scription
3 of the preferred embodiments of the present invention will
interweave a block diagram procedural, systematic description,
such as that exemplified by Figures 2-6 and 8, a block diagram,
10 functional, systematic description, such as that exemplified by
` Figures 7 and 9-14, and a particular example of how the present~
would operate on a particular block of data. Following this,
~ a particular hardware embodiment will be described, with
;~ a further preferred element.
Thùs to illustrate the operation of the compactor
of the present invention, the operation will be followed
through a short, exemplary block of data consisting of four ;~
records which are to be considered printed lines at a
terminal printer. The block of data used shows only the
20 actual data and not the control characters, as these -
;~ control characters will vary depending on the specific
terminal equipment being used. At each step of the
illustration, not only the effect of the present invention
on this specific example of data will be shown, but also
~j ~
, 10
, i :
.. .
: - ,
.~ , .
,,
r - ~
~ 1045;~48 :- ~
1 the general case in which that the data belongs will be
described. Also, in addition to illustrating both the
. ~
specific example and the general case, the illustration
1 will be used to show the operation of the preferred
5 hardware embodiment of the compactor of the present
invention.
:, ..
The example, a short block consisting of four
records, is set out in its entirety below:
. ~
~; LINE 01 = (B )
LINE 02 = (DDDDDDDDD)
.,, . ~.
LINE 03 -- (SrYYDDDTTD)
1 LINE 04 = (; :#?)
`~ All characters set out above are part of the data block.
1 Although this example data block is short, it serves to
`~15 illustrate the use of every-level of compaction of the-- -
Ipresent invention, as will become clearer hereinafter. ;~
.. .. .
First, describing Figure 7 which is a functional ;~
block diagram of a preferred system and apparatus according -
qto the present invention, input/output devices are shown and
~ii20 generally designated 50 and 52. Input/output devices 50 and 52
;~provide access to and from the compactor of the present
;qinvention, generally designated 54.
~'Input/output device 50 then includes a controller
side converter 56 including input data connection 58, as
25 from line controller B, and output data connection 60 to
`3
..
.,
,. ~
., .
!, ~
, . . ,, .. .. , ~
~045Z48
1 an eight bit input shift register 62. Register 62, in turn
includes output data connection 64 to a controller side
FIFO register 66, which in turn includes an output data
connection 68 to a further eight bit shift register 70 having
, . ~
`~ 5 a data output connection 72 to converter 56. Converter 56
then also includes an output data connection 74, as to line
controller B of Figure 1. All of the above are more ful;y
described with reference to Figures 9 and following, hereinafter.
~ ,,.
Input/output device 50 further includes a clock 76
10 connected by logic connection 78 to register 62, connected by
lc)gic connection 80 to register 70, and connected by
. logic connection 82 to converter 56. Further, a logic connection
-, 84 extends from converter 56 with clock pulses. All of the
above æe more fully described with reference to Figures 9 and
15 following, hereinafter. _ __
Further, a principal data connection 86 extends
~' from data connection 64, between register 62 to FIFO 66,
, and from data connection 68, between FIFO 66 and
register 70, and provides a data stream to compactor 54,
20 and specifically to compaction device, coder/decoder 88 therein.
Still further, principal data connection 86 provides a
` data connection between coder 88 and memory, generally
designated 90. Thus, data connection 86 interconnects
, with instruction memory 92, data memory 94, and input/output
- 25 memory 96, all within memory 90. All of the above are more
fully described with reference to Figures 9 and following,
' hereinafter.
;
'.~ s
;l - 12 -
,. ..
: ,. - . . :
- ~ , : -
l~S;~48
- 1 Principal data connection 86 further extends out
of compactor 54 and to input/output device 52 to intersect
with a data connection 98, issuing from a four bit shift register
. .
100 and extending to a modem side FIFO 102. Further,
5 principal data connection 86 intersects with a data connection
104 extending from modem side FIFO 102 and extending to an
additional four bit shift register 106.
Register 106 also includes a logic connection 108~TQ~d'~9
~ from the clock within the modem and an output data connection
'l 10 110 to a modem side converter 114. Clock connection 109 also
extends to register 100. Modem side converter 114 includes
an output data connection 116 to register 100, an input logic
1 connection 118 from the modem clock, an output data connection
Yj 120, as to modem D in Figure 1, and an input data connection
~ y~5 12~ as-from modem D in Figure 1. All of the above are more
Y fully described with reference to Figures 9 and following,
,~
hereinafter. ~ -
Also shown is timing and control block 124
including a general connection 126 to various parts, blocks,
20 and portions of the system, as will be more fully described
with reference to Figures 9 and following, hereinafter. Further
shown is an input/output control block 128 including a
,.!
general connection 130 to input/output devices 50 and 52, as
will be more fully described with reference to Figures 9 and
25 following, hereinafter.
~J
. .
,,`'.,~i
- 13 -
.
., .
, ~ ~
,~ .,
,,.~
: ;: - . ,
,. : .
5Z~8
1 With re~pect to Figures 1 and 7, as the computer
I begins to send data, it raises its request to transmit
signal, in a conventional manner, which signal is transmitted
from the computer and into the controller side converter 56
5 and to the compactor 54 shown in Figure 7. As this request
` to transmit signal issues from converter 56, it is recognized
by the coder 88, which then produces the necessary control
.! logic to start the clock 76. Clock 76 then shifts the
incoming data line 60 into the eight bit input shift register 62.
10 Incoming data then shifts through input device 50 continuously
until it matches a synchronization register, described later.
When syncronization is achieved, the first data character is
transmitted into the controller side memory FIFO 66 via data
~ conne~tion 64 where it assumes a data position at the bottom
'?~ 15 of the~register to await being accessed by coder 88. As soon
as the first character is in a ready status, as will be discussed
further hereinafter, the following character is beginning to
. , .
shift in. This continues with each character being accessed by
the coder 88 and operated on while other chæ acters are
20 being shifted in behind it and held in readiness.
In order to reduce the number of bits required to
'! .
express a given chàracter in accordance with the present invention, -
it has been found that the practice of expressing all characters
in the base 256 (eight bits) can be eliminated. A device according
25 to the present invention accepts the eight bit serial data,
as from line controller B, performs extensive manipulation of
the data, and expresses the data as a string of characters of
varying lengths. That is, the chaxacters are not all
expressed in the same number base. By using different number
bases to express the data, while the length of
j .
I - 14 -
.: ~ .. . . -
11~)45Z~8
- 1 certain characters is increased, it has been found that
- the overall length of the data, in bits, is shortened.
That is, it has been found that by using lower number bases
(fewer bits) to express common characters or situations
5 and higher number bases to express less common characters
or situations the overall data length in bits is shortened.
In carrying out the preferred embodiment of the
present invention, number bases 8 (three bits) and 256
(eight bits) are used to indicate specific characters or
10 sequences of characters. Varying number bases æ e also used ~ -
to indicate conditions such as (1) where the character is the
same as the previous character, and (2) where a character is the
same as corresponding characters in a previous record. In
addition, number base 2 is used where one bit represents
15 one character or one control bit, number base 1/8 is used
. .
;~ where one bit represents three chæ acters or one control bit, and
number base 1/16 is used where one bit represents four
characters or one control bit.
The control codes used in the different steps of
20 compaction use a technique in which specific bit combinations
of number bases 2, 4, 8, 16, 32, 64, 128, and 256 æe used
for control purposes. Therefore, depending on the specific
data being compacted, the preferred matrix is constantly switching
J in and out of 10 number bases in performing its normal
25 operation. A matrix using fewer number bases will be described
s hereinafter for purposes set forth hereinafter.
In order that control may be exercised over the
various ch æ acter groups, control level codes are assigned
corresponding to a shift to a certain level for storage,
^ and the control level codes æ e shown generally in Table I
as set out below-
.. . .
- 15 -
;, . . ~ . . . - : . . ,: . - .. , :
` 1045248
,,
.
1 TABLE I
Control Level Codes Characters
- .
0 Shift to level 1 0 2 1 (blank) 5 . 7 3
, 10 " 2 8 6 4 E 9 A - T
', 5 110 " 3 Characters identical to prior record
.' 1110 n 4 R C D S I O ~ N
11110 ~I 5 P B F G M K L U
! 111110 1l 6 Characters identical prior character
0 n 7 H V * / y &
10 11111110 " 8 J = X W ~ Q Z $
3 11111111 n 9 No compaction mode
`~ Level 3'Codes (base 1/16)
0 Four character group identical to corresponding
group in prior record.
1 Shift to base 2.
~ .
F~evel 3'Codes (base 2)
,~ 0 One character identical to corresponding character
in prior record.
~'~'! 1 Shift to control level.
Level 6 Codes (base 1/8)
,
0 Three characters identical to prior character.
~ Shift to base 2. ~~-~--~--~-~~
Level 6 Codes (base 2)
~0 One character identical to prior character.
-'~25 1 Shift to control level. ,
Level 1,,2, 4,,5,,7,,8 Codes (base 8)
''' NNN Base 8 character to represent 1 of 8 characters in
level.
' Level 9 Codes (base 256)
,i 30 NNNNNNNN Base 256 character to represent 1 of 256 characters
',- in level.
j 11111111 One specific base 256 character designated for
~ shift to control level.
.~, .
, - 16 -
,
; :., . ~ .
: 1!)45Z48
1 Returning to the example, data is in FIFO 66, and as soon as the
first entire eight bit character has been shifted through the
FIFO 66 and is available via data connection 68 at the eight
bit output shift register 70, coder 88 will access this
5 character and begin to operate the compacting logic which
is stored in the instruction memory or the micro cc~e 92 In
~ the case of the above set out example, the first character
;~ to be brought in is an "L" from the word "LINE". As can be
seen from Table I, "L" is a member of level 5 compaction
10 logic. Therefore with reference to Figure 2, the mechanism and
process of compaction, according to the present invention,
', is to bring in the next character, step 10, and then to check
to see if the character brought in is an initial entry, step
'~ lOa. ' Since, in the example set out, the letter "L" is an
~L~i~ial~entr~y~ the me-ch-anism and process, according to the
pre~ent invention, then proceeds to set up this character
without compaction, step 11, and to transmit the data
bits to modem side FIFO, step 12. For this example, it
i~ assumed that the logical representation of the letter "L"
~, 20 is 11010011 in a conventional base 256 system.
;~ Specifically with respect to Figure 7, it can be seen
'~i that coder 88 transmits the eight bits representing the letter
~L~, by grouping them in groups of four bits and transmitting
them via data connection 86 into the four bit shift register 100
25 on the modem side FIFO stack 102. As each four bits is provided
~ to the FIFO 102 via data connection 98 from the input shift
,~,, register 100, it assumes a data position at the bottom of modem
side FIFO stack 102 where it is then shifted via data connection
104 into the four bit output shift register 106. ,As each clock
signal comes in from the modem clock line 118, through
~, ~
- 17 -
1~524~
` l converter 114, and~via connection 108, one bit at a time
is shifted out of register 106 and onto the transmit data
line 110. As each four bits of the data is provided to the
data line 110, the next four bits, which are waiting in
5 the modem side FIFO stack 102, are then shifted into the
`! four bit shift register 106.
` Similarly, and again with respect to Figure 7,
,7 as the data is provided by a data connection 86 to the
four bit shift register lO0, it is simultaneously provided
10 to memory 90 to be stored in data memory 94 in the location
,~ equivalent to its distance from the start of the record.
! At the end of the record, the entire record is saved to
provide a comparison mask for the next record, as will be
."` ~
:3 explained further hereinafter. This storage of each
if 15 character of the record also allows a comparison mask
7' for the next characters, as will also be described further
hereinafter.
f Returning again to Figure 2, the compaction according
to the present.invention now continues by checking if the system
~f 20 i~ currently in level 9 and if it is desirable to lèave level 9.
j Since the system is in level 9 in the example started above
, and because leveI 9 is an uncompacted level, the next compaction
step is to see if it is desirable to leave level 9, step 13.
, .
, 25
f
~ - 18 -
f
~ . . , .:
, .
", ' ' ' ' ~ , _
. , ' :
.
~ 1~4~Z48 ~
1 Since the data charlacter currently being operated upon,
i.e. "L", is not a level 9 character, but a level 5 character
according to Table I and the next three characters "INE" are
~ also not level 9 characters according to Table I, it is
.` S desirable to leave level 9 and the logic then sets up the
eight bit exit control code 11111111, step 14. This particular
: feature of the present invention, termed "lookahead",- will be
discussed further hereinafter in relation to Table II. This
. eight bit exit control code allows the system to leave level 9
~, 10 and enter the control level of the appropriate compaction
logic, for the next character.
The system then proceeds through steps 12 and 12a.
. At step 12a, since the control bits have been set to leave
level 9, the storage is not currently in level 9, and
, .
`...... 15 progress is made to step 15. At step 15 the system checks
y' to see if the current record is complete. Since it is not
complete, as only the first letter has been entered, the
system stores the character just processed, "Ln, into data
~ memory 90 and proceeds back to step 10, to bring in the
3 20 next character.
As indicated in step 10, the compacter then accesses
the next data character, seen from the example given to be
the letter "I" from the word "LINEn. This letter is then
in the form of an eight bit logic output from register 70.
. 25 The system then again checks to see if this letter "I" is
an initial entry or if the system is currently in level 9,
-- 19 --
.
,,, . :
~ . .
.
' :'. ~ ' ' ' . ,.', . . .
`` 1~45Z4~
1 step lOa. Since the system has proyressed out of level 9,
the answer is no, and the system progresses to step 17 of
Figure 2. Since the letter "I", the character currently operated
upon, is not the same as the corresponding character in a prior
.
5 record, since i~ is assumed that there is no prior record,
the system progresses to block 27. Since the letter "I" in the
example given is not the same as the previous letter operated
upon, the letter "L", the system progresses to step 37.
The letter "I" is indicated by Table I as a level 4
10 character, so the system progresses to step 40 where necessary
control bits are set up, specifically a four bit sequence
consisting of 1110. The compaction logic then proceeds to step 42
. where the base 8 data is set up. In this case, for the
:-., letter "In, the base 8 data is 100, the binary code
15 indicating that the letter "I" is the fifth position in the
level 4 table. The system then continues through the process
of transmitting the character, of storing the character in the
data memory, and of preparing to bring in the next character,
steps 12a, 12, 15, and back to 10.
.~1; 20 Compaction level 4 requires four control bits to
reach and three bits to express the character, because
the expression is in number base 8. The compaction of
., a single character then produces a bit string lllONNN where
. the 1110 form the control bits and the NNN are the three
25 bits to identify one of the possible eight characters in
level 4. From Table I, the characters represented by level
~^1
4 are:
R C D S I O , N
. .
~ 20 -
... . .. . .
.... .
, . .
lV45~8
~,
1 Returning again to the example, the next character
brought in is the ~etter "N" from the "LINE", which
` also has been assigned by the preferred embodiment of the
compaction system and apparatus of the present invention
5 to level 4. This character also traverses step 10, lOa,
~.~
17, and 27, and is operated upon in step 37 in a manner explained
previously. Therefore, the same control logic produces the
same set of control bits. However, this time the three bit
data portion is now 111 to indicate that the letter "N"
j lO is the eighth character in the character set.
`~ The system then repeats progress through steps
-~ 12, 12a, and 15, and back to step 10, as previously explained.
To this point, the output from the compaction
since the compactor was entered and including the level
15 9 character and the level 9 exit control, and for the exemplary
s data entered, i.e. "LINn, is . _
~.
11010'011 11111111 1110100 1110111
L 9 exit I N
The above presentation has been spaced for
20 illustrative and explanatory purposes only. It will be
recognized that spaces do not appear during actual transmission.
i~ Likewise, the characters represented by the binary bit string,
and appearing below the bit string, are set out for purposes
of explanation and illustration only.
.
;~ ' ': '
- 21 -
~, ' ,, .
::
.
.
.; . .
.,
1~45Z~8
Continuing with the example, the next data
character brought into the controller is the letter "E",
the last letter from the word "LINE". This character also
traverses step lO, lOa, 17, and 27, and is operated upon in
S step 37 in a manner explained previously. The "E" is assigned
~' to level 2, by the preferred embodiment of the compaction
technique and apparatus found in Table I, and therefore
a two bit control code of "lO" is set up and this two bit
control string is followed by a three bit data string of
`; lO Oll indicating that the letter "E" is the fourth entry in
` the table.
Compaction level 2 is identical to compaction
level 4 except that it only requires two control bits to
;` reach and represents a different eight characters. The
. ,
15 characters represented by level 2, in the preferred embodiment
of the apparatus and system of the present invention as
exemplified by Table I, are:
8 6 4 E 9 A - T
"
' The compaction of a single character in the group
20 assigned to level 2 produces a bit string lONNN, where the
, l and the 0 are the control bits and the bits NNN are the
three bits to identify one of the possible eight characters,
` in the number base 8.
The system then repeats progress through steps
25 12, 12a, and 15, and back to step 10, as previously explained.
- 22 -
., .
~' ~,
lO~Z48
1 At this point the total output according to the
compaction of the ~ata "LI~E" from the compaction
according to the present invention is:
, 11010011 11111111 1110100 1110111 10011
' 5 L 9 exit I N E
The above presentation has been spaced for illustrative
and explanatory purposes only. It will be recognized that spaces
do not appear during actual transmission. Likewise, th~
characters represented by the binary bit string, and appearing
` 10 below the bit string, are set out for purposes of explanation
`j and illustration only. ~ '
The next data character brought into the system
:! iS a blank, between the word "LINE" and the remaining data.
is character also traverses step 10, lOa', 17, and 27, and is
operated upon in step 37 in a manner explained previously.
The blank is found in level 1, of Table I, and therefore ~-
produces' a ~singl'ë'bit`control'code'of O'followed by three'bits '
of data, 011, to indicate its fourth position in level 1 of
Table I.
Compaction level 1 requires only one control
bit to reach and three bits to express the character,
again in number base 8. The compaction of a single
character produces a bit string ONNN where O is the
3~ single control bit and NNN represents the three bits necessary
to identify one of the eight possible characters in number
base 8. This level is used or compacting the eight
i - 23 -
i~ . .
, . .
,. . . .
l~SZ48 :
1 most commonly used,characters, and while these characters
may vary from one application to anothex, the preferred
embodiment of the present invention has assigned level 1
characters as:
0 2 1 (blank) 5 . 7 3
. .
' The system then repeats progress through steps
12, 12a, and 15, and back to step 10, as previously explained.
.~, .
The next exemplary character brought in by the
coder 88 is a "0". This character also traverses step 10,
.~
10 lOa, 17, and 27, and is operated upon in step 37 in a ~nn~P bxplai~ed
previously. Since the "0" is found in level 1, as discussed
above, the operation is similar to that of the preceding
character with the exception that the three bits of data
~' folldwing the control code 0 are 000 to indicate the placement
15 of the character "0" in level 1
: ~ , = ~ . . . . . .. .. . .
The system then repeats progress through steps
~- 12, 12a, and 15, and back to step 10, as previously explained.
The next data character brought in in the
i example lS ~ , and again the operation is similar to
`:~! 20 that previously explained since the "1" is also found in
leveI 1. Again, the only difference is in the three bits
of data to be added to the control code of 0. In the
case of data character "1", the three bits of data are
` 010 to indicate that the character "1" occupies the third
25 place in the assigned level 1 according to the preferred
embodiment of the present invention. --
- 24 -
2,
.~ ' ' '
~ , .
: . ~' '
~:, , ' '
,~ .
iO~ 8
;. 1 The next ex~mplary character brought in by the coder
88 is a "blank". ~his character also traverses step 10, lOa,
:.
..17, and 27, and is operated upon in step 37 in a manner explained
`~ previously. The "blank", in the manner explained above,
.~ 5 produces a compacted code of 0011.
.l At this point, the total output from the compaction
~ according to the present invention for the portion of the
.~ ,
~i example assumed compacted thus far, i.e. "LINE 01 " is
,,~ 11010011 11111111 110100 1110111 10011 ,~ '
`! 1 L 9 exit I N E
:,.! 0011 0000 0010 0011
blank 0 1 blank . .
ll The above presentation has been spaced for
'.J, illustrative and explanatory purposes only. It will be
recognized that spaces do not appear during actual transmission.
Likewise, the characters represented by the binary bit string,
and appear.ing..belo.w.the..bit.string,.are.set.out for purposes
of explanation and illustration only.
The next data character brought in according to the
example set forth above is an equals sign. This character
also traverses step 10, lOa, 17, and 27, and is operated upon in
step 37 in a manner explained previously. The equals sign ~: ;
.~ is found in level 8, and therefore produces eight bits of control -
.I code logic 11111110, followed by three bits of data 001, to
,3 25 indicate that the equalssign occupies the second position of
level 8.
- 25 -
.. , j
:i
~:3 '
,r~
lO~SZ~8
1 CompactiQn in level 8 is identical in operation to
compaction in levels 1, 2, and 4, except for the characters
,; represented. The compaction of a single character produces
a bit string lllllllONNN where the 11111110 are the control
, 5 bits and the NNN are the three bits to identify one of the
~, ~ eight possible characters in this group in the number base 8.
The eight characters represented by level 8 according to
' the preferred embodiment of the present invention are:
' J = X W + Q Z $
.. , :
,, 10 The next exemplary character brought in by
~'~ controller 88 is also a blank, and the compaction logic
produces an output of 0011 in the identical manner to
~ the previous blank discussed.
,~ ' The next character brought in by control logic
15 88 is ,an open parenthesis and this character has been
assigned to level 7 by the preferred embodiment according
to the present invention. This character also traverses
~ step 10, lOa, 17, and 27, and is operated upon in step 37 in a
- manner explained previously.
" 20 Compaction level 7 is identical in operation to
' "levels 1, 2, 4 and 8 discussed previously with the exception
of the characters represented. Compaction of a single
character produces a bit string of llllllONNN where the
1111110 are the control bits and the NNN are the three
25 bits identifying one of the possible eight characters. ,
e eight characters assigned by the preferred embodiment , ,
according to the present invention to level 8 are:
,, H V * / Y & ( )
I ~ - 26 -
!
i, ` .-~
. ,. ~ ., ~
i. . . ~
~ ~ . .r~~
` 1045248
.
~ 1 Thus, the open parenthesis character from the
~.
example produces a~seven bit control code of 1111110 and a
three bit data code llo indicating that the open parenthesis
occupies a seventh position, in order, in the characters
assigned to level 8.
At this point, the total logical output from the
compacter for the example data "LINE 01 = (" is:
.'.~ 110100~1 11111111 1110100 1110111 10011
~ L 9 exit I N E
? 10 0Oll 0000 0010 0011 11111110001 0011 1111110110
~ blank 0 1 blank = blank
-~ me above presentation has been spaced for
illustrative and explanatory purposes only. It will be -
recognized that spaces do not appear during actual transmission.
Likewise, the characters represented by the binary bit
string, and appearing below the bit string, are set out for
L ~ ~puEposes--of--explanation and illustration only.
The system then repeats progress through steps
12, 12a, and 15, and back to step 10, as previously explained.
3f 20 The next data character in the example is "B".
This character also traverses step 10, lOa, 17, and 27, and is
operated upon in step 37 in a manner explained previously.
From Table I, "B" has been assigned according to the preferred
embodiment of the present invention to level 5. Compaction
level 5 is identical in operation to the previously discussed
levels 1, 2, 4, 7, and 8, again with the exception of the
- 27 -
-
..
"~ 104S~48
l characters assigned to this level. The compaction of a
single character p~oduces a bit string of llllONNN, where
~- 11110 are the control bits and NNN are the three bits to
identify one of the eight possible characters of this group,
~'~ , 5 in base 8 logic. The eight characters represented by
`! ' level 5 according to the preferred embodiment of the present
, invention are:
t, .
,~ P B F G M K L U
~,i Thus, the "B" next brought in by controller
` 10 88 produces a control code of llllO and a three bit
`! data code of 001 indicating its second position in the
`~ character string represented by the assigned level 5.
~ The system then proceeds through steps 12, 12a,
',~ 15, and back to step lO, as previous y explained.
,~ 15 ' The final character in the first record of the
,` example set out abov,e is a,close,,parenthesis. The close ' ''
parenthesis falls in level 7, according to Table I.
, Thus this character, in the manner previously set out, ~'~
'i produces a logical output of 1111110111 with the seven bit
20 control code of llllllO discussed above and the three ~ -
bit data code of 111 indicating the position of the ~ ' '
close parenthesis as the eighth position of level 7.
At this point the total compacter output for the
'~ first record of "LINE 01 = (B)" is:
11010011 llllllll 1110100 lllOlll 10011 0011 OOOo
, L 9 exit I N E blank 0
', 0010 0011 11111110001 0011 1111110110 11110001 1111110111
1 blank = blank ( B
- 28 -
.. .
~, . . .
" ' . .' '
-~ :
`~ ~0~5Z48
- 1To this point in the explanation of the present
invention, only character level compaction has been performed.
That is, no step 17 or step 27 compaction, as set forth in
~ Figure 2, has been performed; only step 37 compaction has
`~ 5 been performed. The compaction performed, however, has
reduced a record which was initially 104 bits in length to
94 bits. That is, the first record of "LINE 01 = (B~" consists
of 13 characters and with a conventional representation of `~
eight bits per character, would represent a total of 104 bits.
., ,
10 From the total compaction output set forth above, it can ;~
be seen that only 94 bits are used to represent this data
~ record, previously to the present invention conventionally
3 represented by 104 bits.
The above set out compaction of the first record
5 has also çontained tke overhead of the exit code for leaving
level 9 and has also established a prior record mask which
allows greater compaction in following records. The prior
record mask is stored at the end of compaction upon the first `
record where step 12 is traversed, step 12a is traversed, and
~ 20 the system traverses step 15.
$ The test for record completion, step 15, is totally
dependent on the type of terminal hardware with which the
system of the present invention interfaces. Some terminals
transmit only one record per transmission block, and the end
25 of a record is an actual halt of data transmission. For
. :
r
~. . _ . . .
. ~
~ 1045Z48
1 simplicity, this is,assumed to be the case for the example
of this description. Other terminals, however, use special
~ characters or sequences of characters to indicate the end of
`~ a record has occurred, and this allows multiple records to
S be transmitted and packed into a single transmission block.
; ' If this later technique were to be used, the compactor
passes the special characters or sequences of characters along
in a compacted form in the manner of ordinary data, but logic is
arranged at step lS to recognize these special characters or
10 sequences of characters that separate the records, and
: thus allow each record to be used as a prior record mask.
As can be seen, since the record is now complete,
it is transmitted and also saved, as in step 16, for use which
-~ can now be explained.
Returning again to the data example set out
above, the second record is then ready to be brought
into compacter 54 by coder 88. As can be visually
seen in the simple example given, the first six characters
of the second record are identical to the first six
20 characters of the first record already processed. That
is, from "L" to and including "0", the records are identical
for the first six locations in the prior record. Thus,
compaction according to the present invention would proceed
;.~j
3 from step 10 of Figure 2, through step 10a, as previously
25 described, and stop at step 17 where it is found that
~` a character is the same as a corresponding character in
,i :
~ - 30 -
j: :
! `.
.' ~
. . .. . ~ ~
:
1~5Z~18
` 1 a prior record. The system then proceeds to step 20 where
a three bit control code for level 3 is set up. From Table I,
this control code is 110. The system then proceeds to step 22
' and the remaining steps 23, 25, and 26 in sequence.
... . .
Compaction level 3 is used when portions
of a record repeat the corresponding portions of a prior
record and the three control bits, llO, are used to shift into -
level 3. In level 3, one bit represents four characters
or one control bit, thus assuming a number base 1/16.
` 10 A single 0 bit is inserted into the bit string to identif~
this condition, and further 0 bits are inserted as long as
the condition exists and thus warrants. To shift from this
it ~ .
level, and from the number base l/16, a single 1 bit is
^ inserted into the bit string and, upon so doing, a change
15 to the number base 2 takes place where one bit represents
one character or one control bit. A single l bit releases
~'3 the compaction from the base 2.
i, l
As an example of use of level 3, and separate
and apart from the continuing example considered thus far,
20 assuming ll characters in a row are identical to the prior record,
the bit string produced would be llO 001 0001. Separation
of the bit string is used to show the control bits (110),
the representation to the base l/16 (001) to represent
eight identical characters and a shift from level 3, and
25 the representation at base 2 (0001), representing the
three additional characters and a release from base 2, as
will be explained further hereinafter.
.
r~
;1 r
:i
: . i
:~1 .
i. , ~ .
- 104S248
. , .
1 A second example o~ use of level 3, again separate
and apart from the continuing example set forth above, is the
situation where only two characters are identical. The
; bit string produced would be 110 1 001. Again, separation
5 of the bit string is used to show the control bits and
the data representation. Since there are no groups-of four,
only a single control bit is used in base 1/16, to change
number bases in level 3. The remaining portions of the
bit string (001) represent the two characters and the exit
u~ 10 from base 2, level 3, as again will be explained further hereinafter.
Returning to the continuing example on the
x four records set forth above, it had been found that the
' first six characters of the second record were identical
, ..:
to the first six characters of the prior and first record,
-n-Ln;through and including "0". Utilizing step 22
~:
__ of Figure 2, the compaction according to the present
31 invention sets up the data as a single 0, which indicates
four characters identical to the prior record, and then
sets up a 1, step 23, indicating that no further groups
20 of four characters are identical to the prior record.
Setting up the one control bit in step 23 causes the system ~ ~
~ to shift to base 2, level 3, step 25, where the system sets up a ~-
# bit string 001 to represent the two remaining characters
not yet compacted and a one to shift back to the control
25 level, step 26. Thus, the six identical characters have
now been indicated by one bit at level 3, base 1/16, representing
., .'~ four characters, and two bits at level 3, base 2, representing two
characterst along with two control bits representing the
various number base shifts.
:; :
32 -
s 1~)45Z48
.,.. ; .
~; 1 At this point, the bit string representing the -
compaction output o~ the present invention for record
two is:
.
:' 11001001 . .
~` 5 6L3
I The notation "6L3" indicates that six characters
; ',7 .'
have been replaced by a single level three code.
l The system according to Figure 2 would then
traverse step 12, 12a 15, and return to step 10.
` 10 The next data character in the continuing
example is "2", which is a level 1 character and is handled
~!' in that manner. That is, the system traverses steps lOa, ~;
~!
17, 27, 37, 40, 42, 12, 12a, 15, and returns to step 10.
The bit string output is 0001 representing a one bit control
15 code Qf 0 and a three bit data code, in base 8, indicating
that n2" is the second character in position in the assignment
~ of level 1.
The next four characters of the second record
starting with the blank and ending with the open parenthesis
~i 20 are identical to the four characters in the identical position
~ in the prior record. Again, leveI 3 is used and
.~` . , .
the system traverses steps 10, lOa, 17, 20, 22, 23, 25, 26, ;
12, 12a, 15, and back to step 10. The bit string output is
110011 to include the control code for level 3 (110) the
25 representation that one group of four is present in level 3 (0),
the shift to base 2 (1), and the immediate shift out of base
2 since there are no leftover characters (1).
i
..~
`.``1
~ - 33 - r
:`' :
.... .
~. .
~,. :
~. ,
. :. . , ~ , 1:
1~)45Z~8
1 The next character of record two of the continuins
example is "D". This character is a level 4 character and
is handled in a manner previously explained to produce a
bit string of 1110010, to include the control code for level
; 5 4 (1110) and the base 8 positional information indicating
.~ .
the letter "D" is the third positional letter in level 4
(010) .
At this point, the compaction for record two for
the data "LINE 02 = (D" is:
"~ 10 11001001 0001 110011 1110010 ' '
; 6L3 2 4L3 D
c Starting again at step 10 of Figure 2 and with
the continuing example, the next eight data characters are
all "D", and therefore are the same as the prior character
`~ 15 in the current and second data record. Thus, the system
traverses--s-teps---10-~-lOa-j--~and-17 and descends from step-27 into
steps 30 and following to set up level 6 according to
Table I.
Compaction in level 6 is used when a string of `~
identical characters exists in the same record. Six control
' bits 111110 are used to compact in level 6, and entry into
, level 6 assumes a number base 1/8 or a situation where
one bit represents three characters or one control bit.
A single O bit is then inserted into the bit string to
indicate that this condition exists, and further O bits
are inserted as long as the condition exists and warrants.
~ '
.''.
, - 34 -
.,
..
.. : ~ .. - ., . :,
:, .~: . . . . -
~. . , ;. ,., ~ :
l 1~)45Z48 ~ ~
1 Release from level 6,base 1/8 is by a single one
bit inserted into the bit string. Again, similarly with
.~
~ base 1/16, the release from base 1/8 is always into number base ~ ~ ;
-~ 2 where one bit represents one character or one control bit.
`~ 5 In number base 2, again, a single 0 bit is inserted so long
as the condition exists, and a single 1 bit produces an
exit from number base 2.
.6 Returning to continuing example where eight data
I characters, all "D" exist in record two, the bit string produced
.~
10 would be 111110 001 001. Separation is used here to show
the control bits (111110), the data in base 1/8 (001), and
the data in base 2 (001). Thus, for the above example of
eight identical characters, the level 6, base 1/8 information
includes two zeros indicating two sets of three characters
6 15 identical, a 1 to exit from level 6 and base 1/8, two further
zeros to indicate two remainder characters exist in base 2, and
~ a 1 to exit from base 2.
,~6 Thus~ for the eight identical characters "D"
the system according to the present invention traversed
20 steps 10, lOa, 17, 27, 30, 32, 33, 35, 36, 12, 12a, 15, and -
returned to step 10.
The final data character in the second record
is a close parenthesis, which as discussed above, is a leveI 7
character. This character causes the system to then traverse
25 steps 10, lOa, 17, 27, 37, 40, 42, 12, 12a, 15, and return to step
10 to generate a bit string of 1111110111 representing the
control code for level 7 and the three bit positional code for
close parentheæis.
. ~
~~ '~
~l 35
, .
. . .
1045Z48
i~ 1 At this point, the bit string produced by the
compaction according to the present invention of record two
- consisting of "LINE 02 = (DDDDDDDDD) " is:
11001001 0001 110011 1110010 111110001001 1111110111 .' ,:
6L3 2 4L3 D 8L6
~, .
; The notation "8L6" indicates that eight characters
have been replaced by a single level six code.
The compaction provided by the present invention
with respect to record two may now be discussed. In record two,
further compaction was possible in that it was possible to
utilize both the prior record and the prior character masks
according to the present invention. Thus, record two, as set
forth above, includes 21 characters, which at eight bits per
. . ~
7 character as conventionally encoded, would result in a bit
`~t 15 string of 168 bits. As can be seen from the final compaction
; of record two, through the utilization of the teachings of the-
7 present invention, this 168 bit string has been compacted
to 47 bits. Further, both records one and two have created a
mask which may be utilized in further compacting succeeding
20 records.
:., ~ .,
`~ Returning again to the data example set out ~`
above, the third record is then ready to be brought into
compactor 54 by coder 88 . As can be visually seen in the
,; ~
simple example given, the first six characters of the third
;~} 25 record are identical to the first six characters of the
.,
c.
~ .
- 36- . ~;
'' ~.
,~ ,
.~,' \~.
~~ r~
1~)452~1s8
.
, 1 second record alre~dy processed. That i5, from 'IL'' to and
including "0", the records are identical for the first six
locations in the prior record. Thus, compaction according
to the present invention would proceed from step 10 of Figure 2,
S through step lOa, as previously described, and stop at step 17
'` where it is found that a character is the same as a correspond-
"~3 ing character in a prior record. The system then proceeds to
step 20 where a three bit control code for level 3 is set up.
From Table I, this control code is 110. The system then proceeds
10 to step 22 and the remaining steps 23, 25, and 26 in sequence.
The next data character in the continuing example
',3 iS ~3n~ which is a level 1 character and is handled in that
;~ manner. That is, the system traverses steps lOa, 17, 27, 37,
40, 42,` 12, 12a, 15, and returns to step 10. The bit string
15 output is 0111 representing a one bit control code of 0 and a~
~! three bit data code, in base 8, indicating that "3" is the
eighth character in position in the assignment of level 1.
e next four characters of the third record
'3 starting with the blank and ending with the open parenthesis
, .
i 20 are identical to the four characters in the identical position
~3 in the prior record. Again, level 3 is used and
the system traverses steps 10, lOa, 17, 20, 22, 23, 25, 26,
12, 12a, 15, and back to step 10. The bit string output
~ is 110011 to include the control code for level 3 tllO) the
i 25
~J
- 37 -
. ~ .
:1 ,
.~ ~ "
.; . .
::
,
.:
~ 10~5Z48 : ~
1 representation that one group of four is present in level 3 (0),
~, the shift to level.2 (1), and the immediate shift out of level
.1
2 since there are no leftover characters (1).
The next character of record three of the continuing
S example is "Y". This character is a level 7 character and
is handled in a manner previously explained to produce a
. bit string of 1111110100, to include the control c~de for
:~ level 7 (1111110~ and the base 8 positional information
indicating the letter "Y" is the fifth positional letter in
10 level 7 (100).
3 At this point, the compaction for record three for
1 the data "LINE 02 = (Y" is:
., 11001001 0111 1'0011 1111110100
6L3 3 4L3 Y
.',.',! 15 . The next two characters in the continuing example
i are both ~yn. Since these characters are the same as the
.. - .. . .. . . . :
prior characters, a single level six output of 1111101001 is
generated, in the manner previously explained.
The next three characters in the example are all "D".
2Q Since these characters are the same as in the prior, second
record, a single level three output of 11010001 is generated,
in the manner previously explained.
The next character is the continuing example is
a "Tn. This character is a level 2 character and an output
` 25 of 10111 is generated, in the manner previously explained.
- 38 -
.
., .
~.
-
1045Z48
1 The next character in the continuing example
is also a "T", but this is the same as the prior character of the
pre"sent record, and a level 6 output of 111110101 is
, generated, in the manner previously explained.
, 5 The next two characters in the continuing example
~, are "D)". Since these two characters are the same as in the
prior, second record, a level 3 output of 1101001 is
generated, in the manner previously explained.
At this point record three is complete. The total
10 compacted output for record three is:
110010010111 110011 1111110100 1111101001 11010001 10111 ,.i
6L3 3 4L3 Y 2L6 3L3 T
'", 111110101 1101001 : ~:
lL6 2L3
, 15 The compaction provided by the present invention
, with respect to record three may now be discussed. In _ ord-three-r-further- compaction was possible in that it was
possible to utilize both the prior record and the prior character
masks according to the present invention. Thus record three,
20 as set forth above, includes 21 characters, which at eight
bits per character as conventionally encoded, would result
^,,
in a bit string of 168 bits. As can be seen from the final
compaction of record three, through the utilization of the
~! teachings of the present invention, this 168 bit string has
25 been compacted to 67 bits. Further, record three has created
a mask which may be utilized in further compacting succeeding
records.
,
- 39 -
" .
,.
~!.
.~ :
~ 1~45Z48
1Record four is handled in much the same manner
as the first three records, discussed above, until the
j5 characters of the semicolen, the colen, the number sign,
.
and the question mark are reached. These four characters are
5 used in the present description to represent level 9
logic. Although these four characters are often printable
characters, the vast majority of leveI 9 logic characters
are not printable characters.
~ Compaction level 9 is thus a no-compaction mode.
;~ 10 In some instances, all of the 256 possible bit combinations
are used even though most are not printable characters and
s therefore each of the eight bits are passed along as exactly
received in the number base 256. It is also this mode of
` operation which guarantees that any string of characters, - ;
15 no matter how unusual or unprintable, can be correctly
transmitted through the compactor, even though some
combinations could cause an increase in record size. This
3 level is entered by the use of control bits 11111111 and .
Y therefore the first such character in a contiguous string ~
20 produces a bit string llllllllNNNNNNNN. Once in this mode
of operation, eight specific control bits (11111111) are
~1 also required to leave the level.
Returning again to the data example set out
above, the fourth record is then ready to be brought
25 into compactor 54 by controller 88. As can be visually
- 40 -
s,
,
~
','' ~ ' ' : ' ` ' ~
5Z~3
1 seen in the simple~example given, the first six characters
of the fourth record are identical to the first six
characters of the third record already processed. ~hat
is, from "L" to and including "O", the records are identical
.: .
5 for the first six locations in the prior record. Thus,
`S compaction according to the present invention would proceed
; from step 10 of Figure 2, through step lOa, as previously
described, and stop at step 17 where it is found that
a character is the same as a corresponding character in
10 a prior record. The system then proceeds to step 20 where
a three bit control code for level 3 is set up. From Table I,
~; th s control code is 110. The system then proceeds to step 22
and the remaining steps 23, 25, and 26 in sequence.
The next data character in the continuing example
15 is "4", which is a level 2 character and is handled
in that manner. That is, the system traverses steps lOa,
17, 27, 37, 40, 42, 12, 12a, 15, and returns to step 10.
.i,
$ The bit string output is 10010 representing a two bit control
code of 10 and a three bit data code, in base 8, indicating
20 that "4" is the third character in position in the assignment
of leveI 2.
The next four characters of the fourth record
starting with the blank and ending with the open parenthesis
are identical to the four characters in the identical position
25 in the prior and third record. Again, level 3 is used and
the system traverses steps 10, lOa, 17, 20, 22, 23, 25, 26,
12, 12a, 15, and back to step 10. The bit string output is 110011
to include the control code for level 3 (110) the representation`
1 r
::;';
~ 41 -
10~5Z48
1 that one group of four is present in level 3 (0), the
shift to level 2 (1), and the immediate shift out of level
2 since there are no leftover characters (1).
The next character of record four of the continuing
example is ";". This character is a level 9 character and
is not contained in the levels 1, 2, 4, 5, 7, or 8. Therefore
it must be a level 9 character, as is shown by reaching step .
.~ 46 of Figure 2. The control bits 11111111, which signal an
. entry to level 9, are generated in step 50. The noncompacted -:
. 10 input value for ";" which is 01011110 is also generated and
transmitted.
At this point the compacted output from record four
LINE 04 = ~ n is
~. `1
", , 11001001 10010 110011 11111111 01011110
6L3 4 4L3 9 entry ;
The notation "9 entry" indicates the control bits which cause--~~~ ~~-~~
an entry to level 9. This is then followed by the level 9 :
.. ~ character, as provided to the system of the present invention.
.. ~ The next character in the continuing example is a ":";
~, 20 This is also a level 9 character, so the compactor will remain
:~ in level 9. At the time of the last character a test was
`:.~ made, in step 13, to determine the desirability of leaving
' level 9. A lookahead was done, as will be explainéd further
hereinafter, and if the next three characters were all nonlevel
;i 25 g characters, a level 9 exit code would have been generated.
:
~i .
.,~. ~ .
~ - 42 - -
,.~ .
- ~ .
;.i
.
~ .
- . , . .. . . . . ~
. :
.
16)4SZ48
1 This is not the case in the present continuing example; so the
~` compactor remains in level 9 until three characters in a row are
nonlevel 9 characters, or until the record is finished. In
this case the record finishes first, so the remaining characters
are handled in level 9.
` At the end of record four the compacted code for
! ' ~LINE 04 = (;:#?)" is:
. 11001001 10010 110011 11111111 01011110
~' 6L3 4 4L3 ~ entry
:~ 10 01111010 0~.111011 01101111 01011101 11111111
: # ? ~ 9 exit
;~ The compaction provided by the present invention
with respect to record four may now be discussed. In record
, four again, in compaction, it was possible to utilize both
the prior record and the prior character masks according
to the present invention. Thus record four as set forth
above,-includes 16 characters, which at eight bits per
character as conventionally encoded, would result in a bit
string of 128 bits. As can be seen from the final compaction ;~
~,~ 20 of record four through the utilization of the teachings of the `
present invention, this 128 bit string has been compacted
to 75 bits. Further record four has created a mask which
may be utilized in further compacting succeeding records.
;, .
.,
i ~ 43 ~
.
s
t
-
.
... . . .
1()45248
1 Compaction for the total example may now be examined.
The following table shows the results for the four record example:
Record Length in bits Length in bits Ratio
non-compacted compacted
.'
1 104 94 1.11 ;
2 168 47 3.57
3 168 67 2.51
$ 4 128 75 1.71 ~
~ Total 568 283 2.01
.,1 .
,
It can then be seen that a substantial improvement has taken
place. Although no claim is made that this example is typical
5, data, it is data for which most currently used techniques are
useless. It may also be seen that the ratio of record one may
be disregarded since after one initial record the compactor
may run for long periods of time with each record masking from
;31~d the record ahead. Record four is also nontypical due to the
unusual amount of special characters contained to illustrate
a point. In general, commonly transmitted data would
re~emble records two and three, with similar results, but would
be more compactible due to large areas of blanks in a typical
printed page.
Once the continuing example and the discussion ~-
presented thus far is understood, a discussion and explanation ;
of the present invention may be continued, first with
25 respect to Figures 2-6. ~
s
- 44 - ~
`.,
.
",
~, , .
.~ . .. , !
.. . . .
_ ~ . .
., -. . .. . ; . . . .
lU45248
1 As has now basically been explained, ~igure 2
is a block diagram generally showing the logic created
.,
in the matrix to select the number base and the control
level in going from one number base to another, and
5 to select the control level in going from one number base
~! to another. As each character is read into the mechanism,
it is stored in a temporary buffer and compaction on the
~, record is performed in the manner shown generally in
Figure 2. The compacted data is then transmitted while
;j 10 new data is being read into the device, and as each record
¢' is completed, it is saved to be used as the prior record
~ mask.
`i Compaction of the data always starts at leveI 9,
q and under the worst conditions or when necessary to maintain
.~ompatibilit~ with o$her equipment, this level will
~i continue to be used. Normally, a shift into the control
level is made, and the control level, as explained earlier,
,
~i uses from one to eight control bits to call out various compaction
, ~ .
levels. As also explained earlier, the control strings are
20 arranged so that frequently used compaction levels require
a small number of control bits to reach, and infrequently
used compaction levels require a large number of bits to
reach.
To recapitulate and expand, in Figure 2,
25 assuming the compaction process to begin in level 9,
another character is brought into the matrix at step 10 and,
i - 45 - ~
J
i' ' ~ ' ~ ' ~ ' '
" . ' - ' ,
` 1045248 ~ ~
1 upon comparison at step 10a, a data string is created. The
data string is created, as at step 11, under the base 256,
` and the data is stored in an output buffer, step 12. For
a more detailed description of operation according to the
5 present invention, reference is made to Figure 6. The output
storage buffer 12 has its output compared in step
12a to determine if storage is currently in level 9 and if
it is, then comparison is made to the next character coming
in at step 13a where it is compared to see if level 9 is the
.. . .
q 10 least desirable, and if the answer is no, another character
. is brought in, in level 9, and is applied to the output
~ storage in the fixed code. However, if it appears that
.`.5' level 9 is the least desirable, another comparison is made
~ at step 13b to determine if the compatibility allows a level
.,
5_R~n~r than 9, and again if the answer is no,
another character is brought in, at level 9. Once it is ~ -
-determined that it is desirable to leave level 9 at step 13,
an eight bit exit control code (11111111) is generated at
step 14 and applied to output storage buffer 12. Once it
20 is determined that level 9 is no longer desirable, the next
character being brought into the matrix at step 10a will then
be applied to one of the character groups to determine how
; it may be compacted. Thus far, the current record is complete
` as found in step 15 which produces a mask, step 16, resulting
.,
` 25 from saving the record.
, :
,',~ ~ '
- 46 -
,.
: .~
i
.
,' . ~ " - `
1~452~8
1 Since the,matrix is now operating at some level
~- other than level 9, the next character is compared at step
~;, 17 and i~ the character is the same as in the corresponding
prior record, a control code of 110 control bits is established
5 at step 20. Figure 3 shows a more detailed disclosure of
the steps performed by the matrix where a comparison
i is made at step 21 to determine if there are four characters
.~ the same as in the prior record, and if there are, the
~ characters are encoded where one bit represents four
. .
:.:
10 characters or one control bit, to the base 1/16 as established in
; step 22. If there are less than four characters or there
. is a remainder, a single one bit is inserted into the bit string
by generating a signal of such in step 23, and the remainder
.~, .
is thén encoded in the number base 2 where one bit represents one
15 character or one control bit as found in step 24. As long . . ~ .
as there is a remainder, a 0 bit is established for each
character as in step 25 until the comparison at step 24
.:
produces no further characters being the same as in the
prior record and a control bit is generated at step 26
20 to produce an exit code from the base 2. These bits are
then stored in the output buffer, step 12, with the control
`;I remaining in the control level, and the matrix is now ready
to receive another character.
Assuming at this point that, within the record, a
~ 25 number of identical.characters exist and are brought in at
, steps 10 and lOa, the matrix will recognize the string of
.,
,.~
~ - 47 - '
~1 .
A
-
:
1~)45248
1 identical characters by a comparison, step 27, and 111110 are
generated by a step 30. These six control bits are used to
' shift into level 6 which is shown in more detail in Figure 4.
A comparison is made at step 31 to determine if there are
5 three characters the same as a prior character, and if they are,
the characters are encoded by having one bit represent three
characters or one control bit and are encoded in the base 1/8
as found in step 3Z. A 0 bit is inserted in the bit string
to indicate the three characters and the remainder is encoded
10 at a different base, by first inserting a single 1 as a
control bit into the bit string in step 33. The remainder
is compared to determine if one character is the same as the
prior character, and if it is, it is encoded in the number
~' base 2 in step 35 where one bit is used to represent that
lS one character. Once the remainder is encoded and there is no
~ additional character which is the same as the prior character,
,~ a single 1 bit is generated to develop a control bit at step 36
`~ causing the matrix to return its operation to the control level.
It will also be understood that the characters are stored in
20 the output buffer, step 12, and the matrix is then ready to
receive additional characters.
j After completing the two steps of compaction, 17
and 27, just described without obtaining a "yes" output, a
~ comparison is then made of the characters to determine
q 25 in which of the groups for levels 1, 2, 4, 5, 7 and a the ~
;~ -' . ' -
- 48 - ~ -
~,:
i
~, . - . . -
' :, ' ' ' . .. ': .
,.. . - , , ,: . .. - .
lQ45248
1 characters belong, ~s established in step 37. Reference
is made to Figure 5 for a more detailed disclosure of the
steps in which characters are grouped in levels 1, 2, 4,
5, 7 and 8. Assuming the next character is compared
5 to those of the group to be stored in level 1 at step 40a,
a control level signal represented by a 0 bit is ge~erated
at step 41a, and the character is encoded by three bits
expressed in the number base 8 as found in step 42a, with
the data being stored in the output buffer, step 12. After
10 compaction of a single character, return to the control level is
. automatic and requires no control bits to return operation
` to the control level.
. Compaction at level 2 is identical to that
. I
established for level 1 except a comparison is made at
~ ;s..te.p..40b, and if..the~.character is found to exist in the
-~ group established for level 2, control bits 10 are generated
in step 41b, and the character is then encoded by three bits
~t expressed in the number base 8 as found in step 42b, with
the data being stored in the output buffer 12. After
.j 20 compaction of the character, return to the control level
is automatic and again requires no control bits to return
. the operation to the control level.
The operation is the same for establishing a
~ compaction for levels 4, 5, 7 and 8 in that the control
:~ 25 code is first established and then the character is encoded to the
base 8 code.
.
, - 49 -
'.~
.. .. . ~
10~5,48
1 Returning again to Figures 2 and 6, upon finding
that a character, upon cornparison, does not become encoded
at one of the bases which is less than the fixed base such
^i - as base 256, the character will appear as a level 9 character
` 5 as shown in step 46. Because the character is found to
; exist while in a control level rather than at the level 9!
and further not being co~pactible, control bits 11111111
~ are encoded at a step 50 which permits the character to
`~ be encoded in the fixed base 256 as found in step 11
10 and stored in the output buffer, step 12, in the fixed base code
rather than being compacted.
Lookahead may no~ be explained, i.e. the feature
of the present invention which attempts to assure that the
.. . .
shifting of Levels, as from Table I, would result in an
5 advantageous-resu-l-t on-compaction. --~ - -
In the continuing example, only a very simple form
of lookahead was used, in order to simplify the explanation.
The form used was to enter levels 3 and 6 i~ a single character `
appeared which could be expressed in those levels. Likewise,
20 when in level 9, the test to determine desirability of leaving
level 9 and entering the control level was to read ahead
three characters, and if none of these three would cause a
reentry to level 9, it was desirable to leave level 9.
In some cases it is desirable to use a more complex
25 lookahead technique. This technique uses lookahead to determine
the advisability of entering levels 3 or 6, and also the
advisability of leavin,g level 9. Although this requires some
logic to implement, the overall efficiency of the compactor is
higher if it is used.
:1 :
~ - 50 -
. ~ .
,i :
~045Z48 :~
1 Table II shows the logic required to perform
.
- the more complex lbokahead function relating to entering levels 3
and 6 as well as the lookahead function relating to
leaving level 9 to enter the control level. A comparison
' 5 is made to the total control and character bits required
to enter the control level with the total of the bits required
, .. ..
~ to represent the characters in the noncompacted mode
,, .
, or base 256, and where the number of bits is less to enter
:
the appropriate level, the shift is made to levels 3 or 6.
When in level 9 and the number of control bits to leave
i level 9, including the eight plus the number required to
shift to one of the eight levels, is less than the expression --~
in the base code 256, the control mode is entered.
~j ' .
:i , , -
TABLE II
lS -- Lookahead Logic -
Where:
i Current char = N
~ Prior char in same record = N-l '
'i, Next char in same record = N+l
'1 20 Same char in prior record = M = Mask
;~ - Not required to stay 'in = (~) ; - ;
i~ Lo~ic to enter Level 3 (from control level)
Absolute control level of N
1 2 4 5 7 8 9
i 25 N = M N N Y Y Y Y Y
(N = M) and (N+l - M+L); Y Y Y Y Y - Y Y
` Logic to~enter Level 6 (from control leveL) ' '' ' '' ''~ '
Absolute control level of N
1 2 4 5 7 8 9
~j 30 N = N-l N N N N Y Y Y
(N = N-l) and (N = N+l) N Y Y Y Y Y Y
(N = N-l) and (M = N~l) Y Y Y Y Y Y Y
and (N-= N+2)
Logic to leave Level 9 (to enter control level) ~ -
~ Absolute control level of N
Not req'd to stay in 1 2 3 4 5 6 7 8
`,d,N ~ Level 9 N N N N N N N N
+ N+l ~ Level 9 N N Y N N N N N
~ N+2 ~ Level 9 N N Y N N Y N N
40 + N+3 ~ Level 9 Y Y Y N N Y N N
+ N+4 ~ Level 9 Y Y Y Y Y Y N N
N+5 ~ Level 9 Y Y Y Y Y Y Y Y
; . .
51
~.
.;
.: - . _.
. .
1045Z48
.
1 ` Within T~ble II, the letter "N" under a numerical
column represents the decision "NO". Similarly, within
Table II, the letter "Y" under a numerical column
represents the decision "yes". Outside of the Table
`~1 5 and numerical columns, "N" is defined as the current character.
i ~ As an example of the complex lookahead function as set forth~
by Table II, the effect on the continuing example will now be
considered assuming the complex lookahead had been used.
i With respect to the initial entry of record 1,
,.,
10 the entry was in level 9 as explained above. Since this
first character, nL", would normally have been treated as a
level 5 character, by Table I, the complex lookahead logic
will be controlled by the logic of the Table II under the heading
"Logïc to leave level 9". Under "Absolute control level of N",
15 the column 5, and following down the column until the first Y is
encountered, the minimum condition which makes it desirable to ~
leave level 9 is found, i.e. that N, N+l, N+2, N+3, and N+4 must - ~ -
all be nonlevel 9 characters. Although this is a more stringent
requirement than the simple lookahead used in the continuing
20 example, the result would have been the same and the system
would leave level 9, as in the continuing example.
~ The only part of the continuing example which would !-,
i~ have changed had the complex lookahead been used would have
been the second character "T" in record 3. Using the simple
25 lookahead, this character was encoded as a single level 6
character, which was then expressed as 111110101. If the
complex lookahead had been used, the logic would have controlled,
according to Table II, and particularly under the heading
"Logic to enter level 6". Since the character "T" is a level 2
character according to Table I, the logic according to column fo~
"Absolute control level of N" equal to 2 would control. The first
condition, i.e. of the character being equal to the prior character,
; - 52
,~,. ~: - .... . .
... .. . . ..
-
1045248
l is met, but that is,not sufficient to enter level 6 according
to the complex lookahead. A second condition, as seen from
,
` Table II that the following character "D" also be equal to
the prior character "T", is not met, and level 6 is not entered,
5 the character "T" is coded as a level 2 character of 10111. This
` encoding would then be four bits shorter than the bit string
provided using the simple lookahead. The rest of the example
would have remained as illustrated.
; It is then assumed that the foregoing detailed
~, 10 explanation and example of compaction according to the
~ present invention has been read, followed, and understood.
;3 Based upon this detailed explanation and example
.~' of compaction according to the present invention, decompaction
according to the present invention can now be explained.
15 Since, as can now be explained, decompaction is the inverse
of compaction, the following explanation of decompaction will
y place reliance upon the previous detailed explanation and
example of compaction and thus attempt to avoid unnecessary
repetition of mere detail. For clarity, the continuing
20 example compacted above will be decompacted according to the
present invention.
3 As shown and described with respect to Figure 1,
a compaction device is located on the receiving end of the
transmission line E. Each compaction device contains both
25 a compaction and a decompaction section. Only one of these
sections is used at a given time and which is used depends on the
, direction of the data transmission at that time. The receiving
or decompaction section of the compactor is actually much
simpler than the transmitting or compaction section of the
compactor. That is, the transmitting section of the compac.or,
- 53 -
.. . . . .
. . ~ ;
i 11)45248
, . ~
1 of necessity, requires decisions as to what compacted code
is to be generated, and how, while the receiving section of
the compactor has a much simpler job, and all that is required
of the receiving section of the compactor is to decompact the
5 code received in a mechanical fashion. The receiving section
, of the compactor has no choices to make in the matter of what
~i compaction level is used or what coding is used. Also, because
;,! the decompaction section of the compactor performs operations
,`~! which are merely inverse of the operations on the data performed
0 by the transmitting section of the compactor, no separate block
~1 diagram has been provided for the decompaction section of the
compactor, as Figure 2 with only minor explanatory adjustments,
.~ . .
also represents decompaction according to the present invention. -
Referring again to Figure 2, the decompaction ~ -~
15 section of the compactor brings in the next character at step 10
just as explained above with respect to the compaction section
of the compactor. The character brought in is in whatever data
base is conventionally used by the system, assumed for the sake
of the continuing example to be in base 256 and include eight -
20 bits. Again, this decompaction section of the system assumes
an initial entry currently in level 9, step lOa.
~, With succeeding characters, as will be explained
further hereinafter, the steps of Figure 2 are traversed -
in an identical manner to that set forth with respect to
25 compaction; however, the procedure is inverse to that of
1, compaction. That is, if the character is not in level 9,
step 17 is used to recognize the control bits 110 indicating
that the character is the same as the corresponding character
in the prior record~ If such a condition is found to exist,
._ _ ,. .~
~ :
- 54 -
. ~'
`` -
1()45248
1 the system proceeds) to step 22, but inversely. That is, the
system recognizes the number of 0 bits, which indicate the number
~ of repetitive characters, as discussed in detail above, and
;~ the system will store this information until step 23 is
~,
5 reached and the system recognizes the 1 control bit which
separates the base 1/16 data from the base 2 data. In a
similar fashion, the system stores the number of characters
. :'
~i represented by the zeros in base 2, and finally recognizes
the single 1 control bit which terminates the level 3
10 compaction, as represented by steps 17, 20, 22, 23, 25, and
26.
At this time, the system, from the prior record
mask, is aware of the position in the prior record of the
characters corresponding to the characters currently transmitted,
15 the number of characters in the prior record corresponding to
the data currently transmitted, and stores this information
in memory, step 12, and likewise transmits the data, except
.~ .
in the case of decompaction, instead of transmitting the
s data onto a transmission line, it is transmitted to whatever
. . .
20 apparatus it is desirous of receiving the data or to the
line controller interface at the receive end of the transmission
~ line.
Y Again, assuming operation not in level 9, steps 12a,
15, and 16 are traversed and the system returns to step 10.
25 Again, the only difference between compaction and decompaction
'!~ at this stage is that each time a new character is brought
in, step 10, it is brought in from the communications line,
.~
~ - 55 -
,~L
" .
.
.'. ,.
.,, ....... '
'"~-' ' ~ .-
:` ~
,X
SZ48
"'! 1 in the case of decompaction, and each time data is transmitted
: out, in the case of decompaction, it .is transmitted via the
.~,;
; controller side FIFO and then to the line controller, as seen
`.i in Figures 7 and 1. The inverse operation of decompaction .
5 according to the present invention can now be recognized.
In a similar manner, if step 17 is traversed and
`Y the system finds that, in step 27, the character currently : `
i~ operated upon is the same as a prior character in the current --
~ record, the compacted data is decompacted via steps 27, 3p, ~ :
, 10 32, 33, 35 and 36 in an exactly analogous manner to that set
forth above with respect to step 17, 20, 22, 23, 25, and 26. :
The system then again returns to step 10 via steps 12, 12a,
15, and 16.
Similarly, if steps 17 and 27 are traversed and ~;
15 the system finds that a character currently operated upon _ -
is in a level 1, 2, 4, 5, 7, or 8, as by step 37 and Table I,
the data is decompacted by first recognizing the control code,
~ as will be explained further hereinafter, and decoding the ~ :~
:^ data base stored in memory to find the corresponding eight
; 20 bit, base 256, full data representation corresponding to
the compacted data base received, in a manner inverse to that
~; explained previously with respect to Figures 2 and 5.
~7 Similarly, if steps 17 and 27 and 37 are traversed
$ ana the system finds no control code match, the only possible
:~125 control code left is level 9 entr~ code, 11111111, as recognized
::.in steps 46 and 50. The data is then decompacted by deleting
, : :
~. .
.~
: 56
, . i ,..... . .. .. __ ~.,
.",.;
` ~045248
1 the entry code, st~p 50, and recognizing the level 9 data,
` step 11. Step 12 then follows, but step 12a is omitted as .
` unnecessary in the decompact mode since the decompaction,
: . as discussed above, has no decisional responsibilities.
5 The system then traverses steps 15, 16, 10 and returns to
.
:.! step lOa.
;:~ When the current level 9 condition exists,-however,
step 13 follows step lOa, rather than step 11. If the character
being operated upon is not an exit code, then step 11 follows
., 10 step 13. If, however, it is discovered in step 13 that the
character currently operated upon is a level 9 exit code,
11111111, the decompaction portion o~ the system and apparatus
.. j according to the present invention next proceeds to step 14,
wheré this exit code is deleted, and returns to step 10, where the
15 control.code search.begins again. . . . ~ : ~
.~ Thus, with respect to a situation where the system :~ :
.~ is in level 9, the system traverses steps 10, lOa, and 13. If an
exit code is found, the system next traverses step 14 and returns
to step 10. If no exit code is found, the system next tra~erses
20 steps 11, 12, 15, 16 and returns to step 10.
' Thus, in steps 17, 27, 37, and 46, the control
. bits representing these levels of control are recognized,
~ since these control bits are nonambiguous, and there is
:~ no possible way that these control bits may be misrepresented.
_ 57 _ ~ ~:
.
:....................................................................... :
:` lV~5Z9~8
1 Returnin~ to the continuing example compacted
hereinbefore, the decompaction compactor begins, as set out
immediately above, just as the compaction compactor, in level 9
or a noncompacted level. The first character received from
5 the communication line is a 11010011. Since this character
is in level 9, it traverses steps 10, lOa, 13, and 11, and is
stored and provided to the output at step 12 exactly as it exists
j~ since the above code is a noncompacted representation of the
letter "L". The system then traverses steps 15, 16, and
10 returns to step 10 where the next character, eight bits, is
received. This next character is 11111111 which is a representa-
~-~ tion of a level 9 exit code. The system then recognizes this
level 9 exit code in step 13, deletes it in step 14, and returns
~ to step 10 where the system returns to control level.
;~, 15 Now that the system is in a control level, upon
bringing in the next character, the system has no advance
~;~` manner of predicting how long this character may be. Therefore,
the system begins receiving the incoming data one bit at a time
until the first 0 bit is encountered. The number of bits which
20 the system has read, including the 0 bit, defines the level
of the character to follow. In any case, the character
. ~ .
following is then expressed via the next three data bits.
Thus, it can now be seen and appreciated that the control
bits are nonambiguous and there is no possible manner in
25 which they may be misinterpreted.
. . .
,1
- 58 - '
. j .
~, .
-
.,. ~.
. ~_
.. ~ . . . . ~ .
; . . . . .. . . ..
.
1045Z~8
1 Thus, the first control code after the level 9
exit code rcceived from the first record, as compacted above,,,;1 .
.', is 1110, which describes the character as a level 4 character.
The system would then traverse steps 10, lOa, 17, 27, and 37
5 of Figure 2 and steps 40a, 40b, 40c, 41c, and 42c of Figure 5,
but in an inverse fashion. That is, once the chara~ter has
~ .
been recognized as a level 4 character, the three bits following
the control code æe 100, which step 42c recognizes as the
.. fifth character on that level, which may be seen from Table I
10 to be the letter "I".
At this point the system brings in the next bit string
~'! in the manner hereinbefore described. This bit string, from the :~
continuing example set out above, includes the bits 1110, defining
3~ level 4, and the three following bits, 111, define the eighth
5L--ur-ct.er in level 4~ which is the letter "N".
The next bit string received from the line includes
the initial bits 10 which define level 2. These control bits
are followed by bits 011 which define the fourth character in
level 2, which is the letter "E".
me next bit string received begins with a 0, which
defines level 1, and is followed by the three bit code 011,
which defines the fourth character in level 1, or a blank.
The next bit string received from the line begins with
a 0 which, again, defines level 1, and this bit is followed
;~ 25 by the three bit bit strings 000 which defines the first character
' in level 1, or a 0.
~3
- 59
j ................................................................ . ~ '
.
7~ . . .
- . . . ~ . ~.. . .. . .
: 11)4524~3
1 The next bit string received from the line again
starts with the 0, which indica~es level 1, and is followed by
the bit string 010 which indicates the third character in
level 1, which is the number "1".
The next bit string received from the line in the
~1 continuing example is a n, which again indicates level l,
and is followed by the three bit bit string 011, which indicates
the fourth character in level 1, which is a blank.
The next bit string received from the line includes
^ 10 the bits 11111110, which indicates level 8, and this bit
.
string is followed by the three bit bit string 001 which indicates
.
~ the second character in level 8, which is an equals sign.
-~ The next bit received from the line is a 0 which,
again, indicates level 1. This 0 control code is followed by
~ _~ 15~t_e2_three bit bit string 011, which again, from Table I, indicates
,~"^J. a blank.
The next bit string received from the line in the
-- continuing example is 1111110, which indicates level 7, and
is followed by the three bit bit string 110, which indicates
20 an open parenthesis.
. ^ . .
1~ The next bit string received from the line includes
~` the bits 11110, which indicate level 5, and is followed
by the three bit bit string 001, which indicates the letter "B".
The next bit string received from the line includes
25 the bits 1111110, which indicate the level 7, and this is
~ followed by the three bit bit string 111, which indicate a
`'r close parenthesis.
. .
, - 60 -
.,
" .
. ~, .
, 1
-- -- --
::
,
` lO~SZ48
1 As Can nQW be seen, decompaction according to the
present invention has now taken place for the entire first
record of the continuing example set forth above, and this
decompaction has been performed with no ambiguities and no
`, 5 problems in completely restructuring the original data from
the compacted code sent across communication line E of
Figure 1. Again, as explained above with respect to compaction,
after decompaction has taken place, each character of this
record was sent to the controller side FIFO 66 as it was decompacted
10 for transmission to the controller side converter 56 in a normal
eight bit noncompacted mode. This can be seen with reference
~ to Figures 1 and 7. Also, via the storage of record 1, as
`''!' in step 12, a prior record mask has been created for use in
following records.
~`~ 15 Next, examining record 2 of the continuing example
.~ , ,. ,, . ~ . , . , . , , , . .. ,. , . ,, ~ .............. . as compacted above, and continuing in the control level since
a level 9 character has not occurred, the bit string for the
first character received is 110, which indicates level 3.
~`~ The next bit received is a 0 which indicates that four characters
20 are included in record 2 and are the same as the similarly
positioned four characters taken from the mask created by the
~ prior record. The next bit received is a 1 which indicates that
'~! this condition no longer exits, i.e. that the next four characters
in record 2 are not the same as in the prior record. To this ~ `
25 point, the level 3 decompaction logic has operated in a base
1/16, and with the receipt of the 1 indicated above, the system
shifts into number base 2
i. .
~ 61 -
.
, ! .
~, . ' . . , ' ' ~ '
" '' , . . ` '.' ','. :
,' ' ' : .' '
,'-,' "'' ' ~' ' ~'`
: ~ lU45Z48
1 The next bit received is a 0 which indicates that
one character is the same as the similarly positioned
~! character in the prior record. The next character received
is also a 0, which similarly indicates that an additional
5 character of record 2 is identical and the same as the
similarly positioned character in record l.
The next bit received is a l which indicates the
j completion of the string in base 2 and that a total of six
characters of record 2 are identical to similarly positioned
lO characters in the prior record, record l.
As each bit of the above bit string in level 3 and
level 2 have been received and decoded, the appropriate
characters which are represented by this string, as indicated
above, are extracted from the data memory 94, as shown in
` 15 Figure 7, where the conventional eight bit code for the
characters was stored as received from the previous record,
record 1. These decoded, decompacted, conventionally
represented eight bit characters are then sent to controller
side converter.56 for provision to line controller B of Figure l.
Keeping in mind that the system is yet in the control
level, the next bit received is a 0 which indicates a level l
character, and the next three incoming bits of 001 indicate that
this character is the number "2".
The next bit string received is llO, indicating
25 level 3, followed by a single 0 bit indicating that four
. characters are the same as in the prior record. The succeeding
bit is a l, terminating the base l/16 data, followed by another
.
' - 62 -
~,
,
, . ~
10~5Z48
1 1 indicating immediate termination of the base 2 data. Thus,
a total of four characters o~ record 2 are indicated as
~ identical or the same in as similarly positioned characters
.. of the prior record, record 1.
. 5 The next bit string received is 1110, indicating
level 4, followed by 010, indicating the letter "D".
~ The next bit string received is 111110, indicating
: level 6. This bit string is received and interpreted as a
level 6 control code, whereupon the system enters the base 1/8
.ii 10 decompaction logic.
In base 1/8, the next bit entering the system is
~ a 0, which indicates that three characters of the current - :
.-~ record 2 are the same as the prior character, and the compaction .
:1 logic extracts this prior character from memory in a conventional .
:q 15~eight bi.t.. encoding,.. and. tr.ansmits this character to-controller
,
~¦ side converter 56, three times.
The next bit received is a 0, which indicates that
three additional characters are the same as the last four
:~ characters received, and the decompaction logic again transmits .~
. 20 the last character received to controller side converter 56 ~ ;
:~ in conventional eight bit format, three times, as indicated above. 1
. me next bit received is a 1, which terminates the
base 1/8 control and causes the decompaction logic to shift ~:
into base 2, as explained hereinbefore with respect to compaction.
`. 25
'.
.. ...
~ - 63 - ~.
~ r
,,, . _ . .
~'1 ..
.
.",
_
:,:~,.. ' . ' . : : . '
. . .
1~45Z48
. . .
The next ~it received is a 0 ~hich indicates that
one additional character of the current record is the same
- as the prior character received, and again the system and
apparatus according to Figure 7 provides the conventionally
~; 5 encoded prior character to controller side converter 56.
The next bit received is again a 0, which indicates
i that an additional character of record 2 is the same as the
prior character.
The next bit received is a 1, thus terminating the
10 base 2 representation and the control in level 6. Thus, the
decompaction according to the present invention has indicated
that eight characters were the same as the prior character
received.
e next bit string received from the line is 1111110,
15 indicating a level 7 character, followed by the bit string 111, __
~ which indicates a closed parenthesis.
i~ At this point, record 2 has been completely received,
decompacted, and transmitted to controller side converter 56.
Also, the system, as explained hereinbefore, has generated and
20 stored the record mask for record 2.
Continuing with decompaction according to the present
invention and treating record 3, and again noting that the
compaction system according to the present invention is yet
in the control level, the first bit string received is 11001001
25 which indicates, according to level 3, that six characters
exist in record 3 which are identical or the same as six
characters identically positioned in the prior record, record 2.
.
.. ...
- 64 -
l
.
:. - - . ,. ,
;
. .
; . .
-
; :
16)45248
1 The next ~it string received is 0111, which
,~ indicates level 1 and the number "3", in the manner herein-
before described.
The next bit string received is 110011, which
~',
:. 5 indicates that four characters exist in record 3 which
are identical or the same as four similarly positioned
characters in record 2, in the manner previously explained.
l The next bit string received is 1111110100, which
,~, indicates level 7 and the letter "Y".
j 10 The next bit string received is lllllQ1001, which
' indicates that two additional characters exist in record 3
which are identical or the same as the preceding character
:
of record 3, with the control of the system in level 6.
The next bit string received is 11010001, which
15 indicates three characters of record 3 are identical or :
the same as three similarly positioned characters in the
prior record received, record 2, with the control in level ~ :
. 3. ,
e next bit string received is 10111, which
20 according to level 2, is the letter "T".
The next bit string received is 111110101, which
according to level 6, indicates one character identical with
a prior character.
.~
., 25 - 65 -
.; .
.~
, r
, .
'~
I ' ` `:
- - "
:`
1'~)45Z48
1 The next~bit string received is 1101001 which
indicates two characters of the current record 3 are identical
or the same as two characters identically positioned in the
prior record 2, with the control in level 3. As explained :
5 hereinbefore, the characters are then extracted from memory
and transmitted, and this completes record 3. - ~:
....
., Decomp~cting reccrd 4 and again noting that the
system according to the present invention is yet in the
.
control level, the first bit string received is 11001001,
, 10 which indicates, according to level 3, that six characters
:, of the fourth record are identical or the same as six
.~' characters in a corresponding position in the previous
~: record 3.
~: me next bit string received is 10010 which,
=c~5~ ccor~ing t.o.~level.~2.,..is.*he number ~4n.
;, The next bit string received is 110011 which,
according to level 3, indicates that four characters are
again identical in the current record 4 to identically
position characters in the prior record 3.
; 20 The next bit string received is 11111111, which . .~.
.~ is a level 9 entry code. This level 9 entry code is not
1 stored and transmitted, according to the previous explanation,
~i but rather is used by the compactor according to the present
~~ invention to force the decompaction side to enter level 9 ;~
.. 25 deCompaction-
The next bit string received is taken in an eight
; bit grouping rather than bit by bit since the system is now
~ in level 9. This next eight bit grouping is 01011110, which
is the noncompacted code for a semicolon.
, - 66 -
,~ . .
., ~ , .
-
` lQ45Z48
1 The next eight bit grouping is 01111010, which is
not a level 9 exit code, and thus is transmitted as a noncompacted
code for a colon.
The next eight bit grouping is 01111011, which again is
5 not a level 9 exit code, and thus is transmitted as a noncompacted
code for the number sign.
The next eight bit grouping is 01101111, which again is
not a level 9 exit code, and thus is transmitted as a noncompacted
` code for a question mark.
` 10 The next eight bit grouping is 01011101, which again is
not a level 9 exit code, and thus is transmitted as a noncompacted
`1 code for a closed parenthesis. Note that although the closed ~-
parenthesis is not normally a level 9 character, since it has
been assigned to level 7, it was transmitted in level 9 and
15 it is also received in level 9. The receiving compactor has
i no way of knowing what the true level of this character is
because it was forced into level 9 and has not been released
from level 9.
The next eight bit grouping received is 11111111
20 and this is a level 9 exit command, which the compactor does
not send to the controller side converter 56 but uses in
:i . .
a control fashion to return to the control level. At this
point, record 4 has been completed.
Thus, the complete compaction and decompaction of
25 four records has been shown in detail as an illustrative
embodiment of operation according to the present invention.
With this explanation and operation in mind, an explanation
of an alternate method and apparatus according to the present
,- invention may be explained.
I
, - 67 -
.
r
; lU~5~48
,
;~ 1 It has b~en found that the maximum effectiveness
of compaction according to the present invention is related
`~ to minimum width of data which may be conveniently handled
by the compactor according to the present invention. ~or
5 explanation and description thus far, it has been assumed
that the compactor hardware was capable of handlins thé
co~pacted data on a bit by bit basis, and thus a minimum data
width basis. This approach generally yields the maximum compaction
. :
possible, as it allows the compactor to ma.ch the probability
--~ 10 of occurrence quite closely with the length in bits of compacted
,; ~ .
~ data generated.
:'
However, to compact and decompact data on a one bit
minimum data slice or width basis does require substantial speed
in t~e hardware of the compactor. It thus may be desirable to
~ ~utilize a~ deqraded technique for compaction according
-~ to the present invention, as by utilizing a minimum data slice
or width of either two bits or four bits. It has been found
that use of such an increased slice or data width will generally
reduce the ratio of compaction somewhat, but this technique will
20 also reduce the necessary hardware speed and cost by a much larger
:' . .
`, amount. Conversely, use of an increased data slice or data
r'~ width according to the present invention will allow any given set
of compactor hardware to run at a much higher line and interface,~
speed.
` 25 After considerable study and effort, it has been found
;~
that the hardware configuration, as shown and described in
relation to Figures 15-26 and setting forth the preferred embodi-
J ment of a compactor according to the present invention is
j
currently the most practical for a mass produced product.
:" . . ,
~,i
- 68 -
. ~ :
: .
~045Z48
It has also been determined that this hardware according to
1 the present invention will support a communications line speed
- of 2400 bits per second (bps) if a single bit minimum slice is
used, as described above. It has further been found that, by
using a minimum bit slice of two bits, the compactor, as
described above and as will be described, will support a com-
munications line speed of 4800 bps with only a ~ loss in
~ compaction efficiency. It has still further been found that by
Yt using a minimum bit slice of four bits the same compactor ;~
10 described will support a line speed of 9600 bps with an average
:
loss of only 17~ in compaction efficiency. ~-
t~ Therefore, demand for higher line speeds in communica-
~ tions oriented application has dictated using a four bit minimum
:, data slice at present rather than the originally described one -~
-~ bit minimum data slice. This change to a four bit data slice
. ~
only affects the internally generated bit strings described in
detail above and the method and apparatus described above are
~, . . . .
in no way altered. Therefore, in order to illustrate that this
~i~ change to a four bit-minimum data slice affects only the com-
t~ 20 pacted bit strings produced but does not affect the basic
apparatus or techniques according to the present invention, as
described, the same continuing example of four records will again
be explained in detail using a four bit minimum data slice.
The first alteration, to reflect use of four bits
~, instead of one bit, is to Table I.~ Table I must then be re-
:~ defined to reflect the fact that certain number bases cannot be
~i used and that certain definitions, utilizing only one bit, are
no longer possible. That is, using a four bit minimum data
slice of necessity reduces the total number of numbers available
30 by a substantial amount. Normally the only number bases
.
~ 69
1045Z~B
available would be base 16 (4 bits) and base 256 (8 bits)~
However a number bases 0 has been defined, to represent the
condition where no bits of data are present. This may be used
only where a level contains only one character or situation
and needs no further definition. This level could have been
used with the one bit slice but was not needed. Likewise for
levels 3 and 6, since a minimum of 4 bits must be read, they
may then represent from 1 to 16 characters.
` The result of the above is that while fewer number
~ 10 bases are used, more control levels are needed to maintain
compaction efficiency. This may readily be seen in the follow-
ing Table III, which is Table I redefined for a preferred
four bit data slice approach. Similarly the block flow diagram
. for the four bit minimum data slice is shown in Figure 8, which ~-
;
` similarly is Figure 2 redefined for a preferred four bit data
slice approach.
i
~:
! jl
~ 20
''.
.
!
.. ..
, ~
- 70 -
~,. . .
' . ` - : ~ -
1045~48
TABLE III
Control Level Codes Characters
_
0000 Shift to level 1 0
0001 " 2 2
0010 " 3 characters identical to prior
record
- 0011 " 4
0100 " 5 (blank)
0101 " 6 characters identical to prior
~, characters
0110 " 7 5
' 0111 " 8
1000 " 9 7
1001 " 10 3
1010 " 11 8
1011 " 12 6
10 1100 " 13 4
- 1101 " 14 E9A-TRCDSI~ZI,NPBF
~ 1110 " 15 GMKLUHV*/Y&()J=X
- 1111 " 16 No Compaction Mode
i Level 3 Codes (base 16)
- NNNN This four bit code represents the number of characters
identical to corresponding characters in the prior
record. Value may be from l to 16 where the number of
~, characters is equal to NNNN+l.
Level 6 Codes (base 16)
NNNN This four bit code represents the number of characters
-;~ identical to the prior character. Value may be from
~ 1 to 16 where the number of characters is equal to
',A' NNNN+l.
20 Level 1, 2, 4, 5, 7, 8, 9, 10, 11, 12, 13 Codes (baseO)
These levels have no data bits as each level contains
only one character and that is inherent in the level.
:,
~ Level 14, 15 Codes (base 16)
i`
NNNN This four bit code is a base 16 character to represent ~ ~
, 1 of 16 characters in the level. ~-
-~ Level 16 Codes
NNNNNNNN This eight bit code is a base 256 character to represent
1 of 256 characters in the level.
~, 11111111 One specific base 256 character designated for shift
to control level.
.~
:, :
~ .
.~.
- 71 -
~ ~ .
, ;. . . .. : , .
- ~ ,,. :-
.: .
~0~5i~8
Applying this Table III and the four bit data slice
to the four records set out above, it can be seen that the same
method and apparatus apply.
For convenience, the four records to be used as examples
are again set out below:
LINE 01 = (B)
LINE 02 = (DDDDDDDDD)
LINE 03 = (YYYDDDTTD)
Y LINE 04 = (;:#?)
10 Turning to the example, data is in FIFO 66, and as soon as the
first entire eight bit character has been shifted through the
FIFO 66 and is available via data connection 68 at the eight bit
output shift register 70, coder 88 will access this character and
begin to operate the compacting logic which is stored in the ~ ;
instruction memory or the micro code 92. In the case of the above
set out example, the first character to be brought in is an "L"
from the word "LINE". As can be seen from Table III, "L" is a
member of level 15 compaction logic. Therefore with reference
to Figure 8, the mechanism and process of compaction, according
20 to the present invention, is to bring in the next character,
step 10, and then to check to see if the character brought in is
an initial entry, step lOa. Since, in the example set out, the
letter "L" is an initial entry, the mechanism and process,
' according to the present invention, then proceeds to set up this
~ character without compaction, step 11, and to transmit the data
,~J, bits to modem side FIFO, step 12. For this example, it is ;
assumed that the logical representation of the letter "L" is
; 11010011 in a conventional base 256 system.
Specifically with respect to Figure 7, it can be seen
30 that coder 88 transmits the eight bits~representing the letter
.
"L", by grouping them in groups of four bits and transmitting
them via data connection 86 into the four bit shift register 100
. ~
~ - 72 -
.. . . . ..
.,: ........ , , ~
'
10~5248 ~ ~
on the modem side FIFO stack 102. As each four bits is pro*ided
to the FIFO 102 via data connection 98 from the input shift
register 100, it assumes a data position at the bottom of modem
side FIFO stack 102 where it is then shifted via data connection
104 into the four bit output shift register 106. As each clock
signal comes in from the modem clock line 118, through converter
114, and via connection 108, one bit at a time is shifted out
of register 106 and onto the transmit data line 110. As each
four bits of the data is provided to the data line 110, the next
four bits, which are waiting in the modem side FIFO stack 102,
are then shifted into the four bit shift register 106.
Similarly, and again with respect to Figure 7, as the
,: ~
data is provided by a data connection 86 to the four bit shift
register 100, it is simultaneously provided to memory 90 to be
stored in data memory 94 in the location equivalent to its dis-
tance from the start of the record. At the end of the record,
the entire record is saved to provide a comparison mask for the
next record, as has been explained hereinbefore. This storage
., ,i :
of each character of the record also allows a comparison mask
for the next characters, as has also been described hereinbefore.
Returning again to Figure 8, the compaction according -
~ to the present invention now continues by checking if the system
`~ is currently in level 16 and if it is desirable to leave level
`~ 16. Since the system is in level 16 in the example started above
`` and because level 16 is an uncompacted level, the next compaction
j step is to see if it is desirable to leave level 16, step 13. ~
Since the data character currently being operated upon, i.e. "L", ~;
is not a level 16 character, but a level 15 character according
` to Table III and the next three characters "INE" are also not ;-
level 16 characters according to Table III, it is desirable to
leave level 16, and the logic then sets up the eight bit exit
, control code 11111111, step 14. This eight bit exit control code ~ -
- 73 - ~ -
1045248
allows the system to leave level 16 and enter the control level
of the appropriate compaction logic, for the next character.
The system then proceeds through steps 12 and 12a.
At step 12a, since the control bits have been set to leave level
16, the storage is not currently in level 16, and progress is
made to step 15. At step 15 the system checks to see if the
current record is complete. Since it is not complete, as only
the first letter has been entered, the system stores the
character just processed, "L" into data memory 90 and proceeds
` 10 back to step 10, to bring in the next character.
~ As indicated in step 10, the compacter then accesses
;~ the next data character, seen from the example given to be the
letter "I" from the word "LINE". This letter is then in the form ~--
; of an eight bit logic output from register 70. The system then
again checks to see if this letter "I" is an initial entry or
if the system is currently in level 16, step lOa. Since the
system has progressed out of level 16, the answer is no, and
the system progresses to step 17 of Figure 8. Since the letter
"I" the character currently operated upon, is not the same as
the corresponding character in a prior record, since it is
assumed that there is no prior record, and the system progresses
:,, .
, to step 27. Since the letter "I" in the example given is not the
.,. :
same as the previous letter operated upon, the letter "L", the
system progresses to step 37.
The letter "I" is indicated by Table III as a level
14 character, so the system progresses to step 40 where necessary
`;
control bits are set up, specifically a four bit sequence con- ;
sisting of 1101. The compaction logic then proceeds to step 42 ~ -
~, where the base 16 data is set up. In this case, for the
30 letter "I", the base 8 data 1001, the binary code indicating
that the letter "I" is the tenth position in the level 14 table.
; The system then continues through the process of transmitting
- 74 -
1045;~48
the character, of storing the character in the data memory, and
` to preparing to bring in the next character, steps 12a, 12, 15,
s and back to 10.
Compaction level 14 requires four control bits to reach
and four bits to express the character, because the expression
is in number base 16. The compaction of a single character
then produces a bit string llOlNNNN where the 1101 form the
control bits and the NNNN are the four bits to identify one of
the possible sixteen characters in level 14. From Table III,
10 the characters represented by level 14 are:
E9A-TRCDSI0,NPBF
Returning again to the continuing example, the next
character brought in is the letter "N" from the "LINE", which
also has been assigned by the preferred embodiment of the com-
paction system and apparatus of the present invention to level 14.
This character also traverses step 10, lOa, 17, and 27, and is
, operated upon in step 37 in a manner explained previously.
Therefore, the same control logic produces the same set of control
bits. However, this time the sixteen bit data portion is now
20 1100 to indicate that the letter "N" is in the thirteenth posi-
tion in the level 14 table.
The system then repeats progress through steps 12,
12a, and 15, and back to step 10, as previously explained.
To this point, the output from the compaction since
the compactor was entered and including the level 16 character ~-
and the level 16 exit control, and for the exemplary data entered, - -
i.e. "LIN", is:
11010011 11111111 11011001 11011100
L 16 exit I N
The above presentation has been spaced for illustrative
30 and explanatory purposes only. It will be recognized that spaces
do not appear during actual transmission. Likewise, the
- 75 -
"........ . ............. . , . . , . , ~.
. . . . ~ . .. .
lO~SZ48
characters represented by the binary bit string, and appearing
below the bit string, are set out for purposes of explanation
and illustration only.
Continuing with the example, the next-data character
brought into the controller is the letter "E", the last letter
. from the word "LINE". This character also traverses step 10,
lOa, 17, and 27, and is operated upon in step 37 in a manner
explained previously. The "E" is assigned to level 14, by the
preferred embodiment of the compaction technique and apparatus
found in Table III, and therefore a four bit control code of
1101 is set up and this four bit control string is followed by
a four bit data string of 0000 indicating that the letter "E" is
i~, .
- the first entry in the table.
The system then repeats progress through steps 12, 12a,
.~ ,
and 15, and back to step 10, as previously explained.
At this point the total output according to the com-
paction of the data "LINE" from the compaction according to the `~
present invention is:
, 11010011 11111111 11011001 11011100 11010000 :'~
L 16 exit I N E
The above presentation has been spaced for illustrative
and explanatory purposes only. It will be recognized that spaces
.j,
; do not appear during actual transmission. Likewise, the characters
~, represented by the binary bit string, and appearing below the
bit string, are set out for purposes of explanation and illustra-
tion only.
I The next data character brought into the system is a
;i blank, between the word "LINE" and the remaining data. This
character also traverses step 10, lOa, 17, and 27, and is
operated upon in step 37 in a manner explained previously. The
` blank is found in level 5, of Table III, and therefore produces
a four bit control code of 0100 which is not followed by any data
.''
- 76 -
.~",., ~ '
's;'. ~ ~. : . -
.; ~ . ~ . .
., ,
~, ,
`~ ~045248
bits as it is the only pGSition in level 5 of Table III.
Compaction in level 5 requires four control bits to
reach. No bits are used to express the data as the blank is the
only character contained in level 5. Therefore the compaction
of a blank produces a hit string 0100.
The system then repeats progress through steps 12, 12a,
:~,
and 15, and back to step 10, as previously explained.
The next exemplary character brought in by the coder
88 is a "0". This character also traverses step 10, lOa, 17, and
27, and is operated upon in step 37 in a manner explained pre~
.. ~ ':: " '
!` viously. Since the "0" is found in level 1, as discussed above,
~`~ the operation is similar to that of the preceding character with ~ ;~
the exception that the four control bits are 0000 to indicate the
only level 1 character, which is the "0". --
~ :.
~ The system then repeats progress through steps 12, 12a,
`~ and 15, and back to step 10, as previously explained.
The next data character brought in in the example is
"l", and again the operation is similr to that previously explained
since the "1" is found in level 4. The only difference is in the
20 four control bits 0011 which indicate the single level 4 character,
;~i which is 1.
: ,: '
The next exemplary character brought in by the coder ~ ~-
88 is a "blank". This character also traverses step 10, lOa,
-: .
~ 17, and 27, and is operated upon in step 37 in a manner explained ~ -
-. . ~, - :
previously. The "blank", in the manner explained above, produces
a compacted code of 0100.
~ At this point, the total output from the compaction -
y according to the present invention for the portion of the example
assumed compacted thus far, i.e. "LINE 01" is
11010011 11111111 11011001 11011100 11010000
, L 16 exit I N E
`~ 0100 0000 0011 0100
blank 0 1 blank
- 77 -
,~
,,.~ . . ~. . ,
~, ., . . . :
10~5248
The above presentation has been spaced for illustrative
and explanatory purposes only. It will be recognized that spaces
do not appear during actual transmission. Likewise, the charac-
ters represented by the binary bit string, and appearing below
the bit string, are set out for purposes of explanation and
illustration only.
The next data character brought in according to the
example set forth above is an equals sign. This character also
traverses step 10, lOa, 17, and 27, and is operated upon in step
37 in a manner explained previously. The equals sign is found in
level 15, and therefore produces four bits of control code logic
~ 1110, followed by four bits of data 1110, to indicate that the
:l; equals sign occupies the fifteenth position of level 15.
Compaction in level 15 is identical in operation to
compaction in level 14, except for the characters represented.
The compaction of a single character produces a bit string
~ lllONNNN where the 1110 are the control bits and the NNNN are the
-; four bits to identify one of the sixteen possible characters in
this group in the number base 16. The sixteen characters repre-
sented by level 15 according to the preferred embodiment of the
; present invention are:
GMKLUHV*/Y&()J=X
` The next exemplary character brought in by controller
^~ 88 is also a blank, and the compaction logic produces an output
of 0100 in the identical manner to the previous blank discussed.
The next character brought in by control logic 88 is
an open parenthesis and this character has been assigned to level
15 by the preferred embodiment according to the present invention.
Thus, the open parenthesis character from the example
produces a four bit control code of 1110 and a four bit data
code 1011 indicating that the open parenthesis occupies a twelfth
position, in order, in the characters assigned to level 15.
- 78 -
,
~, .
- ~0~5Z~8
At this point, the total logical output from the
; compactor for the example data "LINE 01 = (" is:
.' 11010011 11111111 11011001 11011100 11010000
L 16 exit I N E
'.' 0100 0000 0011 0100 11101110 0100 11101011
~ blank 0 1 blank = blank
i,
The above presentation has been spaced for illustrative
and explanatory purposes only. It will be recognized that spaces
do not appear during actual transmission. Likewise, the characters
represented by the binary bit string, and appearing below the bit
string, are set out for purposes of explanation and illustration
~ .!
-~ only.
`~ The system then repeats progress through steps 12, 12a,
and 15, and back to step 10, as previously explained.
The next data character in the example is "B". This
~ character also traverses step 10, lOa, 17, and 27, and is operated
-~. upon in step 37 in a manner explained previously. From Table III, ~ ~ -
"B" has been assigned, according to the preferred embodiment of
the present invention, to level 14.
Thus, the "B" next brought in by controller 88 produces
a control code of 1101 and a four bit data code of 1110 indicating
its fifteenth position in the character string represented by
1g the assigned level 14.
The system then proceeds through steps 12, 12a, 15, and
back to step 10, as previously explained.
The final character in the first record of the example
set out above is a close parenthesis. The close parenthesis falls
in level 15, according to Table III. Thus this character, in the
manner previously set out, produces a logical output of 11101100
with the four bit control code of 1110 discussed above and the
four bit data code of 1100 indicating the position of the close
parenthesis as the thirteenth position of level 15.
.
. ,, ~
s - 79 -
'~
. .. .
,... ' . .. ,: ' ,. . ' : ,, ~ : '
1045;~
At this point the total compactor output for the first
record of "LINE 01 = (B)" is:
-- 11010011 11111111 11011001 11011100 1101000~ 01~0 0~Ø0 0011 0100
L16 exit I N E blank 0 1 blank
11101110 0100 11101011 11011110 11101100
= blank ( B
To this point in the explanation of the pres~nt inven-
; tion, only character level compaction has been performed. That
is, no step 17 or step 27 compaction, as set forth in Figure 8,
,.,
: 10 has been performed; only step 37 compaction has been performed.
The compaction performed, however, has reduced a record which
was initially 104 bits in length to 92 bits. That is, the first
record of "LINE 01 = (B)" consists of 13 characters and with a
conventional representation of eight bits per character, would
represent a total of 104 bits. From the total compaction output
;i set forth above, it can be seen that only 92 bits are used to
:,1
represent this data record, previously to the present invention
conventionally represented by 104 bits.
The above set out compaction of the first record has
20 contained the overhead of the exit code for leaving level 16 and
has also established a prior record mask which allows greater
compaction in following records. The prior record mask is stored
at the end of compaction upon the first record, where step 12
3 is traversed, step 12a is traversed, and the system traverses
step 15.
The test for record completion, step 15, is totally
dependent on the type of terminal hardware with which the system
of the present invention interfaces. Some terminals transmit
only one record per transmission block, and the end of a record
30 is an actual halt of data transmission. For simplicity, this
is assumed to be the case for the example of this description.
Other terminals, however, use special characters or sequences
,,,
- 80 -
- .,... - :
, . '-' '- : ' ' - ~
lO~S'~48
of characters to indicate the end of a record has occurred, and
this allows multiple records to be transmitted and packed into a
single transmission block. If this later technique were to be
used, the compactor passes the special characters or sequences
of characters along in a compacted form in the manner of ordinary
data, but logic is arranged at step 15 to recognize these special
characters or sequences of characters that separate the records,
and thus allow each record to be used as a prior record mask.
As can be seen, since the record is now complete, it
~^ 10 is transmitted and also saved, as in step 16, for use which can
j now be explained.
~ Returning again to the data example set out above, the
;~ second record is then ready to be brought into compactor 54 by ~ -
coder 88. As can be visually seen in the simple example given, ~`~
the first six characters of the second record are identical to ~ ~
` the first six characters of the first record already processed. ~ ; `
That is, from "L" to and including "0", the records are identical
for the first six locations in the prior record. Thus, compac~
tion according to the present invention would proceed from step
20 10 of Figure 8 through step lOa, as previously described, and
stop at step 17 where it is found that a character is the same
as a corresponding character in a prior record. The system then
,?` proceeds to step 20 where a four bit control code for level 3 ;~
is set up. From Table III, this control code is 0010. The
system then proceeds to step 22.
Compaction level 3 is used when portions of a record
repeat the corresponding portions of a prior record and the
four control bits, 0010, are used to shift into level 3. In
level 3, a 4 bit count represents from 1 to 16 characters which
~ 30 were the same as in the prior record. The 4 bit count is
s expressed as a base 16 data, with 0000 representing a count of
1, 0001 a count of 2, 0010 a count of 3, 0011 a count of 4, and
"
: -- 81 --
,.
" - , ' : ''
,, .
~045248 ;
~- so on up to 1111 which represents a count of 16.
Returning to the continuing example on the four records
set forth above, it had been found that the first six characters
of the second record were identical to khe first six characters
of the prior and first record, i.e. "L" through and including
"0". Utilizing step 22 of Figure 8, the compaction according
;-s~i to the present invention sets up the data as a 0101, which
~ indicates six characters identical to the prior record.
.i
~ At this point, the bit string representing the com-
; .
~ 10 paction output of the present invention for record two is:
,. 00100101
6L3
The notation "6L3" indicates that six characters have
been replaced by a single level three code. -
The system according to Figure 2 would then traverse
~, step 12, 12a, 15, and return to step 10.
The next data character in the continuing example is u
.. . . .
"2", which is a level 2 character and is handled in that manner.
i-~ That is, the system traverses steps lOa, 17, 27, 37, 40, 42, 12,
12a, 15, and returns to step 10. The bit string output is 0001 -
representing a four bit control code for level 2 which contains
only the character "2". ~ ~
.~ ' - .
The next four characters of the second record starting
with the blank and ending with the open parenthesis are identical
to the four characters in the identical position in the prior
and first record. Again, level 3 is used and the system traverses
steps 10, lOa, 17, 20, 22, 12, 12a, 15, and back to step 10. The
;s bit string output is 00100011 to include the control code for
level 3 (0010) and a character count of 4 (0011).
The next character of record two of the continuing ;~
example is "D~. This character is a level 14 character and is
handled in a manner previously explained to produce a bit string
, .
- 82 -
~ .. . .- .
,.:, . . . . .
;: ': . ., ~ , .
. . , ~ . -: , , ~ :
, :. - . . : : ,
1045Z48
of 11010111.
^ At this point, the compaction for record two for the
data "LINE 02 = (D" is:
,
~' 00100101 0001 00100011 11010111
,s 6L3 2 4L3 D : :
Starting again at step 10 of Figure 8 and with the ~ -
continuing example, the next eight data characters are all "D",
and therefore are the same as the prior character in the current
and second data record. Thus, the system traverses steps 10,
~ - , .
10 lOa, and 17 and descends from step 27 into steps 30 and following
to set up level 6 according to Table III. ;
Compaction in level 6 is used when a string of identical
:s
~ characters exists in the same record. Four control bits 0101 are
" . ~
used to compact in level 6, and entry into level 6 causes genera~
tion of a 4 bit (base 16) character count, which expresses that
` from 1 to 16 characters are the same as the prior character.
Returning to continuing example where eight data -
s` characters, all "D" exist in record two, the bit string produced ~
would be 0101 0111. Separation is used here to show the control -
.
'~s 20 bits (0101), and the data in base 16 (0111).
Thus, for the eight identical characters "D" the system
;~ according to the present invention traversed steps 10, lOa, 17,
~s 27, 30, 32, 12, 12a, 15, and returned to step 10.
l .:
The final data character in the second record is a close
parenthesis, which as discussed above is a level 15 character.
This character causes the system to then traverse steps 10, lOa,
17, 27, 37, 40, 42, 12, 12a, 15, and return to step 10 to
generate a bit string of 11101100 representing the control code
for level 15 and the four bit positional code for close paren-
`'~ 30 thesis.
~ At this point, the bit string produced by the compac-
i~s tion according to the present invention of record two consisting
. ~ , ~
- 83 -
.~ . :
~,,,- . ,
104SZ48
of "LINE 02 = (DDDDDDDDD) " is:
~' 00100101 0001 00100011 11010111 01010111 11101100
~ ~ 6L3 2 4L3 D 8L6 ) ~ -
;Y The notation "8L6" indicates that eight characters
` have been replaced by a single level six code. ;
The compaction provided by the present invention with ~;
^^~l respect to record two may now be discussed. In record two,
further compaction was possible in that it was possible to
~, utilize both the prior record and the prior character masks
. lO according to the present invention. Thus, record two, as set
forth above, includes 21 characters, which at eight bits per
character as conventionally encoded, would result in a bit string
of 168 bits. As can be seen from the final compaction of record
''.! two, through the utilization of the teachings of the present ~ -
31 invention, this 168 bit string has been compacted to 44 bits.
Further, both records one and two have created a mask which may ~ ;
. ,., -: - .
be utiliæed in further compacting succeeding records.
Returning again to the data example set out above, the
third record is then ready to be brought into compactor 54 by
coder 88. As can be visually seen in the simple example given,
the first six characters of the third record are identical to
the first six characters of the second record already processed. - ~-
That is, from "L" to and including n O~ ~ the records are identical
for the first six locations in the prior record. Thus, compac-
tion according to the present invention would proceed from step
lO of Figure 2, through step lOa, as previously described, and
stop at step 17 where it is found that a character is the same
1 as a corresponding character in a prior record. The system then -
proceeds to step 20 where the four bit control code for level 3
30 is set up. From Table III, this control code is 0010. The
~! system then proceeds to step 22 and generates a character count
1 of 0101.
:' - 84 -
:
. ~ ~
:~ 1045248
` The next data character in the continuing example is
"3", which is a level 10 character and is handled in that manner.
That is, the system traverses steps lOa, 17, 27, 37, 40, 42, 12,
~, 12a, 15, and returns to step 10. The bit string output is 1001
representing a four bit control code of 1001 which represents
the character "3" as the only character in level 10.
The next four characters of the third record starting
with the blank and ending with the open parenthesis are identical
to the four characters in the identical position in the prior and
second record. Again, level 3 is used and the system traverses
; steps 10, lOa, 17, 20, 22, 12, 12a, 15, and back to step 10. The
~,
```3j bit string output is 00100011 to include the control code for
` level 3 (0010) and the character count for 4 characters (0011).
The next character of record three of the continuing
example is "Y". This character is a level 15 character and is
~ handied in a manner previously explained to produce a bit string
;~ of 11101001, to include the control code for level 15 (1110) and
the base 16 positional information indicating the letter "Y" is
~ the tenth positional letter in level 15 (1001).
`~ 20 At this point, the~compaction for record three for the
~ data "LINE 02 = (Y" is:
i
~' 00100101 1001 00100011 11101001 i'
~ 6L3 3 4L3 Y
The next two characters in the continuing example are
both "Y". Since these characters are the same as the prior
characters, a single level 6 output of 01010001 is generated, in -
' the manner previously explained.
j The next three characters in the example are all "D".
~; . ,.
Since these characters are the same as in the prior, secand
30 record, a single level 3 output of 00100010 is generated, in the
manner previously explained.
The neXt character is the continuing example is a "T".
.
- 85 -
.,.......... , , - . .
... . . .
11)~5Z48
This character is a level 14 character and an output of 11010100
is generated, in the manner previously explained.
The next character in the continuing example is also a
"T", but this is the same as the prior character of the present
record, and a level 6 output of 01010000 is generated, in the
manner previously explained.
The next two characters in the continuing example are
"D)". Since these two characters are the same as in the prior,
second record, a level 3 output of 00100001 is generated, in the
i 10 manner previously explained.
At this point record three is complete. The total
,
i compacted output for record three is:
,~ , ,
`~i 00100101 1001 00100011 11101001 01010001 00100010 11010100 '~
~ 6L3 3 4L3 Y 2L6 3L3 T
'~ 01010000 00100001
lL6 2L3
The compaction provided by the present invention with
respect to record three may now be discussed. In record three,
further compaction was possible in that it was possible to
.~
utilize both the prior record and the prior character masks
according to the present invention. Thus record three, as set
forth above, includes 21 characters, which at eight bits per
character as conventionally encoded, would result in a bit string
of 168 bits. As can be seen from the final compaction of record -
three, through the utilization of the teachings of the present ~ `
invention, this 168 bit string has been compacted to 68 bits.
Further, record three has created a mask which may be utilized
in further compacting succeeding records.
Record four is handled in much the same manner as the
first three records, discussed above, until the characters ofthe semicolon, the colon, the number sign, and the question mark
are reached. These four characters are used in the present
~,
- 86 -
,,- . , . . - -: , ,
: - ~ - ,. : , . .
-.", . . ~ , ~
1045248 ~
- description to represent level 16 logic. Although these four
characters are often printa~le characters, the vast majority of
level 16 logic characters are not printable characters.
Compaction level 16 is thus a no-compaction mode. In
,.
1 some instances, all of the 256 possible bit combinations are
.,
i~ used even though most are not printable characters and therefore
each of the eight bits are passed along as exactly received in
the number base 256. It is also this mode of operation which
guarantees that any string of characters, no matter how unusual
or unprintable, can be correctly transmitted through the compac- ~
tor, even though some combinations could cause an increase in ~ ;
record size. This level is entered by the use of control bits
. ~y
1111 and therefore the first such character in a contiguous string
produces a bit string llllNNNNNNNN. Once in this mode of
operation, eight specific control bits (11111111) are also re-
quired to leave the level.
Returning again to the data example set out above, the ~ ^
fourth record is then ready to be brought into compactor 54 by
`~ controller 88. As can be visually seen in the simple example
~ 20 given, the first six characters of the fourth record are identical
to the first six characters of the third record already pro- -~
cessed. That is, from "L" to and including "0", the records are
identical for the first six locations in the prior record. Thus,
compaction according to the present invention would proceed from
step 10 of Figure 2, through step 10a, as previously described,
and stop at step 17 where it is found that a character is the
same as a corresponding character in a prior record. The system
then proceeds to step 20 where a four bit control code for level
3 is set up. From Table III, this control code is 0010. The ~ -
30 system then proceeds to step 22 and generates a character count
of 0101.
The next data character in the continuing example is
- 87 -
~;
~.. . . . .
,~-: i, . . '
... . . .
1045Z48 :
"4", which is a level 13 character and is handled in that manner.
That is, the system traverses steps lOa, 17, 27, 37, 40, 42, 12,
12a, 15, and returns to step 10. The bit string output is 1100
representing a four bit control code for level 13 which contains
only the character "4".
~, .
The next four characters of the fourth record starting
with the blank and ending with the open parenthesis are identical
to the four characters in the identical position in the prior and
third record. Again, level 3 is used and the system traverses
steps 10, lOa, 17, 20, 22, 12, 12a, 15, and back to step 10. The
bit string output is 00100011 to include the control code for
level 3 (0010) and a character count of 4 (0011).
` The next character of record 4 of the continuing example
is ";". This character is a level 16 character and is not con-
.~ .
tained in the levels 1, 2, 4, 5, 7, 8, 9, 10, 11, 12, 13, 14, or
15. Therefore it must be a level 16 character, as is shown by
~A~ reaching step 46 of Figure 8. The control bits 1111, which signal
an entry to level 16, are generated in step 50. The noncompacted
input value for ";" which is 01011110 is also generated and
,~ .
-~ 20 transmitted.
At this point the compacted output from record four
nLINE 04 = (;" is:
00100101 1100 00100011 1111 01011110
6L3 4 4L3 16 entry
The notation "16 entry" indicates the control bits which cause an
entry to level 16. This is then followed by the level 16 charac-
ter, as provided to the system of the present invention. ~ ~
The next character in the continuing example is a ":". ~ ~`
This is also a level 16 character, so the compactor will remain
in level 16. At the time of the last character a test was made,in step 13, to determine the desirability of leaving level 16. A
lookahead was done, as was explained hereinbefore, and if the
- 88 -
. . ~,
:. , ,. . , ~ . -
. -~ . - ~ -
~: .
10~5~48
next three characters were all nonlevel I6 characters, a level
16 exit code would have been generated. This is not the case in
, the present continuing example; so the compactor remains in level
-` 16 until three characters in a row are nonlevel 16 characters,
or until the record is finished. In this case the record
finishes first, so the remaining characters are handled in level
16.
At the end of record four the compacted code for
"LINE 04 = (;:#7)" is:
001~0101 1100 00100011 1111 01011110
- 6L3 4 4L3 16 entry
'I 01111010 01111011 01101111 01011101 11111111
-`j : # ? ) 16 exit
., ~
The compaction provided by the present invention with
- respect to record four may now be discussed. In record four
; again, in compaction, it was possible to utilize both the prior
`~ record and the prior character masks according to the present
invention. Thus record four as set forth above, includes 16
~, characters, which at eight bits per character as conventionally
,~
encoded, would result in a bit string of 128 bits. As can be
seen from the final compaction of record four through the utili-
zation of the teachings of the present invention, this 128 bit
` string has been compacted to 72 bits. Further record four has
-~ created a mask which may be utilized in further compacting
succeeding records.
Compaction for the total example may now be examined.
1 The following table shows the results for the four record example:
;~ Record Length in bitsLength in bitsRatio
~ non-compactedcompacted
.~ . .
` 30 1 104 92 1.13
' 2 168 44 3.82
3 168 68 2.47
4 128 72 1.78
Total 568 276 2.06
89 -
'
045248
It can be seen that a substantial improvement has taken place.
Although no claim is made that this example is typical data, it
is data for which most currently used techniques are useless.
It may also be seen that the ratio of record one may be dis-
regarded since after one initial record the compactor may run
, ~
for long periods of time with each record masking from the
~ record ahead. Record four is also nontypical due to the unusual
;~' amount of special characters contained to illustrate a point.
` In general, commonly transmitted data would resemble records two
and three, with similar results, but would be more compactible
`~ due to large areas of blanks in a typical printed page.
Once the continuing example and the discussion presented
thus far is understood, a discussion and explanation of the pre-
, sent invention with respect to the four bit data slice may be
~, continued, with respect to Figures 8 and 3-6.
Also, although in this particular example the alternate,
4 bit minimum data slice version achieved slightly more compac- i~
tion than the optimal, one bit minimum data slice version, this
would not normally occur on larger samples of more typical data.
.. , ;:. .
The alternate version may normally be expected to produce a 17%
longer bit stream than the optimal version.
As has now basically been explained, Figure 8 is a
block diagram generally showing the logic created in coder/
decoder 88 to select the number base and the control level in
going from one number base to another, and to select the control
level in going from one number base to another. As each character
, is read into the mechanism, it is stored in a temporary buffer ~ ;
and compaction on the record is performed in the manner shown ~ -
i generally in F~gure 8. The compacted data is then transmitted
! 30 while new data is being read into the device, and as each record
is completed, it is saved to be used as the prior record mask.
~ Compaction of the data always starts at level 16, and
.~ . 90
. .~. . .- , ~ . ., -
. - .
.... : .
:~ . . . - -
10~52~8
under the worst conditions or when necessary to maintain com-
patibility with other equipment, this level will continue to be
` used. Normally, a shift into the control level is made, and the
control level, as explained earlier, uses four control bits to
call out various compaction levels. As also explained earlier,
the control strings are arranged so that frequently used
~,;.,
compaction levels require a small number of data bits to express,
and infrequently used compaction levels require a large number
~' of bits to express.
To recapitulate and expand, in Figure 8, assuming the
compaction process to begin in level 9, another character is
brought into the matrix at step 10 and, upon comparison at step
10a, a data string is created. The data string is created, as
i at step 11, under the base 256 and the data is stored in an out-put buffer, step 12. For a more detailed description of opera-
tion according to the present invention, reference is made to
Figure 6. The output storage buffer 12 has its output compared
~ in step 12a to determine if storage is currently in level 16 and`~ if it is, then comparison is made to the next character coming
in at step 13a where it is compared to see if level 16 is the
least desirable, and if the answer is no, another character is
brought in, in level 16, and is applied to the output storage in
' the fixed code. However, if it appears that level 16 is the least
, desirable, another comparison is made at step 13b to determine
3 if the compatibility allows a level other than 16, and again if
the answer is no, another character is brought in, at level 16.
Once it is determined that it is desirable to leave^level 16 at
step 13, an eight bit exit control code (11111111) is generated
at step 14 and applied to output storage buffer 12. Once it is
determined that level 16 is no longer desirable, the next
character being brought into the matrix at step 10a will then
be applied to one of the character groups to determine how it
-- 91 --
,. ' ' ~ ~ ' .
,:. .: - : - . . : .
~ lO~SZ48
may be compacted. Thus far, the current record is complete as
found in step 15 which produces a mask, step 16, resulting from
saving the record.
since the matrix is now operating at some level other
than level 16, the next character is compared at step 17 and if
the character is the same as in the corresponding prior record,
.;
a control code of 0010 control bits is established at step 20.
A four bit character count is then generated at step 22. These
bits are then stored in the output buffer, step 12, with the
control remaining in the control level, and the matrix is now
ready to receive another character.
~` Assuming at this point that, within the record, a
~ number of identical characters exist and are brought in at steps
; 10 and lOa, the matrix will recognize the string of identical
characters by a comparison step 27 and 0101 are generated by a
, step 30. These four control bits are used to shift into level 6
Y; where a four bit character count is generated in step 32. It
-~ will also be understood that the characters are stored in the
~ output buffer, step 12, and the matrix is then ready to receive
`.3 20 additional characters. ;
l ,. .
After completing the two steps of compaction, 17 and 27,
just described without obtaining a "yes" output, a comparison is
then made of the characters to determine in which of the groups ~ ;~
for levels 1, 2, 4, 5, 7, 8, 9, 10, 11, 12, 13, 14, and 15 the
characters belong, as established in step 37. Assuming the next
character is compared to those of the group to be stored in a
given level at step 40, a control level signal represented by a
4 bit code is generated, and the character is encoded by either
0 bits or 4 bits as found in step 42, with the data being stored
in the output buffer, step 12. After compaction of a single
character, return to the control level is automatic and requires
no control bits to return operation to the control level.
; - 92 -
, ~045Z~8
Returning again to Figure 8, upon finding that a
character, upon comparison, does not become encoded at one of the
bases which is less than the fixed base such as base 256, the
character will appear as a level 16 character as shown in step
46. Because the character is found to exist while in a control
level rather than at the level 16, and further not being
compactible, control bits 1111 are encoded at a step 50 which -
permits the character to be encoded in the fixed base 256 as
found in step 11 and stored in the output buffer, step 12, in
the fixed base code rather than being compacted.
As in the optimal system, the alternate system using
more than a single data bit slice also utilized the simple
lookahead described above. Further, it is unlikely that the
alternate system would ever require the complex lookahead. A
lookahead which is desirable is to use the automatic exit from
level 16 as used by all the other levels. In this approach, a
level 16 character generates a four bit level 16 control code,
~ the system provides an output of one noncompacted character, and
-~ the system then automatically returns to the control level with
no level 16 exit code required.
Decompaction of the four records compacted utilizing
a four bit data slice will not be discussed in detail since, as
has been set out and explained in great detail with respect to
~ the single bit data slice, decompaction is merely the inverse of
'` compaction. Thus, with an understanding, and appreciation of
the foregoing, a detailed explanation of decompaction of the
compacted data utilizing the four data bit approach is deemed
unnecessary.
Another alternate approach according to the present
invention is to change the location of the characters in the
tables. It can now be seen that this change does not cause a
variance of the procedure or the apparatus in any way but may
~ 93 -
.
1045Z~8
allow for a higher degree of compaction in specific applications.
For example, a bank, which has a high incidence of numbers will
move numbers in the more efficient levels, while a publishing
house, which has a low incidence of numbers, will move common
alphabetic characters into the more efficient levels. Such a
minor alteration of the present invention, as stated, in no way
affects the basic teachings presented here and, in fact, are
; envisioned to tailor the present invention to specific applica-
. tions.
:,
- 10 As a further and quite detailed example of minor
; alterations of the present invention for particular applications~
another alternate approach to specifically tailor the method and
apparatus according to the present invention can now be explain-
ed. The specific application is to support ce~tral processor
to terminal transmissions between an International Business
Machines system 360 or 370 central processor and certain
, terminals, such as terminals models 2770, 2780, 3780,
2701, 2703, 3704, 3705, and 20, all manufactured by
International Business Machines, models 70, 71, 74, and 78 as
manufactured by Data 100 Incorporated, and model 1270 as manu-
~1 factured by Memorex. Further, transmission may be to any
HASP type work station, which may include almost any program-
mable International Business Machines system. This application
is limited to the protocols used on the above named central
-, processors and terminals and only on the EBCDIC version of the
i International 8usiness Machine Binary Sychronous Communication
.~,
Technique, as defined in IBM publication GA 27-3004 and other
` associated IBM documents. The specific configuration to be
- described and explained will also support other terminals which
emulate the above set out terminals, however.
In providing for this specific application, it has
:,
been found that the four bit data slice, described in detail
, above with respect to Table III, would be appropriate for the
``;
. . _ 94 _ 7
:3
., !
. .;.
- 10~5Z48
reasons set out above. It was further found that certain
;` alterations should be made solely for the purposes of the
,
particular application. No limitation to this particular
application is intended, and it serves to illustrate the
;~ flexibility of the method and apparatus according to the present
invention. The alterations made are set forth in the following
Table IV.
.
..,.;
` 1 0
.,
.~.
1.
. ~
$
`;s 20
, -
~ ~i
~, ,
.~, .
,', ,' ~
.,, ~
. ~ .
. ,.~
/
' ~
,, :
, 95
,
.. - . .
lO~SZ48
TABLE IV
:
Control Level Codes Characters
1101Shift to level 1 O
1100 2 2 ,
1110 " 3 characters identical to prior record
or to prior character
1011 " 4
1010 " 5 (blank)
1111 " 6 idle control character
1001 " 7 5
O100 " 8 A
0110 " 9 7
Olll " 10 3 -
OOll " 11 8
0101 " 12 E
1000 " 13 4
0001 " 14 FBPN(OISDCR-9.6T
0010 " 15 ESC YW,K/*HUL)MG DLE SYN PAD
OOOO " 16 No Compaction Mode
.~
Level 3 Codes (base 16)
~ NNNN This four bit code represents the number of characters
;~ which were either identical to similarly positioned
~ characters in the prior record or identical to the prior
', character according to the following list:
OOOO 6 characters identical to prior character
~ OOOl 5
-` OO10 4 " " " " "
OOll 3
`r 010 0 2
? 0101 12 characters identical to prior record
PllO 11
~, 011110 " " " " "
`., 1000 9 " " " " " ~'
1001 8
:~, 20 1010 7
:i 1011 6
`; 1100 5
1101 4 ~ .. "
; 1110 3 " " " " "
, Level 6 Codes (base O)
7 This level has no data bits as it contains only a con-
, trol code used by the compactor to idle the line at
anytime when data is not available quickly enough
from the terminal or central processor. -~
7 Level 1, 2~ 4~ 5~ 7~ 8~ 9~ 10~ 12, 13 Codes (base O) ~ -
; These levels have no data bits as each level contains
only one character and that is inherent in the level.
Level 14~ 15 Codes (base 16)
NNNN This four bit code is a base 16 character to represent
1 of 16 characters in the level.
Level 16 Codes
NNNNNNNN This eight bit code is a base 256 character to represent
1 of 256 characters in the level.
- 96 -
... . .
, - . :
1~4S248
Table IV shows the changes made to the general case
or theoretical approach of the four bit data slice, as set forth
in Table III, in order to implement the practical applica~ion
indicated immediately above. From Table IV, it can be seen that
`~ levels 1, 2, 4, 5, 7, 9, 10, 11, and 13 have not been altered or ;
changed except that the particular control codes described in
Table III to reach these levels have been reordered in Table IV,
in order to provide a faster recognition at the receiving end of
a transmission line.
Further changed are levels 8 and 12 which each have
switched a character with one character out of level 14. That
is, in level 8, the only character contained is now "A", rather
i than a period. In level 12, the only character contained is
now "E", rather than the number "6". This change is made to -
increase compaction somewhat on.alphabetic records, at the
expense of decreasing compaction on numeric records. Further,
control codes were also reordered in these levels.
Levels 14 and 15 are functionally the same as before,
:: :
3 but seven new characters have been added to these levels as
. .
`; 20 follows:
6 . W ESC DLE SYN PAD
The first two characters of these new characters were lowered
from higher levels 8 and 12 as set forth in Table III while the ~;
~, remaining five characters were raised from level 16. Of the five
characters raised from level 16, the last four were raised to
level 15 because they are important control codes used in this
specific application. In order to accomodate these last five
characters in level 15, for this particular practical applica-
tion, five lesser used characters were lowered to level 16.
These characters are:
V & J = X.
- 97 -
.
-
.,., . - : : . .,.-
10~5~
Le~el 16 remains the same as before except for a
control code reordering and oné other change. As set out above~
in utilizing the four bit data slice, it is desirable to use a
level 16 entry mode, but not a level 16 exit code. In the
example of Table IV, level 16 then returns to a control level
after each character, as do the other levels, rather than re-
quiring an exit code, as has been described as an option above.
In order to allow a wide range of interface and line
speeds desirable for this application, in that this application
is intended to interface with various terminals and central
processors, a special idle control character was also added.
This is a control character used only to fill line time when a
gap is caused by too wide a difference between the line speed
and the interface speed. That is, if the line speed is not
exactly compatible with interface speed, with either speed being
greatly in excess of the other, this control character is used.
Again, to accommodate this special character, it was necessary
.;
to again adapt the method and apparatus according to the present
invention, and the adaptation made was to use level 6 for the
special character and to combine the functions of the former
i levels 3 and 6.
:,
~ Therefore, in this specific application, level 3 de-
'~! fines either a prior record match or a prior character match.
In order to effect the above, the particular count following the
level 3 control code then defines which type and how many
characters match. Specifically, a count of 0000 signifies six
characters identical to a prior character, a count of 0001
signifies five characters identical to a prior character, a
count of 0010 signifies four characters identical to a prior
character, and so on up to a count of 0100 which signifies only
' two characters identical to a prior character. Higher counts
are then utilized to signify that certain characters are
.. .
- 98 - 1:
,....... .. .... 1 -
1045Z48
identical to similarly positioned characters of the prior record.
For example, a count of 0101 signifies 12 characters are identi-
cal or the same as similarly positioned characters in the prior
record, a count of 0110 signifies that 11 characters of the
current record are identical or the same as similarly positioned
characters in the prior record, and so on to a count of 1111
which signifies onl~ two characters of the current record are
identical or the same as similarly positioned characters of the
prior record.
It may then be readily seen from Table IV that, while
the number of characters which may be expressed is changed, the
control codes have changed, the levels have been altered, and
,~ the actual bit strings for both the control codes and the counts
have changed from that previously described, the changes made
are- merely adaptations for a specific application and are within
- readily envisioned alterations and changes in the method and
apparatus according to the present invention,
Table IV then illustrates a technique as modified for
a particular application, as indicated. Further modifications
2Q will not be explained, as they are considered too numerous, ~
. -
.,
I
.
., .
, ~ .
3Q
_ 99 _
. . ~
1045Z48
1 and it is believed apparent with the preceding description and
~ explanation that the method and apparatus according to the present
; invention is readils~ adaptable to various particular applications.
Decompaction utilizing a four bit data slice
5 according to Table IV will also not be discussed in detail since,
as has been set out and explained in great detail with respect
~ to the single bit data slice, decompaction is merely the inverse
^~1 cf compaction. Thus, with an understanding and appreciation of
the foregoing, a detailed explanation of decompaction of the
`~ 10 compacted data utilizing the four data bit approach according
to Table IV is deemed unnecessary. -
Thus, the complete compaction and decompaction
~- of four records has been shown in detail as an illustrative
~- embodiment of three types of operation according to the
15 present invention, a single bit data slice, a four bit data
slice theoretical, general approach, and a four bit data slice
particular, practical approach. With this explanation of
3 ~ .
-1~ operation in mind, an explanation of preferred apparatus according
. ,
to the present invention may be explained with reference to
~ 20 Figures 9-26. First, the block diagramatic Figures 9-14
-i will be explained from a general operating standpoint. The
precise physical connections between all parts will not be
$ndicated by the block diagramatic Figures 9-14; however,
i the basic operation of a method and apparatus according to
25 the present invention will be explained. The precise
physical interconnection of electrical components forming
a preferred embodiment of the four bit data slice practical approach
embodiment,will then be explained with reference to Figures 15-26.
. .
-a - -- lO~
'`~, '
10~5Z~8
With respect to Figure 9, this Figure shows an
expansion of memory 90 of Figure 7. Specifically, instruction
memory 92 is shown along with data memory 94 and input/output
memory 96, all interconnected with the eight bit, parallel
' 5 data bus 86 discussed above. Specifically with respect to
Figure 9, data bus 86 provides data to instruction memory 92
through an input 900 and receives data from instruction memory
92 through an output 902. Similarly, data memory 94 receives
data from bus 86 through an input 904 and provides data to
.~
10 bus 86 through an output 906. Similarly, input/output memory
96 receives data from bus 86 through an input 908 and provides
data to bus 86 through an output 910.
~`- Figure 9 then includes the addition of memory
;j.. .
address decoder 912 between the entry of eight-bit parallel
15 data bus 86 into memory 90 and inputs 900 and 904 to instruction
memory 92 and data memory 94, respectively. In particular,
memory address decoder 912 receives data from data bus 86 through-
-~ an input 914 and provides data to bus 86 and thus to instruction
'?~ ~memory 92 and data memory 95 through an output 915.
Memory address decoder 912 then intercepts addresses
in logical form upon bus 86, and determines the page of memory and
the byte of the page in memory that the particular address
intercepted refers to. ~iming on the data bus 86 determines
~ whether an instruction refers to a page or a byte within a page,
25 as will be discussed in detail with reference to Figures 15-26
hereinafter. Since similar logic is used whether or
not an instruction is being requested from instruction memory
92 or data is being requested from data memory 94, only one
~~ ` `memory address decoder is required.
.
~t . ~ O r -
,~,'
.~ .
~._.. ,`~ `
' 1045Z48
'f 1 In the preferred embodiment disoussed hereinafter,
- instruction memory 92 is preferably a read-only memory (ROM~
which in the preferred embodiment is an eight by 1280 bit
memory, which is equivalent to five pages. Similarly, the
:, .
5 preferred embodiment of data memory 94 is a random access
memory (RAM) which is eight by 256 bits long, which is equivalent
to one page of data.
Figure 9 further includes an input/output (I/03
address decoder 916 situated between the entry o~ data bus
10 86 into memory 90 and lnput 908 of I/O memory 96. I/O
address decoder 916 then receives data from bus 86 through
an input 918 and provides data to bus 86 and input 908 of
I/O memory ~6 through an output 920.
~- I/O address decoder 916 is arranged to search
lS for one of the 32 input/output addresses. As one of the
specific addresses is intercepted and decoded, it pro~ides
access to I/O memory 96 and will cause addressing of the
corresponding byte in I/O memory 96 to be provided to
~- data bus 86 through output 910. In the preferred embodiment
20 to be discussed hereinafter with respect to Figures 15-26,
the preferred confiquration of I/O memory 96 is a ROM which
` is eight by 256 bits long, or 256 bytes long, which is
. .
equivalent to one page. Thus, whenever I/O address decoder
~-` 916 intercepts an appropriate address, it is decoded into
25 one of the 256 possible combinations addressing a particular
data byte within the RoM forming I/O memory 96 and causes
... .
- . -
~-' ~ , .. ~ () aJ . . -. .
~, . ..
~ ~... ..
,~' , .
~0g~5248
..
. ~
1 the contents of that data byte in the ROM forming I/O memory
~6 to be immediately provided to data bus 86 through output
- 910. The use of I/O memory 96 in the preferred embodiment
;l is then as an extremely fast table lookup device utilizing
5 a one instruction table lookup routine.
l~ith respect to Figure 10, this Figure shows an
(~ expansion of coder/decoder 88 of Figure 7. In particular,
,',.~.t the eight bit parallel data bus is seen as first traversing
.~,
bus drivers 1000 which provide for practical current, timing,
`~ 10 and voltage requirements on the bus and for the-remainder of
. ~ .
the blocks described. It will of course be recognized that
bus drivers 1000 may not be necessary if the remaining
.~ .
blocks described may operate wit'nout enhanced current, timing, or
~-~ voltage capabilities, or have internal apparatus for the providing
15 of enhancement of current, or timing, or voltage capabilities
for proper transmission on data bus 86.
Connected then to data bus 86 on the interior side
~ .
of bus drivers 1000 is an instruction address register or
program counter 1002 having a data connection 1004 to data
20 bus 86, a memory address register 1006 having a data connection
1008 to data connection 86, and arithmetic and logic unit 1009
,~, .
having a data connection 1010 with data bus 86, and an accumulator
.
1012 having a data connection 1014 with data bus 86 and a
~- further data connection 1016 with arithmetic and logic unit
; 25 ~009, a general purpose register 1018 having a data connection1020 to data bus 86, a return stack of registers 1022 having a
data connection 1024 to data bus 86, an instru~tion decoder register
1026 having a data connection 1028 with data bus 86, an I/O
~ - address register io30 having a data connection 1032 with data
bus 86, and a condition flag register 1034 having a data ~ ~
connection 1036 to data bus 86.
, ~, ,,~,"~ . ,",
. . ~ ~ .
: r.~ IQ3
.
i;'"- - ~ ,........ ....
~ . 1045Z48
. . .
1 All interrelationships with data bus 86 are shown
dias~ramatically and not precisely. The portions o~ coder/decoder
88 shown are the main portions, and all do have access to data
bus 86. Additional portions of coder/decoder 88 will be shown
.: ,
~ 5 and explained with respect to the detailed, four bit data slice,
.:
practical embodiment disclosed with respect to Figures 15-26.
'; Instruction address register 1002, in the practical
preferred embodiment, is a one by eight bit register which
generates or contains the high order byte and the low order byte
10 for the instruction address. At the beginning of each instruction
~i in the micro code, these two b~tes are transmitted via data
connection 1004 to data bus 86, one after the other, in
.. .
i order to set up and properly condition the addressing logic
~3
into the memories as described hereinbefore with respect
15 to Figure 9. This transmission of the high order byte and
the low order byte then produces the instruction itself from
i~ instruction memory 92 which returns along data bus 86 at a
`~i different time interval.
;~ The first byte of this instruction is gated by
~ 20 appropriate timing into instruction decoder register 1026,
-~` which in the preferred practical embodiment is a one by eight
~ bit register which determines the type of instruction stored
1~ ~ within it. Instruction decoder 1026 also determines if more bytes
;~ of instruction are necessary since a given instruction may be
.;~ .
~' 25 one,-two, or three bytes in length. Instruction decoder 1026
i3 also sets up or conditions the appropriate gates, to be
`~ discussed in detail ~urther hereinafter with repsect to Figures
15-26, so that subsequent instruction bytes are provided to
the correct logic, or data bytes are provided to the appropriate
apparatus, or data transfers between various registers are
appropriately made.
,, ~ , ~
,
,
l[)~SZ48
1 In addition to address register 1002 discussed
above, return stack 1022 is used to hold various different
addresses, which may be used at differing intervals in the
program. In particular, in the preferred practical embodiment,
5 return stack 1022 is a set of sixteen eiglt bit registers
used in pairs in the same manner as instruction address register
1002. The registers forming return stack 1022 are configured
,i~ and used as a first and last out register to allow jumps in
the microcode to thus allow large areas of common coding.
Memory address register 1006, in the practical
~- embodiment, is comprised of another pair of eight bit registers.
These registers also address memo~y 90, but instead of addressing
memory during instruction access time, memory address register
~~ 1006 accesses memory during data access time. This will become
15 clearer upon an explanation of the detailed emboaiment of
Figures 15-26.
Memory address registers 1006 may be used to
~~ remove data from data memory 94 for usage by coder/decoder 88
i~ , , .
~"or to restore data to memory 90 from coder~decoder 88.
20 Similarly to instruction address register 1002, memory address
~ registers 1006 hold a high order byte which addresses the
^~ page of memory and a low order byte which addresses the
~` specific cell of memory.
I/O address register 1030 gives the compaction
25 device according to the present invention the capability of
addressing up to 32 various peripheral devices which can also
.~ : .
be connected to data bus 86. In the preferred practical
' embodiment, these 32 possible devices are organized to a
; ~ naximum of eight input devices and 24 output devices. ~owever,
ior the preferred practical embodiment, only 13 of the 32
^ devices have been utilized, 5 input devices and 8 output devices.
~j ~
; ~ 105
1 ~
i ~ .' ' ' ' .
; 1~4SZ48
~ 1 After an instruction has been accessed by the
i
address in instruction address register 1002, by having been
provided to data bus 86, provided to memory 90, decoded by memory
address decoder 912, accessed a particular page and byte in
S instruction memory 92, caused the particular instruction
to be provided by instruction memory 92 to data bus 86
;.1 .
via output 902, the necessary data is brought into coder/decoder
88 as a part of the instruction or from data memory 94. At
this time, generally the various arithmetic and logical instructions
.
10 are to be performed upon data on bus 86 by means of arithmetic and
logic units 1008. Arithmetic and logical unit 1008, in the
preferred practical embodiment, is an eight bit arithmetic
register which can add, subtract, do various logical operations
such as OR, AND, exclusive OR, and both left and right shift
" . , -:
15 operations. Arithmetic and logical unit 1008 always delivers
its results to accumulator 1012 which, in the preferred
; practical embodiment to be discussed, is another eight bit
register designed for holding various temporary results.
~-~ In addition to being the recipient of all arithmetic
20 and logical operations from arithmetic and logical unit 1008,
~-~ accumulator 1012 is also the recipient of all input/output commands,
~,
:~ and is the device which holds the data to be provided to the
~ input/output blocks 50 and 52 upon an output command.
,:~. -
~- In addition to accumulator 1012, general purpose
25 register 1018 may be used to temporarily store data, or
as counters, or for a number of other purposes. In the preferred
,~ practical embodiment, general purpose register 1018 is
comprised of four eight bit registers.
~ `' ' ' .
~i ,.
~.~ s, ., ,,~
t-
F: - -
10452~
... .
1 Lastly with respect to Figure 10, condition flag
register 1034 is, in the preferred practical embodiment,
four bits of flags which-are set as a result of a number
~ of various arithmetic and logical operations, such as
A;~ S compare, AND, subtract, and other well known conditions.
This register is normally set as a result of operation
performed in arithmetic and logical unit 1008, although
certain instructions referencing the general purpose
registers may also set some of the condition flags. The
, . ~ .
10 condition flags would then be testea, and logical decisions
are made in a micro-code according to the particular conditions
set, as is well known by those skilled in the art.
~ With respe~t to Figure 11, this Figure shows
-~ an expansion of timing and control block 124 of Figure 7.
~I
15 Specifically, Figure 11 includes a crystal oscillator 1102
~- interconnected by a data connection 1104 with timing and
~`' control generation logic, designated 1106. The timing
.~, .; .
- and control generation logic 1106 will be discussed further
hereinafter with respect to Figures 15-26. Logic connection -;~
20 126 then extends from timing and control generation logic
,.. ' ~ .
~ 1106 to the remainder of the circuitry, as again will be
`:~!' aiscussed further hereinafter with respect to Figures 15-26.
With respect to Figure 12, this Figure shows
~n expansion of input/output control 128 of Figure 7.
- 25 Specifically, I/0 timi~g and control 128 is seen to include an
input from data connection 86 to eight bit parallel bus
~ . ;
,~ .
.
,., . ., ~,
~ ~ .
. , -
, ,
.~ .
4SZ48
`~i
, 1 drivers 1202. Similar comments may be made with respect
to bus drivers 1202 as have been made with respect to
bus drivers 1000 of Figure 10. Bus drivers 1202 are
interconnected via logic connection 1204 with I/O latches
. 5 1206. As seen, I/O latches 1206 include data connections 130-1
, to a portion of controller side converter 56 and 130-4 to a
`` portion of modem side converter 114.
Input/output control 128 further includes a
clock generator 1208 and a special timing block 1210 ~~
10 providing special timing and control for controller side FIFO 66.
~:........... Clock generator 1208 and special timing block 1210 then
.` have logic outputs 1212 and 1214, respectively, which are -~
interconnected to form logic connection 130-2.
. Input/output control 128 also includes a further
lS special timing.block 1216 providing special timing and control
i ,
~ ~. for the modem side FIFO 102. Special timing block 1216
'7 ~, includes an output 1218 terminating in logic connection 130-3.
Thus, input/output control 128 generates many
~- special timing and control signals used by controller side
.~. 20 FIFO 66 and modem side FIFO 102, as will be explained in
detail with reference to Figures 15-~6. Input/output control
. .~. .
128 also generates the clock which is used by the controller
. .
. ~ 6ide FIFO 66. Input/output control 128 also includes a series of
I/O latches 1206 and provides control signals to controller
25 s~de converter 56 and modem side converter 114 in order to
~ provide a connection between I/O latches 1206 and the
`~ ~ environment outside of the compaction device of the present
~ lnvention.
., ~. ^ .
. ,~. . , , - , .
.,
.... .. ....
: ~
'~' : .
- ( )
1045Z4~
1 With respect to ~igure 13, this Figure ~hows
an expansion of input/output block 52 of Figure 7. Specifically,
.~ ~ eight bit, parallel data bus or connection 86 is shown as
. . .
. interconnecting with block 52 and specifically with bus drivers
:` 5 130~ therein. Comments similar to those comments made with
:~- respect to bus drivers 1000 o~ Figure 10 apply again to bus
drivers 1302 of Figure 13. In Figure 13, a more exact
~` representation of the data path is shown, rather than thestylized general approach shown in ~igure 7. In particular,
~r 10 data bus or connection 86 is seen to provide a four bit
parallel input to synchronization logic 1304 via four bit
.
input 1306. Data connection 86 is further seen to provide
an eight bit parallel data connection to input shift register
00 ' via eight bit input 1308 and accept a four bit parallel
15 output from output shift register 106 and specifically from four
~- bit parallel output 1310 thereof.
,~r~*, , Further,.a four bit parallel data connection 1312 -
is provided between synchronization logic 1304 and input :
~ shift register 100 for purposes which will be explained
.1~ 20 further with respect to Figures 15-26.
The remaining numeration of Figure 13 ~s applicable
`~ from the explanation given above with respect to Figure 7.
.~-..................... Again with respect to the preferred practical
,; ..
~: . embodiment, synchronization logic register 1304 is a one
. ~ .
25 by four bit register which may be loaded by coder/decoder 88.
Input shift register 100 may al80 be loaded in parallel by
.' - coder/decoder 88 via data connection 86 or in serial by modem
:~- side converter 114 via data connection 116.
.
1~,9
,,
~09~5Z48
, .~ ,
~ 1 FIFO stack 102, in the preferred practical embodiment,
:` i6 a register commonly known as a data silo. In the preferred
~^ practical embodiment, FIFO 102 includes l28 four bit registers
which stack data in on a fi~st in, first out basis. At the botto~
5 register of this data silo is an output shift register 106, also
four bits wide so that this output shift register 106 may be ~ -
unloaded in parallel to data bus 86 or unloaded serially back
~ to modem side converter 114, as by data connection 110.
f.~ The modem side converter 114, in the preferred
~^ 10 practical embodiment is nothing more than a voltage converter
-- which converts the 0 and the plus five voltage logic signals
of the preferred practical embo~iment to the minus 12 and plus
. ~
12 voltage signals which are generally utilzed in communications.
With respect to Figure 14, this Figure shows an
expansion of input/output block 5Q of Figure 7. Specifically,
eight bit, parallel data bus or-connection 86 is shown as
interconnecting with block 50 and specifically with bus drivers
1402 therein. Comments similar to those comments made with
respect to bus drivers 1000 of Figure 10 apply again to bus
drivers 1402 of this Figure 14. In Figure 14, the more exact
representation of the data path is shown, rather than the
stylized general approach shown in Figure 7. In particular,
data bus or connection 86 is seen to provide an eight bit
parallel ~nput to synchronization logic 1404 via eight bit ~ -
~nput 1406. Data connection 86 is further seen to provide
an eight bit parallel data connection to input shift register
62 via eight bit input 1408, and accept an eight bit parallel
output from output shift register 70 and specifically from eight
bit parallel output 1410 thereof. ~ ~
~ .
, ,~
. -
~ j, , .
~ 110-
' ,'
. ~; .' ,
1045Z48
1 Further, an eight bit parallel data connection 1412
t is provided betwe~n synchronization logic 1404 and input shift
registers 62 for purposes which will be explained further with
t~ respect to Figures 15-26.
S The remaining numeration of Figure 14 is applicable
from the explanation given above with respect to ~igure 7.
Again with respect to the preferred practical
embodiment, synchronization logic re~ister 1404 is a one
by eight bit register which may be loaded by coder/decoder 88.
. 10 Input shift register 62 may also be loaded in p~rallel by
. coder/decoder 88 via data connection 86 or in serial by .
controller side converter 56 via data connection 60. . ~.
-~ FIFO stack 66, in the preferred practical embodiment,
~ ~ .
is a register commonly known as a data silo. In the preferred
15 practical embodiment, FIFO 66 includes -64 eight bit registers,
which stack data on a first in, first out basis. At the bottom
of this data silo is output shift register 70, also
eight bits wide, so that this output shift register 70 may be
~' .
t~ unloaded in parallel to data bus 86 via output 1410 or
~ 20 unloaded 6erially back to controller side converter 56,
.~:
as by data connection 72.
Basic operation of apparatus according to the
present invention can now be explained with respect to
~igures 1-14. Assuming the system is operating in a
compaction mode, and with reference to the basic system
of Figure 1, data provided to the system via terminal A,
for example, is transmitted to line controller B in an eight
bit parallel fashion and converted by line controller B into
an eight bit serial logic representation. This bit serial
logic is then provided to compaction device C by line controller
B. mus, data is transmitted to controller side converter 56
,,~, j ., ~ ., ,j, ... .~ .
`~ : via data connection 58.
It~-
~ . . - . .
1045248
1 The data then traverses converter 56, which alters
the voltage levels as discussed above, and is transmitted
via connection 60 to input shift register 62.
Data input shift register 62 is then compared,
5 in parallel, against a pattern previously stored in sychroniza-
tion register 1404. When the two patterns match, and a
synchronous condition is reached, the data in input shift
register 62 is transmitted via data connection 64 into FIFO
stack 66.
The exact manner in which FIFO 66 logic operates
depends on whether or not the device is in a transmit
or receive mode. In the transmit mode disc.ussed above where
data is received from the controller side converter 56 and
into shift register 62, the output of input shift register 62
15 is provided in parallel, eight bits at a time, into FIFO 66.
At the bottom of FIFO 66, the first eight bits is trans-
: mitted, in parallel, into output shift register 70 where it
is held until it is accessed by coder/decoder 88 via the
eight bit data bus 86. ~s one eight bit data character is
20 removed from output shift register 70, another eight bitdata character is transferred from the bottom of FIFO 66,.
in parallel, and into output shift register 70. As each
eight bit character is removed from output shift register
70 by coder/decoder 88, the eight bit character is then
25 ~vailable for processing within compactor 54 of the present
invention, and for ~ransmission to the modem side FIFO 102.
- .
,
.~ ",
1045Z48
1 That is, the data removed from output shift register
70 is processed through the micro-code control logic into a
compacted form according to the method and apparatus disclosed
above at least with respect to Figures 1-7. That is, coder/decoder
88 accesses instruction memory 92 and data memory 94 and performs
the steps set forth in Figures 2-6 and described above.
As the compacted orm of the data is created, it is
stored in a parallel form in input shift register 100 of i~puTlou~p~T
block 52. In this mode, input shift register 100 operates as a
10 four bit registèr-rather than an eight bit register. Each four
bits, in the order provided to input shift register 100, is
communicated to modem side FIF0 102 via data connection 98.
Modem side FIFO 102, in this mode, is utilized as
a register four bits wide by 128 bits deep. At the bottom of
`~lS FIF0 102, each four bits are consecutively provided to output
shift register 106 via data connection 104. Each four bit
~-character is then clocked in a serial fashion, one bit at a
time, via data connection 110 through modem side converter 114,
-and to modem D via data connection 120. -~
Clocking out to the modem D is accomplished
through an external clock received via connection 118. This
~ ~ .
~- external clock normally originates from a communications device,
5~ such as modem D. As will be discussed in relation to the detaiIed
~- preferred, practical embodiment of the present invention described
25 in connection with Figures 15-26, modem side FIF0 102 is similar
to controller side FIF0 66 except that modem side FIFO 102 also
includes input/output latches which make it possible to read
. . ~ , ,
~nformation received from modem side converter 114 and to send
-,
information out to modem side converter ~14 to be passed on to
the communications medium.
, . ~- ,,, . ,, " " ,. . .
~ .
~ ; - - - - - ~
104SZ4~3 ~
1 Thus, basic operation of the compaction apparatus
and method of the present invention have now been described
with respect to a transmit mode. Operation of the system is
slightly altered during a receive mode of operation,.as ~ ;
5 follows:
In the receive mode, data is provided to modem side
converter 114 via connection 122 in a serial binary form, bit by bit.
- Data traverses modem side converter ~14 and is provided via
~ connection 116 to input shift re~ister 100. Data within input
,~ .
.`. 10 shift register 100 is compared four bits at a time with data
prestored and held in sychronization register 1304 until a
match in the data within sychronization register 13Q4 and
`.~ input shift register 100 is reached. When a match or sychronous
: condition is reached, the four bits of data are transferred
.. - 15 from input shift register 100 into modem side FIFO 102, four
bits at a time in parallel. Each æucceeding four bits of
information received is likewise transferred from input shift
register 100 via data connection 98 into modem side FIFO 102.
~ Data drops -to the bottom of modem side FIFO 102, is
20 transferred via connection 104 to output æhift register 106, `
again four bits at a time in a paraliel fashion, and is accessed ~-
from output ~hift register 106 via coder/decoder 88.
` Coder/decoder 88 then decompacts and processes the
- data through utilization of the techniques set forth above
25 at least in connection with Figures. 1-8 within compaction
device 54. After the data has been decompacted, the appropriate
eight bit, for example, character representation extracted
. from data memory 94, is then transferred to controller side
- FIFO 66 in a parallel form~and again processed through controller
. ~, ~ . . .. .
~ - .; , ., ~ ,
~45Z48
1 side FIFO 66 and in~o output shift register 70. From output
shift register 70, the eight bit character representation is now
clocked, bit by bit, in serial format, via data connection 72,
through controller side converter 56, and to line controller B. -
It is to be noted that, on the controller side interface,
clock 76 provides the control, whereas on the modem side, the clock
was provided externally. This is not necessary, although it
is conventional in order to provide correct timing with the
modem and to appear transparent to the modem and line controller.
h
That is, the compaction device and methods according
to the present invention are performed in a manner which loo~s
`~ like a modem to the controller B and which looks like a controller
~ to the modem D, and thus provides a transparent interface between
. . .
the two, i.e. an interface which does not appear to be present.
15 It is in this way that the technigue and apparatus of the present
invention can perform the compaction and decompaction function
without affecting any of the normal control procedures between
i. .
a controller and a modem on a transmission line.
~- It is then to be noted that the present invention--provides
20 compaction and decompaction of data, as received, without storing
or destroying the timing relationships of the communications
fiiystem whatever. Further, it is to be noted that the data is -
completely reconstituted, and no portions of the data are deleted
or missed. It is then a primary advantage of the apparatus
25 and method according to the present invention that compaction
and decompaction may be performed in a manner which in no way
interrupts, alters, changes, delays, or degrades transmission.
, .......... . .
, ,
~ ,.. .
., ~,
., ~.
~045248
1 A discussion of the preferred, practical embodiment
of the present invention, as set out in Figures 15-26 and
utilizing the four bit data slice and the particular application
of the method according to the present invention as described in
5 connection with Table IV, can now be described in detail and
explained.
In Figures 15-26, certain of the particular
apparatus set out and described is designed only to support
an enhanced version with multiple coder/decoders 88, extra
10 memories, such as memory 90, and a control console. Since
this circuitry and apparatus is not essential to operation
- of the practical and preferred embodiment according to the
present invention, but only to provide an enhanced version,
-~ it will be identified and described only briefly.
lS Also in connection with the description of
"~ Figures 15-26, the interconnection between figures has been
~ identified by alphanumeric designations, abbreviations, or
acronyms which yield information beyond that which could be
;provided by a mere numeration of the connections. Thus,
20 the origin of a connection on a particular figure is
~-- indicated by the alphanumeric designation upon the incoming
~chematic line, representing a wire connection, and various
~ factual data about the signal æ e contained in the acronym
-~ ~pplied. The acronym, the full meaning of the term, the
25 figure in which the acronym originates or is created by the
circuitry of Figures 15-26, and the other figures in which
the acronym will appear are set out on Table V, following
the description of Figures 15-26.
11
. . i ~ . ,
", , .
L.
(
1045248
1 It will also be noted that the logic diagrams set
out in Figures 15-26 are drawn in accordance with ANSI
standard number Y32.14, 1973, using the specially shaped
symbols set out therein.
. Further, the particular apparatus represented
within Figures 15-26, as by the number attached to the
app æatus, the pæ ticuIar name of the apparatus, the
. manufacturer, if relevant, and the manufacturer's number or
value of the particular pæ t are set out in Table VII following
~ 10 the description and explanation ~f Figures 15-26.
,,: - .
It will further be noted that pin numbers of -~
. the various pæ ts indicated in Table VII are indicated on
.. ~
.~. the drawings 15-26 for the convenience of describing,
understanding, and following the description and explanation
15 of Figures 15-26.
With specific regard to Figures 15 and 16, these
Figures represent an expansion of memory 90 as shown in ~.
Figures 7 and 9. In pæ ticular, instruction memory 92,
..
.~ data memory 94, and memory address decoder 912, which includes .
20 the overall memory system address register and the addressing
~; decoding logic, are shown in ~igures 15 and 16.
: .
In Figure 15, the overall memory system address
~".
~; - register or memory address decoder 912 as shown in Figure 9
i~i . i8 contained in quadruple latch chips 1606-1509 and 1514.
~i 25 ~he address to address memory register 912 as shown in
`. Figure 9 is intercepted from the parallel data bus 86 -~
through the input address register, comprising circuits 1738-1741
de~cribed hereinafter in reference to Figure 17. Conventional
.- timing arrangements are provided through AND gates 1501, 1502
and 1504.
,:
"" ~.~ ;. "~ ~ ~
~- ' .
` 1045248
~ ~ Decoding of the memory address occurs in AND gates
3~ 1510, 1511, and 1520, and further address decoding occurs in
; '`f
decoder circuit 1514, whose outputs are used to select the
.~ various memory pages. AND gates 1516 and 1517 perform further
.~
~`.; 5 address decoding to select page zero in the instruction memory
:~ 92. Latches 1506-1509, which in effect form a duplicate
.j .
.. ` ~econd rank register for the input address registers, 1738-1741
.~, described in connection with Figure 17, are necessary only in
;~ an enhanced system with multiple coder~decoders 88, as explained
~ 10 above.
~ Resistors 1522-1529 are connected to a source of
~ positive voltage, in the preferred embodiment, at terminal
.~ 1539 and these resistors are used as "pull up" resistors to ~ ~:
assure an adequate high level to the MOS circuits used fbr
15 instruction memory 92, data memory 94, and I/O memory 96
deæcribed in connection with Figure 16. Resistors 1532-1536
connected to a positive source of voltage, in the preferred
embodiment, at terminal 1537, are for similar purposes, as
. . .
~i6 resistor 1531 which is connected to a positive source of
~r
;~: 20 voltage, in the preferred embodiment, at terminal 1538.
Resistor 1530 is connected to a positive source of voltage,
. ~,~ .
:~` in the preferred embodiment, at terminal 1540 and is used as
. an inactive logic high input to latch circuits 1508 and 1509..r
;~ . Since the apparatus of Figure 15 is interconnected
25 in the complex fashion clearly set out in the drawing of
. Figure 15, including interconnections between pin numbers for
. the various circuits and apparatus and interconnections
,,
between the apparatus described with respect to Figure 15 and
. the remaining figures, as indicated by the numeric and
` alphanumeric interconnection designations, no further detailed - ~
i ~ description is included here.
'~( .'
~ .' ' , ,, ._
' 104524~
1 With respect to Figure 16, memory element 1601, in
~ the preferred embodLment a MOS ROM, comprises input/output
-~ memory 96 of Figures 7 and 9. Further, memory elements 1602-1606
comprise instruction memory 92 of Figures 7 and 9, and in the
, 5 preferred embodiment are also MOS ROM elements. Memory 94
of Figures 7 and 9 are embodied in memory element 1607-1614 of
` Figure 16, and in a preferred embodiment consist of MOS RAM
: . .
` circuits. Resistor 1662, connected to terminal 1661, and
;! resistor 1663, connected to terminal 1664, and in the preferred
10 embodiment with both terminals connected to a positive source of
~- voltage, are used as "pull-up" resistors to insure adequate
high levels of input to pin 14, the select line, of ROM circuit
. ~~
1601. Resistor 1663, connected to terminal 1664, is also used
-~' in a similar fashion as a "pull-up" to pins 15, the read-write
15 terminals of R~M circuits 1607-1614.
OR gates 1615-1622 serve to multiplex inputs from
an auxiliary external memory onto the parallel data bu~ 86,
. .,.
- ~ and æ e thus necessary only in an enhanced system with anauxiliary memory. -AND gates 1623-1630 are parallel data bus
20 drivers which serve as buffer amplifiers to gate memory data
~`; onto the parallel data bus 86. Terminals 1635-1643 are, in~- the preferred embodiment, connected to a positive source of
voltage and to resistors 1645-1660 which are again used as
~pull-up~ resistors to insure that undriven auxiliary memory
25 input lines or the undriven parallel data bus will return
:s ~ -
Y to an inactive high state.
... . . . .
.
S
j, F . , . .. ~
.:
`'1~ ~'
.~ ~ ` , . . , ,, . ~ .
~ ~ .,
i
`` 10452~8
:.~ 1 Since the apparatus of Figure 16 is interconnected
. . .
- in the complex fashion clearly set out in the drawing of
. . .
` Figure 16, including the interconnections between pin numbers
for various circuits and apparatus and the interconnections
5 ~etween the apparatus described with respect to Figure 16 and the
. remaining figures, as indicated by the numerical and
alphanumerical interconnections described, no further detailed
~.............. description is included here.
,:.,f It can now be appreciated that Figures 15 and 16
~ 10 represent memory 90 as shown ln Figures 7 and ~ except for
.~Ei. I/O address decoder 916 which will be described hereinafter in
: r~ , .
Figure 18.
~` With respect to Figure 17, this figure shows the
logic circuitry comprising the preferred, practical embodiment
~ 15 of code~/decoder 88 of Figures 7 and 10. Figure 17 then shows .
.. ~ a large scale integration ~LSI) MOS circuit 1730. This LSI
circuit contains instruction address register 1002, memory
~ address register 1006, arithmetic and logic unit 1009, accumulator
:
1012, general purpose register 1018, return stack 1022, a
~ 20 portion of instruction decoder 1026, I/O address 1030, and
``~: condition flags 1034 which are identified and described in
. ~
~ ? f connection with Figure 10. The various internal states o
` `~ 'f`'
~- this LSI circuit are decoded in decoder circuit 1728, which
provides urther instruction decoding and timing information
.
25 to control transfers onto the parallel data bus 86 of the ~ ;
system according to the present invention. OR gates 1720 and
.
` 1722 together with their respective ~pull-up" resistors 1767
, . ,
~ ~nd 1768 as returned to terminal 1756, a positive v~ltage
., .
~n the preferred embodiment, comprise a flip-flop circuit which
stores an initialization restart command to the coder/decoder 88 of
. -7' ' . ' .
- 12~ -
. .
.,
;.
, ,
SZ48
1 the present invention. Thii~ flip flop is set ~y AND gates 1706
~l which gate is in turn clocked by clock phase 2 described ~elow
;, in reference to Figure 18, and gated by OR gate 1712, which
.; includes three inputs. One of the inputs to OR gate 1712, to pin 1,
. 5 is used to start coder/decoder 88 at the time power is
applied to the system through power-up start circuitry
, . .
.~ gates 1814, 1826, and 1842, described hereinafter with
:~. reference to Figure 18. A second input to O~ gate 1712,
- on pin 2, is driven by AND gate 2108, again described
~......... 10 bereinafter with reference to Figure 21. A third input
~ to OR gate 1712, on pin 13, is driven by AND gate 1702 in
.~r~.~ conjunction with its "pull-up" resistor 1772 connected to
terminal 53, and again in the preferred embodiment to a positive
.~ source of voltage. This AND gate 1702 is used only for
.~. 15 connection to an external console, thus is used for an ;:
enhanced system, and thus is not necessary in the basic system.
j ~ Resistor 1771, connected to terminal 1752 and
-~ ~ thus in the preferred embodiment to a positive source of
voltage, and resistor 1770,:similarly connected by means of
20 terminal 1754, are used to return the inputs of AND gate 1702
. in the event that an external console is not connected.
.~ . The flip-flop circuits 1720-1722 are cleared by AND
gate 1704, which is in turn clocked by clock phase 2 described
`~ below in reference to Figure 18, and gated by a signal from
~,. 25 decoder circuit 1728 and by a synchronization signal from
LSI circuit 1730 through inverters 1708 and 1710. Resistor
~ 1773 connected to terminal 1751, and in the preferred embodiment
~ to a positive source of voltage, is a ~pull-up" resistor for
$:`: . .open collector inverter i708.
. ,, -- ~,.
.,, 1~1
i~ .. ....
.. , j , . . . . ..
',:1 .
~ .,, , ''' ' '`
~ \~
:~ 11)45Z48
, .i,
AND gate 1718, with ~ts associate~ "pull-up" resistor
',~ 176~ connected to terminal 1755, and in the preferred embodiment
,~' ' to a positive source of voltage, is used to inhibit operation
.~ .,
!~"`'`; of coder/decoder 88 in the event that other coder/decoders
5 88 are used in an enhanced system where several coder/decoders
i 88 are contending for the parallel data bus 86, and thus AND
gate 1718 is only necessary in an enhanced system.
Translation of voltage and current levels from
;,. ~ ,~
the parallel data bus 86 to those levels used by LSI circuit
0 1730 is accomplished by bus driver circuits 1742-1745, which are
,; ,:3,
gated by AND gate 1714 and 1716. These bus driver circuits,
comprise the preferred, practical embodiment of bus arivers
"i~3i~` 1000 as described in connection with Figure 10.
''~ "Pull-up" resistors 1759-1766 connected to terminal
15 1757, in the preferred embodiment connected to a positive
`Fr~,~ source of voltage, provide further enhancement of the voltage
levels to LSI circuit 1730. Resistor 1758, also connected to
terminal 1757 is a "pull-up" for terminals 15 of bus driver
:,',;^': circuits 1742-1745.
The quadruple latch circuits 1738-1741,comprise
. the input address register to address decoding logic such
.~, .
as memory address decoder 912 of Figure 9, and latch circuit
^~ . 1738-1741 are used to prestore memory addresses gated, from
':~ parallel data bus 86 for loading into the system address
~- , 25 register at the appropriate time determined by control functions
`~ ' within the ~resent invention.' Thus, input address register
,,, -comprised by latch circuits 1738-1741 correspond to input
.. , 918 as described above in connection with Figure 9. Address
'v~
~','
:f
:~.
104SZ48
1 data to this input address register is gated at the appropriate
time by signals from decoder 1728 throu~h OR gate 1732/ and
by a synchronization signal from LSI circuit 1730 through inverters
:; 1708 and 1710.
The logic network including AND gates 1724, 1726
and 1734, and OR gate 1736 generate request signals to the
~:s, timing and control section of the present invention,
.~ as set forth in Figures 18 and 19, and these AND gates are
.`.. ~ necessary only in the event of an enhanced system using multiple
~ 10 coder/decoders 88. Thus, this logical network woùld not be
. necessary in the impiementation of a basic model.
Thus, since the apparatus of Figure 17 is interconnected
.~ ~ in a complex fashion clearly set out in the drawings of Figure 17,
including interconnections between pin nunbers for the various
15 circuits and apparatus and interconnections between apparatus
, ~ described wi.th respect to Figure 17 and remaining figures,
.7 S-~ as indicated by the numerical and alphanumerical interconnections
:i ~ designated, no further detailed description is included here.
: ~ - ~ith respect to ~igures 18 and 19, *hese
20 figures show the timing and control logic forming a
~ ~ practical, preferred embodiment of timing and control 124
:~. of Figures 7 and 11 and I/O address decoder 916 of ~igure 9.
'~. The basic timing source for the system is the
:~; crystal oscillator 1102 of Figure 11, and consisting
~r 25 of 8.57 MHz crystal 1802, capacitor 1892, inverters 1804 and
~ . 1806, and resistor 1884 connected to the junction of inverters
1804 and 1806, resistor 1885 connected to terminal 1874,
- and resistor 1886 connected to ground, designated 1895. l~erminal
..~ . 1874 in the preferred enbodiment.is connected to a source of pl~5;ri~lE
voltage. T~e output of oscillator 1102 is then divided in the SCQI4
1 23
:~ :
:, ,
: `
~ 1t)452~8
. 1 of 11 counter comprised by flip-flops 1816-1819 and the counter
.~ control logic AND gates 1808 and 1810 and OR gate 1812 to a
; . . frequency of 779 KHz. The output of this counter is then decoaed
~i into clock phases by AND gate 1830 which is amplified in
5 inverters 1862 and 1846 to provide phase 1, by AND gate 1832
which is amplified in inverters 1864 and 1848 to provide phase 2,
`:;
:~ by AND gate 1834 to provide an early phase 2, and by AND gate 1850
. to provide a late phase 1. Resistors 1888 and 188g, connected to
terminals 1876 and 1877, respectively, provide the high level
10 signals to drive ISI MOS circuit 1730 of Pigure 17.
.i~ OR gates 1814 and 1826, together with the resistive
~,
~'~. capacitive network 1882, 1883, and 1891, the resistive, capacitive
.. .
~. network 1879, 1880, and 1890, together with terminals 1872
": ~;
and 1873 comprise a power on start flip flop which generates
15 a short pulse as power to the system is turned on. This short
pulse signal is amplified in inverters 1860 and 1866 to provide
, ~ .
~ a system master reset signal~ AND gate 1842 senses an internal . .
: ~ ~top state in the coder/decoders 88 and provides a start signal
to initialize and begin all operations of coder/aecoder 88.
20 Resistor 1881 and its associated terminal 1871 and resistor 1878
., .~ .
~: and its associated terminal 1870 provide "pull-up" operation
i to the open collectors of OR gates 1814 and 1826. Resistor 1887
.~ connected to supplied terminal 1875 is used in connection with
i; an enhanced version of the present invention wi.th an external
: 25 ~onsole input, to gate 1822 in order to pull it up or urge it to
-~ the inactive high state when the console is not connectea.
.. . .
.,, . - ~, .
:: - - . .. . - . .. - ..
.... .
" ~ ~
:r .
. ,..
.
.~
.~,
.,~, , .
~ 1~)45Z413
.
` 1 OR gate 1836 provides a read enable signal for reading
memory and for input operations. This read enahle
fsignal together with AND gate 1820 and OR gate 1838 drive
AND gate 1852 which switches the coder/decoder 88 bus driver
`'~ 5 circuits 1000, as expressed preferably as circuits 1742-1745,
;~ to the receive state. AND gate 1868 also us~s this signal to
- gate data and status inputs.
The logical network consisting of AND gates 1822
`-~ and 1854 along with OR gate 1840 provides a memory gating
10 signal to allow data to pass from the memory to the coder/decoder
88. AND gate 1844 switches the coder/decoder 88 bus driver
~` circuits 1742-1745 to the transmit state, and AND gate 1856
and inverter 1897 ga~e output data and command information.
~ ~3 ~
AND gate 1858 provides a write signal to data memory. AND
15 gate 1824 and inverter 1828 are driven by input/output decoder
: ;i.,~
circuit 1934, discussed hereinafter in connecti~n with Figure 19,
and comprise input/output address decoder 916 described
., .
~ hereinabove in connection with Figure 9.
.~
In Figure 19, the main timing chain for the system
20 is contained in quadruple latch chips 1908 and 1909. The
proper starting of this timing chain is assured by the logical
, network consisting of circuits 1901 to 1904. A request for
input/output or a memory operation from request register 1926
~' through OR gate 1928 triggers advancement of the timing chain
~' 25 through ~ND gates 1906 and 1907.
Further, the inverter 1910 amplifies a ready signal
,.,
from an external console, if one is desired, and thus is used
only in the enhanced version of the present invention. The
AND gate 1912 and the logical network consisting of gates 1914-1919
` comprise a priority arbitration network which, again, is used
" ..
j ~ J 2 ~
l .................. . ,~ _
.:, ~
..~ i,
.. , ~ ' .
:~ Lo45Z48
only with an enhanced system according to the present invention
in which multiple coder/decoders 88 are utilized, This network
provides inputs to request register 1926 whose second rank is
~, permit register 1930. Signal inputs whlch are not used in
5 the basic system are forced to the inactive high state by
npull-up" resistors 1940, connected to terminal 1936, resistors
1941-1943, connected to terminal 1937, resistor 1944, connected
to terminal 1938, and resistors 1945 and 1946, connected to
terminal 1939. The presence o a request is sensed in OR gate 1928,
10 and the request register ~926 is clocked by AND gate 1920 and --
~ cleared by AND gate 1921. The permit register 1930 is also clocked
; ~
by AND gate 1924.
, ~,,
Decoder 1934 is used to provide input/output decoding
to the input/output memory 96 of Figures 7 and 9 and also to
15 an external console, if present in an enhanced system. Further
decoding to this circuit is provlded by AND gate 1932. Thus,
^ ~ decoder 1934 functions as I/O address decoder 916, in conjunction
with AND gate 1932.
~Since the apparatus of Figures 18 and 19 is interconnected
. ..
20 in the complex fashion clearly set out in the drawings of Pigures
18 and 19, including interconnections between pin numbers for
~`- various circuits and apparatus within the figures andinT~c~n~c~ionS
- - between apparatus described with respect to Figures 18 and 19 and
~. *he remaining figures, as indicated by the numeric.al and alpha-
::3
25 numerical interconnections described, no further detailed descrip-
tion is included here.
,~.~ . . - .
,
. ~,.~ .,... ~.
" .. ~ ....~
.
:~ 104~S248
. , j .
~ 1 With respect to Figures 2Q, 21,,and 22, these
'~ figures show the I/O control logic forming a preferred,,
' practical embodiment of input/output control 128 ~hown
'~ in Figures 7 and 12.
In Figure 2C, the serial ciocking signals to
. ~
-' ' controller side converter 56 are ge~erated in elements
, 2002-2005. Counters 2004 and 2005 divide'the system clock,
as generated at 779 KHz according to the description of Figurel8~1~
,~l a frequency below 40 KHz acceptable by the device being controlled.
~,
~ 10 Comparator 2002 and flip-flop 2003 are used to strap counter
,~ 2004 for precise adjustment of the output frequency. This
,~i adjustment is accomplished by optional jumpers connected
.-1. .
~ ' between connection 2030 and one of the connections 2031-2034
. :.,-.;
and by optional ~umpers connected between connections 2036-2038
~,- 15 and connection 2035, which is grounded at ground connection 2040,
or connection 2039. For example, the clock frequency generated
in Figure 18 is 779 KHz, and by the connection between junction
points 2030 and 2032, and a connection between junction
.: ~.~ , .
points 2035, 2037, and 2038, and a connection between junction
20 points 2036 and 2039, the frequency of clock generator 1208 is
~i - adjusted to be 19.47 KHz,
'`'''- Inverters 2006 and 2008 ,amplify the master reset
~-- signal generated by the power up circuitry of Figure 18 and
'~- clear this clock to insure proper start of conditions. -;
~' 25 St~rt-stop control to this clock is provided in the logical '~
-.:,
'~ network consisting of gates 2101-2104, described in connection
'~ with Figure 21 hereinafter.
, . -
" ~ .
l2 ~ ~
, ~,
. ;~
:'~, ' .
)
. ~045Z48
.;.
1 The EIA levels to the modem and the controller
are provided by EIA output converters 2022-2024, which
correspond to converters 56 and 114 as described in connection
with ~igures 7 and 12. These converters are driven by the
5 I/O latches 2010, which correspond to I/O latches 1206 in Figure 12,
and proper signal levels are obtained through inverters 2016 and
2018. AND gate 2019 inhibits the controller side clear to
~, send signal when the controller request to transmit signal is
turnedS off or not present. The required drive voltages to these
10 converters are supplied by terminals S0, connected to a negative
supply in the preferred embodiment, and terminal 51, connected
, ~, .
to a positive supply in the preferred practical, embodiment.
The I/O latches 2010 are gated by AND gate 2020.
.. ~-.~ , : -
O decoding occurs in decoder 2014, ana output control
15 information is gated by AND gate 2026. Timing for this
~ AND gate 2026 is provided in inverter 2012. Inverter
`~ buffer 2028 buffers the receive condition signal to provide
the necessary fan out or current capabilities.
Further with respect to Figure 20, resistor 2045
20 connected to voltage supply terminal 2044, receiving a
... . .
positive five volts in the preferred embodiment, provides
a positive five volt "pull up" to inputs on circuits
.... . .
2010 and 2003 and 2002, and resistor 204?, connected to a
milar terminal 2046, provides a "pull-up" to circuit 2002.
.~
With reference to Figure 21, an input/output
restart condition is detected by logical network 2106-2109,
,.. . .
which is used to set the input/output restart flip-flop 2110.
This restart signal is combined with permit information in
AND gate 2112 and inverter 211~ and is used to iset the coderjdecodser
.' ' '~,.~ ~
" 1045Z48
.. ,: .
, 1 restart flip-flop 1720-1722 and gate the necessary restart
. , .
instructions onto the data bus 86 through bus drivers 2125-2127.
System status information is provided to data bus 86 through
bus drivers 2128-2139, and EIA converters 2116 and 2117 change
~ 5 input data levels to the proper logic levels for gating onto
"~ ` data bus 86 through bus drivers 2132, 2129 ,2130.
'.'; 1
'' Noise on the input data signals to converters 2116
~ and 2117 is filtered by capacitors 2154-2158, as is conventional.
~ Flip-flop 2118 delays the input request-to-transmit
~- 10 signal by one serial clock period to prevent pre,mature clearing
~l of the shift register 2501-2502.
'~, Bus drivers 2128-2131 are gated by AND gate 2120,
.~ and bus drivers 2132-2139 are gated by AND gate 2124. In~erter
:,~
,,~ 2122 inverts the controller side send data signal to the proper
-~ 15 level. AND gate 2119 provides an output to coder/decoder 88
:
~ when both FIFO 66 and output shift register 70 of Figure 14 are
. . .
~" empty.
'~, Signals which are not used in the basic system are
. -~,.. .
',f` returned to an inactive, logic'high level by ~pull-up" resistors
,'',1 20 2152 connected to terminal 2150, and 2153 connected to terminal
'`~ 2151.
. ~.i
Logic network 2iOO-2105 provides start/stop control
to the clock counter 2002-2008 to prevent transferring data
A ~nto or out of FIFO stack 66 when it is full or-empty, respectively.
. ~; 25 With respect to Figure 22, a variable speed controller
'~ ' side serial clock may be selected by means of option block 2208.
is option block allows the connection of extra stages in counter
2206 in order to drive clock counter 2002-2005, described in connec-
,tion with Figure 20, at a lower frequency. Normal or variable speed
,~q
.
.~'~ ~ '', . . ...... . . .
~` 10452~8
. . .
1 block options are multiplexed through AND gates 2210 and 221i
.
'~''J~ and OR gate 2212. The slow speed condition, when selected, is
.. . .
"3~ ' ' gated in logical network 2201-2203 and buffered in flip-flop 2204
to insure proper wave shape of the slow clock signal.
.
~Y 5Unused input to flip-flop 2204 is again returned
: .
~ to an inactive, logic high through resistor 2226 connected
. . .
to terminal 22~0. Resistor 2228, connected to terminal 2224,
^ provides a "pull-up" for AND gate 2119.
Since the apparatus of Figures 20, 21, and 22 is
10 interconnected in the complex fashion clearl~ set out in the
. ,~, ~- . . .
drawings of Figures 20, 21, and 22, including interconnections
between pin numbers for the various circuits and apparatus and
~'``'`L~;^ ' interconnections between the -apparatus described with respect
-~ to these figures and the remaining figures, as indicated by
Y-~ 15 the numerical and alphnumerical interconnections described,
~; no further detailed description is included here. -
With respect to Figures 23 and 24, these figures
;~ show the logic circuitry forming a preferred,
practical embodiment of input/output device 52 of Figures 7
- 20 and 13.
In Figure 23, modem side FIFO 102 is shown as
~` including FIFO circuits 2330 and 2331. The input shift
;~
register 100, as shown in Figures 7 and 13, is-designated -
2324 in Figure 23, and output shift register 106 of Figures- 7
25 and 13 is designated 2350 in Figure 23. Gates 23~1-2312
comprise a multiplexer to the input shift register 2324 - ~`-
`~ to allow a selection of either the lower order four bits or
~A .' the higher order four bits when transferring data from parallel
data bus 86 to FIFO 2330 in an output mode.
,~,j . .
.. ..
~ - 130 -
;f~ 7 ~ ',,
.'~'-' . ' ' ~ ' .
104SZ~3
~ 1 ~IA converter 2328 converts signal levels on
.~ the modem side serial clock receive, serial clock transmit,
;~ and read data s-gnals, in a manner explained hereinbefore.
, -1:
~ Input signals to converter 2328 are filtered by capacitors
``1 5 2363-2365.
... ~, Data input to coder/decoder 88 from the mod~n
. ~
~.i side output shift register 106 is inverted in inverters
`~ 2342-2344, and gated onto data bus 86 through bus drivers
:~5- 2346-2349, comprising bus drivers 1302 of Figure 13.
:5~
~- -.10 Bus drivers 2346-2349 are under the control of AND gate 2340.
Gates 2318-2322 provide an input to flip-flop 2334 which is
~:~ a one bit extension of input shift register 2324. Parallel
: ~ or serial mode of the input shift register is controlled
: by OR gate 2323. Quadruple latch circuit 2316 stores the
- 15 synchronization code and forms synchronization logic unit 1304
;l ~. of Figure 13... Quadruple latch circuit 2316 is gated by AND
gate 2314, and a comparison between the contents of quadruple
latch circuit 2316 and the contents of input shift register
l ~ 2324 is made in comparator 2326.
., :`~Y 20 Resistor 2361 and its associated terminal 2360,
provide Upull up" to the open collector outputs of comparator ~.
2326. When comparison is achieved,.the in-synchronization
~-. ~lip-flop 2352 is set. The receive/transmit status of the
~- modem side FIFO 102 is indicated b~ the content of flip-flop 2336.
~-. .25 AND gate 2332 proYides a master reset signal to this receive
flipss-flop 2336, as well as to FIFO circuits 2330 and 2331 and
~utput shift register 2350.
~,.. . ..
l3l
. ~5~s.~5.~
. ~
. ~ ...5
~:: ~.
.' ~,,'
.~ ~ . ` ` .
; 10~5;~48
.,:,, 1 Inputs to the circuits of Figures 23 and 24 are
: . ,
:,,,' "pulled up" by resistor 2362 and terminal 2360,.connected
," ~1 .
,,,~ to a positive five volts in the preferred embodiment of the
:: ~
`';t . present invention.
~ S In Figure ~4, quadruple latch circuit 2402 is
,, useA as a sequential circuit to recover both the leading
.,
: edge and the trailing edge pulses from the modem side serial
,~il clock receive and serial clock transmit signals. The logic
`~i`? network consisting of gates 2422-2427 combines this information
,~ 1~ with output commands and a cloc~ signal to, generate clock
... .
~ pulses to the modem side input shift register 100, as shown in -~
.~ .!: , .
",~ Figures 7 and 13. AND gate 2425 in this network also provides
.~- a parallel enable signal to input shift register lOO:to allow
. . .
loading of parallel input information. Inverters 2428 and 2430
,~ , 15 are used to invert input/output decoder 2014 active-low signals
described above to the active-high levels required by multiplexer
~ AND gates 2301-2308. The logic network 2432-2434 is used to
~ provide the empty condition status signal for the modem side
~: FIFO iO2.and *o generate the empty restart signal from the modem
~, 20 side FIFO 102 to the coder/decoder 88. The modem side output
hift register 106 is clocked by logic network 2406, 2420, and
2440-2441.
Fli~-flops 2436-2438 comprise a counter which counts
.' the number of shifts in the modem side output shift register
,,,- 25 106, ~s shown in Figures 7 and 13. This counter comprised.by
flip-flops 2436-2438 is cloc.ked by system clock, phase 2,
. ~ .
through inverter 2404,,and cleared by logic gates 2408 and
409. The counter is enabled by AND gate 2406, and can be preset to
,~ indicate full status by gates 2412 and 2413. AND gate:2410 also
:`, forms a part of the counter logic.
. . ~ . i~ . , . ~ . ,
~ -- l3
., ~
~ ~'
. , ~ .. .. ... . . . .. .. .... . .
~0~52~
Quadruple latch 2444 .is used to store status
~ information for the modem side input~output circuitry 52
.. and command information to FIFO 102 and:shift registers 100
`. and 106 as shown in Figures 7 and 13. AND ~ate 2446 provides
5 a shift out signal to FIFO 102, and AND gate 2450 provides a
shift in signal to modem side FIF0 102. AND gate 2448 generates
a modem side FIFO 102 full reset signal to coder/decoder 88,
~ and AND gate 2452 is used to preset input shift register 100,
.~ flip-flop 2334.
AND gate 2414 combines shift count information from
,.~
::~ counter 2436-2438 and FIFO 102 not empty status information
to initiate a co~mand to transfer data fram FIFO 102 to the
~^. output shift register 106, which is buffered in latch 2444.
Logic network 2416-2418 senses when input shift register 100
~-~ 15 is full, and initiates a signal to transfer data from input
~ .,
~ shift register 100 to FIFO 102. This signal is also buffered
:~ in latch 2444.
' Inverters 2~42 provide a ~ignal to an
externally attached console, which is used only in an
`~ 20 enhanced system, and is not necessary in t~he basic embodiment
- described here.
Since the apparatus of Figures 23 and 24 is
interconnected in the complex fashion clearly set out in
. the drawings of Figures 23 and 24, including interconnections
25 between pin numbers for various circuits and apparatus and
. interconnections between the apparatus described with respect
to Figures 23 and 24 and the remaining figures, as indicated
by numerical and alphanumerical interconnection designations,
.. no further detailed description is included here. -.l . .
` .`. 1~
. ~
, . . .
`: :
~ ~104SZ48
, 1 With respect to Figures 25 and 26, these figures
, show logic circui* y forming a preferred, practical embodi- .
ment of input/output block 50 o~ Figure 7 and Figure 14.
~` In Figure 25, controller side FIFO 66 comprises FIFO
5 circuits 2503 and 2504. Shift registers 2501 and 2502
), together with flip-flop 2530 comprise input shift register
62 of Figures 7 and 14. Shift registers 2505 and 2506 :'~
comprise output shift register 70 of'Figures 7 and 14.
i
'~ Inverters 2508-2514 invert signals from output shift register
. 10 70 to the proper levels for gating onto data bus 86 through bus
. drivers 2516-2523, comprising bus drivers 1402 of Figure 14.
Bus drivers 2516-2523 are clocked by AND gate 2550. :
The logic network 2524-2527 forms an input multiplexer
7'` used to gate controller side send-data or output-data into the
~ 15 highest order flip-flop 2530 of input shift register 62. AND
.~' gates 2542 and 2544 provide FIFO output request and input
; ,,~ request data to indicate the empty o,r full status of controller
'' ,!~,'
j., side FIFO 66.
,. ~' -La~ches '2532 and 2533 contain the synchronization ' :~
.,,.~
`~t`'`' 20 code and form synchronization logic 1404 of Figure 14. Latches
~ 2532 and 2533 are gated by AND gate 2540, and the contents of
.,.~;~ -. .
these latches are compared with the contents of input shift
' register 62, in the form of registers 2501 and 2502, in
~, comparators 2534 and 2S35. ~ .
.'r 25 . ~esistor 2563 in connection with terminal 2561
...~ .
~id. ~gain forms a ~pull up~ for the open collector outputs of
. ~ ~
,; . co~parators 2534 and 2535 in a manner described hereinbefore.
~, -When comparison is aohiev d, the in synchronization flip-flop
2548.is ~et.
13
t~ Q ~
~;`.";~ ' ' '
.'
, . ~ .
``` ~045248
~ 1 AND gate 2538 is usea to generate a master reset
~ ,
1 signal to the in synchronization flip-flop 2548, and to
`~ controller side FIFO 66, circuits 2503-2504, and its
:
corresponding output shift register 70, circuits 2505-2506.
Flip-flop 2546 contains the receive/transmit status
~ of controller side FIFO 66. Furthe~, unused inputs to the
`~ circuits in Figures 25 and 26 are returned to the inactive,
,l logic high state by resistor 2562 connected to terminal 2560,
and thus to a positive five volt potential in the preferred
.~1 I 10 embodiment.
In Figure 26, logic network 2634-2636 provides
f ~ a restart signal from controller side FIFO 66 to coder/decoder
88, and OR gate 2638 provides restart condition status signals ~-
to coder/decoder 88. The logic network 2626-2632 forms clocking
15 signals to controller side input shift register 62, and AND
gate 2630, in this network, furnishes the controller side
{~ converter serial-clock-transmit signal.
~ Flip-flops 2604 and 2605, which are driven by
`~1 controller side serial clock through inverter 2602, form
i~ 20 a sequential circuit which recovers the leading edge and
the trailing edge pulses from the controller side serial
clock. The controller side input shift register 62 is
clocked through logic gates 2642 and 2643.
AND gate 2608 is used to enable controller side
25 output 6hift regis~er 70 clocking and also controller side
serial-clock-receive signals through inverter 2640 when
` the EIA status register 2010, described Ln connection with
:~ .
::~
Figure 20, contains a true carrier-on flag. This flag
~indicates to the controller that received data is available
from output shift register 70. ~ ~-
3 ~ ~
.{ ~ 3~
::`
'.s,j
.~ . ,,
:,~ . ,
;.... .
1045Z48
1 Counting of the numbex of shifts in the output
shift register 70 occurs in counter 2616 which is driven by
the logical network 2608-2614.
t Quadruple latch 2646 contains controller side
~, 5 FIFO 6fi status information, and latch 2646 is used to
generate commands for shifting information within controller
side FIE''O 66. AND gate 2648 provides the shift-out signal
and AND gate 2652 provides the shift-in signal to controller
~ side FIFO 66. AND gate 2654 is used to ~et the highest order
..,~..
;?~ 10 flip-flop 2530, described in connection with Figure 25, of
- the input shift register 62.
~, AND gate 2620 monitors counter 2616 and the status
bit in latch 2646 which indicates that controller side FIFO
;~ 66 is not empty. Further, AND gate 2620 generates a signal
, . .
15 which permits transfer of data within controller side FIFO
66 into output shift register 70. This signal from AND gate
.~
2620 is buffered in latch 2646.
Transfer from input shift register 62 to
~~ controller side FIFO 66 is initiated by logic networ~
20 2621-2624, which is again buffered by latch 2646. Inverter
2618 is used as an amplifier for system clock phase 2.
Since the apparatus of Figures 25 and 26 is
` interconnected in the complex fashion clearly set out in the
drawings of Figures 25 and 26, including interconnections
~ 25 between pin numbers for various circuits and apparatus
.; and interconnections between apparatus described with
':t, respect to Figures 25 and 26 and the remaining figures, ~ ~
as indicated by the numerical and alphanumerical interconnections
. described, no further detailed description LS included here.
. l,3~
~ , ,
:
. , .
,~
, ~'' ' .
~ 10~524t~
TABLE V
GLOSSARY OF INTERCONNECTION ABBREVIATIONS FOR
-. - FIGURES 15-26
~:i . TERM .FULL MEANING OF TERM FIG. OTHER FIGURES
~ - : ORIG. .. _
-' MADOP MEMORY ADDRESS BIT 0 POSITIVE . 15 16, 18-21,a3,25
, to
~ MAD15P MEMORY ADDRESS BIT 15 POSITIVE 15 16, 18-21,~3~5
` ' MAD12N MEMORY ADDRESS BIT 12 NEGATIVE 15 18, 21
to
: MAD15N MEMORY ADDRESS BIT 15 NEGATIVE 15 18, 21
TS00 TIMING SELECT 00 15 16
!~ TCSl TIMING CHIP SELECT 1 15 16
to
-~ TCS7 TIMING CHIP SELECT 7 15 16
SABON SYSTEM ADDRESS BUS 0 NEG. 17 15
;- to
jt~` SAB15N SYSTEM-ADDRESS BUS 15 NEG 17 15
~,'J' TPl TIMING PERMIT 1 19 15, 17, 21
l XPH2E XTAL CLOCK PHASE 2 EARLY 18 15, 19, 24, 26
~; XP2T XTAL CLOCK PHASE 2 TO TINING. 18 15, 19, 21
:~:...... T22P TIMING STATE 22 POSITIVE 19 15
. SDB0 . SYSTEM DATA BUS BIT 0 17 16, 21
`~ to
-~t:. SDB7 SYSTEM DATA BUS BIT 7 17 16, 21
MMI0 MEMORY MULTIPLEXOR INPUT BIT 0 16
to
~ MMI7 MEMORY MULTIPLEXOR INPUT BIT 7 16
TGMIN TIMING GATE MEMORY IN NEGATrVE 18 16
~. TRW TIMING READ/WRITE 18 16
. TGM TIMING GATE MEMORY 18 16
UWlN CPU NAIT #1 NEG 17 19
I URlN CPU REQUEST #1 NEG 17 19
~ ~ UTlIN CPU INTERNAL STATE TlI NEG 17
~ USTOPN CPU INTERNAL.STATE STOP NEG 17 18
XPlT XTAL CLOCK PHASE 1 TO TIMING 18 17, 19, 24, 26
. TWTN TIMING W~IT CONDITION NEG 19 17
. PWR POWER INTERRUPT CONDITION 18 17
~ FITP FIFO INTERRUPT 21 17
! TCPB TIMING CP TO BUS 18 17
TBCP TIMING BUS TO CP 18 17
TRQlN TIMING REQUEST REG 8IT 1 NEG 19 17
`~- T22N TIMING STATE 22 NEG 19 17
XPlC XTAL CLOCK PHASE 1 to CPU 18 17, 19
~. XP2C XTAL CLOCK PHASE 2 TO CPU 18 17
-.- XP2N XTAL CLOCK PHASE 2 NEG 18 17, 24
.~ UIC CPU INTERRUPT CLEAR 18 17
`f &MRN SYSTEM MASTER RESET NEG 18 24
~: XPHlL XTAL C~OCK PHASE 1 LATE 18 24, 26
:~ TREI TIMING READ ENABLE INPUT 18 21
; TGIN TIMING GATE INPUT 18 21, 23, 25
`........ IGO TIMING GATE OUTPUT 18 20, 21, 24, 26
T32N TIMING STATE 32 NEG 19 . 18
.~ . FINTPN ~IFO INTERRUPT IN PROGRESS NEG 21 .18
.,,...... )~3~
....
.~;
. .
~'
.'
: ~ l ~
:: :
:;
:
lO~SZ48 .
TABLE V - CONTI~UED
TER~5 FULL MEANING OF TERM FIG. OTIIER FIGURES
~ _ _ ORIG.
,.
TIODCl TIMING I/O DECODER 1 19 18
T41N T~IING STATE 41 NEG 19 18
T42P TIMING STATE 42 POS 19
CRDYN CONSOLE READY NEG 19
TRQ2N TIMIN5 REQUEST REG BIT 2 NEG 19
to
TRQ4N TIMING REQUEST P~EG BIT 4 NEG 19
TP2 TIMING PERMIT 2 19
t~
TP4 TIMING PERMIT 4 19
TIODCO TIMING I/O DECODER 0 19
to
TIODC7 TIMING I/O DECODER 7 19
UW2N CPU WAIT #2 NEG 19
UW4N CPU ~AIT #4 NEG 19
UR2N CPU REQUEST #2 NEG 19
UR4N CPU REQUEST #4 NEG 19
CLKI F8 CLOCK COUNTER INPUT 20 22
F8SC F8 SERIAL CLOCK 20 26
P8MRN2 F8 MASTER RESET NEG ~2 20 21
CLH CONTROL LOGIC EIGH 20 21
F4SD P4 SEND DATA ~El~ OUTPVT) 20 MODEM ~Fig. 1)
F8SCT F8 SERIAL CLOCK TRANSMIT ~EIA OUTPUT)20 CONTROLLER (Fig. 1)
F8RD F8 READ DATA ~EIA OUTPUT) 20 CONTROLLER (Fi~
F8SCR F8 SERIAL CLOC~ RECEIVE (EI~ OUTPUT) 20 CONTROLLER (Fig. 1) 3 i
F8CTS F8 CLEAR TO SEND (EIA W TPUT) 20 CONTROLLER (Fig. i) - ~
F8CO F8 CARRIER ON 20 26 t
FGCO FIFO GhTE CONTROL OUT 20 23, 25
F4RCVN F4 RECEIVE STATE NEG 23,25 20, 21, 24, 26
F8RCVN F8 RECEIVE ~TATE NEG 20 21, 22
F8RCV F8 RECEIVE STATE 25 20, 21, 26
FGOCN FIFO GATE OUTPUT CONTROL NEG 20 23, 25
FIODCON FIFO I/O DECODE BIT 0 NEG 20 21, 23, 24, 25, 26
to
FIODC6N FIPO I/O DECODE BIT 6 NEG 20 21, 23, 24, 25, 26 :~
FCCl FIFO CLOCK CONTROL SIGNAL 1 21 20
F8MRN F8 MASTER RESET NEG 25 20, 26
CLKO F8 CLOCK COUNTER OUTPUT 22 20
-12VDC ~12 VOLTS DC POWER POWER 20, 25
SVPPLY
FO40 F4 OUTPUT SHIFT REG BIT 0 23 20
F8SCTN F8 SERIAL CLOCK TRANSMIT NEG 26 20
12VDC ~12 VOLTS DC POWER POWER 20
SUPPLY
FO80 F8 OUTPUT SHIFT REG BIT 0 25 20
FO8CEN F8 OUT SHIFT REG CLOCK ENABLE NEG 26 20
PBRQTN P8 REQUEST TO TRANSMIT NEG 21 26
F8SD F8 SEND DATA 21 25 . ~
FO8R3 F8 W T SHIFT REG COUNTER BIT 3 26 21 ~
FINTC FIFO INTERRUPT CONDITION 26 21
F8IPN F8 INTERRUPT IN PROGRESS NEG 26 21
FI8CK F8 INPUT SIIIFT REG CLOCR 21
F4CTS F4 CLEAR ~O SEND ~EIA INPUT) ~ODEM -21
(Fig. 1) i
F4RQT F4 REQUEST TO l~ANSMIT ~EIA OUTPUT) 20 MODEM ~Fig. 1)
F8COE F8 CARRIER ON ~EIA OUTPUT) 20 CONTROLLER ~Fi~. i)
)3~
~
. r
. ~ . '
"; ' ~- ' ' ' '.- . ' '' '' ` ' ',' i' ~
' ' - - ~
1045Z~8
:~ TABLE V - CONTINUED
TERM FULL MEANING GF TERM PIG. OTHER FIGURES
~'r ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' 'ORIG. : _ .
~ F8RQT F8 REQUEST TO TRANSMIT (EIA INPUT) CONT- 21
.~ . ROLLER ~Fig. 1)
`~ FO8EN F8 OUTPUT SI~IFT REG EMPTY NEG 21 22
` FRCHR FIFO REV CHA~EL RECEIVER 21
.~ F4CO F4 CARRIER ON (EIA INPUT) MODEM 21
(Fig. 1)
F8SDI F8 SEND DATA INPUT ~EIA INPUT) CONT- 21
ROLLER
` (Fig. 1)
`. . F8FN F8 FIFO FULL NEG 26 21
~ F4ECN F4 EMPTY CONDITION NEG 24 21
`,! F4FN F4 FIFO FULL NEG 24 21
~ F8E F8 FIFO EMPTY 26 21, 22
`~1 F8CTSN F8 CLEAR TO SEND NEG 20 22
` F8CTSEN F8 CLEAR TO SEND ENABLE NEG 22 20
j~-` F4CTSN F4 CLEAR TO SEND NE& 21 22
```, FSCEN FIFO SLOW CLOCK ENABLE NEG 21 22
FGFO4 FIFO GATE F4 OUTPUT SHIFT REG 23 24
`' F4SCRN F4 SERIAL CLOCK RECEIVE NEG 23 24
` F4SCTN F4 SERIAL CLOCK TRANSMIT NEG 23 24
j, F4LH F4 LOGIC HIGH 23 24
F40R F4 FIFO OUTPUT REQUEST 23 24
F4IR F4 FIFO INPUT REQUEST 23 24
~ FI40 F4 INPUT SHIFT REGISTER BIT 0 23 24
1:` . F4MRN F4 MASTER RESET NEG .23 24
~`~ F4HIT F4 SYNCHRONIZATION HIT 23 24
F4ISN F4 IN SYNCHRONIZATION NEG 23 24
F4ISP F4 IN SYNCHRONIZATION POS 23 24
~. F4RCV F4 RECEIVE STATUS 23 24
j`~ F4SCRI F4 SERIAL-CLOCK RECEIVE (EIA INPUT) MODEM 23
~ F4SCTI F4 SERIAL-CLOCK TRANSMIT (EIA INPUT) MODEM 23
.u. F4RDI F4 READ-DATA tEIA INPUT) (Fi 1)
FCKFI4 FIFO CLOCK F4 INPUT SHIFT REGISTER (Fig. 1)
~` FSFI44 FIFO SET F4 INPUT SHIFT REG BIT 4 24 23
.~ F4PEN F4 INP SHIFT REG PARALLEL ENABLE NEG 24 23
FO4CK F4 OUTPUT SHIFT REG CLOCK 24 23
F4SI F4 FIFO SHIFT IN 24 23
~ F4SO F4 FIFO SHIFT OUT 24 23
i F4DN F4 FIFO DUMP NEG 24 23
: FPH2 FIFO PHASE 2 24 23
5.t FIODC5 FIFO I/O DECODER OUTPUT 5 24 23
FIODC6 FIFO I/O DECODER OUTPUT 6 24 23
~ -F4EIN F4 EMPT~ INTERRUPT 24 26
.3 F8BRQT F8 BUFFERED REQUEST TO TRANSMIT 21 20
.
`1 -- ~; --
.' `
d `-
f
r
,
1045Z48
TABL~ V - CONTINUED
TERM FULL MEANING OF TERM FIG. OTHER FIGURES
ORIG. -
. ~
F4EN F4 EMPTY NEG 24
F4FIN F4 FULL INT~RRUPT . 24 26
FGF08 FIFO GATE F8-OUTPUT SHIFT REG 25 26
F8LEI F8 LOGIC HIGH 25 26
F80RN F8 FIFO WTPUT RE9UEST NEG 25 26
FI8FP F8 INPUT SHIFT REG FULL POS 25 25
F8IRN F8 FIFO INPUT REQUEST NEG 25 26
F8HIT F8 SYNC CODE HIT 25 26
F8ISN F~ IN-SYNC NEG 25 26
F8ISP F8 IN-SYNC POS 25 26
F8DN F8 FIFO DUMP NEG 26 25
F08CR F8 OUTPUT SHIFT REG CLOCK 26 25
FI8CK F8 INPUT SHIFT REG CLOCK 26 25
F8PEN F8 INP SHIFT REG PARALLEL ENABLE NEG 26 25
FSFI88 F8 INP SHIFT REG SET BIT 8 26 25
F8SI F8 FIFO SHIFT IN 26 25
F8SO F8 FIFO SHIFT OUT 26 25
F8SCN F8 SERIAL CLOCK NEG 26
F8PH2 F8 PHASE 2 26 25
F8F F8 FIFO FULL - 26
.
.,,j~ .
"''~! Some abbreviations as used in the above Table V
are: -
~ aFIFO" indicates a first in first out register.
-~ "I/O" indicates input/output.
~ ~NEG" indicates NEGATIVE.
`~ ~CPU" and "CP" indicate circuit 1730.
, ;.
~REG" indicates REGISTER.
~XTAL" indicates CRYSTAL.
~F4" refers to modem side FIFO 102.
,i .
~ F8" refers to controller side FIFO 66.
. ;, .
~FI4" refers to modem side input shift register 100.
I ~FI8" refers to converter side input shift register 62.
l ~F04" refers to modem side output shift register 106.
~F08~ refers to converter side output shift reqister 70.
Further, as is now obvious, the term or acronym itself
is listed in the left most column, the full meaning of the term
~ 8 in the next column, the figure in which the signal originates
; ~s in the next column, and other figures in which the signal
; may be found are listed in the right most column.
: .
'j
' - 14~) -
.,~ , .
.~ ; ' .
)
" 1045Z48
.
1 Next, Table VI indicates the interconnections between
the electrical connections indicated in Figures 15-26, aside
- from those interconnections which are indicated upon the figures
themselves. It will then be noted that each electrical connection
~ 5 not indicating a specific interconnection with a connection
; of an adjacent figure, with a like applied acronxm, includes
a two digit number either at the interconnection termination
or inserted within the interconnection, and inserted thus for
no electrical purpose but only for the purposes of illustration.
10 The latter two digit interconnection designations then provide
i~ the remaining interconnections for the electronic circuit shown
~`~` in Figures 15-26 according to the following Table VI where
.. . ..
'',~r signal names are set out in the left most columns, and inter-
. "~ .
connections are set out in the next two columns to the right of
-~ 15 the signal acronyms.
nl~ As set out in Table VI, the designation "Jl" refers
to the logical circuitry shown in Figures 9, 15 and 16. me
-`~ designation "J2" refers to the logical circuitry shown in
s~ Figures 10 and 17. ~he designation "J3 n refers to the logical
20 circuitry shown in Figures 11, 18, and 19. The designation
~J4" refers to the logical circuitry shown and set out in
~ Figures 12, 20, 21, and 22. The designation "J5~ refers to
"?~' . ' the logical circuitry shown in Figures 13, 23, and 24. m e
~` designation "J6" refers to the logical circuitry set out
25 in Figures 14, 25, and 26. The designation "J-7" refers to an
n~ empty test socket, not ~hown.
.
3. ..
Therefore, by way of example, the initial entries
~ to Ta~le VI indicates a connection under the acronym ~SDB4n
`~ where the connection is to emanate-from ~Jl-lOn, which is
the circuitry shown in Figures 9, 15, and 16 and extend to
the electrical connection "J2-28n, which is the circuitry
'JI
7 -
~ ;
: ;~
:
~ 1045Z48
1 as found in Figures 10 and 17. For the specific example,
is is found that the "10" designated interconnection emanates from
. ~ .
-~ AND gates 1626 o~ Figure 16, and is then interconnected to
circuit 1742 on Figure 17.
S Thus, Ta~le VI indicates the totality of inter-
: i~
connections between the circuitry set forth in Figures 15-16,
aside from those interconnections indicated directly on the figures.
. , .. ~ .
;~ These figures also include interconnections to a path of,~ - .
transmission of data, as indicated in Figure 1. Thus, certain
10 interconnections are made to a modem, in the preferred embodiment
. : .
example, such as modem D of Figure 1. Further, certain connections
~i are required to a line controller, in the preferred embodiment
~hown in Figure 1, such as to line controller B. These inter-
-~ connections are not included in the associated TABLE VI, but
15 are clearly indicated on the drawings of Figures 15-26 and
the remaining figures, and may be specifically seen from
,.j~,
;~ Table V, where it is indicated that selected signals originate
in certain figures, as indicated, and appear also in Figure 1, where
a connection to a modem or controller is indicated. Since the
0 purpose and termination of these interconnections are indicated
by Table V, and since these interconnections to the modem and
controller are the normal interconnections to be made between -
a modem and a controller, with the compaction device of the
~ ... . .
,- present invention merel~ interrupting these connections
5and acting as a transparent interface, as discussed above, and
~ince these interconnections to modem and controllers are well
; known to those skilled in the art, no further discussion of
these signals is deemed necessary.
;~ , .,
. ~ .
~ r . . . . ~ .
~ -`', ' ' '
.
1045248
TABLE ~I
~` T22~J J3- 7 T0J2-52 TBCPJ3-64 T0 J2-63
T22P J3- 8 Jl-38 TREtJ3-65 J4-48
TP2 J3_ 9 J1- 8 T~1NJ3-47 ` Jl-65
``, TP1 J3-10 J2-62 - XP2CJ3-54 J2-58
:`. J1- 9 J2-62 TCPBJ3-61 J2-61
~, .
`' J3-10 J4-53 FGOC~J3-66 J5-~2
`i~ .XPH1L . J3-15 J5-22 J5-1l2 J6-46
J5-22 J6-56 ... UIC J3-68 J~-51
` TRQ1N J3-22 J2-50.
TWTN J3-36 J2-72 -9VDCJ4-20 T0 J5-i3
XPH2E J3-46 J1-36 J5-13 - JG
:~!. J3_46 J5-32
J5_32 J6-64 Fo40J5-16 T0 J~- 9
~- J3-48 J4-32 F4FNJ5-20 J~-61
~:.- . J4-32 J6-38 F~ECNJ5-58 J4-63
J6-38 J5-48 F4FINJ5-60 J6-53
~` PWR . J3-50 J2-66 F~EINJ5-62 J6-55
TGM J3-51 Jl-63 F~RCUNJ5-70 J4-59
?, ~ ~GO J3-52 J4_26
J~-26 J5-54
~ J5-54 J6-52
: ~; SMRN . J3-53 .J5-18 ~-
J3-53 ~4-38
`;JUP2N J3-55 J5-34
J5-3~ J6-26
J3-55 J2-60
P2T J3-56 Jl-37
J3-56 J4-~3
2P1C J3-57 J2-59
`1-- 5RW J3-60 Jl-30
`! ~PlT J3-63 J2-34
l J3-63 J5-72
- J5-72 'J6-h2 ~ -
. - , . '~ ~- ' .
, . , .. .
~'
r
~ ' ' ' .. . .. ..
~045Z~8
;' TABLE VI CONTINUED
.
~ .
~8SC J4- 7 TO J6-l~2 ShB3N J2- 4 TOJ1-34
FIODC4N J4-29 J5-40 SAB2N J2-36 J1-43
J5-~0 J6-40 SABtN J2- 2 Jl-42
FIODC5N J4-30 J~-46 SABON J2-38 J1-33
FIODC6N J~i_31 J5-56 SAB11N J2-20 Jl-13
FIODClN J4-33 J6-24 SAB1ON J2-53 J1-14
~'FIODCON J4-34 J6-44 SAB9N J2-t8 Jl-15
FGCO J4-39 J5- 4 - ~- SAB8B J2-54 Jl-16.~'` J5- 4 J6-34 SAB7N J2-42 Jl-20
-~8RQTN J4-68 J6-61 SAB5N J2- 8 Jl-26
FtTP J4-27 J2-65 SAB4N J2- 6 . Jl-19
~-FlNTPN J4-~4 J3-59 SAB15N J?^56 J1-48
~~8co J4-41 J6-58' J2-56 J5- 9
pF8SD J4-52 J6-54 -- SAB14N J2-55 J1-49~10VDC J4-14 ~ower Supply ~10SAB13N J2-24 Jl-50
~:~ ^ ' J4-14 J4-16 ' SAB12.N J2-22 Jl'-51
. , ... .' , . '~:
~'' USTOPN J2-64 J3-49 -'
Z'': UWlN ,'J2-68 J3-37
':' URlN ' J2-70 J3-20
r ~. .
~ . SAB6N J2-40 . Jl-27
~" ~.
:...
Z.' :
. .
, . ~ ... ..
., ,
j
1l)45Z48
TABLI:: VI CONTINUED
SDB4Jl-10 TO J2-~8 SDB2 J2-43 TO Jl~-64
. J2-28 J4-~6 J4-64 J~
J4-46 J6-10 J5-1J4 J6-18
SDB6J1-11 J2-~4 MAD4P J1-18 J5-12
J2-44 J~ 9 J5-12 J6- 6
J4-49 J6-12 MAD7~ J1-21 J5-24
MADl1P J1-12 J3-35 . J5-2~ J6-36
J3-35 J4-37 MAD5P J1-22 J5-14
MUD8P J1-17 J3-44 J5-14 J6- 4
MAD9P J1-24 J3-3~ MhD6P J1-28 J5-26
. J3-3~ J4-35 ~5-26 J6- 2
SDB5 Jl-29 J4-66 MADOP J1-32 J4- 2
J4-66 J6- 9 . J4-.2 J5~ 6
J6- 9 J2-14 J5- 6 J6-28
SDB7 Jl-31 J2-30 ~AD3P J1-3~ J4- 6
J2-30 J4-45 . J4- 6 J5-30
' J4-45 J6-11 J5_30 i6_ 8
:MADlOP Jl-25 J3-30 . MAD13N Jl-39 J3-19
":J3-30 . J4-28 MAD12N J1-40 J3-41
. SDBO Jl-44 J2-32 J3-41 J4-54
J2-32 J4-62 MAD1P Jl-41 J4- 4
. J4-62 J5-38 J4- 4 J5- 8
. J5-38 :J6-21 . `- J5- 8 J6-30
-MAD14P Jl-55 J3-45 . MAD2P Jl-~6 J4- 5
~ SDB3 Jl-57 J2-16 . J4_ 5 . J5-10
t' J2-16 J4-50 . J5_10 J6-32
. J4_~0 J5-50 MAD15P Jl-47 J3-62
- J5-50 J6-16 HAD15N Jl-53 J3-18
~. SDBl Jl-58 J2-26 MAD13P Ji-56 J4-36 - -
-. J2-26 J4-60 -9VDC Jl- 2 Power Supply -9 :
J~-60 J5-36 .Jl- 2 J2-39
. ~5-36 J6-19 J2-39 J4-18
SDB2 Jl-64 .J2-43 J4-18 J4-20
~, . .
:~ ' ~ ''
1~
.~ ~; ' .
~` ~045Z~8
. ~ .
~ABLE VI CONTINt~ED
:"
~ ~ .
hADO J7-53 TO J6-28 IODC5 J7-37 TO J3-27
~MAD1J7-54 J6-30 IODC6 J7-38 J3-28
``., MAD2 J7-55 J6-32 IODC7 J7_39 J3-29
M~D3 J7.-56 J6- 8 ``` FPH22 J7-42 J6-13
~D4 J7-57 J6^ 6 ~22C J7-43 J3- 8
.3MAD5J7~5B J6- 4 T42C J7-44 J3-16
.MAD6J7~59 J6- 2 CT1I1 J7~50 J2-57
.1 MAD7 J7-60 J6-36 .. ~ USTOPN J7-51 J2-64
MAD8 J7-61 J3-44 -- TRE1 J7-52 J3-65
MAD9 J7-62 J4-35 SAB15 J7-28 J5-11
;~. MAD10 J7-63 J4-28 CPSlN J7-46 J2-46
MADl1 J7-64 J4-37
MUD12 J7-65 Jl-52
. ~8~EhN J6- 7 TO J4- 8
~ ~ ~ 13 J7-66 J4-36
?~- . Po80 J6-22 . J4-12
: " MAD14 J7-67 ....... J3-45
FI8CK J6-23 - J4-56
MAD1~ .J7-68 J3-62 .
. .~ - ~8RCV J6-48 J4-13
: SDBO . J7- 5 J6-21
SDBl J7- 6 J6-19 ~8IPN J6-50 J4-42
. SD82 J7^ 7 J6-18 F8SCTN J6-57 J~-11
SDB3 J7- 8 J6-16 F08EN J6-59 J4-65
. r~ SDB4 J7~ 9 J6-10 F08X3 ~6-63 J4~5~.
,~ . F8FN J6-66 J4-51
SDB5 J7-10 J6- 9
- .SDB6 J7-11 J6-12 F08CEN J6-17 J4-24
. . FINTC J6-51 J4~40
SDB7 J7-12 .J6-11
~L~lN J7-14 GND
.~CRENP J7-20 J3-17
~ClNTN J7-30 J2-48
.~ClNTPN J7-31 .- ~J3-58
~.IODCO J7-32 ~3-31
r.IODCl J7~33 J3-43 _
ic, IODC2J7_34 J3-32
~ I9DC3J7~35 J3~33 :
:- IODC4.J7-36 J3-26
,, , ., . , , . . :~
~ .
- . .
IY~
.
;
;
~1)4SZ~8
-
1 Ta~le VII may now be explained. Table ~II sets
forth the complete list of instructions which are stored in
memory 90 and in particular in ROM instruction memory 92 and
ROM I/O memory 96 of Figures 7, 9, and 16. In particular,
5 the program listing of Table VII is set out in five columns,
repeated twice across the page, unless a single five column
representati~n is set out. The first column includes four digits,
the first two of which set out an address which defines the
particular ROM in which the eight bits of logic are stored. The
10 next two digits indicate in which of the 256 locations in the
particular preferred memory circuit the eight bits of logic are
stored. For example, the designation 00 indicates circuit 1606
~ of Figure 16; the designation 01 indicates memory circuit 160S
; of Figure 16; the designation 02 indicates memory circuit 1604
`~ 15 of Figure 16; the designation 03 indicates memory circuit 1603
j~ of Figure 16. Memory circuit 1602 of Figure 16 is not currently
used, except for test, and is intended for an enhanced system.
Further, I/O memory 96 of Figure 7 and 9 and memory
Z circuit 1501 of Figure 16 is lastly indicated in Table VII
;; 20 with the designation 00, also. Since circuit 1501 performs as I/O
memory only, this dual use of designation 00 causes no difficulty.
~, Within each memory circuit, i.e. 1602-1605 of instruction
memory 92 or 1601 of I/O memory 96, 256 unique locations are
allowed by the preferred circuit used, as will be set out hereinafter
25 ln Table VIII. Thus, the last two digits of the left-most column
~ndicate the storage location in the ROM circuitry. The
: . .
next column consists of a decimal point followed by two hexadecimal
digits, eight bits in total logic, which is ~tored in the
location indicated. As is well documented by the instruction
.
' ",
';' ' -
~'.
.
045248
1 manual for the microprocessor 1?30, a single microcode instruction
, may consist of one, two, or three eight bit groupings in one, two,
or three successive addresses.
... .
~;~ The first two columns are the only columns containing
5 information required for the operation of the present invention.
The next three columns contain information as an aid to the
, preparation and understanding of the microcode listing. ~he
;~ information in the second column, in fact completely describes
. .~, I . .
the microcode necessary for operating according to the pre$ent
10 invention, and by referencing the manual published by the
~ manufacturer of the microprocessor circuit 1730, the
.,~,
microcode listing may be completely decoded and understood.
i ' ,r
~; ~ However, for ease of understanding of the present invention,,; .,
~ the right most three columns have been included.
,".~
The right most three columns are an easily read
interpretation of the microcode listing. They define the
operation and function of a microcode instruction in a more
s ~ readable form. In particular, the third column contains
~ ~ a symbol which may be used to refer to the location indexed
;~ ~-~ 20 more easily than using its hexadecimal, base 16, address.
s ~ Since comparati~ely few locations need to be referred to
? " during the assembly process, this column is vacant in many
locations. The fourth column contains the mnemonic for the
., .
` !~ ~icrocode instruction.
The fifth and last column is the address field, -
.~ ; -i .
which is useful in connection with all microcode instructions
which are more than eight bits in length. This column may contain
a ~ymbol for a location, which normally references a symbol
found in the third column, or may-contain an absolute hexadecimal
.,. ~., -........................................ .
., .
: ~ '
"~,~ 1~' ,
.,
,, ~ . -
~; 1045Z48
1 description used as a part of the instruction~ The use of
this ~ield is also defined in the instruction manual ~or the
.,,~, . .
microprocessor 1730.
`~ The only dif f erences from the instructions as set
~,, 5 forth in the manual for microprocessor 1730 and the above
,~j are with respect to the mnemonics, which vary from those
used in the instruction manual as follows: the designation
~; "IC" is used in place of the manual designation "IN"; the
~,, designation "DE" is used in place of the manual designation
.,~ .
10 "DC"; and the designation "EX" is used in place of the manual
designation "XRn. Also, one added mnemonic instruction is
r
` included in Table VII, i~e. "DC", which is used to define a
'~ constant which is stored in the ROM and generates eight bits
,', of logic equal to whatever pattern exists in the address field.
~,
~' 15 In addition, three other instructions are included in the listing
~,, of the mnemonics in Table VII, bu,t are used to control the assembly
,., . . :
process only and do not generate any microcode. Thus, these '~
instructions n are not actual instructions, but aids, and these
~, , . :
,~ are: ~EQU" which is used to define the location of a symbol
20 which has been assembled at a different time; "OGN" which is
used to define the starting location of the assembly; and ~END"
w~ich ends the assembly.
` Further, when resort is had to the documentation
,
accompanyin~ microprocessor c~rcuit 1730, care must be taken
~,, ~ 25 to adjust the number bases when necessary. The listing of
Table VII is assembled according to hexadecimal, base 16, ~
, notation entirely for all addressing, instructions~ and other ~ -
'~ numerical values. The microprocessor documentation accompanying
~ circuit 1730 generally ~hows all numerical values in binary
-,~, or decimal base 10. Conversion from hexadecimal to binary or
'~,' decimal base 10 is clearly within the skill o~ the art~
q_
~045248
r- TABL~ ~7II
OOGO ~2F 0Gii 0000 002p ~,Z
0000 ~2F IBo E(~t; 01~7 oo~E; FF DC
0000 2F CSE; l::~V 02FE GO~F . FF DC FF
0000 . 2F C54 EGU 02B3
0000 . 2i` DSS E,GU 03f,5 0030 61 0UT20
OOCG 2F RXO EGiU 0161 0032 0UTl I
OOCO .2F TXO E6~U 016~3 0033 DEL
0000 2F TSO 1:6~U 01 00 OC34 OB I CB
0~00 2~ DFI l:(;iU C200 OC35 .44 JMP -DS5
0000 2F CC2 E(~ C255 037
OOGO 2F CSO E;~U 0^9; ~ . 03
OOCO . CO DF2 LAA C30B o D LLI F6
000394B C~L C?~2 . 003 Fg LI CL
0004. oo 003D. ~B LMD
ooo5644 JMP IBO 003E3C L~
0007. 01 - GG4S:; .80 Ai~
000~3 EO LEA 00426B ~J~C TXO
0009.45 INP2 0043.01
OGOC C3 LAE 004470 J~S PXO
OOOD44 JMP 0008 004747 INP3
OOOFO C t CL 004g7 JTS TS O
OGl I 61 INP2 ~ 004C46 RSO C~L CRO
1~ 43~ INP4 G04F3E Ll`ll 40
0018`- 02 ~ : 0052486 LAI 48 ~
00193A ` CPC . 0053.57 0UT13 `:
OOli3.44 JMP CS8 ooC461 DXO INP5
¦E FF DC FF . ~ . 0053 .FC lWP5 ~-
002161 011LT20 : 005A . 68 JTZ DX2
0022. 45 INP2 : ~ 005C 00
0024o4 NDI 04 ~ 005D3C CPl ~FE
002549 INP4 ~ 005F4~3 JFZ FBD
0027~3 0061 00
002A.23 ATZ 0062 61 DX2 0UT20
-002B.44 JMP CS4 0065.F2 ~ .
~: ~ /5~ -
,
:: i
, ~
.
'.1 ~.
'-J' ' 1045Z48
1~BLE VII CONTINUED
: ~ .
.
~ :.``.
... . .
OC66 .4B JFZ FBD OOhO .00
0067 .7S ` OCAI 36 LLI FF
OOG8 00 OOA2 .FF
00~9 61 0UT20 OOA3 .3E LMI F3
006A 4~ INP5 OOA4 F3
006B 3C CPI F3 OOhS .36 LLI F5
006C F3 OOA6 F5
OO~D 6~ JTZ DX3 GOA7 .26 LEI 40
006E .82 ~ OOA5 .40
006F -00 OOA9 FC CR4 LME
OG70 .3C CPI F~ QOfiA .31 D~L
G071 .FE OOA~ 4~ JFZ C~4
OC72 6~ JTZ DX3 OO~C .A9
0073 82 OOAD .00
0074 00 OGAE .06 LAI CD
0075 .06 F~D LAI 06 OO~F .CD
0076 06 OOBO .44 ~SP CR5
00?7 .57 BUT13 OOBI .D9
007~ 57 0U~13 00~2 .00
0079 .06 LAI FF OOB3 .16 CC~ LCI 40
007A FF 00~4 .40
C07B .5B 0UT15 OOB5 36 LLI 00
007C .06 LAI 48 : OOB6 . 00
007D .48 OOB7 .C8 CCO L~A
007E 57 BUT13 - OOB8 `43 INP~
007F .44 J~P DX2 OOB9 .AO NDA -`
0080 62 OOBA `50 JFS CC2
O~B~ .55
00~2 .36 DX3 LLI FF OOBC .02
0083 .FF ` OOBD 5~ C40 0UT15
0084 .F~ LMA OOBE . Dl C42 LCB
0085 .3C CPI FE OOBF `F9 LMB
00~6 .F~ OOCO 30 ICL
0087 .06 LAI 01 OOCI C6 LAL
00~8 .01 OOC2 `3C CPI F6
0089 .5F BUT17 OOC3 .F6
008A .06 LAI 32 OOC4 23 RTC
003D 32 ` OOCS 36 LLI -06 -`-`
OO~C 45 JFZ ~ DNO `OOC6 06 ` ` ` ;
003D .`30 OOC7 .07 RET
008E 02 OOC8 .FF DC FF
OORF 53 DFO 0UTII - OOC9 FF DC FF
OOgO .53 0UTII - OOC~ FF DC FF
0091 .16 LCl 40 OOCB FF DC FF
0092 .40 OOCC FF DC FF
0093 ~44 ~MP DFI OOCD 61 CFO 0UT2G
~094 .02 ` , OOCE -49 INP4 ~`0095 02 ' OOCF 46 CFI C~L CSO
0096 36 `C~O LLI F8 OODO 98
0097 .F8 OODI .02
0090 C7 - L~ ` OOD2 .OD GF3 RSTI
0099 0~ ~RC OOD3 46 CF4 CAL CCO
009A .03 RFC OOD4 .B7
009~ .2E CP.2L~I 07 OODS 00
OO9C .0~ ~ OOD6 44 JMP CFO
OO9D .36 LLi F8 OOD7 CD
009E .F~ , OOD8 00
009F ;3E - LMI 00 ~ ' OOD9 .51 CRS 0UT10
,; . ~
'` 1~ .` - - ,
., ~ _.
'c ~' ''
:.,j :
': ~ :
!
~ `
~)
~045Z48
~ T~LE VII CONTINUED
, .
``3
Y OODA Sg ~5UT14
'~ OOD3 3 6 LL I F9
; -~ OOI: C . F9
~ .3 OODD F8 LMA
`~ OO~E 07 ~.~T
` .~ OODF I F DC FF
y OOEO 3C DF6 CPI FF
00.:1 . Fl~
~`.. i 00~:,2 . OB P;FZ
OOE;3 . 36 DF7 LLI 05
~, OGE4 Q5
.:. OOE5 . 61 0UT20
~, OOE6 4'3 Il\~P5
, ~ OOE7 . 61 OUT20
.` ~ OOEg 4 6 C~L DF2
00E9 OB
`. 00~'`. 03
. ~' oo~ .44 Jt~P DF7
. . ~ OOEC E3
5',, OOED . 00
-- OOEF FF DC FF
~ ~ OOEF FF DC FF
i ~ OOFO . 60 Ci'.O JTC C42
~3 ` OGFI .BE
;~ OGF2 OG
:~- OOF3 3C CPI 2F
.`:i.`~ OOF4 2F
'`3 OOF5 . OE RFZ
OOF6 36 CXl LLI 00
."'.i-` OOF7 CO ::
OOF8 . 61 0UT20
. ~.`` OOF9 . 49 INP4
,~1. OOFA ~;6 CAL CCO
-~ OOFB . E7
. ~ r 00 i~ C Q O
- OOFD . 4~1 . JMP CH I
~i~ OOFE . F6
~, OOFF GO
.:~. 01~0 . OG E~D
i
`~ ' . .
"~, .
.~`j~`' . , ~ .
'....... ' . . : .'. ~-
:`:X- . ,. ~ ,
:.~ ' ' ,;
~ ' - ;;'- ,
5a - ,, ,,, ",, ~ , ,
: ?~
..i --,
', .
. .
: ,
, .; ...
L ~
.
~045248
TABLE V I I CONl' INU E:D
.
- O1CiO.00 ~GI~ OIOO 0133 .40 JFC T54
O100 OO CP.O EQU OO9 6 O134 31
~ ' 0100.00 C~JO EQU 02~ 0135 .O1
:, 0100. 00 CCA Etlll QOii3 Ol 36 61 CXO 0UT20
0100. 00 CFO EGIU OOCl~ 0137 49 Ii\lP4
Ol 00. OO I~O EQU 0005 O138 . 3C CPI 32
O100.06 TSO LAI 30 0139 .32
,. Ol 01. 30 O1 3t. 6; ~JTZ CXO
010''. 57 elil`13 O133 36
~;~ 0103.O~ LAI OA 013C -O1 : :
`~- 0104.Oi~ 013D .C~ LBA
0105.5F 01~'T17 013r 36 LLI F9
,, :: OlO6`36 LLI F9 013F F9
`~ 0107. F9 ` O1~0 C7 Lh~`~
~:- OIOu .3E L1~I OO 0141 ~O ADh
~'` OIO9 .OO - 0142 .06 LAI 23
P~ O10A .46 CAL C~O 0143 .23
~r^ 01 03 9 6 01 44. 60 JTC CX3 1
;~F``~ O1 0C . OO - 0145 -49
`3,~; OIO~ .36 LLI F~; 0146 .O1
OlOi~ .F8 - 0147 06 LAI 2E
O1 OF ~ 3r LMI 80 014~ 2E
,~A~ 0llO 80 . 0149 .5D CX31 0UT16
~t~ G111 .61 TS11 GUT20 014A.5~' 0T.Jl`15O112 .49 INP4 014B. SD 0UT16
O113 .~61 l~lU'r20 014C .5B BUT15
O114 .49 INP4 Ol~;D.5D 0UT16
.Ol 15 3C CPI 32 Ol~;E.5E 0UT15
.~- O116 .32 Ol4F .5D 0UT16
-`~ O117 4S JFZ FBC 0150 .5B 0UT15
. 01 18 . 61 01 51 5D 0UT 1 6
. '~ O1 19 01 O152 .5B 0UTI 5
~ O11A 45 I.NP2 0153 S~ 0UT16
: ~ ~ O1 1 B. 8 O ADA - Ol 54. 5B 0UT 15
;~ .: .Ol IC ?O - JTS TS3 0155 .5D BUT16
:.~ O1lD .2D - . Ol56 SB 0UT15
.:~ .` O11_ O1 0157 .CI LAB
-011F 47 INP3 ~ -: -O15~` 60 -JTC CNO0120 24 ` NDI 10 : ` ` O1S9 4P
O12 1 10 O1 5h 02
~V` 0122 43 .JFZ TS4 . . .O1 5B46 CAL CCA
` 0125 36 LLI ~FF ~ ~ ~ O15E 4 JMP GF0
O127 C7 LAM : 0160 00
~?~. o1229 3C . CPI l;'E ; ~ ~ 0161 06 FBC LAI 06
"-` 012A 63 ~JTZ TS4 . 0163 57 0UT13
. 012C Ol ol645 o76 0UT13
`~ . 012D . 3G TS3 LLI F9 0166 30
- Ol Z r F9 O1 67 57 0US 1 301 2F 3E L~I 80 Ol 60 44 : JMP TS11
,: : O13 1 . 45 TSq INP2 ` O1 6A . O 1
`0132 -02 ~LC ~`016S .36 `TXO :LLI F6
- 01 6C Ft;
~" . - ` ., ` . .
5~ _ -
. .
:' .
,.,
::` .,
., ~ ' .
~ 10~5'~4~3 )
. TABLE VII CONTINUED
'1 '
. ;~
i
., , ` f
01 GD . DF LD;`I 01 A7 h~ I B 1 E7;A
01 6E: 30 I CL 01A6 SF 0UT17
01 GF .F7 LL~i 01A936 LLI F8
0170 .45 T,~11 INP2 01AA.F8
017 1 . 24 I~DI 21 01 AB C7 LAI~
0172 .21 01AC.~5 ND~ -
017 3 . C3 LAD 01AD. F8 LMA
017 4 . 2B ~.TZ 01~0 6 LAI O 6
0175 47 11~3 01AF.-06
017 6 24 NDi 40 01BO. 57 0UT13
0177 .c;o 01B1;57 eUT130173 .4~ Js z I7:11 01B2. 06 LAI F~
017 9 .`70 01B3 FF
017A .01 01B4SB 0UT15
017B ` 4S INP2 01B5.hi3 E~iA
017C .24 NDI 20 OlB6FO LLA
017D .20 01B7-F6 LMA
017E .44 .JiSP TX2 OlB8.30 ICL
017F CS ~ OlE~9 F; LMAOlc>O 01 01BA .30 iCL
0181 36 ~XO LLI F6 01BB;F8 ~A
0102 F6 01~3C3G 1 CL
018 3 . DF LDM 01 BDF8 L~sA01~4 30 ICL OIBE30 lCL
01~; 5 F7 LLM 01 BF F0 LMA
01~;6 47 RX11 It~P3 01CO-30 ICL
0187 ~5 0 ADA 01 C 1 F8 LMA '`
0188 .-70 ~J~S IBO 01C2.44 JMJ' 003E;
0189 . 05 . . Ol C338
OlôA . QO 01 C4 00
01~6;~ 80 ADA 01C56~ TX2 JTZ TXll
OI~C 70 JTS RX2 01C6.70
018D .9F , 01C701
018E -.01 01C8- 06 CEO LAI 2F -
018F - 45 TNP2 01C92F - -
-0190 24 NDI 24 01CA.CO LAA
0191 . 24 - ~ - ~` oi CR CO LAA
O1g2 `2C ``E~1 24 ~ 01 CC;OD : RST10193 24 01 CD 5D ~IUTl 6
0194 .46 JFZ RX2 01CE.OD RST10195 9F . . C1C~.5E; 0US150196 01 - 01DO--OD ~'.ST1 ;.
0197 .45 INP2 01D1. SE; 0UT15e . 24 ~DI 24 ~ . 01 D2OD RST 1
0199 24 01D3CO LAAOlgA 2C EXI 24 , . 01D4.45 CE2 INP2 `-
01 9B 24 ~ - : 01 D5 24 NDI 04
019C . 68 JTZ IBO . 01D6-.-04 - - :
019D 05 01D7 68 ~JTZ CE3
019E 00 ` 01D8.`E3 .- . . :
019F 45 ~Y2 INP2 - 01D9-.01 - ~ :
01AO .24 NDI OC - 01DA45 INP2 - -
OIAl OC , 01 Di3 24 NDI 04
01 A2 C3 LAD : 01 DC04
01A3 . 2B PLTZ ~ : 01 DD- 6E3 JTZ CE3
01 A4 44 ~M~ PX 11 . 01 DE. E3
~1AS B6 01DF 01
01A6 01 ~ 01EO44 ~ 5P lBO
_ I r' ~ _
~y _ .
.
:~ :
l ..
,
1045Z4~3 - '
~ TA~LE VII CONTIN~ED
. . . .
, .
.; , .
O ¦ ~ ¦ O S
-,. 01E2 .00
~ 01E3 45 C-3 lNP2
:~ 01E4 .24 NDI 82
S .~2 . .
~-, -01E6 80 ADA
3 01E7 -~0 JFC IBG
~`~,0I L8 05
~.01E9 00
1; '01EA .65 ~TZ CE2
~,--01EB D4
.-. OlEC 01
,01~D .~4 J~SP IB0
,.~01EE OS
-.~01EF 00
~-. 01F0 .FF DC FF
`01Fl --FF DC FF
01F2 .FF DC FF
~: 01r3 .FF DC FF
01F4 FF DC FF
~ . OIF5 .FF DC FF
`;`~ 01F6 FF DC FF
-~. 01F7 .FF DC FF
,~- 01F8 FF DC FF
.~:. 01F9 .FF DC FF
~` OlFA FF DC FF
:~:;`. . OlFB .FF ~C FF
OlFC .FF DC FF
01FD Fr DC FF
- OlrE `FF DC FF
01FF .FF DC FF
~: oeoo FF E~D
:^ ~
.~ .J~ . .
l : .
: ................................................. . . , .
~''. ' . .' . , ~
,.-?;,
~``."` , . , ' , ~ ,. , ''.' ~ :
?, ~
,.. ~ . : . ~ . . ' '
.. .
:' ` :
.,: . . ,,:
i ? '~ ~ -
?'. . ~ C
~,'
/
l ~ . .
l ~, .
, r, . ....
1045Z~8
`' TABLE VII CONTINI~D
.
~"
; ~,
.
`'~ 0200 .FF 0GtJ 0200 0 32 .OE DNIl LBI FF
0200 .FF DF2 EQ~ 030B 0233 .I;F
"' 0200.I;'F 1130 EQU OU05 0234 . 61 D1~2 0UT20 ``
,,, 0200 FF C30 E~;IU G3CD 0235 '.4E; ' I;~P5
'' 0200`'FF ESC EQIJ 03E~ 0236 '. 61 1~UT20
0200 'FF CCO EQU OOi7 C237 .EO LE~
`, 0200'.'FF CF3 E~iU OOD2 023~ .4B INP5
0200'.FF DC FF 0^39 '.02 I~LC
`,` , 0201`;FF DC FF 0231~'.02 ~LC
t;202.3`6 DFl LLl 05 0~32 '.C2 r~Lc
,`~ '- 0203'.05 023C `.02 ~LC
~'','~ ' C204 '61 DF1 1 0UT20 023D .P4 NDE
0205.`4P INi~5 023E .'53 0UTll
'',' 02C6 61 ~UT20 023F'.'09 DI~B
~'' 0207 46 , CAL DF2 0240 '.68 ~JTZ IBO
~-` ' 020Ei.`OE 0241'.`05
~- ' 0209'.'03 0242 .'00
020A'.44 J'IP DFll 0243 `.3C CPI FF
'1~ 020S`.04 ' `0244.'FF
,~ ~ 020C''02 024~ . GS JTZ DN2 -
02CD 'FF DC FF ' 0246 ' 34
~,;, 020E'.FF DC FF 0247'.'02
`'` 020F`.'FF DC FF 024~3 ` 44 ~ P DNII
0210` C6 DC C6 0249 '.32
``;`i`"` 0211 '-C2 DC C2 024P '`02
0212'.`D7 DC D7 024B .'SB CWO 0US15
~''c~ 0213 `-DS DC D5 024C '.5D , 0US16
0214'.'4D DC 4D 024D `,'61 CN2 0US20
'~ 0215`'D6 DC D6 024E `.49 INP4
0216'.'C9 DC C9 oe4F 5I3 BUSlS
0217'.`E2 DC E2 ` 0250 ''OD P.STI
' `0218'.-C4 DG C4 0251 ' 5D 0UT16
~` ~,, 0219' C3 DC C3 0252 '.44 JMP CN2
~; -021A'.D9 DC D9 0253 '.`4D
, ~ ~ , C21B''60 DC 60 0254 ''02
` 021C F9 DC F9 ~ 0255 ' 6~3 CC2 JSZ C12
,` , 02ID''413 - DC 4B 0256 -.63
,`~` `' ' -021E - F6 ' DC F6 ~10257 ' 02
~' ; 021F .E3 DC E3 ` 0258 ' 80 ADA
`~ 0220-.`27 D~ 2? ,~ oe59'.' IA RAR
' 0221.'E8 DC E8 025~ '.70 JSS C12C
' 0222''E6 DC E6 025B ' 6C `-
~'- 0223' 6B DC 6~ ' 025C - 02 `
'~` , 0224 '2 'DC D2 025D ' 44 J~P C80
~'e . ~ 0~25 61 DC 61 025E ''CD ,
'~ 0226''5C DC ` 5C 025F - 03
~ " - 0227' C8 DC C8 0260 ' FF DC FF -
'`i~" ` 0228 'E4 DC E4 ' 0261 ''FF ` DC FF
~y,; `0229.'D3 DC D3 ; -0262'.F'F , DC FF
,-`-' ` 022A` 5D ` DC 5D ' '0263 -.5D C12 0UT16
'~"'' 0228 D4 DC D4 0264 -.OD ~SSl ,~ ~'
022C`'C7 DC C7 C265 C1 LAB`
022D` 10 DC 10 0266 '.5D BUT16
022E`.32 DC 32 0267 ' OD ~STI
,~``` 022F' FF DC FF ` oe6S`.'5S 0UT15
, `0230 '.53 DNO 0UT11 0269 '.44 JMP ETC
;' `0231 53 0UTll Q26A `'~
, `' ' -, '- 026B .'03 ` -
3` `
:.
^ 15l~-
. .`
,
: .
..
. .
- 1045~248
TP.~I,E VI I CONT~ 'FD
.
026C ~24 C12CJ~DS OF O.'h6 25 RST4
026D . OF ~ 02A7 .2S RSS4
02. G1~ . SD 0UT 1 6 02Af~ DO CS3 LCA
02 6i . 34 0r.l FO 02A9 . 0 6 LAI E5
0270 ~ FO ' 02AA . E5
0271 '01) nSTl ' 021~B ~`5D CS31 OUT16
0272 .`5D '0UT16 02AC '. OD RS'T1
0273 .'OD i~S1`1 02AD . 5Ei eUTI 5
0274 '.'53 1~5UT15 02AE 61 QiUT20
0275 .'3C C~I F8 02AF '.49 lNP4
0276 ~F~3 ' 02BO .44 J;~iP CSA
G277 .40 JFC C12D 02i31 .97
02?P .~53 02B2 '.'02
027 9 ~ 02 02B3 31 C54 DEL
Q27A . 3C CPI F6 02B4 -'.'EO LEA
C27i3 '.FG ' 02B5 C1 LAi3
027C '.'68 JTZ C12~ 02E~6 ~CC LBB
027 D ' 58 G2B7 '~'9 6 SUL
C27 E ' 02 02B8 ' 48 JFZ CS4 1
Oc7F '60 JTC C12F 02B9 CC
028 0 ' ~ 5 02BP. . 02
0281 '~ 02 ' 02BB ' ' C7 CS40 LAil
0282 .36 LLI OB 022C .E6 LEL
0283 '~ Ov 02ED . 36 LLI FE
0284 . C7 RET ~ 02BE '~' r E
Q28S .`36 C12F LLI 08 02E;F 'F9 LMB
0286 ''08 02CO '.F4 LLE
oe87 07 RET 02C 1 '~'4 6 CAL CCO
02~8 '.36 C12E LLI 06 02C2 .'B7
02 i9 '.G6 , 02C3 '.00
oe8A '~'07 RET 02C4 ''E6 LEL
028B '~E6 C12D LEL 02CS .36 LLI FE
028C ' 36, LLl F8 ' 02C6 ' FE
028D . F8 ` 02C7 C7 LAPS
02s~E, '. C7 LA~ 02C8 ' F4 LLE
02&F '~34 0RI 01 02C9 ~44 JMP CSO
0290 '~'01 ' ;~ - 02CA '.'St8
0291 '~ F8 LMA ' 02CE~ ' 02
OE~92 ' F4 LLE ' ' 02CC '~'24 CS41 NDI EF
0293 ; 07 RET - 02CD '. EF ~ ` '
0294 '. FF DC F'F 02CE .5D 0UT16
oess '~'FF DC FF 02CF ' OD RSTI
0296 ' FF DC FF '02DO 5B 0UTi 5
0297 '~30 CSA ICL 02Dl ' Cl LAB'
0298 ' E3F CSOCP~I 02D2 ' D7 LC~I `
0299 .43 JFZ C55 oeD3 `;30 ICL
029A 'D9 ' 02D4 ` 44 J~5P CSO
029B '~ 02 ' ' 02D5 .9~ `
oe9 C ' CE CS2LE~L ' ~ oeD6 '.` 02
Ce9D ~25 ' R5~4 ' ' O2D7 '~FF DC FF
029E '. 25 RST'4 ~ 02D8 '~ FF DC FF
029F 25 RST4 02D9 ~'BA CSS CPC
02AO ';25 RST4 ' ~ oeDA '.'48 JFZ CF3
02A1 25 RST4 - 02Di3 '~D2
02A2 ' 2 5 RST~ 02DC ' ' GO
12A3 ~25 R5T4 , -02DD ~`CE CS6 LBL
02A4 ~ 25 P~ST4 02DE '~ F8 LMA
02AS ' 25 RST4 oeDF ~15 RST2
j~ t.'. ~ s 7 --
, - . . . -
.. 3~, .
.
.
.. ~i ~ .
~-:
:f .: . `
:~ `' ' . ' .
104S2~8
.3 TA~LE VII CONTINUED
~ ' ' ' - ', : '
..02~0 .F~ Ll~A
'!;' 02EI 15 p,ST2
~- 02E2 .F8 Li~A
. 02E3 .15 ~.S1`2
I - 02E4 F~ L~iA
:~ 02E5 .15 ~ST5 - . -
02E6 .FB LMA - ~ -
~; .02E7 . 15 r~sT2
02~V~ .Fc; L~h - -
~':. .02E9 .OG CS7 LAI EO ~ :
. 02EA EO
~`....02~ .4~ Jl~ C53~
~:02EC -~r~ :
~ 02E~ .02
;~02EE ~FF DC FF : ,
. 02EF FF DC FF
02FC .FF DC FF
~: r~-02r 1 FF DC Fr `~
~` ~-:02F2 FF DC FF ~ ~:
`.~02F3 .Fg DC F8
O~F4 CI DC Ci :~
02F5 C5 DC C5
.~`02F6 .F7 DC F7
. ~ ~ - oe F7 r3 DC F3
- 02F8 F4 DC F4
~`02F9 F5 DC F5
02FA 4C DC 40
.02FB FI DC Fl
oeFc F2 DC F2
~:~02FD ~FO DC FO
`< ~02FE 31 CS8 DEL . -~
`02FF EO LEA
.;0300 ~EO END : . -
, ~
~' :' ~ ' ' '- ' - . .
, . , - - ' -.
. ~' - - .
,
" ~ ,
. ~ ' ' , ,
( J.045Z48
~L~ VII CO~TINUFD
. ! . ! ' .
''' ,0300 .EO 0GN 030C 0330 .6~ JTZ D8A
'-i 0300 'EG CS40 ~GU G23B 0331 39
0300 '.EO C541 EQU G2CC 0332 .03
,': 0300 .'EO I~O EQU -G005 0333 .40 JFC D3B
~ . .03 00 r O C42EQU OOv~ 0334 39
'' 0300 EO DFll&QU 0204 0335 .'03
~',` 0300 ~ &0 D42 EQU G3~15 0336 '44 J1~P D12
0300 ~0 Ci~OE~U OOFO 0337 .4C
~ 030G `-EO DF6 EQU COEO 0338 .'03 '' ''
,~`- 0300 'CI LhB 0339 .'4' DS~ INP5
,, 0301 'CC L~E 033A .24 NDI lF
~` C302 .9G SUl, 033B .IF
~r. 0303 .6~ JTZ CS40 033C .E6 D40 LEL
;, 0304 .B~ G33D '.FO LL~
~' 0305 ''02 033E 2E LHI 02
~;r~., 0306 .'14 SUI CB , 033F '02
i~ 03C7 .'G~ ' 0340 C7 L~`~
'~ '030~ .44 Jt`;P CS41 0341 `.'53 0UTll
! 03G9 - CC ` , 0342 F4 L~E
-,030A `.`02 0343 2E Llil 07
030B `.'3C DF2 CPI F3 0344 07
030C ' F3 0345 .DOD42 LCA
``~ 030D `'60 JTC DF21 0346 `'F8 LMA
~ 030~ ;2E 0347 .31 DEL
.~r 030F '.'G3 0348 .0~ RFZ
0310`.'3C CPI FE 0349 `'36 LLI F5
0311 `.F~ ` 034A F5
0312 ''60 JTC D40 034B .'07 RET
, ~ 0313 3C 034C 4B D12 INP5
,~ - ` 0314 -03 ~ 034D '.'G2 ' P.LC
" ~ - 031S ' 68 JTZ DSO ' 034E .02 RLC
~ 0316 '.~5 034F 02 ~LC
,~' ~ ' 0317 '.03 ' 0350 '0? ~LC
'~ ~ - 0313 'OE MKO LBI FF 0351 C~ LBA
,,~, ~ 0319 '.'FF 0352 61 0UT20`,~ ~-`' 031A .09 MK2 DEa ` 0353 ''4B INP5
,~ ~,, ,, 031B .68 JTZ IBO , 0354 Al ND~ ,~ `
,, ~ `-031C '05 -'' ~ ' 0355 C3 LBA -
~``' ~ 031D '.00 - ' 0356 3C CPI FO
~, 031E '47 INP3 ' 0357 ' FO
'~ ' 031F '~0 A~A ', ~ 0358 ''6G JTC D12A
`` 0320 '70 ~TS IBO 0359 .-60 ' "~-
`0321 '~05 ~ ' ~ ' , 035A 03
0322 OG / '' - 035B '3C `CPI FA .
0323 '4B / lNP5 ~ 035C '.'FA
' 0324 ' 61 / ~UT20 035D 60 -JTC D12B
'~ ` 0325 '3C / CPI F~ 035E .D3 ~ ' ~
032 6 F`F / 03 5F ~ G3 ; ~ -
~ . . 0327 63 ,/ JTZ ~K2 ~ C36053 D12A 0UTl l~ . 032c IA / `~ 036144 JMP D42
`:~ . . . 0329 03/ 03624S . - -. -
032A . 44 ~P DF2 . 03 63 03
032B ~ 03~i 03 64 F~s DC FA
` 032C G/3 ~ 036S~ 03 DC 03
!~i;- - 032D l~F DC F-~ :0366 -~3C D12C CPI F8
:'...... 032E 3C .DF21 CPI Fl .- 0367~F~ . -
I i,.- 0~2F ~Fl ~ i 036~~40 JFC D12D
03 69 ~ ~ C
.,; .- . . ~ . ~ ,
-:~ . " ' ,i . : - ' -
.;... .. .
:~- i . - ~ lSq--
; ~. - . I .
. ~ .
~v~
~:
. ,.
E : - - -
1045Z48
Tl~RLE VII CONTI~ D
`. '' .
, .
. 0361~ . 03 - -
.~: 03613 .3C CPI ~6 03A4 .35 RST6
~, 03C~C . F6 03A5. 30 D55 I CL
- 036D `. G~ JTZ D12~ 03A6 .44 JMP DS5A
; ,036E .'79 03A7 -D6
,,,,, 03~ .,03 , 03A~ '03 ' '`
0370 60 JTC D12F 03A9 04 DS3 ADI OA
~ 0371 .' 7 6 03~ 0
''~' 0372 . 03 03A~ . C~ LB~
,,~' 0~73 .`3G LLI F0 03AC . C2 L~C
0374 .FO ' 03AD 'FA L~IC . . -
037.5 . C7 nET , 03AL . 35 P.ST6
,,~ 0376 .'36 , D12F LLI F3 03AF .FA LMC
~ 0377 .F3 , 03BO '.35 ~.ST6
E; , 0370 .07 ~ET 03B1 .FA LMC
,-~'' 0379 36 D12F LLI F5 03B2 '35 RST6
- 037~ . F5 03B3 '.-FA LMC
~,, 037~ '.07 , RET 03B4 '.35 RST6
'037C .E6 D12D LEL ' 0325 . FA L~C
037D .36 ` Ll.I F~ '03~6 '.35 ~ST6 - ~ ` -
037E .F~ '03B7 .FA LMC -.
~i,,'' 037F '. C7 L~S 03B8 35 RST6
,-'`~ 0380 .34 0~.I 01 03~9 4B D8B INP5
~ , 03BI .01 ' ' 033A ''24 NDI 2F
1~`~ 03~2 '. F~ LM~ 0333 2F
, 03~3 '.'F4 LLE 03BC '.'E6 LEL
~, 0384 .07 Rr T 03BD 'FO LLA
~ 0335 '.'4B DSO INP5 03BE''.2E L~I 02
,~' 03~6 3C CPI F5 03BF ''02
,~' 03~7 .r5 03CO 3C CPI 2D
' 03~3 '.60 JTC D53 03C1 '.'2D
038g ~A9 03C2 C7 L~ . -
-038A '`03 03C3 ''53 0UT11
03~B ';C3 LEA 03C4 '. F4 LLE'
, 03~C ''09 DEB 03C5 '.2E L~I 07
~- , C3~D `C7 D52 LAM 03C6 '.'07
'03~E'.35 RST6 ' 03C7 -60 ' J~C D42
~i ~ "033~ '.'C7 ` LAM ' ' 03C8 '.45 , '~ C
';i~ ~ 0390 '35 RST6 03C9 '03 ' "'~ ~ ``'`~ ,''''
0391 'C7 L~ 03CA 44 J~P DF6, 03g2 '35 RSS6 03CB-' EO
,0393 ''C7 L~ 03CC ''00 .,,~, 03~4 35 ,~SS6 03CD '5D C~O 0~T16
:'t~.. '.. ,' - 0395 'C7 LA~ ~3CE '.'OD ~SS1 '`
03 9 6 3 5 RS S 6 03 C F 53 - 0UT 1 5
;~C 0397C7 LA~S ~ 03D03C CPI 2D
` 039835 P~ST6 03DI. 2D ` ~. -
~. ~ 0399 C7 LAtS 03D244 .JMP CH0
;`~.` 039A 35 RST6 03D3 F0
~;;`. 039BC? LAt~l . 03D4 00
',~,J~"''.'' ' ` 039C 35 RST6 03D5 07 DC 07
039D. C7 LAt~ 03D6D7 DS5A LCM i -
i ~ 039E35 ~ISS6 . 03D731 DEL ~ -
039FC7 LA;I 03D~344 ~IMP DFll
03A035 ~ST6 , 03D904 :~
~^ 03AlC7 LAM 03DA02
,~ 03A2. 35 RST6 0:3DBE6 Dl 2B LEL
3A3 ~ C7 LA~ ; 03DC `- F0 LLA - - `
`:' - 03DD . 2E l~SI 03
, ~ , .
. - . , - _
~ - 16~ -
~ .
-
, .,
.`
L ~.~
1
104S29~8
`~ TABLI: VII CON~INUED
.
, - .
I . .
,:! . ' . . - ` : ` `
03DE . 03
C3DF C7 I,hM
03E:0 .2E LHI 07
03 E l 0'7
03E2 . F4 LLE
03E3. 53 0t,'TI I
03E4Cl LAB
031~5 . 44 - Jt'~P ~1
031~6 .`G6
03E7 03
03~,. 44 ETC J~P C42
03 E9 . E~ E
03E.'` .00
03E~ . FF DC FF
03EC FF DC FF
03 ED .- FF DC FF
03 r E ~ FF DC FF
03 EF FF DC FF
03 FC 02 DC 02
03Fl . lE DC IE
03F2 .15 DC 15
03F3 . 25 D~ 25
03F4 . OB DC OE3
03F5 OC DC OC
03F6 lF DC IF
03F7 `- 00 DC 00
03r ~ 2D DC 2D
03F9 ~-3D DC 3D
Q3FA . FF DC FF
03 FB FF DC FF
03FC . FF DC FF
03 FD ` FF DC FF
03FE . FF DC FF
03FF . FF DC FF
rO OO . FF ~D
~ ~ r
1, . ~ ' ,' , ;
.: ..
~. . ' . .
:' ~ . .
~' ~
; ~:,.
~ F~
-
~ 10~5248
~BLE VII Co~TINU~D
.,
OGCb . 07 0GI~ 0000 003B . 00 D(; 00
0000 .47 DC 47 0039 . 00 DC 00
0001 .GO DC 00 . 003A .00 DC 00
000~ 40 DO 40 003B . OG DC OG
0003 . OG DC o~r 003C 00 DC 00
OOC4 00 DC 00 j 003D . 49 DC 49
OC05 . 00 DC 00 1 003~ OC DC 00
OC06 . 00 DC 00 i 003E . OG DC 00
OOC7 . 00 DG 00 0040 . 8A DC ~A
000~ .CO DC CO OU41 . 00 DC 00
OOG~ .00 DC 00 , 0042 . 00 DC 00
GOO~ . GO DC 00 0043 . CO DC 00
oQo3 . 44 DC 44 0044 . 00 DC OG
OOOC 45 DC 45 0045 . 00 DC 00
OOOD 00 DC 00 004G 00 DC 00
OOOE . 00 DC 00 - 0047 .GO DC 00
ooor . oo DC GO 0045 . 00 DC 00
0010 . 2D DC 2D 0049 . 00 DC - 00
0011 .00 DC 00 004A .00 DC 00
Q012 . 00 DC 00 . 004B . lD : DC - lD
0013 .00 SC 00 004C .OG DC 00
0014 .00 - DC 00 004D .14 DC 14
0015 .42 DC 42 004E 00 DC 00
001 6 . 00 DC 00 004F . 00 DC 00
0017 . 00 DC 00 - 0050 . OG DC 00
001~ . 00 DC 00 005. . 00 DC OC
0019 .00 DC 00 0052 .00 DC 00
OOIA . 00 DC 00 0053 00 . DC 00
001~ . 00 DC 00 0054 . 00 DC 00
001 C . 00 DC 00 0055 . 00 DC 00
OOlD . 00 DC . 00 ~ 0056 . Oû DC 00
OolE .41 DC 41 0057 .00 DC 00
001F 46 DC 46 0053 .00 DC 00
0020 . 00 DC 00 ; 005~ . 00 DC 00
002; 00 - DC 00 : 005A . 00 DC 00
D022 00 DC 00 005R . 00 DC 00
00Z3 DC 00 005C .26 DC 26
024 . 00 DC 00 - 005D 2A DC .2A
0025 43 : :DC 43 ' ` : ~ 0Ci5E .00 DC 00
0026 . 00 DC 00 OOSF . 00 DC 00
0027 .20 DC- 20 ~ 0060 . 1;'` DC IB
0020 .00 DC CO I 0061 .25 DC 2S
OC29 00 - DC 00 , - 0062 00 DC 00
002A 00 :DC 00 1 . : 00 63 . 00 DC 00
002i~ . 00 DC 00 ~ 0064 . 00 DC 00
G02C 00 DC 00 ¦ . 0065 00 DC 00
C02D 48 DC 48 0066 00 DC 00
002E 00 DC 00 0067 . 00 DC 00
002~ 00 DC 00 ` ~ 006~ 00 - DC 00
0030 . 00 DC 00 006g 00 - DC 00
0031 00 DC 00 ~ 006A . 00 DC - ~ ~ 00
0032 2E DC 2E . . 006s .23 DC 23
0033 00 DC 00 - C06C . 00 DC 00
0034 . 00 DC 00 ~ 00 6D . GC DC 00
0035 . 00 DC 00 ~ `006E 00 DC 00
0036 00 . DC 00 ~ OG6F 00 --DC - 00
0037 . 00 DC OG ~ ` 007 0 . 00 DC 00
- . . G071 -00 DC 00
. . . ..
.` ..
J~2
. ~ . . . .. ~ , .
:
1045~8
T~BLE VII C0~1TIr~F~
,
` 0012 .00 DC 00 ' OOAC 00 DC 00 -` 0073 .00 DC - 00 OOAD .00 DC 00
~-.....0074 00 DC 00 OOAB .00 DC 00- 0075 00 DC -00 . OOAF .00 ~C oo
~` 0076 .00 - DC oo 0030 .OC DC GO
0077 00 DC 00 OOBI 00 DC 00
-0078 00 DC 00 00~2 .GO DC 00
' 0079 00 DC OOB3 .00 DC -00
:~007A .00 . DC 00 DC :-CO
. ? ~ '007B oo DC oo O~B5 00 DC 00- OO?C 00 DC 00 DC 00
~ 001D .00 DC -Oo ` 00~7 .00 DC 00
.;.'i,~-007~ .00 DC 00 ~ OOB~ .00 DC
007F 00 DC 00 OOB9 .oo DC 00
00~0 00 DC 00 -` OOBA .00 DC 00
~,:.0081 00 DC 00 - OGBB .00 DC 00:`~ -OC~2 00 DC 00 GOBC 00 DC 00
0083 00 DC 00 OOBD .oo DC 00
;~ - ~ 0084 00 DC 00 OOBE .00 DC 00`;~`` `0085 ~00 DC 00 - OOBF 00 DC `00
~-: 00~6 00 DC GO - OOCO.. OO -DC 00
00~7 00 DC 00 OOCI .84 DC 84
0088 00 DC 00 OOC2 .ll DC ll
0089 00 DC 00 OOC3 .l9 DC 19
~` : 008A 00 DC 00 OOC4 .18 DC 15
. - 008B .oo DC 00 OOC5 .85 DC 85
- 008C 00 DC 00 OOC6 .lO DC lO
.- . 008D OC DC 00 ~ OOC7 2C DC 2C
` .008E 00 DC 00 OOC8 .27 DC 27
~ `` oo~ oo . DC 00 - OOC9 16 ;DC 16~ 0090 00 DC 00 -OOCA .00 DC 00
. ~ 0091 00 . DC oo . OOCB .00 DC 00
~ ~ 0092 .00 DC 00 ' OOCC 00 DC 00
.: ~ :.0093 .00 DC -00 ` '~ OOCD .00 DC
: ~. 0094`-00 ~DC `GO OOCE 00 DC 00.~ ~`;,`0095 CO .DC 00 ` OOCF 00 DC 00
.` ~ 009~ 00 --~ -DC 0O ~ -OODI 00 -~`DC ~ oo
: ~ 0098 00 -DC -00 , `OOD2 .24 -DC 24
:. ~7 0099 00 DC 00 OOD3 .29 DC 29
~`` `:009A .00 . DC 00 ~ `.OOD4 .2B ~DC 2B
. ~ 009B .oo . -`DC 00 -OODS .13 .:DC 13~` , 009C 00 `DC :00 ~ ~ ; -`OOD6 15 `:DC l25
- `-009E 00 DC 00 ;-; OOD8 00DC 00 :
. ~ . 009~ 00 . DC 00 00~9 IADC lA
40AO 00 - DC 00 OODA 00.DC 00
~ .OOAI .00 , DC 00 - OODB 00DC -00
:, ~ ~. OOA2 00 DC - 00 ; -OODC 00DC -00
~OOA3 .oo . . DC 00 -OODD 00 ~ DC : 00.. ~ OOA4 00 DC 00 -~: :OODE oo ~DC ~`00
~OOA5 .Oo DC 00 OODF .00 DC 00 -
; ~`OOA6 00 DC 00 , - `OOEO .00 DC - 00
'OOA7 .00 DC 00 OOEI .00 DC -00
. OOA8 .00 DC 00 OOE2 l7 -DC ~ 17OOA9 00 .DC 00 OOE3 IF DC lFOOAA .00 -DC oo `OOE4 .2~ `DC 28
';OOAB -OO ---` -DC 00 00~5 00 ~ ~ .. DC 00
_.
. ~L.,~ -
. , - _ ~6g_~ - ,
., .
. ii
h~:
104SZ48
,. .
~LE: VII CONTINVE:D
' . ` ~ - - .
OOE6 . 22 DC 22
OGE;7 OO DC OO
COL8 .21 DC 21
OGL~ . OO DC OO ~ -
OoEr~ OO DC GO
OOEB OO DC OO
ocr(: . oo DC OO
GOED . OO DC O~
OOEE . OO DC OO
OOEi; . OO DC OO
COFO ~3D DC oV
OOFI .8B DC 8B
OOF2 .8C DC 8 C
OOF3 .~7 DC E~7
OOF4 . 8~ DC 83
OOFS . 39 DC 89
OOF6 .IE DC IE
OOF7 8 6 DC 86 ` - ~
OGFo . B 3 DC B 3
GOF9 . IC DC IC
OOFA . OO DC OO
OOF& . OO DC OO
OOFC . OO DC OO
OOFD . OG DC OO
OOFE; . OO DC OO .
OOFF . 2F DC 2F
O100 .2F a~D
, ' .
' , .
' `
~` ~ ' ` ' ' ' ~ ` ' ` .
. 1 , ~ . - ~ . .
~ ~ ' I _ ` ' ' ~ ~ " ' `
I l, 'I
~ _ , `
'~
~,
~ i
~ .
1045z4~3
:~ ;
1 Preferred valucs of the electrical components for
the preferred, practical, four bit data slice embodiment of
` Figures 15-26 may now be set out. It will be realized by
those skilled in the art that no limitation to these values
5 is intended, and the values are given as a guide and aid
to persons lawfully using and utilizing the present invention.
The electrical components are set out in the attached
Table VIII, where each particular part number of Figures 15-26
, is separately set out, the part is id~ntified, the manufacturer
;~; 10 is given, and the manufacturer's number or the value of the
' part is given, where any manufacturer's part will do.
`? It will be realized by those skilled in the art that t
.~! individual components, such as AND gates, OR gates, inverters,
and like logical components are incorporated in multiple
15 units and are not individually purchased. Therefore, where
a composite component is indicated in Table VIII, it will be
immediately recognized by those skilled in the art that the
~,1
~` particular part numbered may be included within the manufacturer's
~^~ part indicated, with the particular portion of that part being
~r~ 20 indicated on the drawings of Figures 15-26 by the identification
of inputs.
It will be lastly recognized that no designation of
power supply or filter capacitors has been provided, as these
components-are dictated by particular logic requirements, are
25 well set out in manufacturer's specifications, and are well
within the skill of the art.
~ - 171 -
.. ~ , .
.-~
'' , , .
I
.
. i` .:
~ ~ .
: ~" ,
. ~'.''` - .
~` (
~ 104SZ48
``' . . . . . . . . .
. ` . ... .
. ' TABLE VIII
., PART PART - MANUFACTURER MFR ~/VALUE
'`,l 1501 AND GATE SIGNETICS N7408
~i ' 1502 SEE 1501
.:;` 1504 SEE 1501
.~, 1506 QUADRUPLE LAl'CH SIGNETICS N7475
~'~ 1507 SEE 1506
.~, .1508 QUADRUPLE LATCH SIGNETICS N74175
.~ 1510 SEE 1501
i!~ 1511 NAND GATE SIGNETICS N7400
:`. 1514 3-8 LINE DECODER SIGNETICS N74155
,.~. 1516 SEE 1511
::~ 1517 SEE 1511
1520 SEE 1511
.~. 1522 RESISTOR ALLEN BRADLEY 1000 OHM, 1/4 WATT
,,,': 1523 SEE 1522
,'', 1524 SEE 1522
1525 SEE 1522
~` 1526 SEE 1522
i~'' 1527 SEE 1522
, 1528 SEE 1522
. 1529 SEE 1522
1530 SEE 1522
1531 SEE 1522
~ 1532 SEE 1522
: ~ 1533 SEE 1522
1534. SEE 1522
. `.. ; 1535 SEE 1522
1536 SEE 1522
~.,. 1538 SEELTAlG53E7TERMINAL PLUS S VOLTS
'~.` 1539 SEE 1537
'~ .1540 SEE 1537 ~ :~
1601 READ ONLY MEMQRY INTEL 1702
`~;~ 1602 SEE 1601
~,`.,~ 1603 SEE 1601
.1604 SEE 1601
... ~'1605 SEE 1601
`:`.'1606 SEE 1601
~ 1607 RANDOM ACCESS MEMORY SIGNETICS' 2501
.~., 1608 SEE 1607
" .1609 SEE 1607
1610 SEE 1607
~:' 1611 SEE 1607
,,. 1612 SEE 1607
'~.` 1613 SEE 1607
.`~''1614 SEE 1607
i,--~ 1615 '~EE 1511 . - , :
,. 1616 SEE 1511
." ..... 1617 SEE 1511 . ' - ''
.~ 1618 SEE 1511 ~'
.;~ 1619 8EE 1511
~,! .
':~
;,
, f'~
i .,
~.: '' . , ' _
-. 1045Z48
.,
,~
.` TABLE VIII CONTINUED
; PART PART MANUFACTURER MFR #~VALUE
~ NR .....
. .
i 1620 SEE 1511
1621 SEE 1511
`` 1622 SEE 1511
~' 1623 NAND BUEFER SIGNETICS N7438
, 1624 SEE 1623
~il 1625 SEE 1623
1626 SEE 1623
1627 SEE 1623
~- 1628 SEE 1623
; 1629 SEE 1623
` 1630 SEB 1623
-~ 1635 SEE 1537
1636 SEE 1537 . -1637 SEE 1537
~- 1638 SEE 1537
.~. 1639 SEE 1537
~ 1640 SEE 1537
i' 1641 SEE 1537
~`, 1642 SEE 1537
~i` 1643 SEE 1537
'~ 1661 SEE 1537
~- 1662 SEE 1522
.~ 1663 SEE 1522
1664 SEE 1537
`,~` 1702 NOR GATE SIGNETICS SP381A
~ -1704 NOR GATE SIGNETICS 8875
E 1706 NOR GATE ~ SIGNETICS N7402
1708 SEE 1702
: 1710 SEE 1511
1712 SEE 1704
1714 SEE 1511
1716 SEE 1511
.~ - 1718 SEE 1706 `:
-`-`- 1720 SEE 1702
~:~ 1722 SEE 1702
~ 1724 SEE 1706
`~ 1726 SEE 1704
. 1728 3-8 LINE DECODER SIGNETICS 82S50
1730 MICROPROCESSOR INTEL 8008
~ 1732 SEE 1501
::~ 1734 SEE 1511
1736 SEE 1706
. 1738 ~VADRUPLE LATCH SIGNETICS 8T10
~ ` 1739 SEE 1738
,''I. 1740 SEE 1738
. . 1741 SEE 1738 ~-
i~: 1742 BUS DRIVER SIGNETICS 8T26 ~:
-. 1743 -SEE 1742 - -~ -
1744 SEE 1742
~ 1745 SEE 1742
;~ 1749 GROUND TERMINAL OR SIGNAL GROUN~ ~ `
`:' 17.50 SEE 1749
~:. . 1751 SEE 1537
~: ~ 1752 SEE 1537
... `g ll,~
':' -- ~3 -
.
::~. r~:
: .;,
: ~.,
:: ~,
., ~. "
. ~'. .
: .
:
10452~8
` TABLE VIII CONTINUED
~ ~ .
` PART PART MANUF~CTURER . MF~ #~ALUE
1753 SEE 1537
:. 1754 SEE 1537
~; 1755 SEE 1537
~ 1756 SEE 1537
1757 SEE 1537
-~ 1758 SEE 1522
~ 1759 RESISTOR ALLEN BRADLEY 12 KOHM, 1/4 WATT
s 1761 SEE 1759
`:~ 1762 SEE 1759
`, 1763 SEE 1759
1 1764 SEE 1759
-'. 1765 SEE 1759
:i 1766 SEE 1759
~ 1767 SEE 1522
:~. 1768 SEE 1522
.;} 1769 SEE 1522
1770 SEE 1522
1771 SEE 1522
1772 SEE 1522
~ 1773 . SEE 1522
`i`~ 1802 CRYSTAL INTERNATIONAL 8.57 MHz
CRYSTAL N74S04
~` 1808 SEE 1511
1810 SEE 1501
~ 1812 SEE 1511
`i.i~ 1814 SEE 1702
i,- 1817 SKEFlL8IlP FLOP SIGNETICS N7476
:~ 1818 SEE 1816
1819 SEE 1816
~i 1820 NAND GATE SIGNETICS N7410
` 1824 SEE 1706
-.;;: 1826 SEE 1702
~ 1830 SEE 1511 SIGNETICS N7404
.~ 1832 SEE 1511
- 1834 AND GATE SIGNETICS N7411
`:s 1838 SEE 1511
~ 1840 SEE 1511
~3 1842 SEE 1706
1844 SEE 1706
d ' 1846 .SEE 1804 `~
~ 1848 SEE 1804
`~ 1850 SEE 1501
s 1852 SEE 1501
1854 SEE 1834
.3 1856 SEE 1834
j 1858 SEE 1501 ~ `
'i :
. ~ .
.
` 1045Z48
i . .
TABLE VIII CONTINUFD
~ PART PART MANUFACTURER MFR ~VALUE
';`!' ; NR` . .. .. .... :
. `' . .
`1860 SEE 1702
:,1862 SEE 1804
.. 1864 SEE 1804
., 1866 SEE i828
1868 SEE 1511
~ .1870 SEE 1537
-'. 1871 SEE 1537
` 1872 SEE 1537
1873 SEE 1537
1874 SEE 1537
:.~ 1875 SEE 1537
`~ 1876 SEE 1537
~' 1877 SEE 1537
~- 1878 SEE 1522
'~i 1879 RESISTOR ALLEN BRADLEY 10 KOHM, 1/4 WATT
1880 RESISTOR ALLEN BRADLEY 47 KOHM, 1/4 WATT .;
~` 1882 SEE 1522
`~ 1883 SEE 1522
1884 RESISTOR ALLEN BRADLEY 2 2 KOHM, 1/4 WATT
. 1886 SEE 1522 ALLEN BRADLEY 5 6.KOHM, 1/4 WATT
~ 188i SEE 1522
: 1888 SEE 1522
` 1889 SEE 1522
`' 1890 CAPACITOR KEMET 22 MFD, 20 VOLT
-- 1894 SEE 1749 CORNELL DUBILIER 51 PF MICA
~`:`l`` 1895 SEE 1749
~`` 1896 SEE 1749
:~ 1897 SEE 1828
.-i.~,~.~1901 SEE 1828
~j~ 1902 SEE 1511
:i~` 1903 SEE 1511
~ 1904 SEE 1820
:~ 1906 SEE 1511
.~` 1907 SEE 1706
:~ 1908 SEE 1506
`~- 1909 SEE 1506
1910 SEE 1828
~' 1912 NAND GATE SIGNETICS N7420
~:~ 1914 SEE 1511
1915 SEE 1820
- 1916 SEE 1828
1917 SEE 1706
- 1918 SEE 1706
: 1919 SEE 1706
-~ 1920 SEE 1501
:~ 1921 SEE 1511
.~. 1924 SEE 1501
:-. 1926 SEE 1508
Y 1928 SEE 1912
-~ 1930 SEE 1506
.
.~ ~
. :.
(
`~ 1045Z48
,... .
s~ TABLE VIII CONTINU~D
- PART PART MANU~ACTURER MFR # ~ ALUE
NR :- ` .......... .
..
. 1932 SEE 1511
1934 SEE 1514
`` lg36 SEE 1537
` 1937 SEE 1537
. 1938 SEE 1537
~ lg39 SEE 1537
: 1940 SEE 1522
~` 1941 SEE 1522
' 1942 SEE 1522
- 1943 SEE 1522
;~ 1944 SEE 1522
.`. 1945 SEE 1522
i 1946 SEE 1522
2002 EXCLUSIVE NOR SIGNETICS 8242
`` 2003 SEE 1816
2004 COUNTER SIGNETICS.N7493
-, 2005 SEE 2004
- 2006 SEE 1828
2008 SEE 1828
~ 2010 SEE 1508
: . 2012 SEE 1828
.`- 2014 SEE 1514
:'. 2016 SEE 1828
:~', 2018 SEE 1828
2019 SEE 1511
2020 SEE 1706
2022 EIA DRrVER FAIRCHILD 9616
: 2023 gEE 2022
`~c 2024 SEE 2022
2026 SEE 1706
~;` 2028 SEE 1828
"~- 2030 JUNCTION POINT
. ~ ~ V ~ C U .~ V
- 2032 -SEE 2030
~:;'R 2033 SEE 2030
2034 SEE 2030
~:` 2035 SEE 2030
l 2036 SEE 2030
"~ 2037 SEE 2030
~ 2038 SEE 2030
i 2039 SEE 2030
:~` 2040 SEE 1749
`;~ 2044 SEE 1537
`;~ 2045 SEE lS22
`~~ 2050 TERMINAL -12 VOLTS DC
~ 2051 TER~INAL ~12 VOLTS DC
2101 SEE 1828
, 2102 SEE lSll
~-.. . 2103 SEE 1511
2104 SEE 1834
`~ 2106 SEE 1511
t 2107 SEE 1828
. . ~
.
- 17~ - _
1'
....
` .
.~; .
.r -~ . . .
: 1045Z48
:'
~` ~ABL~ VIII CONTINVED
1 . . . .
,,
` ~ART PART MANUFACTVRER `MFR # ~ ALUE
NR` ` ` ` ` . . . . . . . . .
.
2108S E 1
. E 834
i, 2110SEE 1816
;~ 2112SEE 1511
2114SEE 1828
~" 2116 EIA RECEIVER FAIRCHILD 9617
:`. 2117 SEE 2116
` 2118 SEE 1816
Zll9 SEE 1623
2120 SEE 1706 -
2122 SEE 1828 :~
.. 2124 SEE 1706
~ 2125 SEE 1623
:~ 2126 SEE 1623
.`.j:. 2127 SEE 1623
``~......2128 SEE 1623
~ 2129 SEE 1623
`~ 2130 SEE 1623
2131 SEE 1623
`'`~ 2132 SEE 1623
2133 SEE 1623
i'i 2134 SEE 1623
`'1`` 2135 SEE 1623
2136 SEE 1623
2137 SEE 1623
. 2138 SEE 1623
~r 2139 SEE 1623
`~, 2150 SEE 1537 .
:~:- 2151 SEE 1537
2152 SEE 1522
`~4` 2153 SEE 1522
2154 CAPACITOR SPRAGUE 0.001 MFD CERAMIC
:2155 SEE 2154
::~ 2156 SEE 2154
2157 SEE 2154
,)~ 2158 SEE 2154
- 2160 SEE 1749
~` 2201 SEE 1511
~' ~202 SEE 1511
~ 2203 SEE 1828
.', .2204 SEE 1816
"J,. ~ ``2206 SEE 2004
~- -~208 OPTION BLOCK
.. `2210 SEE 1511
`. 2211 SEE 1511
.2212 SEE 1511
.2220 SEE 1537
-,. Z222 SEE 1537
2224 SEE 1537
, 2226 SEE 1522
;~ 2228 SEE 1522
.2230 SEE 1749
2301 SEE 1511
.' ~302 SEE 1511
.~. 2303 SEE 1511
: 2304 SEE 1511
.:i
`.`. .
..
., .
., _ .
i
:1045~48
.
, . . . . .
. TABLE VIII CONTI~ED
.,
PART PART MANUFACTURER MER #~VALUE
2~R ' ' ` =
~ . 2305 SEE 1511
'' 2306 SEE 1511
2307 SEE 1511
~`~ 2308 SEE 1511
:` 2309 SEE 1511
2310 SEE 1511
.2311 SEE 1511
,~ 2312 SEE 1511
2314 SEE 1706
2316 SEE 1508
;. 2318 SEE 1828
- . 2319 SEE 1501
.. ; 2320 SEE 1706
;~` 2321 SEE 1706
~,~ 2322 SEE 1828
;.~; 2323 SEE 1501
~:~ 2324 SHIFT REGISTER FAIRCHILD 9300
2326 SEE 2002
2328 SEE 2116
~ ` 2330 FIFO FAIRCHILD 3341
'`51, . 2331 SEE 2330
.E 2332 SEE 1511
~` 2334 SEE 1816
" 2336 SEE 1816
~. 2340 SEE 1706
";, 2342 SEE 1828
. 2343 SEE 1828
2344 SEE 1828
2346 SEE 1623
~,. 2347 SEE 1623
.. '1. 2348 SEE 1623
2349 SEE 1623
`.~ 2350 SEE 2324
` 2352 SEE 1816
"'`. 2360 SEE 1537
2361 SEE 1522
. 2362 SEE 1522
~ 2363 SEE 2154
:`-,;`.: 2364 SEE 2154
`.' 2365 SEE 2154
:'.~ 2402 SEE 1508
~`," 2404 SEE 1828
` 2406 SEE 1834
-~`` 2408 SEE 1511
'1,: .2409 SEE 1511
~-~.; .2410 SEE 1834
2 '~ 2412 SEE 1511
- 2413 SEE 1501
`` 2414 SEE 1501
".`~ 2416 SEE 1511
: 2417 SEE 1511 --
2418 SEE 1511
.
,'.',
:.,
, ~" .
, !" - . .. .
L ~_~
1045Z4~3 :
TABLE VIII CONTINUED
~, PART PART MANUFACTURER MFR #~VALUE
NR - : : . ...................... ..
. . . _ _ .
- 2420 SEE 1828
2422 SEE 1834
. 2423 SEE 1511
......... 2424 SEE 1828
2425SEE 1511
.i 2426SEE 1511
'' 2427SEE 1501
~" 2428SEE 1828
:~ 2430SEE 1828
-j; 2432SEE 1511
2433SEE 1511
~`. 2434SEE 1511
.i- 2436SEE 1816
.s. 2437SEE 1816
2438SEE 1816
~. 2440SEE 1511
i~ 2441SEE 1501
'. 2442SEE 1828
.`~` 2444SEE 1508
~ 2446SEE 1501
``.`.`: 2448 SEE 1511
- 2450SEE 1501
` 2452SEE 1511
2501SEE 2324
2502SEE 2324
2503SEE 2330
- 2504SEE 2330
;.~s,, 2505SEE 2324
`.. ;~.~,~ 2506 SEE 2324
2508SEE 1828
2509SEE 1828
. 2510SEE 1828
~ 2511SEE 1828
.','7S'~' 2512 SEE 1828
. 2513 SEE 1828
25~4 SEE 1828
. 2516 SEE 1623
~```2517 SEE 1623
.`.'~'- -2518 SEE 1623
```x~2519 SEE 1623
.~`:^2520 SEE 1623
2521 SEE 1623
` 2522 SEE 1623
:. 2523 SEE 1623
i`,...... 2524SEE 1501
.. 2525SEE 1706
~: 2526SEE 1706
.~ 2527SEE 1828
.. ? 2530 SEE 1816
~i 2532SEE 1508
'~ ~ 2533SEE 1508
`~, 2534SEE 2002
~, .
,.'~
~,
à, ,
;~
1` lV45248
. ~
TABLE VII~ CONTINUED
PAR~ PART . MANUFACTURER MFR #~VAhUE
. . ~
.
2535 SEE 2002
2538 SEE 1511
`- 2540 SEE 1706
2542 SEE 1511
`. 2544 SEE 1511
.2546SEE 1816
2548 SEE 1816
. 2550 SEE 1706
; 2560 SEE 1537
2561 SEE 1537
~ 2562 SEE 1522
`, 2563 SEE 1522
2602 SEE 1828
~-. 2604 SEE 1816
:~ 2605 SEE 1816
.~ 2608 SEE 1501
1 2609 SEE 1706
-'1; 2610 SEE 1820
;.` 2611 SEE 1511
`` 2612... SEE 1511
. 2613 SEE 1706
~ 2614 SEE 1834
`~ 2616 SEE 2004
~....... 2618 SEE 1828
``~ 2620 SEE 1501
. : 2621 SEE 1834
`~ ` 2622 SEE 1511
-; `. 2623 SEE 1511
`~ 2624 SEE 1511
:~,2626 ~ n~n
$~~ ~
~ 2627 SEE 1706
.~......2628SEE 1511
`,: 2629 SEE 1820
2630 SEE 1511
.~- 2631 SEE 1511
~f.~. 2632 SEE 1501
. 2634 SEE 1511
`' 2635 SEE 1511
~. 2636 SEE 1501
:~, 2638 SEE 1820
2640 SEE 1828
.2642SEE 1511
. 2643 SEE 1501
-` 2646 SEE 1508
.~~ 2648 SEE 1501
2652 SEE 1501
. 2654 SEE 1511
~ ,
~" , 1 ~
:`. ~ -- ,,
.,,, : .
-,;i .
~t
'f
;,~" ,
.~, . .. . .
~ ` ~
-
1045248
,, ., ,~
~,
~3 1 With the foregoing understood, further subtleties
.
of the present invention may be appreciated. For example,
~ .
the interaction between compaction device 54 of Figure 7 and
the input/output structure in the form of input/output
mechanism 50 and 52 of Figure 7 may now be appreciated.
Basically, the input/output structure, especially FIFOs 66 and
102, control the action of compactor 54 of the present invention,
~P while coder/decoder 88 in turn controls some of the interface
.,..j
;,'i signals and accomplishes the compaction and decompaction.
~ .
At original power on, coder/decoder 88 energizes the
I/O hardware, 50 and 52, and proceeds through an initialization
sequence, as discussed above, which generally consists of
clearing all registers and memory and I/O lines. Subsequently,
.,~ - .
~; coder/decoder 88 runs continuously, as instruction address
15 register 1002 of Figure io runs from a free running clock. C~mpQc~o
54 of the present invention then runs continuously, whether or
not data is being compacted or decompacted. There are no
on/off or other controls to operate the compaction device
according to *he present invention, and the compaction device
54 of the present invention runs continuously whenever it is
energized by a suitable power source, not specifically 6hown.
~-~ After initialization, compaction device 54 immediately
enters the receive/decompact mode, i.e. the compaction device
54 attempts to obtain data from modem 6ide FIFO 102. If
;~ 25 data is available from modem side FIFO 102, coder/decoder 88 will
¢~1 obtain the data as from output register 106, and proceed through
~~ the decompaction process as outlined in great detail ~bove~ -
. ,~ , . .
. -, ... .
.i
~". .
,~j
.
~.
.. .
.
,, .~ :` -' , -,
1045248
' 1 However, even in the event dat~ is being received by
modem side converter 114, compaction device 54 of the
present invention generally operates much faster than the
communications line which pro~ides the data, and in this -
~- 5 event, compaction device 54 soon exhausts the supply of
data available and ready in modem side FIFO 102.
In this event, i.e. where moaem side FIFO is empty
~;- of data, and at a location in the microcode as set forth
above with respect to Table VII, when the coder/decoder can
10 safely stop without losing data or causing any timing
problems to the IjO interfaces to the communciations path
with which the compaction device 54 of the present invention
.-.~,;.
interacts with the outside world, coder/decoder 88 will
execute a OUT20 command, which is an output to device 20
.-~
lS instruction. Device 20 is not truly an output device, but
rather a signal to FIFOs 102 and 66. If it is necessary,
because controller side FIFO 66 is completely full of data
s . . .
~` or modem side FIFO 102 is empty of data, that the FIFOs need
to idle coder/decoder 88 and delay compaction, or decompaction
according to the present invention, then the time immediately
following an output to device 20 is the appropriate and safe
,".`.f` time to do so. This output to device 20 signal can then be
,; executed at some point in the above microcode between any two
~" successive microcode instructions providing for input from
.- 25 FIFO 102 or 66 or any two successive instructions in the
.. ,~: . . ..
microcode providing for any two outputs to FIFOs 66 or 102.
.,j
i t .
.~: . -- ,
., - . ,,, . - .~ .
tl~
. . .
`'.
:
'.-` ,'~
.' ~;` ,' ' ' ' ' ' '
` 1045248
1 The logic of both controller side FIFO 66 and modem side
FIFO 102 is then arranged to receive this output to device 20
logic signal, and if either FIFO is not in a condition to
accomplish the required function of providing an input or
~5 an ouput, because of a full or an empty condit-on, the FIFO
.,,,~
--jlogic will immediately force the coder/decoder 88 into an
`; idle ætatus.
.~ ,~ . .
When coder/decoder 88 enters an idle status,
I/O control logic is arranged to take control of data bus 86
"~. .
~;~ 10 from the logic associated with memory 90, stop the flow of
' ~'1' ' . . ~ ~
instructions emanating from instruction memory 92 of memory 90,
and substitute instructions from the logic within FIFOs 66 and
102 which coder/decoder 88 proceeds to execute. That is,
;the instructions provided by FIFOs 66 and 102 are directly
15 substituted for an expected instruction from memory 92, and
coder/decoder 88 has no way of noting the-source of the
instruction, but merely executes the instruction provided.
The effect of the instruction provided by FIFOs 66 or 102 is
to force coderjdecoder 88 into an idle status loop where it remains
20 until logic within FIFO 66 or 102 again indicates that the
full or empty condition which forced coder/decoder 88 into
an idle status has abated. That is, a continuous s~atus check
is made, and the loop is continued so long as the 6tatus which
,~ .
~,~ forced the idle status condition exists. At a time when the full
25 or empty status condition has abated, input/output control
logic 128 provides for a change of ~tatus, and allows coder~decoder
.,
~- 88 to leave the idle status and resuT~e the compaction or
,~ . .. ~ .
decompaction process.
",'' ' ': ' ' ' ' ' ' ::..T
`: ~
.. :~"
~. .
.. .
.. ..
` ~ 1045Z48
`,`. :
~ 1 As alluded to above, eithex of FIFOs 66 or 102 c~n
;~ force coder/decoder 88 into an idle status. Modem side FIF0 102
will cause such an idle status if the compaction device 54 of the
`! present invention is in a receive mode, and FIF0 102 is unable
; S to supply data to compaction device 54, i.e. FIF0 102 is empty
of data. Controller side FIF0 66 will force coder/decoder 88
into an idle s~atus if compaction device 54 is in a receive mode,
and FIFO 66 is unable to accept data from compaction device 54
`3
of the present invention, i.e. FIFO 66 is full of data and has
10 no further ability to accept more without a loss of data.
-~!
The foregoing then describes the interaction of
compaction device 54 and input/output members 50 and 52 during
~: the receive mode. As a further subtlety of the present invention,the normal state of compactor 54 of the present invention is
15 the receive mode, and either in an idle or active status depending
on the status of FIFOs 66 or 102 as discussed above. If no data
is being transmitted to compaction device 54 of the present
invention, the compaction device at each end of the data path
or transmission line E of Figure 1 will exist in the receive
20 mode and also in idle status. Two specific conditions can release
compactor 54 from its idle status. The first factor is if modem
~ide ~IF0 102 should become not empty, i.e. ~ome data should
~ r . :.
enter modem side FIF0 102, and also controller side FIF0 66
~~ become not full, i.e. be in a condition to receive and accept-data.
. ~ .
25 The logic circuitry for both FIFOs 66 and 102 will then provide
logic signals to coder/decoder 88 indicating their condition
and since control logic for coder/decoder 88 is constantly
monitoring the logic signals from FIFOs 66 and 102, the
. .,; ,
;~ - control logic for coder/decoder 88 enables leaving the idle
` status. Compactor 54 will then return to the active status - ~~
... .
~ r '~~' in the receive mode.
~ ,' 1~
.- ~ .. , ~
,... ~
,, ~
.
10~524#
1 The remain~n~ cond~ti~n which allows compaction
: device 54 of the present invention to leave the idle ~tatus
~s when a status line RQT ~ignal, request to transmit signal
~ ,.
from line controller ~ in the exemplary example, becomes high
S which is evidenced by the transmission of a positive 10-volt
signal in the example given. This signal from controller B
. ~
i indicates that the line cor.troller B has data ready to ~end.
. .~, . .
Coder/decoder 88 then leaves the idle status. receive m~e,
and enters the active ~tatus, transmit mode. The necessary
10 and conventional control signals are then transmitted by
coder/decoder 88 to the controller ~, and further appropriate
clock signals are provided to controller side converter 56 which
~`, then attempts to synchronize on the data in a well known fashion
used by many communications devices. Coder/decoder 88 then
15 ~egins attempts to remove data from output register 70. If data
is not yet present, logic associated with controller ~ide FIFO 66
.... .
again takes control of data bus 86, in the manner discussed above,
~n and coder/decoder 88 is forced into idle status, transmit
~ode which is identical to idle status, seceive mode, ~xcept
` 20 that coder/decoder 88 will return to the transmit mode upon
leaving idle status.
r.. ' The necessary conditions for coder/decoder 88
to leave the idle status, transmit mode ~re tl) ~ontroller !side
FIFO 66 not empty and modem side FIFO 102 not full or t2) the
25 RQT, reguest to transmit, 6ignal from controller B low, off,
or at a voltage of a minus 10 in the present çxample~Qn~inQ~dirion
~odem side ~I~O 102 empty. In the first condition, compaction
~evice 54 will enter active status, ~transmit mode, and in the
event ~f the second condition, compaction ~evice S4 of ~he
Fresent invention will retuxn to idle status, receive mode.
1~9
-- ~5 --
- . ' ' - - ,, - ,., '.
.
,
,
A . . : :
10~5248
. .
. ~
1 In summary, the interaction between the status
of FIFOs 66 and 102 and the mode of compaction device 54
according to the present invention is: compaction device 54
will always be in the receive mode if a RQT signal is low,
~ S at a minus 10 volts in the present example, and compaction device t
;~ 54 will always be in the transmit mode if an RQT signal is
, . . .
high, a positive 10 volts in the present example. If compaction
device 54 is in the receive mode, cader~decoder 88 will be
;~ in an active receive status if modem side FIFO 102 is
``~ 10 not empty and thus coder/decoder 88 may obtain data, and
controller side FIFO 66 is not full, and thus coder/decoder 88
has a temporary storage location into which to put data. If
:. ,
compaction device 54 is in the transmit mode, coder/decoder 88
will exist in an active status, transmit mode if controller side
`1 t ` ~ `
` 15 ~IFO 66 is not empty and thus coder/decoder 88 may obtain data
to transmit, and modem side FIFO 102 is not full, thus offerin~
coder/decoder B8 an opportunity to store data without a loss.
The transition between modes is occasioned by an RQT signal
~` change. For example, if the RQT signal drops low while connection
20 device 54 is in a transmit mode, coder/decoder 88 will and
~ust wait unti~ any data in modem side converter 102 has been
. clocked out onto the transmission path or transmission line E.
~` However, upon an RQT signal returning high while compaction
~: . .
:r~" controller 54 is in the receive mode, the transition to transmit
25 mode is immediate.
In further summary, the.transition betweeen idle
~status an~ active ~tatus in either mode is totally dependent on
;~ the status of PIFOs 66 and 102, and the 6tatus of these ~IFOs
i~ ~s in turn dependent upon external circumstances such as line
... ..
`~- speed, data patterns, interface speed, and like circumstances.
`.' .,
~ 18~ -
~;. ~
, ~. ' '
1;- ~ ' . .
`; 104524~
.
1 The transition from active status to idle status and back
again may not happen at all in a given block of data, or
:, it may happen as often as every data character which crosses
.,;
. either converter.
S For further subtleties according to the
present invention, the action of coder/decoder 88 while in
the active status can now be further appreciated. As data is
. made available to coder/decoder 88 from controller side FIFO 66
at the transmitting end of the line, each character is first
10 checked to see if it is the same as a similarly positioned
~ character in whatever prior record is stored within data memory
::,s- 94. If the current character is found to be identical to a
. ~.7 .
character positioned in the prior record in the same position
. as the current character occupies in the current record, the number
... ~ 15 of like characters are counted and an appropriate code is sent. ~ to modem side FIF0 102.
.~- This check for a 6imilarly positioned character is
;~ ~ccomplished by successively providing the current characters
.. from the ~elected FIF0 into accumulator 1012 of coderjdecoder ::
20 88 and directly comparing the character in accumulator 1012
against the contents of the memory location representing the
position of the current charaater in the current record.
That is, $f the current character is the tenth character in
the record, it is compared against the tenth character of the
~,
~`F - 25 prior record, as stored in data memory 94. Data memory 94
~ . $s then continuously compared against the current character ln
:~ accumulator 1012, and the result tested. So long as the current
:-. character and the character residing in memory compare, the memory
., ~ ~ ~,
address register i8 ~ncremented and a new character is read from
i controller side PIFO 66 to compare against the currently addrèssed ~
~ character in data memory 94.
;, ~ ~ } ,
:'.
,.~, ,
':~, ~.. , ,, , , , . ' ,
i 1045Z48
.
1 As soon as a no match conditio~ exists, a brief arithmetic
calculation is accomplished ~y arithmetic and logic unit 1009
of coder/decoder 88, and the code shown in Table IV is produced-
; indicatin~ the number of similarly positioned identical
; 5 characters. It is to be noted that this comparison procedure
always takes place utilizing data as it is received from or
delivered to controller side FIFO F8, that is noncompacted
data.
-`i, .
Upon finding a prior record match, the system produces
. ':~ .
^~ 10 the level 3 code, indicated in Table rv, to indicate this condi-
,-
tion exists, and prior record, or vertical compaction may take
~^ place. This level 3 code is then followed by a count indicating
!
the number of identical characters in the manner set forth
i;;-
~- hereinbefore. -
~- 15 When a nonmatching character is reached, or a no
match condition exists, the nonmatching current character is
next subjected to a test to indicate if it may be the same
as the prior character of the current record being compacted.
~ If the current character is identical or the same as the
-~ 20 prior character of the record being compacted, again the number of like characters are counted and an appropriate code is
created in much the same manner as discussed above with
., : .
- respect to prior record comparison, and the encoded or compactedr
data is transmitted to modem side FIF0 102 in the manner
~" 25 previously described. ~ ;
~ This transmission occurs until a no match
;~ condition exists between the current character tested and the
~ prior character fitored in a general purpose register 1018, -
?,'i~
~* whereupon coder/decoder 88 holds the current character in
' accumulator 1012 and performs an INPl, input from device 1,
,
.
~ - - 18B -
`L
. . .
: ( ~
`` 1045Z48
`.
1 instruction. This instruction sends the INPl and the contents
of accumulator 1012 onto data bus 86, and then follows by accept-
` ing the contents of data bus 86 into accumulator 1012.While the contents of the accumulator and the INPl
5 ihstruction are provided to data bus 86, the I/0 memory 96
~` logic is performing a simultaneous process. The logic of
`! I/O memory 96 first holds the contents of data bus 86 in
-~ a register, then, if the next eight bits appearing on
data bus 86 comprise a~ INPl instruction, I/O memory 96 uses
10 the first received data to address the indicated location
~ in I/O memory. The logic associated with I/O memory 96 then
i ~ piaces the contents of the conforming memory location back
onto data bus 86 in time for coder/decoder 88 to read the
contents of the memory location back into accumulator 1012.
. ., ~. . .
~ 15 The entire process takes place during the execution of a
,. ~t,~ .
~`~ single INPl microcode instruction by coder/decoder 88.
., .,~ ~,
`~` ~ Once the contents of the particular memory location
-~ of the I/O memory have been read into accumulator 1012 of
; ~ coder/decoder 88, coder/decoder 8B then checks the eight bit
~.,.,
20 code by adding the accumulator to itself in the arithmetic and
logic unit 1009 to thus sot the condition flags and then checking
~ the condition flags. The eight bit code is as shown in the
*~ 11sting for the I/O memory, found in Table VII, and this code
~111 determine exactly what particular compacted code
25 i8 sent to modem side FIFQ 102 for provision to co~unications
.. , :. .
;~- -line E. The current character is then shifted back to its
,, ~ .
~ original position in accumulator 1012.
.
"~
~ IY3
.
. , '
,., ~
,t .
.,Y,, ~ `
'~ . _, ' ' ` `
:`
1045248
,
1 Thus, for the preferred embodiment of the present
invention utilizing a 256 character character set, one memory
location in I/O memory 96 is allocated to each character. As
each character is stored in accumulator 1012, the character
5 forms an address to I/0 memory 96 to provide an access to
~`- the code associated with that particular character. Further,
the codes associated with the respective characters have
~ been uniquely selected to minimize the data transmission and
;~ maximize the compaction according to the present invention.
`` 10 This subtlety of the present in~ention may be more easily
explained after a discussion of the particular codes.
At this point, it must be understood that the
eight bit code read out of the I/O memory 96 is not necessarily
the code which will be transmitted to the modem side FIF0 102.
;
15 Since a given compacted code ma~ be 4, 8, or 12 bits in length
and the I~O memory contents is always 8 bits, this clearly
cannot be the case. Rather, the eight bit code which is
obtained from I/0 memory 96 is provided to accumulator 1012 to
provide the information from which the coder/decoder 88 can rapidly
;i~ 20 generate the actual compacted code which is then transmitted to
n~dem side ~IF0 102, and then onto the communications line E.
As each class of code is obtained from the I/O memory 96,
coder/decoder 88 generates the actual compacted code as set out
in Table IV in such a way as to minimize the actual amount of
25 data tra~smitted.
. ., ~
.. ,~,i ~ - . .
. ` ' . _ .
.:
,~ '^''. ' ~ ' ` '
'.' . ~ '.
.~ i.'
.
. 1045Z48
...
. ~,
`,,.5! 1 ~ Therefore, if the code retrieved from the I/0 memory is
' 'i
a hexadecimal 00 as represented by the bit string 00000000, -
this is uniquely indicated by the zero f.lag on in condition flag
1034, and this hexadecimal 00 code indicates a level 16 character,
~ 5 as set out in Table IV. In this situation, the lower four bits
~j of 0000 are sent to modem side FIFO 102, as the control code set
ci' out in Table IV, and the eight bit character itsel~ follows as
.~ data from a general purpose register 1018 within coder/decoder 88,
where the character was stored while the I/O memory 96 code was
c 10 provided to accumulator 1012.
3 As an example, if the input data character is a
`~ hexadecimal 54, i.e. one of the unnamed characters in the EBCDIC
set, this would cause the coder/decoder 88 to input location 54
.~ ~ from the I/O memory 96 as shown in Table VII. The content of
`~ . 15 this.location is a hexadecimal 00, which would cause a control
code output of a hexadecimal 0 followed by a data output of
;~
hexadecimal 54. This three hexadecimal digit output may also be
~- represented as a bit string of 0000 0101 0100 as shown in Table IV.
If the code extracted from I/O memory 96 in.response to
20 the character address is a hexadecimal 4N, where N indicates
`! - any hexadecimal character, the hexadecimal 4 is uniquely indicated
.. '.~ by the sign flag on, in condition 1ag 1034, and this also
.~
indicates a level 16 code, but a code reserved for special control
~s`~ characters for particular protocols and requires special attention.
25 The iprotocol codes are used to flag when a block or a record
,:i? ends or beginst where records are not otherwise separated, in
` order to save data for the prior record mask. For this condition,
.
~i four bits of the hexadecLmal 0 iare first sent out, to indicate a
:: .
- level 16 code, then four bits of the hexadecimal F, and ~hen the
~: low order four bits fram the I/0 memory.
.... .
,., . -~ - .
,'~- ~t- , , -
~ 10452~8
1 As an example, if the input data character was
a hexadecimal 2D, i.e. an "ENQ" control character in the
EBCDIC set, this would cause the coder/decoder 88 to input
location 2D from the I/O memory 96 as shown in Table VII. The
5 content of this location is a hexadecimal 48, which would cause
a control code output of a hexadecimal 0 followed by a data output
.,
of hexadecimal F8. This three hexadecimal digit output may
also be represented as a bit string of 0000 1111 1000 whlch is
a modification of the normal level 16 character to flag it as
`-~ 10 a control character in this specific application.
~ . .
; If the code extracted from memory is a hexadecimal 8~,
where N again represents any value permissible, this condition
,
'```".-' ~S uniquely indicated by the carry flag on in condition flags
. . ~ ., .
~ 1034 and indicates a level 1, 2, 4, 5, 7, 8, 9, 10, 11, 12, or 13
:.`.'~'
;j3 15 control code which, from Table IV, requires only a four bit control
code and no data code since only one character is represented at
these levels. The low order four bits from I/O memory 96 æ e then
transmitted to modem side FIFO 102 as this control code.
.Xr~ As an example, if the input data character was a
; 20 hexadecimal C5, i.e. an alphabetic nE" in the EBCDIC set, this
would cause the coder/decoder 88 to input location C5 from the I/O
' memory 96 as shown in Table VII. The content of this location
~- is a hexadecimal 85, which would cause a control code output
of a hexadecimal 5. No data bits follow as only one character
25 exists at this control level. This one hexadecimal digit output
may al80 be represented as a bit string of 0101. As may be seen
by Table IV, this is the control code for level 12, a which
only the letter E exists.
;. . - . ~- ~ . .
.,. . :
:
,t;
,t .
. } .`,. .
, ` .
.' i'
..~..
" ~045248
1 If the code is a hexadecimal lN, with N again indicating
any permissible character, this condition is uniquely indicated
by bit four, and indicates a level 14 code which requires a four
bit control code and a four bit data code, as discussed above with
5 respect to Table IV. The high order four bits then are provided
to modem side FIF0 102 as the control code and the low order four
.,
bits from memory follow as the data.
As an example, if the input data character was a
,
hexadecimal C6, i.e. an alphabetic "F" in the-EBCDIC set,
10 this would cause the coder/decoder B8 to input location C6 from
~.
the I/O memory 96 as shown in Table VII. The content of this
~ location is a hexadecimal 10 which would cause a control code ouptut
-~ of a hexadecimal 1 followed by a data output of hexadecimal 0.
.. ~
~his two hexadecimal digit output may also be represented as
15 a bit string of 0001 0000. As may be seen by Table IV, this is
the bit string for the first character in level 14, or an alphabetic
F.
~
If the code retrieved from I/O memory 96 is a hexadecimal
~ 2N, where N ~gain represents any permissible character, this
`~ 20 condition is indicated uniquely by bit five and indicates a level
`~7~c 15 code. From Table IV, a level 15 code requires a four bit
; control code and a four bit data code, and thus the high order
four bits retrieved from memory 96 are provided to modem side
FIFO 102 and are followed by the data as similarly retrieved.
As an example, if the input data character was a
.
; hexadecimal E8, i.e. an alphabetic "Y in the EBCDIC set,
this would cause the coder/decoder 88 to input location E8 from
the I/O memory 96 as shown in Table VII. The content of this
~location is a hexadecimal 21 which would cause a control code
; , , . _, ,
~ I 0 ~
I ~ I
.
. ~ ~
1045Z48
. . .
1 output of a hexadecimal 2 followed by a data output o~ hexadecimal
1. This two hexadecimal digit output may also be represented as
a bit string of 0010 0001. As may be seen by Table IV, this is
the bit string for the second character in level 15, or an
5 alphabetic Y.
- Thus, coder/decoder 88 uniquely proYides the appropriate
x codes to modem side FIFO 102 for transmission to the modem and
to data path or communications line E. As each character is
:
~ pro~ided from controller side FIFO 66, and the eight bit format
'`:?': 10 assumed for the example set out, it is then first checked in
the manner set out above in an attempt to determine if it is
identical or the same as a similarly positioned character in
` SI .
a prior record, by a direct comparison against the appropriate
- location in data memory 94, and if no match is found, is
~- 15 checked as indicated above in an effort to find if the current
. . .
character is the same as a prior character by direct comparison
against this prior character held in a general purpose register
1018, and if neither condition exists, resort is had to the code
stored in I/O memory 96 to generate the appropriate control and
20 data codes.
.. . .
If at any time, output shift register 106 for modem
side FIFO 102 becomes empty, and there is no four bit code
waiting in FIFO 102 to drop into register 106, the logic
associated with modem side FIFO 102 will shift in a hexadecimal
- 25 F for transmission as a normal character. -~his hexadecimal ~
- character F is the compactor ~idle" used to compensate for the
; wide variety of line speeds,~interface speeds, and data patterns
encountered. This i6 interpreted at the receive end as a
`'' ` 'r level 6 control code.
.... . .
, ,, ~
~ 8
!`
~ ~ , ' '
;
1045Z48
: .~
1 As the data then passes across the dat~ path or
.:, . . . .
transmission line E, the data becomes available at the modem
side FIFO 102 of the device at the receiving end of the line
~` in the manner previously desc~ibed. At the tLme data is available
~` 5 at the receive modem side PIFO 102, this FIFO allows coder/decoder
~` 88 of the receive compaction device to enter the active state,
receive status.
As coder/decoder 88 of the receive compaction
device extracts the first four bits from output register 106
10 Of the receive modem side FIFO 102, these four bits are
tested by the coder/decoder 88 for the appropriate control level.
i.~
`l If the first four bits represent a hexadecimal F, this indicates
~- à level 6 idle control character, as indicated in Table IV,
and the control character is deleted-without being passed on to
, ~$~. 15 controller side FIFO 66.
If the first four bits are a hexadecimal 0, and the
."~:
next eight bits are not a hexadecimal F0 through F9, this is
;j indicative of a level 16 character as represented in Table IV,
and coder/decoder 88, under the direction of instruction memory 92,
~ 20 deletes the initial four bit control code, and passes the next
`~ eight bits representing the character to input shift register 62
for transmission to controller side FIFO 66.
If the first foux bits xeceived represent a hexadecimal
0, and the next eight bits received represent hexadecimal F0
~, 25 through F9, this also represents a level 16 control code; but,
.
not as represented in Table IV, but a special control character
- for the given control protocol which requires special attention.
:,
These characters are decoded and used to flag start and stop
points for a block or record and allow the data compression device
... .
~ )8~
^r: . -
~',' ' .
:
." la4sz4s
' 1 of the present invention at the receive end of the line to note
" the end or beginning of a record and thus allow the compression
', device at the end of a line to maintain its prior record mask
identical to the record mask at the transmit end of the line.
:; .
In this case, the hexadecLmal 0 control code is dropped by
'? , coder/decoder 88 under the direction of instruction memory 92,
., ,~; .
"'!" and the next eight bits form the address ~or ROM 1603 forming
~ a portion of instruction memory 92 as represented in Figure 16,
'~- where the appropriate character is stored. This character ,-
10 is then transmitted to controller side FIFO 66.
If the first four bits represent a hexadecimal 1,
this code identifies a level 14 character. In this case,
'~ the hexadecimal 1 and the next four bits form an eight bit
~ address ~lN~ which is the location in ROM 1604 of instruction
''.. 'i~ ! ' ~
,~ 15 memory 92 in which the eight bit character may be found. This
- 1`
eig,ht bit character is then transmitted to input~output 50
under the control of coder/decoaer 88.
If the first four bits represent a hexadecimal 2,
~'' this indicates a level 15 character, and again the hexadecimal ~ - ,
20 2 and the next four bits form an eight bit address "2Nn
which is the location in ROM 1604 of instruction memory 92
where the eight bit character may be found. This character
is similarly passed to controller siae FIFO 66. , ~,
If the first four bits from modem side FIFO 102 ~-
25 repre6ent hexadecimal number6 3, 4, 5, 6, 7, 8, 9, A, B, C, or
. ~ -; .. . . . . .
,~ D, these codes signify control levels 11, 8, 12, 9, 10, 13, 7,
,~ , .
~, 4, 2, or 1, respectively. Upon the finding of one of the
~bove enumerated codes, a hexadecimal F i6 provided by the~
~- coder/decoder 88 ~nd is used for the high order four ~its of the
~,~ address along with the control code a6 the lower order of four bi-'s
." . . .
:~ .
~, 1045Z48
,
1 o~ the address, and together the eight bits form the address in
ROM 1604 where the character may be found and provided to controller
~ide FIFO 66 in the manner described above.
,
If the first four bits represent a hexadecimal
. ~
5 E, this character indicates control level 3 as described in
... .
~able IV. The next four bits received then indicate the
count and whether the bit string is the same as the prior
record, representing vertical compression or compaction,
i
``! ~ or the same as the prior character of the current record,
i~ 10 representing horizontal compression or compaction. The
i
appropriate characters are then extracted and passed to controller
` ~ side FIFO 66 as described hereinbefore.
.~. .
If the second four bits represent a hexademical 5
through a hexadecimal F, this indicates prior record compaction
. ,- .
~ 15 and the appropriate number of characters as shown in Table IV are
~, .
extracted from the data memory 94 and passed on to the controller
side FIFO 66. If the second four bits represent a hexadecimal
0 through hexadecimal 4, this indicates prior character
compaction and the character in general purpose register l018 is
20 extracteA an appropriate number of times as shown in Table IV
and passed on to the controller side FIFO 66.
~,- At the completion of a block of data, the compactor
u~ at the transmit end of data path or line E, is forced into
, . - ~
a receive mcde, idle status, by the fact that the RQT ~request
-25 to transmit) signal has dropped and that modem side FIFO 102 :
~ndicates an empty status. Also, the compaction device at ;~
c
~ the receive end of the line has also been forced into a receive
~ :.
.
, ,.: . . . . .
: . .
) q I
, .. . . ... .. .
~ .~'~.,`'.~.;` `,; ~
,, ..
.' . ~ , , .
1045248
, .
. .
.. .
`~ 1 mode, idle status, by the fact that modem side FIFO 102 also
,,i .
~ inaicates an empty status. sOth compactors are then ready
:,i
`~i for the next block of data, regardless of which end of the
line the data emanates from.
~':3! 5 It can now be seen and appreciated that coder/decoder ~8
and the logic associated with FIFOs 66 and 102 share the control
; of compaction according to the present invention to achieve a
device which has the maximum efficiency in terms of speed capacity
.,. .~,:
` when the data rate is highest and the minimum efficiency at
.. ~ .
'~ 10 times when the data rate is low or absent. This is possible
by making all status changes to an idle status by external
logic of the FIFOs 66 and 102. This relieves the coder/decoder
:,~
of any responsibility for monitoring the FIFOs when it is busy.
By comparison, when idle, the coder/decoder 88 has nothing to do and
. i ~
15 does most of the monitoring of the FIFO status lines. This is
contrary to normal practice which usually gives the heaviest
;~ ~ extra load to the main logic device just when the load is ~~-
, .~ ~ .
heaviest.
- -It oan also now be seen and appreciated that
20 I/O memory 96 logic in conjunction with coder/decoder 88 can perform
~` a 256 way table lookup in one machine instruction.
It can now also be seen and appreciated that
the compaction code provides a rapid compaction and decompaction
by a high degree of table usage. All of these ta~les have been
25 shoWn in the microcode of Table VII. - ~-
It can further be seen and appreciated that the
compaction code is completely nonambiguous and that all informa-
:;:,. . .
i~ tion needed to decompact is self-contained in the code or is
.~ .
` `-~ extracted from the code. - - -
. ~ - ,.
: . ,, ~
~ .d r' ~ : ~ I92~
. ~ `
., .~, ,- . . . .
.. , . . ..
(
1045Z48
:;
j
1 It can still further be seen and appreciated that an
idle character may be used to allow a high degree of flexibility
~ with respect to line speeds, interface speeds, and data content
and type.
... .
It can still further be seen and appreclated that
`~ compaction a~cording to the present invention is highly adaptive
~ to the format and content of data passing through the device
`~ according to the present invention, and that since this adaption
is done after the fact, no data is delayed more than a few
10 milliseconds. This sequential, real time, adaptive data compression
makes a data compactor according to the present invention the
compactor of choice, if not ideal, for many applications where
' ' ' t
other techniques may not be used due to an inherent delay in
working on a block by block basis incorporated in these previous
15 and prior techniques.
It may still further be seen and appreciated that
a total and completely accurate reconstitution of the data
compacted according to the present invention renders the
- present invention the compactor-of choice, if not ideal and
20 required, for any application where total accuracy is a requirement.
It may now further be seen and appreciated that the
present device provides a transparent intOE face which interferes
r in no manner with data transmission on a data path.
`.,: 4.~ ~ .
~ It may also be seen and appreciated that data compaction
. . . .
25 aooording to the present invention integrates prior record, prior
~- - -~haracter, and character frequency techniques into a single,
~:; .................................... . .
"t integrated, highly expandable data compression method and apparatus,
~- heretofore not available and oonsidered only remotely possible if
-at all. ~~Y `
. ~ .
~ 193
: ~
t'~'t.~:'X'~
:
~.' .'
.' : . . .
`~ ) ~
1045Z48
,
i 1 It can further now be seen and appreciated that
,~
an entire 256 character character set is usable according
~i to the present invention through its use of a variable number
base encoding scheme, and that the present invention allows
5 an open ended and highly expandable further encoding scheme
allowing thousands of characters to be utilized ana processea
~` without an addition or disturbance of the normal character
set or the techniques or apparatus presented herein, with the
minor exception of increased memory size.
It can further be appreciated and seen that the
present invention utilizes FIFO stacks to smooth the flow
of data and guarantee a maximum throughput.
. i .
Now that the basic teachings of the present invention
; ;~ have been explained, many extensions and variations will be
15 obvious to one having an ordinary skill in the art. For
example, the present invention has been explained in relation
~ to a specific transmission path between a controller and a
`-;~ ~ modem and another modem and a controller and for a specific
. ~.. ~. ,
~:~ -application. No limitation to this approach is intended. It
20 is intended that the techniques and apparatus of the present
invention be utilized upon any transmission path between any
two devices or upon a looped transmission path. Thus, by
way of example and not limitation, compaction devices according
; to the p~esent invention are envisioned as usable between~
25 bulk-storige or external memory devices or large computing
i``` systems, such as disc or core storage, magnetic tape storage,
' i': .
.... . . .
. ~9~ .
... . ~, ....
. .~ . ; " . ~.,,
.. .
.. - ~ .
., .. , , . . . , ,, - - - - - - ` - -
:: `
~ ~045Z48
1 paper tape storage, and the like, and the central processor
, . ~ , .
.i for that computing s~stem; between two such storage devices
:~ themselves; between two such central processors themselves;
. between two peripheral devices, whether with a central processing
i 5 unit or not; between a peripheral device and a storage device,
;;;~ either with or without a central processing unit; and between any
::~. two communication devices; or in a data loop interconnecting with
: one or more of the above devices, or similar or other arrangements,
~ as will now be obvious to those skilled in the art.
-~ 10 Also, the present invention has been explained
.. ~ utilizing input/output devices, such as devices 50 and 52 of
. ~ the figures. It will now be recognized that these devices
.
: ~ are not necessary. Systems and apparatus may thus be designed
~ ~.~ with or without such input/output devices. The techniques
j ~ 15 and apparatus associated with compactor 54 are not dependent
.
. i~ upon the input/output devices set out; but the input/output
.~ ~ devices set out are clearly preferred for the environment set
. ~.. ; forth.
~, ~ .
Further, the word "compaction~ as used in the description :
20 of the present invention indicates both the generic meaning of
. ~ a device utilizing the teachings of the method and apparatus
`. according to the present invention, including compaction, only
t ~ decompaction, or both and the particular section of a device
~ccording to the present invention which compacts data or ~ymbols.
Furthermore, while the compactor according to the
- present invention has been described herein as including both
.`. a compaction section and a decompaction section on both ends
~ of a transmission path, this is not necessary either. .. Sy~tems
.:. -
,.,
,,
., ~i'.' '
. ~
;; li
- iO45Z48
,,
y 1 such as a simple path to a stor~ge device may utilize only
two lines, a line into the storage device
and back from the storage device, and only one compaction
device according to the present invention. Also, special
5 situations may dictate the use of only compaction or only
, decompaction on one or both ends of a transmission path.
~` All of these situations are intended to be`embraced within
~ the teachings of the present invention. ` ~`
'`~; Furthermore, one device according to the present ~ -~
10 invention may be utilized with more than one transmission path, -
~ or one device according to the present inventiqn may accept
- many inputs from various other devices, provide an output to
,`~ one device, or alternately one device according to the present ~ -
invention may accept an input from a single device and provide
` 15 an output to many devices, or any combination or intermediary
arrangement may be utilized. Also, any of the above may occur
" with or without additional buffering.
~; Still further, it will be recogniz d by those~skilled
in the art that the teachings according to the present invention
20 can be utilized with or without buffering in any environment.
, ~
~ ~., .
~. ' ' ~ ''
: .
; ~
., ~.c: .
~,, -
.~ .
.~ . . .
. ~ , ~
, -
. .
.
.
,~ ,
. ;'
, , 1 9(~
,, c, _ ~ _
., ,. .. ~.... .,.. . ,, . , , ~ .
. .~
.. . . . . .
