Note: Descriptions are shown in the official language in which they were submitted.
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C:~NTR~L PROCE~ G l~NI~ FOR
A DIG:ITA:~ CO~P~ER
Backgrouna Or tho Inve~tion
A number of digital computers hav~- b~en developed
in recent years with virtual memory management systems, 32
bit data paths, data caches, the ability to use a variety of
data types and addressing modes, variable length instruction
~ormats, and other advanced ~eatur~s. To date, however, the
result of including such features has been a computer of
considerable cost and physical size. Fox example, it woulA
: not be unusual for the central proce~ing unit o a computer
having the attributes listed above to occupy 500 sguare
inches of circuit board space. As a consequence, it has been
impo~sible or impractical to use such c~mputers in many
applications.
8um~ary o th~ In~entio~
~ he present invention provides a central processing
unit for a digital computer that is compact and economical,
and yet supports a 32 bit da ta path, varia~le length
: 20 instru~tions, a variety of addressing modes, and other
advanced featur~s. The central processing unit utili2es a
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pipelined, micro-programmed design and includes a number of
hardware features that permit implementation of powerful
functions with extremely compact microcode.
In a preferred embodiment, the central processing
unit of the present invention comprises a plurality of
pointer registers which may be used to indirectly address
oth~r registers. Each of a plurality of general r~gisters is
assigned a register address. During the decoding of a
macroinstruction that re~erences a particular general
register, a pointer register may be loaded with the reglster
address of the general register. When the macroinstruction
is executed, the general register is accessed ~y using the
contents of -the pointer reyister as an address to select the
general register. Each pointer register has a~signed to it
(i) a direct address specifying as an operand the contents of
the general register, and (ii) a unique indirect address
specifying as an operand address the contents of the general
register~
The invention may be summarized according to a
first aspect, as a central processing unit for a computer for
decoding and executing macroinstructions comprising an
operation code (op-code) and first and second operand
specifiers, wherein each operand specifier includes a
register field and a mode field for specifying literal
operands or direct or indirect addressing modes, each
macroinstruction heing executed by executing a series of
- 2a - 72786-lD
microinstructions corresponding to said macroinstructi~n op-
code, and including a micro op-code a:nd first and second
micro-operand specifiers having register and mode fields,
said central processing unit comprisi:ng: a pluraiity of
yeneral registers for the temporary storage of data
represellting operands or location of operands, each general
register having a unique address associated therewith; at
least two pointer registers for the temporary storage of
data, including data specifying the address of a general
register and data representing the literal value of an
operand, each pointer register having assigned to it ~i) a
direct address specifying as an operand the contents of the
general register addressed in the register field o~ one of
said micro-operand specifiers and (ii) a unique indirect
addre~s specifying as an operand address the contents of the
general register addressed in the register field of said
micro-operand; decoding means for decoding the
macroinstruction and for loading the register fields thereof,
without alteration, into respective pointer registers; and
2~ execution m~ans for executing the macroinstruction by
executing said corresponding series of microinstructions, the
execution means including an ALU having first and second
irput ports, and register accecs means Por providing data
:
3~
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specifie~ by a first pointer register to said ~irst input
port and ~or providing data specified by a second pointer
register to said second input port.
The invention may be summari.zed according to a
second aspect, as a method for executing macroinstructions in
a central processing unit, via arithmetic logic unit (ALU)
means having first and second input ports, said
macroinstructions comprising a macroinstruction operation
code (op code) and first and second operand specifiers each
lC including a register field and a mode field for specifying
literal operands or direct or indirect addressing modes, each
macroinstruction b~ing executed by executing a series of
microinstruc~ions corresponding to the macroinstruction
operation code, each microinstruction including a micro
operation code and first and second micro-operand specifiers
having register and mode fields, said met~od comprising the
~teps of: temporarily storing macroinstruction data
repreRsnting operands or location of operands in one or more
general registers each having a unique address associated
therewith; loading the register fields accompanying a
macroinstruction, without alteration, directly into
corresponding ones of a plurality of pointer registers, each
; pointer register adapted to tempvrarily storing
~: macroinstruction data and having assigned to it (i~ a direct
~ address specifying as an operand the contents of the general
:
~ ', ':' .
366G
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register addressed in the register field o~ one o~ said
micro-operand specifiers and (ii~ a uni~ue indirect address
speciXying as an operand address the contents of the general
register addressed in the register field of said micro-
op2rand; specifying th~ pointer register data as the literal
value of an operand whe~ said mode field in said decoded
macroinstruction specifies a literal oparand; designating
the pointer register data as a direct address when said
decoded mode field specifies a direct addressing mode;
designating the pointer register data as an indirect address
when said decoded mode field specifies an indirect addressing
mode; providing data specified by the first pointer register
to said first input port of said ALU; providing data
spec.ified by the second pointer register to said second input
port of said ALU; and executing said macroinstruction by
executing said corresponding series of microinstructions by
using as operands data provided by said first and second
pointer registers to said ALU ports.
The invention will now be described in greater
detail with reference to the accompanying drawings, in which:
Figure 1 is a block diagram of a computer system
: incorporating the central processing unit of the present
invention;
Figure 2 is a block diagram of one embodiment of a
central processing unit of the present invention;
~:s~
- 2d - 72786-lD
Figure 3 is a block diagram of a microsequencer ~or
usa with the central processing unit of the present
invention;
Figure 4 is a table illustrating the method ~or
determining the nsxt microaddress by the microsequencer;
Fiyure 5 is a table indicating the control signals
that
e 72~86-lD
~2~-
may be used to modify the next microaddressi and
FIGURE 6 is a block diagram detailing the con-trol logic
unit of the central processing unit o~ the present invention.
FIGURE 1 illustrates a computer system which includes
a preferred embodiment of the central processing unit of the pre~
sent invention. The computer system incl.udes central processing
unit (CPU) 10, system bus 20, memory array 22, and console ter-
minal 24. The computer system can also include various peri-
pheral devices (not shown) connected to system bus 20, for example
disk controllers and network interfaces. Console terminal 24 may
be omitted if a suitable interface is provided on bus 20, e.g., an
interface to a local area network. CPU 10 consists of memory
control module 12 and data path module 14. The actual execution
of program instruc-tions is controlled by data pa-th module 14,
and memory control module 12 acts generally as an interface between
the data pa-th module and the system bus. The memory con-trol and
data path modules communicate via memory control bus 16 and memory
data bus 18.
Memory control module 12 is a microprogrammed device that
operates asynchronously with respect -to data path module 14. The
memory control module provides an interface between the CPU and
the system bus and, in addition, provides address translation,
instruction prefetch, and data cache functions Eor data path
module 14. Address translation refers to the translation of
virtual addresses specified by data path module 14 into actual
physical
.~2~
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addresses. The term data cache refers to means for the storage o~ recently used
data in high speed memory arrays within the CPU.
Referring now to ~IGURE 29 memory control module 12 includes
transceiver 30, buses 32 and 34, translation buffer/cache ~0, physical address
5 register ~2, system bus interface 44, merge/rotate lmit ~8,
microsequencer/control store 50, bus controller 529 and instruction prefetch
unit 56. The f~mction of the memory control units will be described by outliningthe sequence of operations that takes place when data path module 14 requests
that data be read from a specified virtual address. The data path module places
the virtual address in bus latch 6~ from which point it is sent to memory control
module 12 over memory data bus 18. The address passes through transceiver 30
onto bus 32. The virtual address on bus 32 is presented to translation
buffer/cache 40 and if the required translation entry is present (i.e., a cache hit),
the corresponding physical address is produced on bus 34. From bus 34, the
physical address is loaded into physical address register 42, from which point it is
loaded onto bus 32. The physical address on bus 32 is then simultaneously
presented to translation buffer/cache 40 and to the system bus interface unit ~4.
If the required data is in the cache, the translation buffer/cache 40 asserts the
requested data onto bus 3~ in the next machine cycle. If a cache miss occurs, a
20 system bus cycle is executed to fetch the requested data from rnemory array 22.
When the data is received from memory, it is passed from system bus
interface 44 onto bus 34. Once the data from the cache or from memory is
received on bus 34, it is loaded through merge/rotate unit 48 back onto bus 32.
The requested data is then passed to data path module 14 via transceiver 30 and
25 memory data bus 18, completing the virtual read cycle. The above-described
sequence of memory control operations is carried out and coordinated by control
signals emanating from microsequencer/control store 50. The particular
rnicroprogram executed by microsequencer/control store 50 is selected by
memory control command 28 sent by data path module 14 to memory control
30 module 12 over memory control bus 16. This command is asserted at the same
time that the virtual address is placed on memory data bus 18. For memory
control module microprograms that require the use of system bus 20, the
microprograms operate through bus controller unit 52.
An additional function performed by memory control module 12 is
35 the prefetching of instructions for e2~ecutioll by dnta path module 1~. Thc
prefetched instructions are stored in hlstruction prefetch unit 56, and are passed
to data path module 1~ as needed, one byte at a time~ via memory control
bus 16. Memory control bus 16 thereforc performs two distinct functions: the
7 2 7 8 6 - l D
transfer of instructions from mernory control module 12 to data path module ~
and the transfer of memory control commands from data path module 1~ to
memory control module 12.
Each macroinstruction executed by data path module 14 generally
consists of an operation code (op-code) followed by one or more operand
specifiers. The operand specifiers specify either the data or the location of the
data upon which the macroinstruction is to operate. Xn the former case, the datacontained within the operand specifier is termed a literal. In the latter case, the
operand specifier designates the addressing mode and the number (i.e., address)
10 of a register. Examples of addressing modes are direct~ in which the designated
register contains the data, and indirect, in which the designated register contains
the address of the data. By way of example, in a maeroinstruction to add the
contents of registers 3 and 4, the op-code would specify addition, and the two
operand specifiers~ would specify register 3 direct and register ~ direct,
15 respectively. In the preferred embodiment described herein, each op-code and
operand specifier consists of one or more bytes, and such macroinstruction bytesare recei~ed and processed one byte at a time by data path module 14.
Referring now to data path module 14 in FIGURE 2, the execution
of rmacroinstructions is carrieci out by means of microinstructions executed by
20 control logic Ullit 60. The control logic unit includes the ~LU, the general
purpose registers, two pointer registers, the macroprogram counter, and other
elements as described below. For each macroinstruction, control logic unit 60
executes a series of microinstructions stored in control store G2. The
microinstruction sequence commences when the op-code of a new
25 macroinstruction is loaded into instruction register 70 from memory control
bus 1~. The value of the op-code and a portion of the current microinstruction
are used to address a location in decode ROM 74. In response, the decode ROM
supplies a number of outputs: a next microaddress, which specifies the address
in control store 62 of the first microinstruction corresponding to the
30 macroinstruction op-code; a SIZE signal indicating the length in bytes of thedata upon which the macroinstruction is to operate; and a CC CLf~SS (condition
code class) signal whose function is described below. WhelI the instruction
register contains an operand specifier, decode ROM 7~ in addition supplies a
REGIST~,R signal indicating whether or not the addressing mode is direct.
The next microaddress supplied by decode ROM 7~ is passed by
microsequencer 76 to control store nddress register 78. The acldress in cont~ol
store address register 78 specifies the microinstruction which is accessed in
control store 62. Portions of the accessed microinstruction are routed to a
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number of destinations. One portion ~oes to control logic unit 60 for execution.A second portion goes to microse~uencer 7~ where it can be used to determine
the address of the next microinstruct;on. In certain situations, control store 62
also supplies memory control signal 28 and values to be loaded into size
5 register 88 and CC logie 90. After the first microinstruction has begun
executing, microsequencer 76 eauses the address of the next microinstruction to
be placed into control store address register 78, and the sequence continues until
all microînstructions corresponding to the macroinstruction have been executed.
Microstack 80 i9 included to permit the use of microsubroutines and microtraps
l0 in the microprograms in control store 62. The operation of the microstack is
described in detail below.
Other elements included in data path module 14 are bus latch 64,
buses 82 and 84, latch 86, size register 88, condition code logic 90, index
register 92, console interface ga~, interrupt control logic 96, and instruction
15 register buffer 98. Buses 82 and 8A are used in a variety of contexts to pass data
between data path elements. Latch 86 provides isolation bet~veen buses 82
and 84. Size register 88 is used to hold a code, usually derived from the SIZE
signal from decode ROM 74 or from control store G2, indicating a default data
path width for control logic unit 60. Condition code logic 90 is used to control20 the setting of rnacrolevel condition codes based on control logic unit 60 outputs.
Index register 92 is a four-bit register that may be used by microsequencer 76 to
determine the next microaddress. Console interface 94 is a serial port used to
interface the data path module with console terminal 24 (FIGURE l~. Interrupt
control logic 96 compares any interrupt received from system bus 20 with the
25 current state of the CPU, to determine whether the interrupt should be taken.Instruction register buffer 9~ provides a means for sending the contents of
instruction re~ister 70 to control logic unit 60 via bus 82.
The function of microsequencer 76 is to determine the sequence in
which microinstructions are executed by control logic unit 60. It accomplishes
30 this by determining, durirlg the eYecution of a given microinstruction, the
address in control store 62 of the next microinstl uction, and placing that address
in control store address register 73. The microsequencer determines the next
microinstruction address l~ased on informatioll coded into the current
microinstructioll, and on the si~l~als on vnrious status and control lines.
FIGURE 3 illustrates microsequencer 7(; in ~renter detail. T lle
next microaddress is detcrlnined by the output o~` MU~ (multiple:;er) 200. Thc
inputs to MU~ 200 are page register 201, microprogram counter 202, and OR
gate 204. The selection between these inputs is determined by the output o~
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JUMP MUX 20~ and by certain other control signals to be described. Page
register 201 contains the high order bits of the current microinstruction address.
Microprogram counter 202 contains the low order bits of the current
microinstruction address, plus one. Page register 201 and microprogram
counter 202 therefore together point to the next sequential microinstruction
address. The selection of these inputs by MUX 200 represents the simple case in
which the computer system executes microinstructions in a sequential fashion.
OR gate 204 performs a logical OR operation between the output
of OR MUX 208 and the address on bus 210. Bus 210 contains an address
l0 determined either by decode ~OM 74, jump register 212, or microstack 80. The
bus 210 address is derived from decode P~OM 74 when a macroinstruction
op-code or operand speciier byte is being decoded. In this case, the decode
ROM provides either all or part of the address of the first microinstruction
required to carry out the function specified by this macroinstruction byte. In
15 general, jump register 212 is the source of the address on bus 210 when a
nonsequential jump or branch is to be taken in the microinstruction sequence~
The address to which the branch is to be takell is derived from the contents of
the current microinstruction in control store 62 and placed in jump register 212.
Finally, microstack 80 is the source of the address on bus 210 when a return from
20 a microsubroutine or microtrap is to be taken. The return address is stored in
microstack 80 when the original subroutine call or trap is taken. The return
address is determined either by the contents of page register 201 and
microprogram counter 202 for a subroutine call, or by the contents of the page
register and the microprogram counter less one (i.e., the current microaddress)
25 for ~ trap. In the latter case, conditional decrementer 214 is used to subtract
one from the contents of microprogram counter 202.
Each microinstruction stored in control store 62 includes three
fields: a data path control field, a condition code/size field, and a ne~t address
control field. The data path control field is used to control the execution of the
30 microinstruction by control logic unit 60 (FIGURE 2). The condition code/size field is discussed below. The next address control field is used by
microsequencer 76 to determine the address of the next microinstruction. The
next address control field can conceptually be broken down into four subfields as
f ollows:
Type
Jump Condition
OR
Jump ~ddress
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The Type subfield specifies one of the branch types listed in FIGURE 4 and
e~plained more fully below. The Jump Condition subfield specifies the cond;tion
to be tested to determine whether or not a nonsequential branch is to be taken in
the microinstruction sequence. Referring to FIGIJRE 3, the Jump Condition
5 subfield in part determines which of the inputs to JUMP MUX 206 is selected for
control]ing MUX 200. Typical Jump Conditions which may be selected are the
ALU condition codes, whether or not an interrupt or console halt has been
received, whether or not the outputs of OR MUX 208 are zero, and whether the
signal IR INVALID has been asserted. The IR INVALID signal is generated by
l0 instruction prefetch unit 56 whenever instruction register 70 does not contain
valid information. In general, if the selected condition is true, then MUX 200
selects the address supplied by OR gate 204 and the branch is taken. IE the
condition is not true, MUX 200 selects the next sequential address supplied by
page register 201 and microprogram counter 202.
The OR operation performed by OR gate 204 only operates on the
less significant bits of the address on bus 210. In a preferred embodiment of the
present computer system, the output of OR MUX 208 is four bits wide, and, for
certain microinstruction branch types, these four bits are ORed with the low
order four bits on bus 210. The OR MUX is thus capable of providing
20 multidestination branching (i.e., casing). The output of OR MU~ 208 is
controlled by the OR subfield of the current microinstruction. FIGURE 5 shows
one preferred embodiment of the present invention in which the OR subfield is
up to three bits wide and capable of selecting from up to eight sets of four bitinputs. For each selection, corresponding to OR subfield values zero through
25 seven, FIGURE 5 lists the values ~or each of the OR MUX output bits ORMUX3
through ORMUX0. For a subfield value of ~ero, all OR MUX outputs are zero.
Por a value of one, ORMIJ~0 is set to one if the IR INV~LID signal is asserted.
For a value of two, ORMUXl is set to one. This value may conveniently be used
to provide multiple returns ~rom microsubroutines. For a value of three, the OR
30 ~IU~ output is determined by the signals on four memory control status lines as
indicated. MEM ERR refers to a miscellaneous error signal from memory
control module 12. PAGlE CROSSING indicates an attempt to access data thRt
crosses a 512 byte page boundary. TB MISS indicates that a translation entry fora requested virtual address was not found in translation buffer/cflche ~l0.
35 ~qODIFY REFUSE indicates thllt a memory write oper~ltion could not be
performed because the modify bit in tile corresponding translntion buEfer entry
was not set. For a code value of four, the OR MUX output is determined by the
IR INVALID signal and by BR FALSE, the latter indicating whetller a mflcrolevel
9&~
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branch will be taken. For a code value of five, the OR MUX output is
determined by the indicated sta~us signals. O~JERFLOW refers to the PSL V
code described below. INTERRUPT and CONSOLE HALT refer to signals from
interrupt control logic 96 and console interface 9~, respecti~ely. For ~ code
5 value of six, the OR MUX output is equal to the contents of index register 92
(FIGUR~ 2)~ For a code value of seven, the OR MUX output is determined by
the contents of size register 88
FIGURE 4 summari~es the methods by which microsequencer 76
selects the next microaddress~ The Type subfield of the current microinstruction
l0 specifies one of the branch types listed in the first column of FIGURE ~. Theoperation of these types is described in the following paragraphs. In FIGIJRE ~,the symbol ~PC stands for microprogram counter 202.
When the branch type is Jump or Jump to Subroutine, the address
contained in the Jump Address subfield of the current microinstruction is loaded
15 into Jump Register 212. This address is enabled onto bus 210, from which point
it passes without modification through OR gate 204 and MUX 200. The next
microaddress is therefore determined entirely by the Jump Address subfield of
the current microinstruction. Jump and Jump to Subroutine branch types are
used to cause unconditional branches in microinstruction flow. When a Jump to
20 Subroutine is executed, the contents o~ page register 201 and: microprogram
counter 202 are pushed onto microstaclc 80.
A branch type of Branch is used to perform a conditional Jump to a
microaddress within the current page. As indicated in FIGURE 4, the high order
five bits of the next microaddress are determined by page register 201, and the
25 lo~r order eight bits are determined based on the Jump Condition. IÉ the Jllmp
Condition is true, the low order bits are derived from the low-order Jump
Address sub~ield of the current microinstruction via Jump Register 212. If the
Jump Condition is false, no jump is taken, and the low order bits are derived
from microprogram counter 202. The Jump Condition is equal to the signal
30 selected by Jump MU~ 206 based upon the Jump Condition subfield of the
current microinstruction.
The Case branch type is similar to E~ranch, except that i~ the Jump
Condition is true, the low order bits of the next microaddress are determined bythe Jump Register in comhinntion with the OR MU~ output. In pnrticular, the
four OR MUX output bits (FIGURE 5) are ORed with the low order four bits oî
the Jump Register by OR gate 20~.
The I3rallch to Subrolltille and Trap branch types al e similar to
Case, except that if the Jump Condition is true, the high order bits of the ne~t
,
:
3~
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microaddress are forced to zero, and either the next sequential microaddress
(Branch to Subroutine) or the current microaddress (Trap) are pushed onto
microstack 80.
The Return branch type is used to return to any microaddress
which has been pushed onto microstatck 80. The Return branch type is
conditional, and will only return if the Jump Condition is true. A false Jump
Condition will cause the next sequential microaddress to be selected by
microsequencer 76.
FIGURE 4 alsc illustrates the way that the next microaddress is
determined when control logic unit 60 executes a microinstruction which calls
for the decoding of an op-code or an operand specifier in instruction register 70.
For an op-code decode, the next microaddress is determined by the address
supplied by decode ROM 74 if the specified Jump Condition is false. In this
event, the high order bit of the next microaddress is set to zero. However, if the
l 5 specified Jump Condition is true, then the next microaddress is determinedentirely by the four bit output of OR MUX 2~8, and the current microaddress is
pushed onto microstack 80. In general, the Jump Condition specified in an
op-code decode microinstruction will be the IR INVALID signal. As a result,
when data path module 14 attempts to decode an op-code which is not yet
available in instruction register 70, a trap is taken to a low microaddress where a
subroutine waits for instruction prefetch unit 56 to catch up.
When an operand specifier decode microinstruction is e2cecuted, the
next microaddress is determined by two signals: the IR INVALID signal and the
REGISrE}~ signal supplied by decode ROM 74, the latter indicating whether the
~5 addressing mode of the operand specifier is direct. If the instruction register is
valid and the mode is direct, then tlle ne~t sequential microaddress is selected.
If the instruction register is valid and the mode is indirect, then the
microprogram jumps to a subroutine at an address whose high order portion is
determined by the high-order bits of Jump Register 212, and whose low order
portion is equal to the microaddress supplied by decode ROM ~4. The address in
Jump Register 212 is derived from Jump Address subfield of the current
microinstruction. ~inally, if the IR INVALID signal is asserted, then the
microprogram traps to a subroutille whose address is specified by the output of
OR MU~ 2~8, which in this case is set to a vulue equal to one.
The last situation illustrated in I~IGURE 4 is power~up or a pnrity
error. In this case, data path module 14 begins executing microinstructions at
address zero.
L_
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FIGURE 6 illustrates control logic unit 60 in greater detail. The
control logic unit includes buses 100 and 102, ALU 104, result registers 106
and 107, barrel shifter 108 and associated shift count register 110 and result
register 112, pointer registers 120 and 122, register file 124, program
counter 126, constant ROM 130, register save stack 132, I/O port 134, and
control store register 140.
The execution of a microinstruction by control logic unit 60
commences when the data path control field of the microinstruction is loaded
into control store register 140 from control store 62. In general, the data path0 control field includes a miero op-code and two micro operand specifiers. Whenthe micro op-code specifies an arithmetic or logical operation (e.g.~ Add, ~nd,
Mask, Compare), the operation is carried out by ALU 104. The two required
operands are supplied via buses 100 and 102, and the result of the operation is
placed in result register 106 or 107, depending on a bit contained within the
current microinstruction.
Barrel shifter 108 is used for shift operations. The shift count may
be stored in shift count register 110 or supplied as a literal in the
microinstruction. The result o~ the shift operation is stored in result
register 112.
Register file 12d~ contnins a number of general registers accessible
to the macrolevel program, plus both general and speciul purpose microlevel
registers. The term general register will hereafter be used to refer to both
macrolevel and microlevel general purpose registers in register file 124. Each
register may be read from either bus 100 or 102, but may be written only from
bus 102. ~ach register in register file 12~ has a unique register address
associated with it, the register ad<:lress being used as described below to specify
the register during microinstruction execution.
Size reg;ster 88 is used to control the width of the data path
utilized by control logic unit 60, ar.d to control rnicroprogram branching as
indicated in FIGURE 5. In a preferred embodiment of the present computer
system, the data path can be up to 32 bits wide, althougll particular
macroinstructions may specify a smaller data path such as byte (eight bits) and
word ~16 bits). For e:Yample) a macroinstruction might specify that a byte is tobe retrieved from a particulnr virtual memory address and loaded into gelleral
register 3 (i.e., the general register in register file 12~t having a register address
of 3). This macroinstruction would affect only the low order eight bits of
general register 3, leaving the high order 2~ bits unaffected. A full 32-bit block
of data is referred to ns a longword.
,
-11~ 72 786-lD
Size register 88 i5 loaded with a two-bit code directly from decode
ROM 74 when a macroinstruction op-code is decoded. In one preferred
embodiment, the coding scheme is:
0 - byte
1- word
2 - not used
3 - longword
Thus the data path width specified by an op-code can be made available to the
control logic unit (as signals SIZE0 and ~IZE1) during the entire execution
10 sequence for that op-code, without the use of ~LU operations for masking, and without any moving, rotating, or refreshing of the register.
The contents of the size register can be altered when a
microinstruction for performing an operand specifier decode is executed. When
such a microinstruction is executed, the condition code/size field of the
15 microinstruction is loaded from control store ~2 into size register 88 i~ the value
of the field is zero (byte), 1 (word), or 3 (longword). If the value is 2, then the
size register 88 is unaffected, leaving intact the size specified by the preceding
op-code.
Aside from decode microinstructions, the size register can be
20 modified only by Move microinstructions that explicitly specify the size register
as their destination operands. Microinstructions other than decodes can,
however, control the data path width during their execution by means of their
condition code/size field. For ALU and shift microinstructions, the conditlon
code/size coding is discussed below. For other microinstructions, (e.g., l~ove,
25 Memory Request), the condition code/size field coding is as follows:
0 - byte
1 - word
2 - use size register
3 - longword
30 Thus a given microinstruction can either specify its own data path width, or can
specify the size register and thereore use the width specified by a preceding
op-code or operand specifier. The result is that the efficiency gained by the use
of size register 88 does not cause any corresponding loss of flexibility in the
microprogramming of the present computer system.
Pointer registers 120 nnd l22 are six-bit registers that cnn each
serve two functions: thcy cun contain the address of (i.e., point to) a particular
general register ill r~gister file 12~, or they can contain u literal value derived
from an operand specii(~r. Pointer registers 120 und 122 can be read from
5d'3 ! ' ` 6
- 12- 7278~-lD
buses 100 and 102, and written from bus 102. The use of two pointer registers
provides significant advantages in the execution speed of many macroinstruc-
tions. For example, a macroinstruction to add the contents of general
registers Rl and R2, placing the result in general register R2, might be coded as
5 follows:
Op-code - Add
Operand specifier 1 - R1, direct mode
Operand specifier 2 - R2, direct mode
with each operand specifier including a mode field specifying the addressing,
10 mode and either a register fieldcOntainingthe address of a register (as above) or
a literal. Without the use of the pointer registers of the present invention, the
microinstruction sequence for this macroinstruction would require seven steps asf ollows:
- 1. Decode op-code
152. Decode operand specifier 1
3. r~aove R1 to TE MP 1
. Decode operand specifier 2
5. Move R2 to TRMP2
6. Add Tr.MP3 = TEMPl -~ TEMP2
207. Move TEMP3 to R2
where TEMPl, TEMP2 and TEMP3 stand for general microlevel registers. The
use of two pointer registers reduces the required number of steps to five, as
follows:
1. Decode op-code
252. Decode operand specifier 1, place address of Rl in PTRl
3. Decode operand specifier 2, place address of R2 in PTR2
4. Add TEMPl = @~TR1 + @PTX2
5. Move TEMP1 to @PTR2
where the symbol @ ~ signifies the location (i.e., register) whose address is in30 register X, and where PTRl and PTR2 specify pointer registers 120 and 122. Asindicated in steps 2 and 3 above, an operand specifier decode causes one of the
pointer registers 120 or 122 to be loaded with the number of the register
specified by the operand specifier. This loading of a pointer register tal~es place
regardless of the addressing mode specified by the operand specifier. In tlle case
35 of an operand specifier containing a literal, the literal is lil;ewise loaded into a
pointer register. In all cases, a bit in the microinstruction for performing theoperand specifier decode determines whicll pointer register ~120 or 122) is
loaded. Referring to FIGUl~E 2, the pointer registers are loaded from instruc
,~
-13- 72786-lD
tion register 70 through instruction register buffer 9~, bus 82, latch 86, bus 84,
I/O port 134 and bus 102.
The Add and Move microlnstructions in steps d~ and 5 of the second
e~ample above indirectly address registers R1 and R2 through the use of pointer
registers 120 and 122. To implernent such an addressing method, two register
addresses are assigned to each of the pointer registers, a direct address and anindirect address. The direct address of a pointer register is fully analogous tothe address of the registers in register file 124, and is used to speci~y the
contents of that register. For example, for a microinstruction such as Move 3, 4in which the first and second micro operand specifiers specify the registers in
register file 124 whose addresses are 3 and 4 respectively, the result would be
that the contents of register 3 would be moved to register 4. Poin-ter
registers 120 and 122 provide a different and generally more efficient method ofaccomplishing the same result. Each pointer re~ister is assigned a unique
indirect address different from the direct address of any register. When the
indirect address is speeified by a micro operand specifier, the register actually
accessed is determined by the contents of the indirectly addrcssed pointer
register. For example, if pointer registers 120 and 122 were assigned indircct
addresses of 5~ and 55, and contained the numbers 3 und 4, then the micro-
instruction Move 54, 55 would be equivalent to Move 3, a~.
Program counter 126 is a register which stores the address of the
next macroinstruction byte to be executed. As with pointer registers 120
and 122 and the registers in register file 124, program counter 126 may be read
from either bus 100 or 102, and may be written from bus 102. Program
2~ counter 126 is automatically incremented, by 1, 2 or ~, when one of the following
occurs:
(1) An op-code decode microinstruction is executed.
(2) An operand specifier decode microinstruction is e2~ecuted.
(3) The current microinstruction specifies instruction
register 70 as the location Oe one of the microinstruction operands.
(~) A microinstruction is executed which specifies retrieval of
data rom the macroinstruction instruction stream.
Cases (1) and (2) have already been described. Rrogram
counter 12G is incremented by one whenever a new mncroinstruction bytc is
clocked out o~ the instruction register 70, such thnt the nddress in program
counter 126 corresponds to the virtual address of the new macroinstruction byte.An example o~ case (3) is a situation in which a byte in the macroinstruction
stream contnins literal data. I or e~ample~ one type of operalld spccifier
6~
72786-lD
specifies the address of the operand by specifying a register which contains a
base address, and a fixed offset to be added to the base address found in the
register. In this situation, the operand specifier would consist of two bytes, the
first byte specifying the register address (e.g., register 2) and the addressingmodeg and the second byte containing the fixed offset (i.e., a literal). The
microinstructions for accessing such an operand would begin by decoding the
first operand specifier byte and putting the value 2 (the register address) in
pointer register 120. The following microinstruction would then ~dd the value
pointed to by pointer register 120 to the literal contained in instruction
register 70. The microinstruction would reference instruction register ~0 by
specifying a unique register address assigned to the instruction register. The
literal would reach ALU 104 from instruction register 70 through instruction
register buffer 98, bus 82, latch 86, bus 84, I/O port 134 and bus 102. The
execution of the Add microinstruction specifying the address of instruction
register 70 as an operand causes program counter 126 to be incremented by 1.
Case (4) listed above is termed an instruction stream memory
request. When such a microinstruction is executed, control signals are sent fromcontrol store 62 to memory control module 12 via memory control bus 16. At
the same time, the unincremented contents of program counter 12G are driven
onto bus 84 via bus 102 and I/O port 134, and frorm there sent to memory controlmodule 12 via memory data bus 18. Program counter 126 is then incremented
by 1, 2 or 4, depending upon whether the instruction stream memory request
microinstruction specified a byte, word or a longword. On memory control
module 12 (FIGURE 2), instruction prefetch unit 56 maintains a prefetch buffer
filled with macroinstruction stream bytes. An instruction stream memory
request first clears the prefetch buffer, then reads a byte, word, or longword
from translation buffer/cache ~0 or memory array 2~ and sends the resulting
data to data path module 14 via memory data bus 1g. Instruction prefetch
unit 56 then refills the prefetch bnffers beginning with the next byte in the
macroinstruction stream following the bytes sent to data path module 14.
Register save stacl~ 132 is a LIFO stack used to temporarily store
the contents of specified registers. Each entry on the stack consists of the
contents of a register and t~le address (number) of that register. An example
illustrating the use of the register save stack is the decoding of an operand
specifier that specifies nn nutoincrement addressin~ mode. In sucll a mode, the
contents of a specified register is first used as an address to access the operand,
and the register is then automatically incremented by 1, 2 or 4. ~Yhen an
autoincrement mode operand specifier is decoded, the unincremented contents of
J~ J5~
-15-- 727~6-lD
the register are automatically puslled onto the register save stack. If the
attempted memory access then results in an error condition, the register ca~l berestored to its pree~cisting condition by popping the stack. The push operation is
controlled by the current microirlstruction, which contains a bit that determines
5 whether or not ~ push will occur. 1 a push is to occur, one of the micro operand
specifiers contains the address of the register.
Condition code logic unit 90 is used for storing and controlling two
sets of condition codes: microprogram level (ALU) condition codes and macro-
program level (PSL) condition codes. Four conditions are provided at each level:l 0 N - negative
Z - zero
V - overflow
C - carry
The ALU condition codes reflect the result of the last microinstruction executed15 by control logic unit ~n, which specified in the condition codelsiæe field that the
ALIl condition codes were to be loaded, and comprise four of the inputs to JUMP
MUX 206 (FICUR~ 3). The ALIJ condition codes can therefore be ~Ised as jump
control signals by microinstructions, as indicated in FIGURE 4. The PSL
condition codes are the condition codes available to the macroprogram level, and 20 may be used by the macroprogram to determine whether a macrobranch should
be taken.
When an op-code is decoded by decode ROM 74, a two-bit Condi-
tion Code Class signal is produced and sent directly to a condition code class
register (not shown) contained within condition code logic unit 90. The contents25 of the condition code class register determine how the ALU codes are mapped to
the PSL codes as follows:
Condition Code
Class ReFister Class
0 L,ogical ALU N to PSL N
ALU Z to PSI. Z
ALU V to PSL Y
PSL C to PSL C
1 Arithmetic ALU N to PSL N
I~Ltl Z to PSL Z
ALU V to PSL \l
ALU C to PSL C
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2 Compare ALU N to PSL N
- ALU Z to PSL Z
Clear PSL V
ALU C to PSL C
3 Floating ALU N to PSL N
Point AL~ Z to PSL Z
AI.U V to PSL V
Clear PSL C
The aetual setting of eondition codes by a given mieroinstruction is determined
by the condition eode/size field of that microinstruetion. As deseribed above,
eertain types of mieroinstruetions (e.g.1 Move, Memory Request, Decode) use the
condition code/size field to specify data path width, and for these microinstruc-
15 tions, the condition codes are never set. ~or other mieroinstructions (e.g., Add,
And, Shift) the condition code/size field controls data path width and conditioneode setting as follows:
Condition Code/ Dat~th
Size Field Value Width
0 longword condition codes
not affeeted
1 longword set ALU condition eodes
2 longword set ALU & PSL eondition
eodes
3 per size set ALU ~c PSL eondition
register eodes
For sueh microinstructions, the contents of the eondition eode/size field is sent
directly to the CC logic unit 90 from control store 62.
:
~ !
~.~
