Note: Descriptions are shown in the official language in which they were submitted.
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APPARATUS FOR RAPIDLY CLEARII~G THE OUTPUT
DISPLAY OF A COMPUTER SYST~M
E~ACKGROUND OF THE INVENTION
The present invention relates to logic circuitry and, more particularly, to
logic circuitry used to provide extremely rapid switching between output
display frames in a computer system.
I~ISCUSSION OF THE PRIoR ART
l O As computer systems such as work stations have grown more and more
sophisticated, it has become clear that they might be conveniently utilized for
providing the animation features that one associates with motion pictures and
television. A computer which is capable of providing an animat~d output offers
a distinct advanta~e over television and motion pictures because it, unlike the
others, allows both the construction and revision of the images of animated
displays. The ability of computers to provide three dimensional displays has
hastened and heightsned the desire for systems which are capable of handling
animated subjects.
A major problem in utilizing computers to provide animated output is that
animation requires the display of frames which vary by small increments and
succeed one another in rapid sequence. In order to display a single frame of
~raphical material on a cathode ray tube (CRT), it is necessary to store an
indication for each position (pixel) which is to appear on the cathode ray tube
or other display of the information which is to b~e displayed at that position. With
ZS large and detailad displays, the number of pixels on the cathode ray tube may
average approximately 1,000 in a horizontal direction and a like number in the
vertical direction giving a total of approximately one million pixels about which
information is to be stored. In a preferred system which is capable of providinga number of different colors and hues on the cathode ray tube, each of these
pixels contains twenty-four bits of di~ital information specifyin~ the particular
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color output. Consequently, approximately twenty-four million bits of
information needs to be stored for each frame to be presented at the output.
However, not only does writing the approximately twenty-four million bits
to each storage position of a frame to be provided as output to a cathode ray
5 tube require a substantial amount of time, but the clearing of those bits in order
to provide the next frame requires an additional amount of time. Some of the
delay between frames has been obviated by using double buffered systems in
which two full screen bitmapped memories are provided and switched
alternately to the cathode ray tube output. SsJch a system reduces
10 substantially the time between presentation of two frames of information blltdoes not eliminate the need to rapidly clear each of the display memories so
that they may be written to for the frames which follow. Consequsntly, even
such double buffered systsms are too slow to provide optimum outputs for
animation purposes.
It is, therefore, an object of this invention to improve the speed at which
images may be switched from frame to frame and presented at the output of a
computer system.
It is another object of this invention to eliminate a substantial portion of
the delay associated with clearing display memories between frames in a
20 computer system.
It is another object of this invention to eliminate the necessity o~ clearing
display and depth memories between frames in a computer system.
An additional object of this invention is to improve the speed at which
computer systems operate.
1 3 1 627 I
SUMMARY OF THE PRESENT INVENTION
The present invention improves the speed at which individual frames
may be switched to the output of a computer system by essentially eliminating
the time normally used for clearing the display memories in such a system. The
5 system accomplishes this by providing double-buffered frame identification
memory to store indications of the frame being stored corresponding to the
information in an associated display memory. Each pixel in the display memory
has an associated, corresponding pixel in the frame identification memory.
When a frame which has been written into the display memory is to be
10 read out, an output frame identification register provides an indication of the
frame to be read out as a frame number, and that frame number is compared
with the value of each pixel in the frame identification memory as the frame
identification memory and the display memory are scanned for cathode ray
tube refresh. Only those pixels in the selected frame are provided as output
l S from the display memory to the cathode ray tube. At pixels at which the number
in the output frame identification register and the frame identification memory do
not compare, a background color generator is activated to provide information
to the cathode ray tube. This allows frame to frame writing to the display
memory to continue without erasing the display memory and erasing only a
20 small portion of the frame identification memory.
An additional somewhat similar logic arrangement is provided for
determining the depth to which pixels of a particular frame are to be written
along the Z-axis so that three dimensional figures may be accurately
represented on a two dimensional output display. The invention allows frame-
Z5 to-frame use of the Z bufter to continue without erasing the Z buffer. Moreover,
another similar logic arrangement is provided for determining ths window in
which pixels of a particular frame are to be written so that windows may be
handled in the same system.
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Accordingly, in one aspect the invention provides
a computer output system for displaying a plurality of
individual frames of information on display means
including a display, comprising; first memory means
including a first memory having a plurality a pixel
storage positions for storing said frame information at
said pixel positions; second memory means including a
second memory having a plurality of pixel positions
corresponding to said pixel positions in said first memory
for storing one of a plurality of n-bit frame indications
at each said pixel position in said second memory, each
said n-bit indication indicative of one of said plurality
of individual frames of information stored in said first
memory; input means coupled to said first memory means and
to said second memory means for inputting into said first
memory said frame information and for inputting into said
second memory said n-bit frame indications such that said
frame information and said n-bit frame indications occupy
the same pixel positions in said first and second
memories, respectively; first comparison means coupled to
said second memory means for comparing an indication
indicative of a particular frame to be displayed on said
display with said indications stored at said pixel
positions in said second memory means such that if said
indications are equal said frame information stored at
said corresponding pixel positions in said first memory is
displayed on said display; and clearing means coupled to
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said second memory means for clearing consecutive portions
of said second memory after each said particular frame of
information has been displayed on said display, said
portions cleared comprising at least the pixel positions
of said memory storing the n-bit frame indication of said
particular frame of information displayed.
In a further aspect, the invention provides a
computer output system for displaying a plurality of
individual frames of information on display means
including a display such that said information appears
three dimensional on said display, comprising: first
memory means including a first memory having a plurality
of pixel storage positions for storing said frame
information at said pixel positions; second memory means
including a second memory having a plurality of pixel
positions corresponding to said pixel positions in said
first memory for storing one of a plurality of n-bit frame
indications at each said pixel position in said second
memory, each said n-bit indication indicative of one of
said plurality of individual frames of information stored
in said first memory; third memory means including a third
memory having a plurality of pixel positions corresponding
to said pixel positions in said first memory for storing
depth information at each said pixel position in said
third memory; input means coupled to said first memory
means, said second memory means, and said third memory
means for conditionally inputting said frame information
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1 3 1 6~7 ~1
i.nto said first memory, conditionally inputting said n-bit
f.rame indications into said second memory, and
conditionally inputting said depth information into said
third memory such that said frame information, said n-bit
S frame indications, and said depth information occupy the
same pixel positions in said first, second, and third
memories, respectivelyi first comparison means coupled to
said second memory means for comparing an indication
indicative of a particular frame to be displayed on said
display with said indications stored at said pixel
positions in said second memory means such that if said
indications are not equal said input means stores said
frame information at said corresponding pixel positions in
said first memory, said indications at said pixel
positions in said second memory, and said depth
information at said pixel positions in said third memory;
and second comparison means coupled to said third memory
means and to said input means for comparing said depth
information stored in said third memory with said depth
information input by said input means when said
indications compared by said first comparison means are
equal such that if said stored depth information has a
value that is greater than or equal to said depth
information input by said input means then said input
means stores said frame information at said corresponding
pixel positions in said first memory, said indications at
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said pixel positions in said second memory, and said depth
i.nformation at said pixel positions in said third memory.
In a yet further aspect, the invention provides
a computer output system for displaying a plurality of
individual frames of information such that said
information can optionally be displayed inside windows,
and three dimensionally on display means including a
display, said output system comprising; first memory means
including a first memory having a plurality of pixel
storage positions for storing said frame information at
said pixel positions; second memory means including a
second memory having a plurality of pixel positions
corresponding to said pixel position~ in said first memory
for storing one of a plurality of n-bit frame indications
at each said pixel position in said second memory, each
said n-bit indication indicative of one of said plurality
of individual frames of information stored in said first
memory; third memory means including a third memory having
a plurality of pixel positions corresponding to said pixel
positions in said first memory for storing one of a
plurality of said n-bit indications at each said pixel
position in said third memory, each said indication
indicative of a window to be displayed on said display;
fourth memory means including a fourth memory having a
plurality of pixel positions corresponding to said pixel
positions in said first memory for storing depth
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1316271
information at each said pixel position in said fourth
memory; input means coupled to said first memory means,
!' said second memory means, said third memory means, and
said fourth memory means for conditionally inputting said
frame information into said first memory, conditionally
inputting said n-bit frame indications into said second
memory, inputting said window information into said third
memory, and conditionally inputting said depth information
into said fourth memory such that for each particular
frame said frame information, said n-bit frame indication,
said window information, and said depth information occupy
the same pixel positions in said first, second, third, and
fourth memories, respectively; first comparison means
coupled to said third memory means for comparing an
indication indicative of a particular window to be
displayed on said display with said indications stored at
said pixel positions in said third memory means; second
comparison means coupled to said second memory means for
comparing said indication indicative of said particular
frame to be displayed on said display with said
indications stored at said pixel positions in said second
memory means such that if said indications are not equal
and said indications compared by said first comparison
means are equal then said frame information is input into
said first memory, said n-bit indications are input into
said second memory, and said depth information is input
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into said fourth memory; and third comparison means
coupled to said fourth memory means and to said input
means for comparing said depth information stored in said
fourth memory with said depth information input by said
input means when said indications compared by said first
and second comparison means are both equal such that if
said stored depth information has a value greater than or
equal to said depth information input by said input means
then said input means stores said frame information at
said corresponding pixel positions in said first memory,
said indications at said corresponding pixel positions in
said second memory, and said depth information at said
corresponding pixel positions in said fourth memory.
These and other features and advantages ot the present invention will
become apparent lo those skilled in the art atter having read the following
detailed description in conjunction with the several figures of the drawing.
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IN '1311E D R A W IN G S
Fi~ure 1 is a block diagram illustrating a arrangement in accordance
with the invention for selecting individual frames to b~ displaysd on a computer5 output device.
Flçiure 2 is a block diagram illustrating an arrangement in accordance
with the invention 10r selecting individual windows to be displayed on a
computer output device.
Fi~ure 3 is a block diagram illustrating an arrangement in accordance
l O with the invention for selecting particular frames involving three-dimensional
1igures to be displayed on a computer output device.
Fl~ure 4 is a truth table useful in illustrating the operation of the
arrangement shown in Fl~ure 3.
Fl~ure 5 is a block diagram of a system incorporating arrangements for
15 selecting windows, frames, and depth dimensions of signals to be provided on
a computer output device.
Flgure 6 is a truth table useful in illustrating the operation of the
circuitry shown in Flgure 5.
Fl~ure 7 is a block diagram illustrating the r~isters and memories
20 which are addressable on the host aWress bus from tha central processing unit in accordance with the present invention.
Figure 8 is a diagram useful in und0rstandin~ the operation for clearing
frame identification memories in accordance with the present invention.
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DETAILED DESCRIPTION OF THE INVENTION
FRAME IDENTIFICATION-
Referring now to Fl~ure 1, there is shown a display output system 10
for processing information rapidly in accordance with the invention. For the
purposes ot this explanation, a frame may include a particular ~raphical or datastructure which it is desired to present as a full screen presentation on a
cathode ray tube or other computer output device. The system 10 operates
under control of a central processing unit (CPU) not shown in Figure 1.
When it is desired to write a particular graphic frame to an output device
such as the cathode ray tube (CRT) 12 shown in Fi~ure 1, the actual
information to be displayed is written to a display memory. The system 10
comprises a first display memory A (13) and a second display memory B (14).
The use of two display memories in parallel, the output of which may be
selected by a multiplexor 15, allows the rapid switching between the frames of
a display which is necessary to accomplish animation. In the usual case, a
frame is written to display memory A while the frame in display memory B is
being fumished as output to the cathode ray tube. The information in the frame
in display memory A is then furnished as output to the cathode ray tube while a
new frame is wrinen to display memory B.
In prior art systems, each of the display memories A and B must be
cleared before new information can be stored in it. This clearin~ step, with a
display havin~ a si~nificant number of pixels and storin~ twenty-four bits of
information at each pixel as in ths preferred embodiment, requires a significantamount of time and may slow lhe operation of the system to the point where its
25 ~se in animation is impractical.
To obviate this loss of time and provide the switching spced necessary
for animation, the output system 10 of the present invention also includes an
input frame identification (FID) register 16, a pair of frarne identification (FID)
memories A (17) and B (18) each associa1ed with the similarly named one of
30 the display m0mories A and B, an output frarne identification (FID) re~ister 19, a
background color r~ister 20, and a control register 2~. The system tO also
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1316271
includes a multiplexor 22, a comparator circuit 23, a write enable logic circuit24, and a lo~ic circuit 25.
The operation of the system 10 is as follows. The CPU writes a value to
the control register 21 using the host data bus to select which of the FID
S memories A (17) or B (18) and its associated display memory A (13) or B (14) is
to be written to.
The CPU then provides a frame identification number which is stored in
the input frame identification register 16 used for all of the information to bewritten for that ftame. In a preferred system, sixteen frame numbers (0-15) are
l o utilized. Atter the input trame idsntification register has been initialized with the
frame number, the actual information to be displayed on the output device is
sent from the CPU to the selected display memory A or B. The display
memories A and B are each full screen bitmapped memories. The frame
identification memories A and B are also full screen bitmapped memories, each
l S receivin~ input from the input FID register 16 and providin~ outputs to a
multiplexor 22 which allows them to be rapidly switcheJ for the presentation of
animated graphic images.
Each piece of input information on the host data bus from the CPU
carries a pix81 address, and color information (an RGB color value, for
20 example). Presuming that the display rnemory A and the FID memory A have
been selscted, the RGB color value is written to tha appropriate pixel address
in display memory A while the frame identitication number is written to the samepixel address in the frame identiflcation memory A. In a preferred system, ths
frame idantification number requires four bits of stora~e while the RGB color
25 value requires twcnty-four bits of stora~e at each pixel.
Consequently, when any particular tull frame has been written to display
memory A, the dispiay memory A contains, at tho addressed positions chosen
tor th0 particular frame, the representation to be displayed in RGB color values.
Presumin~ that a trian~le (such as that shown in the upper bft comer of CRT
30 1 2)is to ba stored in the display memory A and written to the cathoda ray tube
12 shown in Fl~ure 1, the color values for that tfian~b are placed at the
13t627'1
appropriate pixels of the display memory A while a triangular indication is
stored at the same pixels in the frame identification memory A but as the frame
identification number.
For example, if the triangular indication has been stored as frame zero,
S the color indications are provided in triangular forrn in the display memory while
the numbers zero are stored at the same triangular positions in the associated
FID memory. When it is time to display frame zero at the CRT, the CPU, using
the host data bus stores the frame identification number, a zero in this case, in
the output frame identification register 19 (again a four bit register in the
l O preferred embodiment). The CPU also writes to the control register 21 so that
the multiplexors 22 and 15 controllin~ the outputs of the frame identification
memories and the display memories, respectively, are set to select the output
from memories A. Then, as each pixel in the display memory A is scanned to
the output throu~h its associated multiplexor, frame identification values are
S also scanned from the frame identification memory A for that particular pixel.The values from the frame identification memory will be zero on~y at the
positions where the triangle is stored. Consequentty, a comparator circuit 23
comparing the output from the selected frame identification memory and from
the output frame identification register 19 provides a signal indicating those
20 pixels of the frame identification memory A where frame zero has been written(i.e., the triangle having a frame identification number of zero). Therefore, atthose positions at which the frame identification memory A stores a zero frame
identification number, the comparator circuit provides an equal output
indicating a pixel which is a part of the current frame; and the RGB color signal
25 stored at that pixel in the display memory A is fumished to the cathode ray tube
via lo~ic arcuit 25. On the oth~r hand, at all pixels other than those having a
frame identification number of zsro in the frame identification m(emory A, the
compara~or circuit 23 providas a not equal output indicating that the pixel is not
a part o~ the current frame; and a background color is provided from the
30 back~round color re~ister 20 and transfsrred to the cathode ray tube 12.
1 3 1 6 2 7
This arrangement for processins signals has a number o~ si~nificant
advantages. For example, the system requires that color values be stored in
the display memories only at positions indicative of foreground data.
Back~round colors need not be stored in the display memories. Consequsntly,
storage of information may proceed at a more rapid rate than with the usual
system where twenty-four bits of information must be stored at each pixel. More
importantly, a display memory need not be erased after the information for a
frame is read out in order to write the next frame in that memory.
For example, after frame zero has been processed as explained above,
the next frame to be processed by the particular FID memory has the next frame
number which is one. The information written to the FID memory and to the
associated display memory may, consequently, simply bs written on top of the
information in those memories because the only information which will
ultimately be furnished to the display will be information associated with framel S number one, as selected by the FID output register.
It will be appreciated that this arrangement which eliminates the need to
clear the display memory significantly speeds the operation of the system and
allows the rapid switching necessary for animation.
Although the use of FID memories and registers allows the system to
function without clearing the display memories between particular frames, the
number of bits utilized in the frame identification number system, four bits in the
preferred case, determines how many total frames may be writtan before the
FID memories must be cleared. With four bits of dignal storage to record the
frame number, sixteen total frames may be utilized. H the FID memories have
2~ not been cleared after si~neen frames, then it is possible that infomtation rela~ing
to a previous zero frame, for example, will remain in an Fll) memor~ as the zeroframe is a~ain rsached. Since this information might be erroneous, the system
does require that thc FID memori6s ba cleared at least once in sach sixteen
us~s.
An advanta~eous way of accomplishing the clearing wlthout slowin~ the
opsration of the system to any extent is to clear at least one-fifleenm or ~reater
1 31 627,
of an FID memory afler each fram~ is written to the output device. For example,
Fi~ure 8 illustrates the division of an FID memory into fiftsen horizontal strips.
After the zero frame has bsen displayed on the CRT, a clear value of ~zero"
frame number is written to the uppermost horizontal strip of the FID memory; and5 after the one frame has been displayed, a clear value of ~one~ frame number iswrinen to the next horizontal strip of the memory. Similar values are applied toeach succeeding horizon1al strip after each succeeding display of a frame.
Consequently, the next time a zero frame is to be written to the FID memory, thememory will be entirely clear of zero values because all horizontal strips below10 the top strip will have been purged of zero values and the top strip of FID
memory, which originally heW zero values, will have been filed with values of
fiReen, the last FID frame number to have been used. Consequently, no old
zero frame si~nals will be present to distort the information to be stored in the
FID memory. The same result will occur as each next frame number is written,
1~ the memory will have been cleared of all indications of that frame number just
before the new frame is written. Clearing the values from memory is, of course,
accomplished in a manner well known to the prior art by means specific to the
particular storage elemsnts.
It will be clear to those skilled in the art, that clearin~ one-fifteenth of the20 FID memory after each output of a frame to the CRT is significantly faster than
the arrangements used by prior art systems which required the clearin~ of the
entire display memory with each output to the CRT. First, the display memory
includes twenty-four bits at each pixel, and each must be cleared. On the
other hand, the FID memories hold only four bits at each pixel. This alone
25 would make the system six times faster even if the FID memories w~re to be
clearsd entirely after each write to the output device. In the preferred
embodiment which clears on~ one-fifteenth of the FID memories, ~he ffme
requirsd is but one-fiflesnth of that to cl0ar the full FID memory. Consequently,
th~ to1al tim~ utilized for clsarin~ in the present system is approximately one
30 ninetieth of that required in prior art systems havin~ equivalent dispby
1 31 b'7l
memories. This advantage can be easily increased if using FID memories with
more bits.
~INDOW ¦DENTIFICATION;
The output system described with respect to Flgure 1 may
conveniently be utilized in a computer system which makes full use of multiple
windows. For example, FlgurQ 2 illustrates a window identification output
system 30 which may be utilized with or apart from the frame identi~lcation
arrangement described above. The system 30 is utilized to provide output
signals to a cathode ray tube 12 which signals appear in different windows on
the cathode ray tube.
System 30 includes a pair of double-buffered display memories A (13)
and B (14), each of which is a fùll screen bitmapped memory. In a preterred
embodiment each display memory may include twenty-four bits of storage for
l s each pixel for storing color information. The system 30 also inc~udes a window
identification (WID) register 34 which in a preferred embodiment stores four bits
of information and a window identification (WID) memory 35 which in the
preferred embodiment is a full scrsen bitmapped memory which stores four bits
of information for each pixel. A window identification (WID) comparator 36
receives output signals from the WID register 34 and the WID rroemory 35. The
system 30 also includes a multiplexor 37, write enable logic 38 and a control
re~ister 39 for selectively enabling each of the display memories A and B.
In operation, windows are first selected by values provided from the
CPU. These values include both a pixel address and a window identification
number for each pixel of the window. The window identification number is
written to each corresponding pixel of the particular window in the window
identification memoly 36. When a first window is written to ths window
identification memory, each pixel within that window carries the window
identifica~ion number for that window. When a next window whch lies in front of
the first window is written to the window identification memory, the pcnions of
the second window which overlay the first are wfitten on top of the over apping
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1 ~1 b271
pixels ot the nrst and, therefore, automatically cover and clip the first. After all
of the windows desired have been written, ths window identification memory 35
has stored indications as shown in the display of the CRT 12 in Fi~ure 2.
When it is desired to write information to a display memory for particular
s windows (the system for windowing may ba used with single display memories
as well as double-buffered systems), the information is written into the displaymemory from the CPU through the data bus. This information includes a pixel
address, an RGB color value as discussed above, and a window identification
number. The window identification number is stored in the window
o identification register 34 and compared to the window identification number
s~ored at that pixel in the window identification memory 35. If the window
identification number stored in the window identification memory 35 is the same
as that in the window identification re3ister 34, the comparator circuit 36
causes the write enable lo~ic 38 to allow the RGB information to be written to
15 the addressed pix~l of the selected display memory. If the comparator circuitry
determines that the window identification number is not the same as the num~er
stored at that pixel in lhe window identification memory, then the RGB
information is not stored in the display memory. Consequently, only at those
addresses of the selected display memory which are within each particular
20 window will a signal for that window be written. The signal written to the display
memory is ultimately transferred from the particular display memory via a
multiplexor 37 to the cathode ray tube 31 shown in Fi~ure 2.
A number of additional advantages are realized by the use of the
window identification system herein described. For example, without more, the
25 window idenlification system provides that the information in a particular
window is written to ths correct area of the display and that portios of any
particular window which lie behind other windows are appropriately clipped.
Moreover, since the window identification memory is a tull screen bitmapped
memory, the windows may be of any shape which it is possible to describ~
30 rather than simply rectan~ular windows as in the usual case.
1 3 1 6 7
DEPTH INFORMATION:
The system shown in Fl~ure 1 tor providing rapid switching between
fraMss of display memory without clearing those display memories may also
incorporate apparatus for providing olnput indicative of the depth of each pixelS provided for a particular display on the cathode ray tube. Various systems areknown in the prior an for providing depth information, but the usual manner is to
provide an indication with each pixel to be writtsn on the display of the position
of that pixel along a Z-axis (third dimensional axis).
Fl~ure 3 illustrates a system 40 for including this information. The
l o system 40 adds to the circuitry illustrated in Fl~ure 1 a Z buffer memory 41which stores Z or depth information values; a Z buffer comparator arcuit 42
which compares stored Z buffer values to new Z values for each particular
pixel, a multiplexor 43 at the output of the FID memories, and a comparator 44.
The write enable logic circuit 24 is also ultilized for controlling ths writing of
l 5 information to the FID memories, the Z buffer memory, and the display
memories.
As is the case with the display memoriss, in order to speed system
operation, it is desirable to utilize a Z buffer memory 41 which does not require
clearin~ during operation. The normal Z buffer memory is a full screen
20 bitmapped memory which, like the FID memory, the display memories, and the
window memory, stores at each pixel address an indication of the particular
position that pixel is to take along the Z-axis. In the preferred embodiment of
this invention, the Z buffer memory stores twenty-four bits at each pixel;
consequently, the process of clearing this memory can substantially slow the
25 system.
In prior an systems, the Z buffar memory is first cleared to the
back~round Z value after each frame. This occurs because the Z buffer
mqmory tor sach frame stores only the frontmost value for each pixel. Since the
back~round is ths deepest indication which may be displayed, the Z buffer
30 memory is norrnally cleared to background before any trame is written. Unlessit is cleared, after the system has been operated for any time, the Z Wer
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1 3 1 6 2 7 ~
memory contains intorrnation from a number of previous frames, and it is
necessary to know which pixels are to ~e utilized and which are to be
dbre~arded.
In order to know if a new pixel should be written to a display memory, it is
first necessary to know whether that pixel of the frame identificalion memory
contains information in the frame being written. This determination is made in
the system 40 using the input frame identification register 16 and the particular
FID memory 17 or 18 selected by the control register 21 as described above.
The incomin~ FID number is compared with the FID number stored at the
l O indicated pixel in the FID memory; and if that comparison shows that the
numbers are equal, then the FID comparator 44 provides an equal output to the
write enable logic 24 which indicates tha~ the FID number stored at that pixel is
in the frame bein~ written and, ther0fore, that the pixel has been writtsn at least
once ~or this frame. If the FID numbers are not equal, then this pixel has not
l 5 been written before in this frame, and the comparator circuit 44 provides a not
equal signal to the write enable logic which causes the incoming inforrnation tobe written to the various memories. In this case, the selected display memory
receives the color display signal at the pixel position, the selected FID memoryrecsives the new frame identitication number, and the Z value is written to the
Z buffer memory.
If the si~nals from tha FID comparator 44 are equal indicatin~ that lhe
pixel has besn pr~viously written in this frame, then a Z buffer comparison is
necessary to determine whether to write. The Z buffer comparator 42 boks at
ths Z valus at that pixel position in ths Z buffer memory and compares it to thenew Z value. n the Z buffer comparison s~ows that the Z number is bss than or
equal to that which is stored in memory, ~en the new pixel is in a position at the
same plane or in tront of the pixel previously written; and the write enabb logic
is enabled to write the pixel to the appropriate display memory, the FID
memory, and the Z buffsr memory.
A tmth tabl~ is shown in Fl~ure 4 which shows the comparison values
to be used in the FID comparator 44 and the Z buffer comparator 42 in order to
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1 s16 ;~
operate the writs enable lo~ic so that a pixsl may be written io the dispiay
memory and the other memories. In the table, for the comparator outputs, a one
indicates that the = or ~= condition is true, a ~ero means that th0 condition isnot true, while an X indicates that the comparison condition is not used. For
5 the write output, a zero means a write will not occur and a one means a write
will occur. As the table shows, if the rasult of the FID memory comparison is
that the FID numbers differ, then a new frame is being written and the write
enable circuit is operated whatever the Z buffer comparison may be. On the
other hand, if the FID comparison shows the FID numbers to be the same, then
l O the resu~s of the Z buffer comparison control the operation of the write enable
circuitry.
Fi~ure 5 illustrates a system 50 which incorporates the ~lements of the
present invention previously described to provide extremely rapid switchin~
between frames to be displayed by a pair of double buffered display memories
5 at an output cathode ray tube. This system includes a control register 21 which
receives input signals from the CPU on a data bus and sends signals to enable
the window identification circuitry, the Z buffer circuitry and the frame
identification circuitry. The control re~ister also selects which of the double
buffered display m~mories 13 and 14 and frarne identification memories 17 and
20 18 are to be selected for any parlicular operalion such as input or output.
The system 50 also includes write enable lo~ic 24 which operates as the
central control to cause inforrnation to be written to the frame identification
memories, the Z buffer memory, and the disp~ay memories.
In operation, ths system 50 works in the following manner. The control
25 re~ister 21 recsives a value which indicates which of the particular elements of
circuitry are to be enabled. For example, the particular pro~ram may or may
not opera~a wi~h the window comparison drcl~itry, with ~he frame identification
re~isters, or with the Z buffer memory circuitr~. This is tnue because the
particular pro~ram may not have enabled ths window operation, may not be
30 operatin~ in the three~imensional domain, or may not be used to provide
ani~nation at the particular moment. The followin~ discussion presumes that all
l4
1 31 ~27~,
three of the subsystems have been enabled by signals to Ihe control register.
The basic operation of this system 50 is to first determine whether data signalsare within 8 particular window, then to determine whether the data si~nals tall
into the particular frame being written, and flnaliy to determine whether the data
S si~nals to be stored for that frame lie in front of data signals already stor~d in
that frame.
The first step in any operation is to store the windows to be utilized in the
window identification memory. This is accomplished by writing to the window
identification memory 35 values from the CPU which are indicative of each of
10 the windows to be utilized.
Thereafter, when it is desired to write a particular pixel to a display
memory 13 or 14, a value is stored into the control register 21 to select the
appropriate A or B display memory and the appropriate associatad frame
identification memory 17 or 18. The CPU writes the values of the current
15 window into the WID register 34 and the value of the current frame into the inpln
FID register 16. In the window identification circuitry, the window number in the
WID register 34 is compared with the window identification number stored in the
window identification memory 35 and if they are equal (that is, the information at
that pixel lies in the window), then an enab1e signal is transferred to the write
20 enable logic 24.
At the input FID comparator 44, the frame number in the input FID
registsr is compared with the frame number stored in the frame identification
memory which has been selected by the control register. If the comparison is
unequal, then that pixel has not yet been written for this frame and a signal is25 provided directly to the write enable logic 24 which causes the write enable
b~ic (if it has received an enable si~nal from the window identification
comparison circuit) to write to each of the memori~s. That is, the write enable
b~ic writes to the particular FID memory which has been selscted, to the Z
buffer memory, and to th0 display memory which has been selected by 1he
30 control re~ister.
1 3 1 ~
If no enable signal has been received from the ~nndow identification
cornparison, then the enabling signal from ths FID comparator doss not cause
the write enable lo~ic to write to any of the memories.
Presuming that the window comparison has provided an ~nable signal
and that the comparison of the signals in the FID register and th~ selected FID
memory shows that the pixel identification is the same, this indicates that thispixel has already been wr~tten to at this address for this frame; and it is
necessary to make a Z buffer comparison in order to deterrnine whether the
present pixel is in front of the pixel already stored. The Z buffer comparison
l O compares the Z value fumished by the CPU with the Z value stored in the Z
buffer mernory for that pixel. If the Z value furnished by the CPU is equal to or
less than that stored in the Z buffer memory, then the new or present pixel is in
front of the pixel stored; and a signal is provided to cause the write enable logic
24 to write to the FID memory, the Z buffer memory, and the selected display
l 5 memory.
Fi~ure 6 is a truth table illustrating how the results of the the
comparisons at the window comparator circuitry, the frame identification
comparator, and the Z buffer comparator control the operation of the write
enabls circuitry of Figur~ 5.
The other portions of the circuitry shown in Fi~ure 5 for system 50 are
substantialiy identical to those previously described and will not therefore be
described in detail again. For exampla, the background color register 20 is
utilized to provide background color in the positions in which the pixel to be
displayed on the CRT is n,ot a foreground piXBI in the selected frame. The
2~i output FID reyister 19 is usad, as described abovs, to determins by
comparison of the output frame idcntification number with the frame
identification number stored in the selected FID memory and to ~nable output
from the approprlate display memory or the back~round oolor re~ister.
Although the present invention has been described in terms of a
preferred embodiment, ~t will be appreciated that various modifications and
alterations mi~ht be made by those skilled in the art without departin~ from the --16--
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1 3 1 ~ 2 7
spirit and scope of the invention. The invention should therefore be measured
in terms of the claims which ~ollow: