Note: Descriptions are shown in the official language in which they were submitted.
" 1040;~91
1 BACKGROUND OF THE I~VENTION
1. Field of the Invention
The presen-t invention relates to testing circuits and
more specifically to circuits for monitoring the operation of
step data compasses.
2. Description of the Prior Art
"Step data" gyrocompasses produce electrical output
signals in the form of 3 phase-displaced, modulated pulse signals.
As the compass heading changes, pulses are developed in each of
the three phases. The number of such pulses is determined by
the magnitude of the heading change.
In many compass systems, especially on larger marine
vessels, two or more gyrocompasses are used at different
locations aboard the vessel. By comparing the output signal of
pairs of gyrocompasses, faulty operation can be readily detected.
Apparatus for monitoring the operation of pairs of such gyro-
compasses has been devised using mechanical assemblies of
differentially connected step motors. However, such assemblies
are relatively expensive, difficult to operate and maintain, and
require substantial amounts of power.
SUMMARY OF THE INVENTION
According to the principles of the present invention,
step data from each of the compasses to be compared is converted
into a number of COUNT UP or COUNT DOWN pulses, indicative of the
magnitude and direction of heading changes experienced by the
compasses. Whenever the compasses diverge by a predetermined
amount, an appropriate pulse is transferred to storage. If the
compasses later converge, pulses are subtracted from storage. An
alarm is actuated if the number of stored pulses exceeds a
preset level.
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104029~
1 According to the present invention, there is provided
apparatus for comparing the output signals from pairs of step
data compasses, each of said compasses being of the type that
produces output signals consisting of phase-displace trains of
modulated pulses per degree of compass rotation, pulse
conversion means for converting the output signals of each of
the compasses into separate UP or DOWN pulse trains as the
associated compass rotates in first or second directions
respectively, said pulse conversion means being differentially
connected so that rotation of both compasses in the same
direction produces UP pulses from one compass and DOWN pulses
from the other compass, storage means for separately storing each . :
category of UP and DOWN pulses, clock means for sequentially . . . .
interrogating the individual storage means, means in said clock
means for producing UP and DOWN control signals during the ~,
interrogation of UP and DOWN storage means, respectively,
storage counter means coupled to receive signals read out of
each of said storage means in response to interrogating signals
from said clock means, means responsive to control signals from
the cloc~ means to cause said counter to count in opposite ~ .
directions in response to pulses read out of UP and DOWN storage :
means respectively, means to actuate an alarm after the count in
said s~torage counter reaches a specified value.
The invention will now be described in greater detail with
reference to the accompanying drawings in which~
Fig. 1 is a series of graphs illustrating waveforms appearing
at various points in the circuit;
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104~)291
1 FigsO 2a and 2b are a block diagram of a circuit employing
the principles of the invention; and
Fig. 3 is a diagram illustrating a particular pulse
generator that may be used in practicing the invention.
D~SCRIPTIO~ OF THE PREFERRED EMBODIME~T
The top group of pulse trains in Fig. 1 represents the
signal output from a typical step data compassO Such a compass
produces three phase-displaced pulse trainsO ffl ically, the output
circuit of such a compass is energized from a 60 Hz source. The
alternating current signal is full wave rectified and applied to
suitable utilization equipment. As the compass heading changes,
a train of modulated pulses appears at each phase output terminal.
m e modulated pulses in the various trains are phase displaaed by
120 degrees. Normally, the compass output circuits are constructed -
so that a modulated pulse exists throughout a 1/2 degree variation
in compass heading and the inter-pulse interval is equal to the
modulated pulse width. Thus, for example, a full-wave rectiied
signal will appear at the output of phase B when the compass
heading is between 0 degrees and 1/2 degree whereas no output
20 signal will appear on phase B when the compass heading is between
1/2 degree and 1 degreeO
Since the pulse trains in the three phases are phase-
displaced, the direction in which the compass heading is changi~g
can be determined by the sequence in which the pu}ses appear on the
various phases.
Since the modulated pulses from the v æ ious trains overlap,
combinations o~ high and low signals occur as the compass
rotates through 1 degree. Thus the compass heading can be -
determined within l/6th degree,
Re$erring now to the block diagram of Fig. 2, the output
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104Q291
1 signals from the two compasses to be compared are applied to first
and second line isolators and level shifters 11 and 13 respectively.
Each line isolator and level shifter contains straightforward input
circuits which effectively filter and invert the modulated pulses
as depicted in curves A, B, and C of Fig. 1. As presently
preferred, the level shifted step data pulses have a magnitude of
10 volts and are suitable for C-M0S logic levels.
m e levelshifted step data pulses, like the modulated step
data pulses from each compass, provide six ,combinationsof high and
low signals as the compass heading changes.
Since the compass comparator of the present invention need
not have a resolution of l/6th degree, each line isolator and level
shifter further contains straightforward logic circuits which
convert the level shifted step data into a three step sequence as
~ndicated by curves Al, Bl and Cl of Fig. 1. m us, the logic
circuits provide a high level ~ voltage during the occurrence of
a high level ~ signal and a low level B signal. m e logic circuits
further produce a high level Bl signal in response to a high level
B signal and a low level C signal and a high level Cl signal during
the occurrence of a high level C signal and a low level A signal
As can be seen from Fig. 1, the three step sequence provides
sequential Cl, Bl and ~ pulses as the compass heading changes in
one direction and an opposite sequence of pulses as the compass
headi~g changes in the reverse direction.
m e three step s~quence pulse trains from the line isolators
and level shifters 11 and 13 are applied to pulse generators 15 and
17 respectivelyO
Each pulse generator serves as a pulse seque~ce detector
which senses the sequence of ~ , Bl and Cl pulses applied to its
3~ input terminals and also serves to pro & ce sharp output pulses on
one or the other of its two QUtpUt terminals depending upon the
sequence of the ~ , Bl and Cl pulses.
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Fig. 3 depicts a presently preferred design for a pulse generator,
although it will be appreciated that variations of the circuit of Fig. 3
may be used in practicing the invention.
Each of the Al, Bl and Cl pulse trains corresponding to the output
of a given compass is applied to an individual input channel in the pulse
generator.
Thus Al input signals are inverted and applied through an OR gate
19 to a one-shot multivibrator 21. The Al pulses are also applied directly
to an Al bus.
During the occurrence of an Al pulse, the corresponding Al bus
is at a high level. At the termination of an Al pulse, the one-shot multi-
vibrator 21 is triggered through the inverted signal applied to the OR gate
19 and produces a sharp output pulse ~typically in the order of a few micro-
seconds duration) at its Q output terminal.
The output pulse from the one-shot multivibrator 21 is applied to
a corresponding common bus A2.
As can be seen from Fig. 3, busses Bl and B2 are energized in a
similar fashion in response to a Bl input signal and busses Cl and C2 are
energized in response to a Cl input signal.
The relationship of the pulses appearing on the various busses can
be visualized by referring to the pulse generator and three step sequence
pulse trains depicted in Fig. 1.
In the presently preferred pulse generator circuit, the sequence
of pulses is detected with the aid of AND/OR/INVERT gates 23 and 25.
As presently preferred and as indicated in Fig. 3, Motorola Semi-
conductor Products, Inc. catalogue number MC14506 components may be used
for each of the gates 23 and 25. When these particular components are biased
as indicated in Fig. 3, coincident signals applied to input terminals
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1 A and B or C and D will cause, a~ output signal to appear atterminal
Z. An input signal applied to terminal E' or coincident signals
applied to terminals A' and B' will cause an output signal to appear
at terminal Z'.
By connecting the gates 23 and 25 to particular combinations
of busses, the gate 23 may be used to produce a train of UP pulses
in response to compass heading changes in one direction and gate 25
may be used to produce DOWN pulses in response to compass heading
changes in the opposite direction.
It will be seen that each pair of input terminals on the gates
23 and 25 is connected to receive a unique combination of signals
from the two sets of busses. Furthermore, each pair of input
termi~als on the gates 23 and 25 is connected to receive one signal
from the first set of busses which operates as an enabling signal
and a second signal from the second set of busses which operates
as a trigger signal.
As presently preferred, NAND~NOR logic is used in the comparator
of the present invention. In keeping with this technique, an output
signal will be produced by one of the gates 23 or 25 when a trigger
pulse is applied to that gate in combination with an appropriate
high level enable signal.
Thus referring to FigO 1, which depicts conditions when the
compasfi heading is increasin~, it can be seen that A2, B2 and C2
pulses occur on high to low transitions of ~1, Bl and Cl
respectively. For decreasing headings, the A2, B2 and C2 pulses
wQuld be displaced 1/2 degree to the left on the diagramO
Thus it ca~ be seen ~hat A2 and Cl or B2 and Al or C2 and -
Bl must produce cou~k up pulses for increasing headings while
A2 and Bl or B2 and Cl or C2 and Al must produce count down pulses
for decreasL~g headi~gsO Pu}se generator 15 perforns this function
for compass No. 1 and pulse generator 17 performs this function for
compass No. 2.
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1 Again referring to Fig. 2, the output pulses from the
generator 15 are applied to appropriate count up and count down
pulse storage circuits 27 and 29 respectively, whereas the corres-
ponding pulses from the pulse generator 17 are applied to individual
count up and count down pulse storage circuits 31 and 33 respectively.
Each of the pulse storage circuits contains a flip-flop
which is set in response to a signal from the associate~ pulse
generator and triggered by means of a clock pulse from a four-phase
clock 35. m e clock sequentially triggers the individual pulse
storage circuit and typically produces pulses in the order of 100
microseconds duration~ The clock also produces a train of square wave
UP/DOWN control pulses synchroni~ed with the clock pulses so that
successive clock pulaes are accompanied by alterate UP or DOWN pulses.
Since the compass heading changes will be random, output
signals from the pulse generators 15 and 17 will occur at random
intervals. When these pulses occur, they are temporarily stored
in the~appropriate storage circuit until that circuit receives a
clock pulse. Thus the storage circuits act as maans to co~vert the
random step levels into a synchronous clock step level. Without such
synchronization, a pulse might be received during the clocking
operation and the pulse would be lost.
The circuits intercoupling the compasses and the various pulse
8torage means are differentially connected so that a heading change
experienced by one compass will produce UP pulses whereas the identical
heading change in the other compass will produce DOWN pulsesO
Pulses clocked out of the various storage means are applied to
a storage counter 37 through an OR gate 39. m e storage counter is
basically a conventional up-down counter which counts in a direction
determined by the instantaneous value of an UP/DOWN control signal
30 received fram the clock 35 through an initial count up only circuit
41, which will be described
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104~)Z9l
1 As long as the two compasses being compared are operating
normally, the storage counter experiences no net change. ~ssume,
for instance, that both compasses are operating normally and a
heading change is experienced which produces an UP pulse from the
pulse generator 15. m is will be stored in the storage circuit 27
and clocked into the storage counter in response to a clock A
timing pulse. At the same time, the UP/DOWN control signal from the
clock 35 will cause the storage counter to count up. Because of the
differential connection, the same heading change experienced by the
second compass will cause a DOWN pulse to appear at the output of the
pulse generator 17 which will be stored in the pulse storage
circuit 33. This pulse will be clocked out of the pulse storage
circuit 33 in response to a clock D timing pulse. Since a clock D
timing pulse is accompanied by a low-level UP/DOWN control pulse,
the pulse from the storage circuit 33 will cause the counter to
count down and thus cancel the pulse earlier received from the
pulse storage circuit 27.
On the other hand, if the heading changes in the two
compasses are not identical, the number of pulses clocked out of the
storage circuits associated with the two compasses will not be equal
and the storage counter will experience a net change.
In a preferred embodiment, the storage counter 37 may
include conventional means for dividing the signal from the gate
by three so that one count is transferred to the output terminals
Qo~Q3 in response to a net accumulation of three count up or count
down pulses. With this arrange~ent, the output of the counter
ch~nges in 1 increments.
The binary coded output of the storage counter 37 appears at -
the terminals Q0-Q3 and is applied to a digital comparator 43 wherein
it is compared with the binary coded output from an adjustable alarm
set 45O
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1 Since the digital comparator is unidirectional, whereas the
storage counter must respond to pulses in both the up and down
direction, the initial count up only circuit 41 and the zero
detector 47 are used to modify the operation of the storage counter
so that the accumulated count is always in the up direction.
The zero detector 47 is a straightforward circuit and may,
for instance, consist basically o~ a NOR gate which will provide a
high level signal to the initial count up only circuit 41 whenever
the output of the storage counter becomes zero. Such a condition
occurs when the start button 49 is depressed at the beginning of a
measurement interval so as to provide a manual reset signal to the
storage counter. ~he count in the storage counter may also be
reduced to zero during the course of a routine comparison. For
instance, the first two pulses received from the gate 39 during a
comparison may be UP pulses which are then followed by a succession
of two DOWN pulses. The storage counter will respond by counting
up to 2 and then returning to zero.
m e initial count up only circuit 41 responds to an output
of the zero detector circuit so as to assure that the first pulse
received after the count in the storage counter has been reduced
to zero will cause the storage counter to count in the up direction.
The circuit 41 is straightforward and consists essentially of an
exclusive OR gate having one input terminal coupled to receive the
UP~DOWN control pulses and the other inputterminal coupled to
receive high or low level signals from a multivibrator which is
switched in accordance with the value of the UP or DOWW signal from
the gate 39 in the presence of an output signal from the zero
detector 47. When the count in the storage counter goes to zero,
the zero detector produces an enabling signal which permits the next
pulse from the gate 39 to set the multivibrator. If thi~ pulse is an
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1 UP pulse, the multivibrator provides a low level signal to the
exclusive OR gate so that the UP/DOWN pulse train passes directly to
the counter 37. On the other hand, if the first pulse were a DOWN
pulse, the multivibrator would produce a high level signal to the
input of the exclusive OR gate so that the circuit 41 would
effectively invert the UP/DOMN control pulses.
As soon as the first count is stored in the counter, the
zero detector output signal will cease and the initial count up
only circuit will continue to provide either direct or inverted
UP/DOW~ control signals until the count in the storage counter is
again reduced to zeroO
It will be appreciated that both UP and DOWN pulses from the
gate 39 have the same amplitude, polarity and direction, but are
distinguished only by their timing with relation to the UP/DOWN
control pulses. Therefore, even though the storage counter has been
initially set to count up, it can count in either direction in
response to the value of the individual pulses after the first pulse,
until the count is again reduced to zero.
m e alarm set is used in conjunction with the digital
comparator 43 to select a value of maximum divergence between compass
readings which can be tolerated before a warning signal is applied :~
to an alarm logic circuit 49O ~ ;
m e alarm set 45 typically contains a straightforward selector
switch which provides a parallel binary coded ~utput signal
equivalent to values of compass divergence typically in the range of
one degree to 15 degrees.
m e digital comparator 43 is a conventional circuit connected
so that if the count in the storage counter 37 reaches the binary
value selected for the alarm set, a warning signal will be applied
to the alarm logic 49.
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1 The alarm logic ~s lntermittently enabled through an alarm
pulser 51 after a predetermined delay established by means of an
adjustable alarm delay 53. The alarm pulser is a conventional
pulse generator and the alarm delay may be any suitable time delay
network such as an R-C network.
m e alarm delay is included in the circuit so that spurious
transients will not actuate the alarm devices, whereas the alarm
pulser is included in the circuit to provide intermittent audible
or flashing visible signals.
Provisions for a remote alarm may also be included in the
circuit if desired.
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