Note: Descriptions are shown in the official language in which they were submitted.
K(A 67,'~0~
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II)is invcntion rclatcs to a semiconductor device
and a mcthod Or elcctrically isolating circuit components
thereon. More ~rticularly, thc invention relates to an
integrated circuit dcvice and a method of electrically
isolating activc components formed in the integrated circuit.
In the manufacture of certain integrated circuits,
such as those utilizing epitaxially deposited silicon on a
suhstrate of sapphire, for example, electrical isolation
between circuit components of the integrated circuit has been
accomplished by forming islands of the silicon layer, whereby
the islands are separated by air. Further electrical
IS isolation of the silicon islands has heen obtained by covering
the islands and the space therebetween with a layer of
dielectric material. While such electrical isolation of
circuit components in an integrated circuit is satisfactory
for some semiconductor devices, isolated islands of
semiconductor material present certain problems associated
with the edge effects of these islands. For example, the
threshold voltage of a field-effect transistor (FET~ formed
in a semiconductor island can be unstable. Also, the
breakdown voltage of such a field-effect transistor is
usually lower than when formed in an integrated circuit
whose surface is substantially planar. Furthermore,
integrated circuits that comprise a plurality of separate
islands of semiconductor material on an insulating substrate
present serious problems for obtaining good metallization
over the edges of the islands without any discontinuities
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1 or unwanted excessive resistance in the metallization.
Field plates,or shields, have been used insemiconductor devices comprising bulk silicon, but the effect
of the field plates in these devices is primarily to act as
channel stoppers. It is not easy to get substantially
complete electrical isolation between spaced-apart circuit
components in devices formed in bulk silicon because it is
not possible to completely deplete the region beneath the
field plate in such devices.
In accordance with the present invention, a novel
semiconductor device and method of isolating circuit
components thereon are provided wherein the structure is
planar so that there are no islands to provide step heights
whicl1 present metal coverage problems. Also, by not
utilizing the island-isolation techniques of the prior art,
problems relating to the threshold instability and voltage
breakdown of the semiconductor device are markedly reduced or
substantially eliminated.
The novel semiconductor device comprises a layer
of semiconductor material on an insulating substrate. At
least two circuit components, each separated from the other
are formed in the layer of semiconductor material. A layer
of electrically insulating material is over the layer of
semiconductor material, and a layer of electrically conductive
2S material, which functions as a field plate, or shield, is over
the layer of insulating material. In accordance with the novel
method of the present invention, means are provided to bias
the layer of conductive material with respect to the layer
of semiconductor material to form a depleted region in the
3 layer of semiconductor material opposite to the layer of
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1 conductive material and between the circuit components.
In one embodiment of the novel semiconductor
device, the circuit components comprise field-effect
transistors, having source and drain regions formed in a
layer of single crystal silicon. The layer of silicon is
epitaxially deposited on a substrate of sapphire, and the
circuit components are adapted to be isolated from each other
by a depletion region that extends through the complete
thickness of the layer of semiconductor material between the
circuit components. The depletion region is obtained by
bias means, preferably by electrically connecting a field
plate to the layer of semiconductor material and utilizing
the voltage provided by the work function between the field
Z plate and the layer of semiconductor material.
In the drawings:
FIGURE l is a fragmentary cross-sectional view of
an embodiment of the novel semiconductor device taken along
~ the plane l-l of FIGURE 2;
j FIGURE 2 is a fragmentary plan view of the novel
semiconductor device shown in FIGURE l;
FIGURES 3-7, 9, lO and 12, are fragmentary cross-
sectional views of the novel semiconductor device in
difference stages of its construction; and
FIGURES 8 and ll are fragmentary plan views of the
2S novel semiconductor devices in different stages of its
construction.
Referring now particularly to FIGURES l and 2 of
the drawing, there is shown one embodiment of the novel
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I~(A 67908
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I semiconductor device 10 of the present invention. The semi-
conductor device lO comprises at least two circuit components
12 and 14, illustrated herein as field-effect transistors
(FET ' S) . The semiconductor device 10 comprises an
insulating substrate 16, such as sapphire (A1203), spinel,
or titanium dioxide, (TiO2), for example. A layer 18 of
semiconductor material such as N- type silicon, germanium,
or gallium arsenide, for example, is epitaxially deposited
on the su~strate 16. Source channel, and drain regions of
the FETs 12 and 14 are formed in the semiconductor layer 18,
as will hereinafter be explained.
A layer 20 of electrically insulating material,
such as silicon dioxide, silicon nitride, or aluminum oxide,
~or example, is over the semiconductor layer 18. An
electrically conductive layer 22, such as of doped
polycrystalline silicon, often called polysilicon, is over
the electrically insulating layer 20, except where the circuit
components 12 and 14 are formed. An electrically insulating
layer 24, such as of silicon dioxide, for example, is over
the conductive layer 22 and around electrical contacts of
the circuit components 12 and 14, as best shown in FIGURE 1
for the circuit component 14. A (phosphorus) doped poly-
silicon layer 26 is over the insulating layer 24, except in
the region of the component 12, and a (boron) doped layer 28
of polysilicon is over the doped polysilicon layer 26 and
over the portions of the component 12, as will hereinafter
be explained.
The circuit component 14, as shown in FIGURES 1
and 2, is a deep depletion type FET having an N+ source
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l region 30, an N- channel region 32, and an N+ drain
region 34. A gate electrode 36 is separated from the
channel region 32 by a portion of the insulating layer 20,
and electrical contacts 38 and 40 make contact with the
source and drain regions 30 and 34, respectively. An
electrical contact to the gate electrode 36 is not shown.
The circuit component 12 is a P-channel FET
comprising a source region 42, a channel region 44, and a
drain region 46. A gate electrode 48 is separated from the
channel region 44 by a portion of the insulating layer 20,
as shown in FIGURE 1. A metalized contact 50 is connected
to the gate electrode 48. Metal contacts 52 and 54 are
electrically connected to the source and drain regions 42
and 46, respectively.
lS Since the source, channel, ant drain regions 30,
32, ant 34, respectively, of the circuit component 14 are
formed in the same semiconductor layer 18 as the source,
channel, and drain regions 42, 44 and 46 of the circuit
component 12, it is most desirable to separate, that is, to
electrically isolate the circuit component 12 from circuit
component 14. In accordance with the present invention, a
region 60 of the semiconductor layer 18, between the circuit
components 12 and 14 of the device 10, is depleted by
biasing the conductive layer 22 with respect to the semi-
conductor layer 18. This may be accomplished under
appropriate conditions by connecting the conductive layer 22
to the semiconductor layer 18, as by connectingthe metalized
contacts 56 and 38 to a common connection, such as ground.
The bias means in the novel device 10 is preferably
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~ 4~ 3 ZO l a voltage provided by the work function difference
resulting from the different materials of the (field plate)
conductive layer 22 and the semiconductor layer 18.
Other bias means, however, such as a battery of suita b~e
voltage, may be connected between the conductive layer 22
and the semiconductor layer 18 to completely deplete the
region 60 of the semiconductor layer 18 between the circuit
components 12 and 14.
Due to the work function difference between the
(doped polysilicon) conductive layer 22 and the (single
crystal silicon) semiconductor layer 18, an electric field
exists at the surface of the semiconductor layer 18.
~lectrons which were initially present in the regions 60
of the semiconductor layer 18, opposite the conductive layer
22, are affected by the electric field and are swept out,
leaving the region 60 depleted of electrons. The depth
of the depleted region 60 depends upon the thickness of
the semlconductor layer 18 and its doping concentration.
Where the semiconductor layer 18 is relatively
thin , silicon, that is, less than 1 micron in thickness,
the concentration of carriers in the N- type silicon layer
18 is between 1 and 2 X1015/cm3, and the conductive layer 22
is (boron) doped polysilicon, the region 60 can be
completely depleted by connecting the layers 22 and 18 to
each other, by a common connection, such as ground, whereby
the circuit components 12 and 14 are substantially electrically
isolated from each other.
The novel semiconductor device 10 can be made as
follows: Referring now to FIGURE 3, there is shown the
insulating substrate 16 which may be a wafer of sapphire,
spinel, or titanium dioxide, for example, having a
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1 thickness of about between 250~m and 500 ~m. A layer of
semiconductor material, such as N- type silicon, having a
carrier concentration of between 1- 2xI015/cm3 and a
thickness of between about 0.5 ~m and 0.7 ~m is epitaxially
deposited on the surface of the insulating substrate 16. The
semiconductor layer 18 may be doped with either arsenic or
phosphorus, for example.
The layer 20 of electrically insulating material is
preferably a layer of silicon dioxide which can be grown
thermally on the semiconductor layer 18, as by oxidizing
the semiconductor layer 18 in steam at a temperature of
about 900C for between 30 and 60 minutes. The insulating
layer 20, shown in FIGURE 4, should have a thickness of
between about 500A and l,OOOA.
Next, a layer 22a of polysilicon is deposited
upon the insulating layer 20, as shown in FIGURE 5. The
polysilicon layer 22a can be deposited upon the insulating
layer 20 by any suitable method, as by the decomposition of
silane, SiH4, at a temperature of about 700C in a chemical
vapor deposition system. The thickness of the polysilicon
layer 22a is between about 0.1 ~m and 0.5 ~m. Means are
provided to dope the polysilicon layer 22a, shown in
FIGURE 7, to make it conductive. To this end, a layer 23
of P+(boron) doped glass, as shown in FIGURE 6, is deposited
over the polysilicon layer 22a. The layer 23 of P+ ~boron)
doped glass can be deposited by reacting silane (SiH4) and
oxygen in the presence of diborane at a temperature of
between 320 and 450C in achemical vapor deposition process,
well-known in the art. The thickness of the layer 23 may be
in the neighborhood of about 3,OOOA and should have a
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concentration of about 102/cm3.
Ihe boron glass layer 23, shown in FIGURE 6, is
defined with a photoresist, not shown, to form the field
plate 22, in the pattern shown in FIGURE 7 The defined
boron glass layer 23 is then etched as with a buffered HF
solution; and the remaining defined boron glass layer 23 is
heated for abo-lt 10 minutes in helium at a temperature of
about 1,050C to diffuse the boron into the field plate 22.
The boron glass 23 is then stripped from the field plate 22,
using an HF acid solutio~. The portion of the polysilicon
layer 22 that is not used for the field plate is then
removed, as with a solvent which does not substantially
attack boron doped silicon, such as a solution of KOH, water,
and N-propanol at a temperature of about 70C.
The structure shown in FIGURE 7 is now treated to
form the gates 36 and 48, of the circuit components 14 and
12, respectively, and to provide means for forming the source
and drain regions of these circuit components. To this
end, the layer 24 of silicon dioxide, having a thickness of
between 500A and 1000A, is formed over the structure shown
in FIGURE 7 as by heating in steam at 900C for about
30-60 minutes, shown in FIGURE 9. A polysilicon layer (not
shown) is deposited over the layer 24 and a boron doped
2S glass layer (not shown) is deposited over the last-mentioned
polysilicon layer in the manner previously described. The
boron doped layer is then covered with a photoresist which,
in turn, is defined to form the gates 36 and 48 by
photolithographic means well known in the art. The boron
glass is now etched, leaving boron glass portions over the
polycrystalline layer which will be the gates 36 and 48.
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The structure is now heated to diffuse boron into the
polysilicon layer to form the gates 36 and 48. The
remaining boron glass and portions of the polysilicon layer,
other than the gates 36 and 48 of the circuit components 5 14 and 12, respectively, are now etched away. Portions
of the insulating layer 20 are next etched away to expose
portions of the surface of the semiconductor layer 18 for
diffusing impurities therein to form the source and drain
regions of the circuit components 12 and 14, as shown in
FIoURE 10.
- The source and drain regions 30 and 34 of the
component 14 (FIGURE 1) are now formed by depositing a
layer 26 (FIGURE 12) of phosphorus doped polycrystalline
silicon ov0r exposed portions of the surface of the semicon-
lS ductor layer 18, the phosphorus doped layer 26 is deposited in
a chemical vapor deposition system from a mixture of silane
and PH3 at a temperature of between 320 and 450C to a
thickness of about l,OOOA. The concentration of phosphorus
in the doped polycrystalline silicon layer 26 is about
1019/cm3. The phosphorus doped layer 26 is defined with
photoresist over the source and drain regions 30 and 34. The
layer 28 of boron doped polycrystalline silicon is now
deposited over the structure shown in FIGURE 12 for the purpose
of forming the source and drain regions 42 and 46 of the com-
ponent 12, as shown in FIGURE 2. The boron doped layer 28 and
the phosphorus doped layer 26 are then heated to a temperature
of about 1050C for about 15 minutes in helium to diffuse
the boron and phosphorus into the semiconductor layer 18,
simultaneously whereby to form the source and drain regions
42 and 46 of the device 12 and the source and drain regions
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30 and 34 of the device 14.
Contact regions to the sources and drains of the ~
circuit components 12 and 14 and also to the field plate 22 ~;
are formed by photolithographic means, using a photoresist
and a buffered HF for etching, in a manner well-known in the
art. Metal contacts 38 and 40 for source and drain regions
of the circuit component 14 and metal contacts 52 and 54 for
the source and drain regions 42 and 46 of the circuit ~
component 12, as well as a metal contact 56 for the field ~ `
plate 22 are formed by thc vacuum evaporation of a metal,
such as aluminum, in a manner well-knwon in the art.
While the novel semiconductor device 10 has been
doscribed with components 12 and 14 formed in the
somiconductor layer 18 of N- type somiconductor material,
it is within the contemplation of the present invention to
lnclute semicontuctor tevices with components formed in P
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type somiconductor material as where the conductive layer 22
can~be phosphorus doped polysilicon or a metal. If the
; 20 contuctive~layer 22 is~ a metal, then the bias applied between
the~contuctive layer~22 and the semiconductor layer 18 may be
other than zero, that is, either a positive or a negative
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potential in order to effect the completely depleted region
0~within the semicontuctor layer 18.
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