Note: Descriptions are shown in the official language in which they were submitted.
~ 3~Z~
: - .MULTI-FREQUENCY SIGNALING DECODER -
, . ...
This invention relate~ to multi~frequency signaling ~coders.
.. '' . '"''- . .
A multi-frequency signaling decoder is used or
detecting the presence within an input waveform of
predetermined combinations of predetermined frequency
~ components in respective frequency bands. The most common
; ~ application for such a decoder is in a telephone switching
office which receives multi-frequency waveforms produced
by push-button telephones.
The predetexmined frequencies or tones used in
telephone systems fall into two groups, a "low" group
-- and a "high" group. In the low group are the frequencies
.697 Hz, 770 Hz, 852 ~z, and 941 Hz. In the high group are
the frequencies 1209 Hz, 1336 Hz, and i477 ~z. Some
~5 systems also have the frequency 1633 Hz included in the
high group. The presence of a predetermined combination of
a pair of tones, one from each group, in the multi-frequency
waveform identi~ies a particular digit that has been signaie~.
It would be ideal from the-viewpoint of ease of decoding
if the multi-frequency waveform contained only the above-
. mentioned frequency components~ -In practice, however~ this
is not the case. Instead, there are also present wide-band
noise, transients resulting from lighting and other
electrical phenomena, and various other unwanted frequency
components such as those resulting from the dial tone and
such as the sum and difference frequencies related to the
tone pair. In addition, voice frequency components are
frequently present in the waveform. This occurs whenever
a person is talking to someone else in the room during
intervals between successive operations of the push buttons.
Further complicating factors reside in the tolerance that
. "`' ~I~' '' ' ' ,,~ .
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~, -
~L043~24
exists on the signal frequency components, and in the need
for quick response to keep pace with rapidly signaled digits.
Each of these complicating factors precludes the use of very
narrow detection bandwidths that, were it practical to use
them, would eliminate much of the noise and thereby simplify
the detection task.
Various approaches have been taken in the past in
attempts to achieve noise immunity in a multi-frequency
signaling decoder. One such approach is described in an
ar~icle by Battista, Morrison, and Nash, entitled "Signaling
System and Receiver for Touch-Tone Calling", which was
published in March 1963. Their approach is directed to
exploiting a principle sometimes called "guard action of a
limiter". Significantly, they teach that to render this tool
most effective, the largest possible portion of the speech
spectrum should be given access to each limiter. Accordingly,
the multi-channel system they propose employs a pair of
band-elimination filters, one for each channel. The band
elimination filter for each channel thus substantially
attenuates the out-of-channel frequency components, but
passes a wide spectrum of noise.
A somewhat different approach, not involving such
band-elimination filters, is described in U.~. Patent No.
3,790,720 of K.R.Sharfmann, issued February 5, 1974 to
Northern ~lectric Company Limited, Montreal. The system
described therein employs a high-pass filter for one channel,
and a low-pass filter for another channel. Each filtered
signal is processed by digital circuitry that provides an
indication of the average frequency thereof, as measured during
a measurement period.
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~L~43C~24
This approach has a number o~ disadvantages. To
begin with, the low pass filter does not filter out the dial
tone. As to the frequency averaging, it is necessary to
ensure that the average is not unduly weighted one way or
the other by initial transients. Thus, in the system
taught in U.S. Patent 3,790,720 there is provided means for
postponing the commencement of the measurement period. And,
the longer this is postponed, the less time is available for
performing the averaging, otherwise the system would not
comply with requirements as to minimum response times. A
more subtle disadvantage, which will be better appreciated
after considering the ensuing description of the preferred
embodiment of this invention, relates to what is referred to
as resolution. Finally, and perhaps most significantly,
a frequency averaging system by its very nature ignores the
presence of jitter. Thus, it is possible for the frequency
averaging system to mistake voice frequency components for
signaling frequencies, despite the substantial jitter that is
occasioned by voice frequency component modulation.
Summary of the Invention
This invention is directed to an improvement in a
multi-frequency signaling decoder, which achieves substantial
noise immunity as a result of the combined effects of band-
pass filters and jitter-detecting means.
In accordance with the present invention there is
~` provided a multi-frequency signaling decoder having at least
a pair of signal processing channels for detecting the
; presence within an input waveform of predetermined combinations
of predetermined frequency components in respective frequency
bands, the improvement wherein each channel comprises:
~ - 3 -
:10~3(t~:~
filter means having an input connected to respond
to the input waveform, and an output on which it produces a
filtered signal;
means responsive to the filtered signal for
sequentially producing control pulses in substantial
synchronism with the filtered signal;
time-range quantizing means controlled by the control
pulses to produce a digital signal that in substantial
synchronism with the filtered signal indicates whether the
filtered signal has, within a predetermined limit, a period
corresponding to one of the predetermined frequency components;
jitter detecting means responsive to the digital
signal for producing a gating control signal which indicates
whether jitter in excess of a predetermined jitter tolerance
exists in the filtered signal; and wherein the decoder includes
outputting means responsive to the gating control
signal produced in each channel for indicating the continuous,
substantially jitter-free detection of a pair of the pre-
determined fre~uency components for at least a predetermined
interval of time.
The invention can be embodied in a decoder having at
:~ least a pair of channels for detecting the presence
within an input waveform of predetermined combinations of
2;
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~0gL3(~24
1 predetermined frequency components in respective frequency
bands.
Each channel includes filter means having an input
connected to respond to-the input waveform, and output on
which it produces a filtered signal, and, in the preferred
embodiment, a band-pass input-to-output characteristic.
Preferably, each filter means comprises a plurality o~ active
filter circuits arranged to provide the band-pass characteristic.
Means in each channel provlde for se~uentially
producing control pulses in substantial synchronism with the
filtered signal. Preferably, this includes in tandem
connection a limiter circuit and a frequency divider
circuit. The divider circuit produces a time-varying,
binary-valued waveform that oscillates at a sub-multiple
of the filtered.frequency, and the control pulses are
produced at the sub-multiple frequency.
Each channel further includes time-range quantizing
means controlled by the control pulses to produce a digital
~signal that in synchronism with the filtered signal
~` 20 ~indicates whether the filtered signal has, within a
; predetermined limit, a period corresponding to one of the
frequency components. Preferably, the time-range quantizing
; means includes: a resettable counter, the control pulses
being coupled to it to reset it in synchronism with the
2 input waveform; means for clocking the resettable counter
so that it accumulates a count during the time~between
successive control pulses; decoding means for decoding a
plurality of preselected accumulated counts to identify
the entry into and exit from at least one count range; and
I 104~24
recording means triggered by the decoding means into
sequential states that altexnately indicate that the
accumulated count is outside and in~ide such a count range;
and means responsive to the rec~rding means for providing
the digital signal.
In the preferred emboaiment, the recording means further
includes means ~or providing a period-range identification
signal that, on each occasion that the resettable counter
. . is reset before the decoding means identifies the exit from
- ~ 10 a count range that has been entered, has a binary coded
: value identifying that particular count range that had not
been exited.
A very significant feature of the invention is that
each rhannel includes jitter-detecting means responsive to
.15 the digital signal for producing a gating control signal
. ~w~ich indicates whether jitter in excess of a predetermined
:~. . jitter tolerance exists in the filtered signal. Accordingly,; during intervals in which each of the filtered signals has,. ; as a result of such factors as the presence of voice frequency
components and the like, an average freguency that could be
. mistaken for a multi-frequency signal component, the jitter
detecting means detects the accompanying relatively
substantial edge jitter or phase modulation of the waveorm
so as to preclude the decoder from making a false aetection.
2 In the preferred embodiment, the jitter-detecting
means includes a save register having an output for
. providing an indication o a binary coded value loaded
therein; means for loading the save register with the
. . r~nge identification signal on command by the digital
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1043~24
1 signal; and comparator means connected to the save register
and operable to compare binary coded values successively
loaded therein for producing the gating control signal.
The.decoder further includes gating signal controlled
S outputting means for indicating the continuous, substantially
. jitter-free detection of a pair of the pr~determined
.. frequency components for at least a predetermined interval
. of time. Preferably, the outputting means includes a timing
circuit shared by each of the channels, the timing circuit
0 being operative to recommence timing a predetermined interval
of time on each occasion that any of the channels, as
. .. indicated by the respective gating control signal thereof,
: detects an excessive jitter in its respective filtered
. signal.
.. . . - _
5 . ` .
Brief Descri~tion of the Drawinqs
.
~; FIG. 1 is a block diagram depicting the general
.. : . organization of the preferred embodiment of this invention;
FIG. 2 is a more detailed.block and schematic diagram
2 of the front end stages of.the preferred embodiment;
. ~IG. 3 comprises FIGS. 3a and 3b, each of which is a
~. . schematic of an active filter that is used as a building
- . . block in the band pass filters shown in FIGS. 1 and 2;
. . .
; . . FIG. 4 comprises FIGS. 4a and 4b, each of which is a
graph depicting the input-to-output characteristics of a
: respective band pass filter used in th~ preferred embodiment;
', , . ' ,
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1~ ~10430.4
1 FIG. 5 is a logic block d.iagram depicting the
preferred arrangement of the period boundaries detector in
the "low" channel o FIG. l;
. FIG. 6 comprises FIGS. 6a-6g which are wavef~rm diagrams
illustrating how the period boundaries detector of.FIG. 5
produces control pulses in substantial synchronism with
the filtered s~gnal produced in the "low" channel;
FIG. 7 is a block diagram depicting the preferred
. - arrangement of the time-range quantizer in the "low"
0 channel of FIG. l;
FIG~ 8 comprises FIGS. 8a-8h which are waveform
.. .diagrams illustrating how the time-varying range quantizer
. . of FIG. 7 produces a digital signal used to control the.
: . jitter detector in the "low" channel of FIG. l;
: - 15 FIG. 9 is a logic block diagram depicting the preferred
. arrangement of the jitter detector;
. FIG. 10 is a more detailed.block diagram depicting
the preferred arrangement o~ the control gates and shared
. gates shown generally in FIG. l;
FIG. 11 is a more detailed block diagram depicting the
preferred arrangement of the interval timing circuitry
. shown generally in FIG. l; and
. . . FIG. 12 comprises FIGS. 12a-12f which are waveform
diagrams illustrating how the interval. timing circuitry of
2 FIG. 11 produces an output signal for indicating the
. continuous, substantially jitter-free detection of a pair
. of predetermined frequency components for at least a
predetermined interval of time~
................ ...... ......... ,
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. 1043U24
1 Detailed Description of the Preferred Embodiment
A telephone switching exchange, whether in a telephone
company central office or in a private branch exchange,
performs a variety of functions. The principal function
5 is to connect together any arbitrary two subset loops served
by the exchange so ~hat voice transmission can take place.
A switching exchange performs this function in response
to a call signaling pattern produced on a subset loop by
call signaling circuitry in a calling telephone. Many
0 switching exchanges now installed throughout the world have
been designed for compatibility wlth the characteristic
features~of the pulse patterns produced by rotary dial
~ telephones. Ir general, these switching exchanges are not
; compatible with the signal patterns developed in the form
1~ of multi-frequency tone bursts produced by push-button
telephones.
The assignee of this invention has produced an interface
system for converting ~signal patterns in the form of
multi-frequency tone bursts into the type of pulse patterns
with which conventional switching exchanges are compatible.
In the process of effecting this conversion, the interface
system performs a number of relatively routine tasks such
as buffering digit-defining, parallel-by-bit data signals,
converting the parallel-by-bit data signals to serial pulse
2 trains, and outpulsing the serial pulse trains with
- appropriate inter-digit intervals. Various known digital
circuit arrangements are suitable for performing these
relatively routine tasks.
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1 A key task, fraught with difficulty, that the interface
system performs is to produce the digit-defining, parallel-
by-bit data signals in response to the input waveform. That
portion of the interface system invol~ed in this decoding
task embodies the improvement of this invention, and its
general organization is depicted in the block diagram of
FIG. 1.
As indicated in FIG. 1, an input waveform is coupled
to band-pass filters 10 and 12 which form the front end
0 stage for "low" and "high" channels respectively. The
input-to-output characteristics of the filters used in the
preferred e~bodiment is shown in FIG. 4 which is described
in more detail below.
The Fourier-spectrum of the input waveform is quite
; 15 complex and variable. Fre~uency components present ~herein
include wide-band noise, high frequency noise resulting from
transients~ dial tone and, ~uite often, voice frequency
components and various harmonics and beat frequencies related
thereto. It lS important that these not be mistaken for the
2 signal frequency components which fall into two groups, a
high group and a low group. The low group includes the tones
or frequencies 697 Hz, 770 Hz, 852 Hz and 941 Hz. The high
group includes the frequencies 1209 Hz, 1336 Hz, and 1477 Hz.
An additional signal frequency component sometimes used is
2 1633 ~z. It will be apparent from the ensuing description
that only minox modifications to the "high" channel would be
~ecessary to decode this additional signal frequency component.
~ush-button telephones are designed to comply with an industry
; standard to the effect that each of the actual tones produced
3 must have a fre~uency within +1-1/2% of the nominal frequency.
,. . ~ . .
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10431)Z4
1 I With reference again to FIG. 1, each of the channels
¦ provides for sequentially producing control pulses
¦ (nPQT/Lo and nPQT/~i~ in substantial synchronism with the
¦ filtered signal output of the channel band-pass filter.
5 ¦ To this end, the low channel includes a limiter 14 and an
¦ n Period Boundaries Detector 16, and the high channel
¦ includes a limiter 18 and an n Period Boundaries Detector
¦ 20~ The construction and operation of the control pulse
` ¦ producing means in the high channel is essentially the
10 ¦ same as that for the low channel; thus only one bears
¦ explanation in detail.
. ¦ As shown in FIG. 5, the filtered signal LoFo is limited
¦ by the limiter to produce the signal SQLoFo whose waveform
¦ is depicted in FIG. 6b. A flip-flop 22 triggered by the
signal SQ~oFo produces the signal 2PLoFo whose waveform is
depicted in FIG. 6c. The detector 16 further includes a
shift register comprising D-type flip-flops 24 and 26. Each
of these flip-flops is triggered by a clocking pulse train
MC/4 ~provided by a conventionaI clock source not shown)
2b operating at 250K Hz. FIG. 6a shows the waveform for this
clocking pulse train~
The D input o flip-flop 24 receives the 2PLoFo signal
and produces the complementary output signals SRQl and
~ . The D input of flip-flop 26 receives the SRQl signal
and produces the complementary output signals SRQ2 and
SRQ2. A pair of ~AND gates 28 and 29 decode the state of
. the shift register and produce the signals 2PQ~/Lo and
MInO/Lo respectively. It will be seen from a comparison
o~ FIGS. 6 a~d ~b th~ the sign~l 2PQ~/Lo
assumes a '0' binary value once (or a 4 ~icroseconds
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~0431~Z4
1 ¦ pulse interval) every other cycle of the SQLoFo signal.
¦ During the time intervening between these pulses, the
¦ 2PQT/Lo signal has a binary '1' value.
¦ It bears mention that an attempt is made herein to give
5 ¦ suggestive names to these signals so as to make it easier
¦ to recall what role they play ~n operation. For example,
¦ the acronym 2PQT was selectea so as to suggest that this
¦ signal has a binary '1' value during a 2-Period Quantizing
¦ Time interval. Similarly, the acronym MInO was selected
10 ¦ to suggest that this signal has a binary ~1I value during
¦ a time in which it gives a command to Memorize Ins and Outs.
¦ As mentioned above, the detector 20 (for the high
channel) is essentially the same in construction and mode
of operation as the detect~r 16 (fox the low channel). The
only difference between them resides in the use of a
higher clock rate (500K Hz3 for triggering the shift register
i~ the detector 20.
This same difference is the ~rincipaI difference b~tween
a time-range quantizer 30 fot' the low channel of FIG. 1 and
- 23 a time_range quantizer 31 for the high channel. Each o~
these ~uantizers is controlled by control pulses supplied
- thereto from the respective boundary detector to produce a
digital signal ~SAVE ds). This digital signal, in substantial
synchronism with the filtered signal, indicates whether the
filtered signal has, within a predetermined limit, a period
corresponding to one of the predetermined signal frequencies.
- Consider now FIG. 7 which depicts the preferred
arrangement of time-range quantizer 30.
.
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~;043~
1 The quantizer 30 includes a resettable counter 32.
During the 2-period quantizing time (when 2PQT/Lo is 'l'),
the counter 32 counts at a 2501C Hz rate as a result of
being clocked by the MC/4 pulse train. In the preferred
5 embodiment, the resettable counter comprises three decaae
counters (not separately shown) each of which is an integrated
; circuit sold by the RCA Solid State Division under the
designation CD4017. This integrated circuit includes ten
decoding gates for providing a one-out-of-ten code indicating
the present count of the counter. With three of these
integrated circuits connected in tandem, there is provided
an overall counter ~hat can count from decimal o oa to decimal
999 and that produces hundreds, tens, and units outputs,
with each of these outputs being coded in the one-out-of-ten
code.
The sequentially produced control pulses of the 2PQT/Lo
signal (see FIG. 6f) are inverted by a NAND gate 33 to
reset the counter. Thus, for a brief interval (4 ~s)
occurring once every other cycle of the filtered signal,
2 the counter 32 is reset to zero. Immediately after it has
been reset, the counter 32 starts f~om OOQ~to count ur~lar~ly
toward 999. The counter, however, is prevented from ever
counting to its maximum by virtue of the operation of a
feedback path through NAND gate 33. This feedback path is
provided for the following reason. The lowest valid
frequency to be decoded by the low channel is only slightly
lower than 697 Hz. Thus, the maximum 2-period quantizing
time for a valid signal here is only slightly ~ ater than
2870 microseconds. Inasmuch as the counter is clocked at a
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-. 1 10430Z4 ~ '
250KHz rate, the maximum count it will accumulate while
~uantizing a valid signal will be only slightly greater
than 718 [i.e., ~870 microseconds)/(4 microseconds per count)].
~hus, there is no need to count any higher than about 800
or 900 because such an excess count could not result from
a valid signal. Moreover, if the counter were not so
automatically xeset there would be a small possibility that
the presence of a very low non-signal frequency component
' would cause the counter to recycle into a valid count range
10 and thus lead to a false detection. For the foregoing
reasons the 9th digit output of the hundred's counter
portion, which equals '1' when the counter reaches a count
' of 900, is connected to an inverter 34. The output of
inverter 34 therefore forces ,the N~D gate 33 output to
reset the counter in the event it accumulates such an
excess count. ' '
The quantizer 30 further includes entry point and exit
point decoder 35 that interconnect the counter 32 and a
. NOR ~ate 36. -The NOR gate 36 produces a signal InO (an
acronym for In's and Out's3. The waveform defined by the
signal InO is input signal dependent. For a representative
case in which the filtered and limited signal SQLoFo has a
period of about 1180 microseconds, the waveform defined by
the signal InO is shown in FIG. 8f. ~ 5 particular period
2 falls within the predetermined limits for decoding the signal
frequency 852 ~z.
The time scale for each of the wave~orms of FIG. 8 is
indicated at the top of the figure. FIG. 8a indicates ~he
decimal value of the count accumulated in counter 32 at
' 3
:; ' . ' . . , .'. '
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~, . . .
; 1 various points in time. FIG. 8b shows that, for this
representative case, the filtered and limited signal SQLoFo
switches from '0' to '1' at about: 1 microsecond on the
time scale. As indicated in FIG. 8c, this positive-going
edge triggers the flip-flop 22 lFlG. 5), thereby causing
the signal 2PLoFo to switch from '1' to '0'. As indicated
in FIG. 8d, coincident with the leading edge of the next
succeeding clock pulse (i.e., at 4 microseconds~, the signal
2PQT/Lo switches from '1 to '0' and remains there for four
microseconds. Consequently, the counter is reset, an~ as
indicated in FIG. 8a, has an accumu~ated count of decimal
, 000 at 8 microseconds on the time scale.
When the four- microsecond wide control pulse defined
by the signal 2PQT/Lo ends at 8 microseconds on the time
scale, the signal MInO/Lo (FIG. 8e) switches to '0'. It will
be recalled that this signal is produced by i~AND gate 29
(FIG. 5) of the detector 16. This si~nal is received by
the clear input of each of three flip-flops 37, 38, and 39.
In the preferred e~bodiment, there is used a ingle integrated
circuit that includes these three flip-flops and also the
NAND gate 29 ~FIG. 5) in a single package. This integrated
circuit is sold by National Semiconductor Corporation, among
others, undex the designation SN7493. Each of these flip-
flops have the following characteristics: 1) it is held in
the zero state whenever a logical '0' is applied to its
clear input; and 2) it changes state whenever, at a time
that a logical '1' is applied to its clear input, there is
a negative-going transition in the signal applied to its CP
input.
, . ' ,' ' '~.;.
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1~ 104~U~4
1 The flip-flop 37 receives the signal InO at its
CP input, and at its output provides a signal QrI 5an
acxonym for Quantizer In). An inverter 40 produces the
complementary signal QrO . (an acronym for Quantizer Out).
S The flip-flop 38 receives the signal QrO at its CP
. input, and its output is applied to the CP input.o flip-
.. flop 39. It will be appreciated that this interconnection
of the flip-flops forms a three-stage counting register
that is operative to count pulses defined by the signal
InO so long as the.counting register is commanded to do
.. so by the MInO signal. . .
......... .. ... .... ... It bears mentlon here that the first stage of this
oounting register (i..e., flip-flop 37) serves as a recording
.. means triggered into sequential states that alternately
. 15 ¦ indicate that the accumulated count is outside and inside
.. a predetermined count range. To explain this point further,
.. reference is again made to the waveform diagrms of FIG. 8.
~ - As ~tated above, when the four microsecond .control
; . pulse defined by the signal 2PQT/Lo ends at 8 microseconds
2 ¦ on the time scale; the signal MInO/Lo (FIG. 8f) switches to
'O'. For a relatively long time thereafter (in comparison
¦ with the 4 microsecond divisions of the time scale), no
change occurs in the binary value of any of signals depicted
in FIGS. 8b-8h. This fact is indicated in the waveform
diagrams by the breaks in the waveforms. lThe counter 32
. of couxse continues to accumulate.) Slightly before 592
:- microseconds on the time scale, the signal SQLoFo switches
from '1' to '0'. ~his negative-going transition in and of
. itself has no effect on the flip-flop 22 (FI~. 5). ~hus,
3 none of the other slgnals change binary value then~
..' . .. , ,. ,,, '. .,
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1 Slightly before 1180 microseconds on the time scale,
the signal SQLoFo switches from 'C' to '1' to commence the second
of the ~ pe~iods being quantized. As depicted in FIG. 8e,
coincident with ~he leading edge of the next succeeding
clock pulse ti.e., at 1180 microseconds), the signal MInO/Lo
switches from 'O' to '1'. This signal therefore commands
the counting register to memorize the number of pulses defined
in the InO signal.
The next event of interest occurs a~ 2076 microseconds
on the time scale. For a four microsecond long interval
commencing at this time the counter 32 has an accumulated
- count of decimal 516. This is the entry point for the
count range corresponding to the signal frequency 941 Hz.
The decoders 35 output (waveform not illustrated) defines a
four microsecond wide negative pulse while the counter 32
is at this entry point count. Owing to propagation delays,
- this negative pulse lags the clock somewhat. However, the
NOR gate 36 is directly responsive to the clocking pulse
train MC/4 as well as this delayed pulse and its output
2 signal (InO) is precisely sychronized with the clock pulse
train.
~ hus, as indicated in FIG. 8f, the signal In~ defines
a two microsecond wide positive pulse whose trailing or
negative-going edge occurs at 2080 microseconds on the time
2 scale. In response to this trailing edge, the flip-flop 37
changes state and its output signal QrI switches to '1'.
This binary value indicates that the counter 32 has entered
or is inside a predetermined count range. If the counter 32
were to be reset at this point, the conclusion would be that
' 3
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. 1 104~1)Z4
1 the filtered signal had a period corresponding to 968 Hz
which is within 2.8~of 941 Hz. In short, a binary '1' value
for the QrI signal indicates that at least for the moment
it appears possible that a valid signal component is present
in the filtered waveform.
In this representative case, however, the counter 32
. . is not reset at this point, and instead continues to count.
: The next event of interest occurs at 2200 microseconds on
the time scale. For a ~our microsecond interval commencing
~ 10 at t~is time, the counter 32 has an accumulated count of
; decimal.S47. This is the exit point for the count range
- .corresponding to the signal frequency 941 Hz. Again, in
the manner descri.bed above, the signal InO defines a two-
microsecond wide positive pulse. The trailing edge of this
second pulse occurs at 2204 microseconds on the time scale.
- . In response to this trailing edge, the flip-flop 37 changes
state and its output signal QrI switches back to '0'. Now,
the signal QrI indicates that the counter ~2 has exited
or is outside a predetermined count range. In other words,
this binary '0' value for the QrI signal indicates that at
. least for the moment it does nvt appear that a valid signal
component is present in the filtered waveform.
. The next event of interest occurs a~2284 microseconds
on the time scale. For a four microsecond interval
~ 2 commencing at this time, the counter 32 has an accumula~ed
: . . . count of decimal 568. This is the entr.y. point.~or the count
range corresponding to the signal frequency 852 Hz. Again,
in the manner described above, the flip-flop 37 is caused
. to change state so that its output QrI switches back to '1'.
- 3
. . ., '' '.
:.' '
30Z4
The next event of interest occurs at 585 microsec~nds
on the time scale. At this time, the filtered and limited
- signal SQLoFo switches from '0' to '1'. This of course
constitutes the end of the second of the two periods~bein~ i
quantized. Coincident wlth the next succeeding leading
edge of the clock pulse train, the four microsecond wide
control pulse is defined in the signal 2PQT/Lo. As stated
above, the occurrence of this control pulse results in the
resetting of the counter 32. Inasmuch as this event occurred
at a time when the then accumulated count was in the count
range for a valid signal requency (here, 852 Hz~, it is
concluded that it is quite likely that the period of a valid
signal frequency has just been quantized. This likelihood is
indicated by a positive pulse defined in a signal SAVE ds
(waveform shown in FIG. 8h).
This signal is produced by an AND gate 41 which responds
to the QrI signal and the signal produced by NAND gate 33
to reset the counter 32. As will be explained in more detail
below, the CAVE ds signal is as a command for a save register
20 in jitter detecting means. From what has so far been
explained, however, it will be appreciated that the SAVE ds
signal constitutes a digita~ signal that in substantial
synchronism with the filtered signal indicates whether the
filtered signal has~, within a predetermined limit, a period
25 corresponding to one of the predetermined signal frequencies.
One of the advantages of the time-range quantizer is
that flexibility is provided as to setting the limits of the
count ranges. In particular, the entry points and exit
points for any particular count range can be independently
; 3
. . . . . .- .
" ." ' ,''~, ,'," ' ....
~` ~ . ' ' ' '' '.
.- ~04302~
1 preselected; and different count ranges can have
independently selected widths. It will be appreciated that
the count range limits play àn; - important role in
defining~the overall detection bandwidths of the decoder.
Other contributlng factors such as thé band-pass filters
and the jitter detecting means ma~e the overall detection
bandwidths somewhat narrower than the respective count
ranges or ~uantizing bandwidths. As a result of the
flexibility as to the setting of the quanti2ing bandwidths,
the overall detection bandwidths can be easily controlled
in the light of empirical results. In further e~planation
. of this point, consider the following. As stated above,
in the preferred embodiment, the entr~ and exit point counts
for the nominal signal frequency 941 Hz are set at 516 and
547. This corresponds to a quantizing bandwidth of 54.9 Hz
around this nominal frequency~ If it were desired to narrow
this quantizing bandwidth slightly, the respectlve decode
counts coul~d be set to 517 and 54~. This would give a
~- corresponding quantizing bandwidth of 51.4 Hz. It bears
emphasis that far less resolution as to the control over
the bandwidths is provided in the frequency averaging approach
~taught in U.S. Patent 3,790,720.
In combination with the band-pass characteristics
discussed below with respect to FIG. 4, and in combination
2 with the jitter detecting means, particular success has
been achieved with the count ranges being set in accordance
with th llowing tables.
. . ' .
' ' . , ' ' .
. - ~9
4ao24
LOW CHANNEL (uses 250 KHZ clock)
E~NTRY POINT EXIT POINT
l~ominal
Tone Decoded2 PQ~ DurationDecoded2 P~T Duration
FrequencyCount(microseconds)Count(microseconds)
697 Hz 698 2792 735 2940
770 Hz 630 2520 666 2664
852 Hz 568 2272 605 2420
941 Hz 516 2064 54 7. ~ 2188
.' . ' ' , ,'' , .','',' .~ .
- HIGH CHA~ EL (uses 500 KHZ clock)
ENT~Y POII~T . EXIT POINT
Nominal
ToneDecoded2 PQT Duration Decoded 2 PQT Duration
Frequency ~ Count (microseconds) Count (mic~oseconds)
1209 Hz 808 1616 844 1688
1336 Hz 732 1464 766 1532
1447 Hz . 661 1322 69C 1392
. . ' ' ' ' ' '
. . ,
. . - ' .
'' . ',
.
' . ' - '.
~ 25
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.
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: ~ ¦ As to the internal construc~ion of the entry point
¦ and exit point decoder 35 shown as a single block in FIG. 7,
, ¦ it comprises a plurality of parallel NAND gates feeding a
¦ multi-input AND gate which imp:lement a Boolean function
5 ¦ characterized by the Boolean equation: X = (Hil~ Til~ Uil)
¦ ~H 1 Tol~ U01) + --,(Hij Tij Ui~) , 0j ij ij)
, , I ( in in Uin) + (Hon' Ton~ Uon)- In this equation t X
. ¦ represents the output of the decoders 35, H, T, and U
. ¦ represent hundreds, tens, and units, and the subscript
lP ¦ represent the various entry and exit points.
. ¦ With reference again to FIG. 7, the quantizer 30 shown
.. . . therein produces not only the digital signal SAVE ds/Lo but
'. also a p,eriod-range identification signal ds/Lo. This
., signai is a parallel-by-bit signal comprising dsA/Lo and
dsB/Lo which are produced by the flip-flops 38 and 39
.
.. respectivelyO~ As stated above, these flip-flops together
~. . with the flip-flop 37 and the inverter 40 form a counting
; .. régister that counts or records the number of pulses defined
~ - ~in the signal InO during the 2-period quantizing time. In
: 20 the course of this counting, the period identification
~: . signal progresses throu~h a series of binary coded values
so as to identify the different count ranges through which
the counter 32 moves.
,
~. ~5 . . ' ' '' ' .
.. . ~ , ' .
' ` '30
'
,. . '','
. , , , ,.. , . . ' ' '
104-Z4
1 ¦ The following table gives the counting sequence for
the counting register in ~uan~izer 30.
. Signal Frequency
Corresponding to
. ¦ InO/Lo Pulses Signal Binary Values Period Identified
. 5 ~ dsB/Lo dsB/10 QrI/Lo
- . ¦ None O O O None
¦ First O 1 1 941 Hz
. ¦ Second O 1 0 None
¦ Third . 1 O.1 852 Hz
¦ Fourth . i O O . None
0 ¦ Fifth 1 1- 1 ?70 Hz
. . ¦ Sixth -1 1 0 . None
¦ Seventh O O 1 697 Hz
¦ Eighth O 00 . None
, .
15 - ~s to,quantizer 31 (FIG. 1) in the high channel, the
counting sequence for its counting register is given in the
. .
following table.
- Signal Prequency
:- Corresponding to
. InO/Hi Pulses Siqnal Binary Values Period Identified
:~ dsB/Hi dsA/Hi QrI/Hi
2Q 'None O O O None
. First O 1 1 1477 Hz
Second O 1 0 None
: Third 1 0 1 1336 Hz
Fourth . 1 0 O None
~- . 25 Fifth 1 1 1 1209 ~z
Sixth 1 1 0 . None
~' . .
., .
.,
' . ..
' . ,. . '.
.. ' . .. "' ~. . ' .,.
' ~ 10-30Z4
1 ¦ With reference again to FIG. 1, the low channel
¦ includes a jitter detector 43 and the high channel includes
a jitter detector 45. Each of these jitter detectors
¦ produc~ a gating control signal (Lo jitter free and Hi
5 ¦ jitter ~ree) which indicates whether or not jitter in
¦ excess of a predetermined jitter tolerance exists in the
¦ respective channel's filtered signal.
I A portion of the apparatus shown in FIG. 1 is shared
¦ between the channels. Thls shared portion includes control
¦ gates 47 which operate to provide inter~channel jitter
I detector control; shared gates 48; and interval timing '
¦ circuitry 49 is shown in FIG. 11. The shared circuitry
¦ shown in detai] in these figures constitutes the preferred
I arrangement of a gating signal controlled outputting means
15 ¦ for indicating the continuous, substantially jitter-free
- ¦ detection of a pair of the predetermine~ signal frequencies
for at least a predetermined interval of time.
In the preferred embodimentj this output indication is
given by the signal GOOD whose waveform for a representative
case is shown in FIG. 12c. As will be developed in more
detail bPlow, so long as a gating control signal produced
, ,-
in each channel (i.e., Lo Jitter free and Hi Jitter free)
switches from '0' to ll' and remains equal to '1' for at
~ least a predetermined interval of time (21 milliseconds in
-~ 25 the preferrecl embodiment~, then the signal GOOD will switch
from '0' to Sl' so as to indicate valid decodings.
; Consider now in more detail the preerred construction
and operation of the jitter detector 43. As indicated in
F~G. 9, the jitter detector 43 receives the following inputs:
SAVE dsfLo; ds A/Lo; ds ~/Lo; DO~'T FORGET; and KEEP JITTER
.'..
. , ' , ' `.
.23.
-.- .. . . . . ..
.
. ~
1O4Q~24
1 C~ECKING. As to the jitter detector 45 in the high
channel, it i5 identical in construction and receives the
~, corresponding input signals from corresponding portions of
the high channel.
As for the SAVE ds/Lo signal, it will be recalled that
this signal serves as a'command for a save register. As
shown in ~IG. 9 9 the save register comprises two D type
flip-flops 50 and 51. The D inputs of these two flip-
flops receive the ds A/Lo and ds B/Lo signals respectively.
As for these two signals, it will be recalled that in
combination they serve as a period identification signal
that progresses through a series of binary coded values.
: The DON'T FORGET signal is received from the control
gates 47 which are further described below. The waveform '
1 defined by this signal is very slmple and can be explained
; without the need for a separate illustration thereof in ~he
drawings. Briefly, it eguals '0' only when the result of a
2-period quantization of either channel indicates that
no valid signal freguency i5 present. At all other times,
it equals '1'. When equal to '0', it causes the save
register to be cleared or reset. While equal to '1', it
commands the save register not to forget the most recent
~' binary coded value loaded therein. This loading occurs
coi'ncident with the leading edge of each pulse occurring in
the SAVE ds/Lo signal. What is then loaded into the save
register is the then current binary coded value defined by
the period range identification signal.
' The remainder of the circuitry shown in FIG. 9
constitutes a comparator means which is operable to compare
.. .' ', ''.
,
. ' ''-' " ' ' '..
1~:10Z4
1 ¦ successive binary coded values loaded into the save
¦ register. When the c~mparison shows equality, the gating
¦ control signal JITTERFREE/Lo, produced by NOR gate 52,
¦ e~uals ~1'. If it shows inequality, JITTERFREE/Lo equals
S I 0-. ' ' ', . .
¦ The comparator means includes a pair of latch circuits
. ¦ 53 and 54, a pair of exclusive-OR gates 55 and 56, and the
. . ¦ NOR gate 52. In the preferred embodiment, these two latch
.- . ¦ circuits as well as the corresponding two latch circuits
. 10 ¦ in the high channel are contained in a single integrated
. . ¦ circuit. National Semiconductor Corporation, among others,
. - . ¦ sells this type of integrated circuit under the designation
.. . ¦ "quad latch" - SN7475.
.. . ¦ Both latch circuits 53 and 54 are controlled by the
15 ¦ signal KEEP JITTER CHECKING whose waveform for a representative
.. case is shown in FIG. 12d. While their signal equals '1',
- . it serves as a command for the latch circuits 53 and 54 to
: . copy the signals LVA/L~ and LV~/Lo provided by the save
register flip-flopsO When it switches to '0', the latch
circuits operate in the memory mode and continue to hold the
. binary values then being copied.
; Before describing in further detail the operation of
;. the jitter detector, a more detailed explanation of the
. construction of the circuitry shown in FIGS. 10 and 11 will
be given.
As shown in FIG. 10, the shared gates 47 comprise a pair
o~ parallel NOR gates 57 and 58 that feed an AND gate S9.
The DON'T FORGET signal is produced by ~he NOR gate 59.
. From an inspection of FIG. 10 it will be appreciated.that
. . , .
. 2~ .
'~ ' ' . '' ' " ' ,~
lO:~Z4
1 ¦ this signal equals '0' whenever either both E2PM~Lo and
¦ QrO/Lo equal '1' or both E2PM/Hi and QrO/Hi equal '1'.
¦ In other words, whenever either o~ the time-range quantizers
¦ at the end o~ a 2-period quantizatiGn, indicates that the
5 ¦ quantizer counter is out of a valid count range, the DON'T
¦ FORGET signal defines a negative-going pulse. Otherwise,
¦ the DON'T FORGET signal remains equal to '1'.
¦ Also as shown in FIG. 10, the shared gates 48 comprise
¦ an AND gate 60 and a NAND gate 61 which produces a
10 ¦ MISCOMæARE signal. From an inspection of FIG. 10 it will
: ¦ be appreciated that the MISCOMPARE signal equals '1'
¦ whenever any one of the JITTER FREE/Lo, JITTER FREE/Hi, or
¦ DON'T FORGET siynals equals '0'. In other words, the
~ISCOMPARE signal equals '1' whenever there is excess jitter
detected in either of the channels or whenever a non-valid
` signal period quantization occurs.
-With reference now to FIG. 11, the interval timing
circuitry 4~ includes first and second timer 62 and 63,
and a pair of D type flip-flops 64 and 65. In the preferred
embodiment, both timers are contained in a single integrated
circuit package of the type designated SN74123 by National
Semiconductor Corporation. lThe external R-C circuits for
the timers are not shown.
Consider now an overall operation in which a pair o~
valid tone bursts arrive. The band-pass filters separate
; the ~wo, and the resulting pair of filtered si~nals are
each limited by the limiters 14 and 18. In response to
the filtered signals, the boundaries detectors 16 and 20
sequentially produce the control pulses 2PQT~Lo and 2PQT/Hi
- 30 in substantial synchronism with the filtered signals.
.-, .
, ' " ' ' ' "
;
. ~3436~Z4
Under the control of these control pulses, the time- -
range quantizers 30 and 31 produce the digital signals
SAVE ds/Lo and SAVE ds/Hi. With the pair of valid tone
bursts being present in the input waveform, these digital
S signals will substantially synchronize to the filtered
¦ signals and define pulses indicating that the filtered
signals for the low and high channels each have a period
corresponding to one of the valid signal frequencies. As
a result o~ initial transients, this will not occur
immediateiy, and until it does so, the controi gates 47
will control the MISCOMPARE signal to define one or more
ti~e spaced-apart pulses.
; In the waveform diagrams of FIG. 12, the last of these
initial-transient pulses in the MISCOMPARE signal commences
at time To. At this time, the KEEP JITT3R CHECKING SIGNAL,
produced by the Q output of flip-flop 64 (FIG. 11) equals
!l' as indicated in FIG. 12d. Accordingly, the latch
circuits 53 and 54 (FIG. 9~ are commanded to copy the save
register. -
A~ter the initial transients die down, and commencingat time Tl, the time spaced-apart SAVE ds pulses are
provided. Also, the DON'T FORGET signal equals '1' because
the resettable counters will not be outside a valid count
range when they are repeatedly reset at the end of their
2 respective 2-period quantizing times. Under these conditions,
the SAVE ds pulses result in the save registers, in the
jitter detectors being loaded with the binary coded values
pro~ided by the counting registers in the ~uantizers.
So long as the successively loaded binary coded values
3 remain the ~ame, the comparators in the jitter detectors will
.,
..., , ,, '.
2~
. ' ' . ' ' ,'.~.
104~
1 ¦ indicate this. That is, the JITTER FREE signal for each
¦ channel equals '1'.
¦ At time To, the leading edye of the MISCOMPARE pulse
; ¦ triggers the timer 62. In response, its Q output switches
5 ¦ from '1' to '0' This is depicted in FIG. 12a, the waveform
¦ for the GOOD TRIGGER signal which is the signal produced
¦ by this Q output. In the preferred emhodiment, the timer 62
¦ is a re-triggerable timer that times out at least 21 milli-
I seconds (msO~ interval. Tha~ is, if it is not re-triggered
durin~ this 21 ms. interval it will return to its stable
state. If re-trigyered earlier than that, it will remain in
its unstable state. In short, once triggered, it will
remain in its unstable state until there elapses a 21 ms.
interval during which no miscomparisons are indicated.
At time Tl (i.e., 21 ms. after time To), the GOOD
TRIGGER signal switches to '1'. At this time, an INT?
si~nal (FIG. 12e) equals '1'. Consequently, the flip-
; flop 64 is free to respond to the positi~e-going transition
in the GOOD T~RIGGER signal~ In response, it changes state,
and the GOOD signal switches to '1' and the complementary
signal, ~EEP JITTER CHECKING, switches to '0'. This places
the latch circuits 53 and 54 (FIG. 9~ in their memory mode.
In short, they are fro2en at this point and continue to
store the then prevailing binary coded value being copied.
2 In the representative case now being explained, the
next event of interest occurs at time T2~ At ~his point,
a brief interruption commences. That is, as a result of
some noise phenomena, a miscomparison occurs. It is of
course important that this not be mistaken for the end of
~ , . ' . ' , .
~ 2~
, " , '' ' " '. ...
:. I 104:10Z~4
¦ a tone burst pair, otherwise a single tone burst pair
¦ would result in a double outpulsing. The manner ln which
¦ this is precluded from happening will not be explained.
¦ At time T2, the GOOD signaL equals '1'. Thus, the
: 5 ¦ timer 63 is free to be triggered by the leading edge of
¦ the interruption pulse definea in the MISCOMPARE signal.
¦ By virtue of the provision of a feedback path from its Q
¦ output, the timer 63 is arranged to operate as a non-re-
~- - triggerable timer. The timing interval it defines lasts
35 ms.in the preferred e~bodiment. In resonse to the
above-mentioned leading edge, the timer 63 changes to its
unstable state and its output signal, INT? TRIGGER, switches
to '0'. .; `
At time T3 (less than 35 ms. aft~r time T2), the
interruption pulse defined in the MISCOMPARE signal ends.
At time T4 (35 ms. after time T2), the timer 63 returns to
its stable state and the- INT? TRIGGER signal switches back
to '1'. At time T3, the GOOD signal still equals '1'. Thus
the flip-flop 65 (FIG. 11) is free to respond to the
- ~0 positive-going edge of the INT? TRIGGER signal. Inasmuch
as the MISCOMPARE -signal now equals '0', the 1ip-flop 65
: does not change state at this time. Thus, its output, INT?
(FIG. 12f), continues to equal '1'.
The next event of interest occurs at time T5. This
marks the point at which the tone buxst pair actually ends.
Again the MISCOMPARE signal switches to '1'. This time,
however, it remains equal to '1' for the follo~ing reason.
It will be recalled that the latches 53 and 54 (FIG. 9) were
frozen at time ~1 And of course the corresponding latches
.- . ~ .q ' .
.' ' ' ' ' ~.
iL~) 4 3~
in the high channel were also frozen at that time. Inasmuch
as the tone pair burst has now ~ended, both save registers
are cleared by virtue of the DON ' T FORGET signal equaling
'O'. Consequently, there will be a difference between the
binary coded values that are frozen in the latches and the
binary coded values presented thereto by the save registers.
The exclusive OR gates will detect this difference and
through the JITTER FREE signals cause the MISCOMPARE signal
to remain equal to '1'.
10Thus, when at T6 (35 ms. after T5) the INT? TRIGGER
signal a~ain triggers the flip-flop 65 (FIG. 11?, the INT?
signal switches to '0'. This in turn clears the flip-flop
64 and after a slight propagation delay, the GOOD signal
switches to '0'. This in turn clears the flip-flop 65
and the INT? signal returns to 'O'. In short, the INT?
TRIGGER signal provides for the flip-flop 65 to sample
- whether or not after`35;ms. ~herei:is still a miscomparison.
If there is, this is too long a time to be simply a noise
interruption-and instead represents an end of a ~alid tone
2 pair.
With reference now to FIGS. 2 and 3, consider further
the preferred arrangement of the band-pass filters. As shown
in FIG. 2, the input waveform is carried by RING and TIP
~ines and is amplified by a buffer amplifier 70. The
2 output of the amplifier 70 is appli~d to both the low
channel and high channel band-pass filters. Each of these
preferably comprises three states of active filters.
To ensure linear operation of the active filters, the
buffer amplifiex in the preferred embodiment has a gain of
3 -20 db.
., . ,.
3~
. , ' . ' ',.
'' 104302~ '
1 ¦ Of the six active filters, four have the configuration
. . ¦ shown in FIG. 3a and the other two have the configuration
: . ¦ shown in FIG. 3b.
. ¦ With reference to FIG. 3a, the T-network comprising
. . ¦ impedances Zl, Z2, and Z3 is connected between the input
¦ to the active filter stage and the non-inverting input
¦ terminal of an operationa? amplifier 73. Gain stability
¦ is provided by the negative feedback network comprising
¦ impedances Z4, ZS, and Z6. The other T-network comprising
10 ¦ impedances Z7, Z8, znd Z9 has its center leg (Z9) connected
. ¦ to the stage output and thus provides some positive feedback,
- ¦ thereby increasing the overall gain to some extent over a
. . . ¦ selected frequency range.
In the preferred embodiment, the components used for
the impedances Zl through Z10 are as follows.
. - . . FIRST STAGE ACTIVE FILTER
.. Impedance Impedance Low Channel (71-1) High Channel (71-2. Reference llo. Type . Value Value
: Zl ~ Resistor261K lSOK
Z~ Resistor261K 150K
~ . Z3 . Capacitor 2200 pf 2200 pf
: ~4 Resistor193K 193K
Z5 ResistorlOOK lOOK
. Z6 ResistorllOK 36K
Z7 Capacitor 1100 pf 1100 pf
: Z8 Capacitor -1100 pf 1100 pf
Z9 Resistor130.SK 75K
Z10 Resistor267K 154K
~ '. . ' , . ' '~
~ ~ .
. 3~ .
.~ 104aOZ4
. ¦ SECOND 5TAGE ACTIVE FILTER
. Low High
. I Impedance Impedance Channel (71-3.) Channel (71-4.)
¦ Reference No. Type Value Value
¦ Zl Capacitor 1100 pf 1100 pf
5 ¦ Z2 Capacitor 1100 pf 1100 pf
. ¦ Z3 Resistor fi0.5K 34.9K
¦ Z4 Resistor 193K 193K
¦ Z5 Resistor 100K 100K
¦ Z6 Resistor 0~L . O ~
¦ Z7 Resistor 121K 69.8K
¦ Z8 . Resistor 121K 69.8K
Z9 Capacitor 2200 pf . 2200 pf
. Z10 Capacitor 1100 pf 1100 pf
, . :', ' ", . . .
With the foregoing values, these four active filters
. hav~ the following transfer ~unctions: . . .
.. 2 93 ~S2 ~ 1.20(107)]
1. Stage 71-1 52 $ 380 s ~ 3-56(10
2 93 152 + 3.60(107)~
. 2~ stage 71-2 ~ s2 + 660 s + 1-07(lO )
20
3. Staga 71-3 _ 0-977 [s ~ 5 60(107)j
. s2 + Z77 s ~ 1.88(10 )
2 ~ ~80 s ~ 5.67(10 )
With reference to FIG. 3b, the components used in the
preferred embodiment have the following values.
'.'
. . ' 3~~ .
1 104~0Z4
1 I Impedance Low Channel (7.2-1)High Channel(72-2)
. ¦ Reference No. ~ Value Value
; . ¦ 75 1.58K . 1.58K
76 ~ lOOJ~ lOOJ~
¦ 77 14.0X 16.2K
78 14.0X 16.2K
.79 . . 2200 pf ' 1100 pf
~.lSM 1.33M
. 81 ~ 2200 pf - llOG pf .
0 With the foregoing values, these two active ilters
have the following transfer functions:
.. " . . ' '
. 1. Stage 72-1 -0.59 s (791)
. ~ s2 + 791 s + 2.59tlO )
0.59 s (1374)
2. Stage 72-2 -2 - 7
s + 1374 s + 7.79(10 )
. FIGS. 4a and 4b show the overall input-to-output
characteristics of:the.band pass filters. Advantageous
features thereof are that the gain ripple in the pass band
20 provides peaking of multi frequency signal components and
. ~ . .
very ste skirts are provided.
~; .
~:', ' . ' "
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