Note: Descriptions are shown in the official language in which they were submitted.
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The invention relates to a circuit arrangement Eor the frequenc~
division of high-frequency pulscs, comprising a first pair of transistors
which are alternately driven into conduction by the pulses, whose output
currents are each passed through a group of at least two transistors.
Such a circuit arrangement is known from Netherlands Patent
Application No. 7,000,815, which was laid open for public inspection on . -
July 23, 1970. In this known circuit arrangement a second transistor of the
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opposite conductivity type is added to each of the transistors of said
groupsJ together forming a b7stable trigger. From each bistable trigger a
coupling circuit leads in a cyclically shifted sequence to another bistable
trigger which belongs to another group for presetting said other bistable
trigger in dependence on the energizing state of the one bistable trigger.
Said known circuit arrangement operates satisfactorily up to ~ -
frequencies of 600 Megahertz. For still higher frequencies, for example 1
Gigahertz the use of additional transistors is not or hardly possible owing
to the low efficiency of very high frequency transistors. The number of
transistors should therefore be minimized for this purpose.
According to the invention, there is provided a circuit arrange-
ment for frequency division of high-frequency pulses applied thereto,
comprising: first and second equal sized groups of n transistors where n
is an integer greater than one, a cyclic electrical sequence being deined
for said,transistors, said sequence alternating between said groups so that
each of said transistors is followed in said sequence by a transistor of
the other group, each of said transistors having a collector, base and
emitter; electrical resistances connecting the collectors of adjacent -
transistors in said sequence as a closed loop~ each of said electrical
resistances having a tapping electrically connected to the base of the
n-lth transistor preceeding in said sequence the pair of transistors be-
tween the collectors of which said tapping is disposed; and first and second
driver transistors which are alternately driven into conduction by said
pulses, the output from said first driver transistor being electrically
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connecte~ to cacll of thc emitters o~ the transistors o~ said irst group,
the output from said second dr3ver transistor hcing electrically conTIccted
to each of the emitters of the transistors of said second group.
In the circuit arrangement according to the invention no additional
transistors are used and therefore a much larger bandwidth is obtained.
Measurements conducted on a first experimental embodiment of a circuit
arrangement according to the invention revealed a satisfactory behaviour of
the circuit arrangement at frequencies up to 1.3 G~lz.
Apart from the minimum number of transistors required, the circuit
arrangement according to the invention exclusively comprises the said
resistors. Therefore, it is advantageous to provide a preferred embodiment
of the invention, executed in integrated circuit technology, with a semi-
conductor element in which the various transistors take the form of junction
transistors, in which an island of a first conductivity type, which island
functions as the common collector of at least the transistors of said groups,
at least four mutually isolated base zones are formed of a second opposite
conductivity type, geometrically arranged in a sequence which corresponds
to said cyclic sequence, the base zon0 of each of the transistors of one
group o~ said first and second groups being followed in said geometrically
arranged sequence by the base zone of a transistor of the other of said first
and second groups, in which base zones emitter zones of the first conductivity
type are formed conductor tracks connecting the emitter zones of the transis-
tors belonging to one group to each other and to the collector of the associ-
ated transistor of the transistors which are alternately driven into conduc-
tion, terminals on the base zones of the transistors of said groups being
connected in a cyclically shifted sequence via conductor tracks to terminals
on said island between each time two adjacent other base zones, from which ~-
terminals the desired resis~ors lead to the collector-base depletion layer
of the associated transistors, and a power-supply terminal contact
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is disposed on said island~ ~rom which desired resistors lead to the base-
collector depletion layers of the transistors of said growps.
Said integrated circuit according to the invention is based vn
the recognition that the eircuit arrangement according to the invention
leads to a required resistor configuration which can be realized in a
common colleetor se~iconduetor layer by utilizing the internal resistanee
of sueh a semieonductor layer, so that a very eompaet eonstruetion of the
integrated eireuit is possible
In the eolleetor semieonductor layer, whieh also constitutes the
1~ resistor configuration~ the frequency divided signal,pro;p~g~s, as it were -
as a travelling wave. It is inter alia this travelling-wave coneept whieh
explains the extremely satisfaetory behaviour at very high frequeneies.
In an integrated circuit aceording to the invention it is advan-
tageous that a highly-doped buried layer is formed in said island. ~-
In an integrated eireuit aeeording to the invention it is
furthermore of advantage that in said island underneath said eonnection
points zones are provided of the same eonduetivity type as the eondue-
tivity type of said emitter ~ones
The first further ~tep has the advantage that said divided
resistors are eonstituted by the internal resistanee of the buried layer~
whilst the seeond step has the advantage that the location of the connec-
tion points relative to the emitter zones is constant because the two
ean be realized in one diffusion step with one mask. ~ ;
An integrated circuit aeeording to the invention employing
integration teehnology, oxide layers being provided to isolate various
elements~ is charaeteri~ed in that an o~ide layer surrounds said island.
The invention will be deseribed in more detail with referenee
to the drawing.
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Figure I shows tho circuit di.l~r~m of the circuit arrangcmcnt
contained in ~he integr~ted circu:it accordin~ to the invention~
Figure 2 shows thc plan view of an embodiment of an integrated
circuit according to the invention.
Figure 3, appearing on the same sheet as Eigure 1~ shows a
cross-section of the integrated circuit of Figure 2 at the line III-III.
Figure 1 shows a circuit arrangement according to the invention.
The circuit arrangement comprises a first~ second, third~ and fourth
transistor~ designated T1, T2, T3 and T4 respectively. The collectors-
of these transistors are connected to a power supply terminal 3 via the
resistors R 1~ R 2~ R 3~ and Rc4 respectively. The emitters of the trans-
istors T2 and T4 are jointly connected to the collector of an input
transistor T5, whilst the emltters of the transistors T1 and T3 are jointly
connected to ~he collector of an input transistor T6. The emitters of the
input transistors T5 and T6 are jointly connected to a power-supply ter-
minal 3' via a ourrent source I~ and the base electrodes to the input
terminal 1 and 1' respectively.
The transistors T1 and T3 are connected as a bistable trigger
in that the collector of transistor T1 is connected to the base of
transistor T3 via the resistor R1 and the collector of transistor T3 to
the base of transistor Tl via the resistor R3 . Similarly~ the transistors ;~
T2 and T4 are connected as a bistable trigger in that the collector of
transistor T2 is connected to the base of transistor T4 via the resistor
R2 ~ and the collector of transistor T4 to the base of transistor T2 via
the resistor R4 . The collector of transistor T1 is connected to the base
of transistor T4 via the resistor Rl~g the collector of transistor T2 to
the hase of transistor Tl via the resistor R2b~ the collector of transistor
T3 to the base of transistor T2 via the resistor R3b, and the collector of
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transistor T4 to the base o:~ transi.stor T3 ~1a the rosi.stor 1~4b.
In order to obtain an owtput si~naL tho connectiorl ~o:int betwoen
the resistors R1b and R2 in the embodiment shown is connected to an outpwt
terminàl 2 and the connection point between the resistors R3b and R4a to an
output terminal 2'.
To explain the operation of the circuit arrangement o~ Fi~ure 1
it is assl~ed that the input signal is such that the base of transi.stor T6
has a higher potential than the base of transistor T5. The current from
the current source I will then flow entirely through the collector-emitter
path of transistor T6 provided that the potential at the base of trans-
istor T6 is sufficiently high relative to the potential at the base of the -:
transistor T5. This current then flows in the common emitter circuit of
therltransistors T1 and T3. These two transistors are connected as a bistable
tri.gger, so that only one of the two transistors can conduct. ~hen it is
assumed that transistor T1 is conductive~ the other three transistors T2,
T3, and T4 will not conduct and the potential at the collector of trans- :~
istor T1 will be low relative to the potential of the collectors of the
other three transistors. Owing to the coupling resistors the potential at ~:
the bases of the transistors T3 and T4 is then low relati~e to the poten-
tial at the bases of the transistors T1 and T2, so that transistor T
which together with transistor T1 constitutes a bistable trigger~ remains
reverse biassed and the potential at the base of transistor T2, which
together with transistor T4 constitutes a bistable trigger, is high rela-
tive to the potential at the base of transistor T4. At the instant that
the input transistor T5 is biassed in the forward direction by the input .:
signal, transistor T2 will consequently have preference over transistor T4,
so that transistor T2 becomes conductive and via the resistor R2 keeps
transistor T4 reverse biassed. Via the resistor R2b the potential at the
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base of transistor Tl is kept low re~lative to the po~cntial at thc base ot
transistor T3, so that at the instant that input translskor r6 bogins to
conduct the current from the current source~ transistor T3 becomes con- -
ductive. Similarly, at the instant that input transistor T5 becomes con-
ductive~ transistor T4 will ~ake over the current from transistor T3.
In the manner described above~ the current from the current source
I is transferred to a subsequent transistor upon each zero passage of the
input signal. A full cycle has been completed after two cycles of the
input signal, so that frequency division is obtained.
For illustration Figure 2 shows a schematically represented struc-
ture in a semiconductor body of the circuit arrangement of Figure 1. The
driver stage consisting of the input transistors T5 and T6 is not shown
in integrated form because various solutions are possible for this. The
input transistors T5 and T6 will generally be included in an integra~ed
circuit together with other circuits, which integrated circuit, also in-
corporates the, isolated, semiconductor island in which the four transjstors
and the resistor network is accommodated.
In such a semiconductor island 4 of a first conductivity type,
for example the n-type~ four base zones b1~ b2~ b3 and b4 of a second con~
ductivity type, for example the p-type are formed by diffusion. In these
base ~onesg in t-heir turn, emitter zones e1, e2, e3 and e4 are formed of
the first conductivity type~ for example the n -type. Thus~ the four trans~
istors T1, T~, T3~ and T4 are formed~ of which transistors the collectors ~ ;
areconstitutedby the semiconductor island 4, the bases of the base zones
b1, b2, b3 and b4 respectively and the emitters by the emitter ~ones el,
e2, e3 and e4~respectively. Centrally among the four transistors a power
supply terminal 9 is arranged on the semiconductor island 4~ from which a
conductor track leads to the terminal 3. Between the base ~ones of the
transistors T1, T2, T3 and T4 and T~ terminals 5, 6~ 7 and 8 are arranged
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in a cycLically shifted sequence~ for examplc tho tcrminal 5 bctween tho
base zones of the transistor Tl and T2. FIom these terminals 5~ 6~ 7 an~ -
8 conductor tracks lead to the bases of each time a transistor other than
an adjacent transistor in a cyclically shifted sequence, for example from
the terminal 5 to the base zone b3. Owing to the internal resistance of
the semiconductor material from which the collector semiconductor layer 4
is made the variousresisitorsRc~ c4~ Rla R4a lb 4b
relevan~ base-collector depletion layers. These resistors are shown dashed
in Figure 20
A conductor track connects the emitter zones e2 and e4 to the
collector of input transistor T5, and similarly a conductor track connects
the emitter zones el and e3 to the collector of input transistor T6. These
input transistors T5, and T6 which may for example also be of the insulated
gate type~ are located outside the semiconductor island 4. This semi-
conductor island 4 will therefore be surrounded by an isolation diffusion.
It is also very favourable to use an in~egration technique in which the
isolation layer is obtained by local oxidation of the silicon.
The terminals 5~ 6~7J8 and 9 may be formed directly on the
semiconductor island 4, but also on diffusions formed on the island, which
diffusions are of the same material as the emitter diffusions el, e2a e3 and
e4, for example an n+ diffusion in the case of an n-type semiconductor
island 4. This has the advantage that this can be effected simultaneously
with the emitter diffusions. As a result, the location of the terminals
5-9 is defined relative to the location of the emitter diffusions, which
is advantageous because in the case of high frequency transis~ors the
transistor action mainly takes place directly underneath the emitter zone,
so that the various resistors are not or hardly changed upon a displace-
ment of the relevant diffusion mask~
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~ s the intcrnaL resistance of ~hc semiconductor rnaterial from
which the colLector layer 4 i~ made i~ GeneralLy comparativoly hi~h~ a
buried layer 12 of the sL~mc conductivity type bwt rnorc heavi~y doped than
the semiconductor material of the island 4, is used underneath the base
7ones b1-b4. The various resistors are then mainly located in said buried
layer l2.
In addition to the structure of the integrated circuit according
to the invention shown in Figure 2, various other structures are possible,
for example a structure in which the transistors T1-T4 are disposed in
line, whilst the two ends of the island 4 which is then oblong, must then ~ -
be connected by a semiconductor track in order to obtain a cyclic circuit
arrangement.
Figure 3 shows a cross~section of the integrated circuit of Fig-
ure 2 at the line III-III.
On a substrate 10, which may be in common with the substrate
of further integrated circuits and which is of the second conductivity type,
for example p-type, the semiconductor island 4 is formed~ isolated from
further integrat~d circuits by isolation regions 11J for ex~mple p~ iso-
lation diffusions. In this island a buried layer 12 of the heavily doped
first conductivity type~ for example n , is formed. Furthermore, Figure 2
shows the base diffusions b3 and b4 and the emitter diffusions e3 and e4,
which are visible in this sectional view. The terminal 7 is formed by
diffusion together with the emitter diffusions, for exa~ple an n+ diffu-
sion. On this structure an isolation layer 13 is superimposed on which
various conductor tracks 14 are arranged, openings being formed in said
isolation layer 13 at various locations, so as to enable contacts with the
the underlaying active regions~ The resistors R3b and R4 are constituted
by the resistances of the connection paths from the terminal 7 via the
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buried layer 12 to the base-co:LIector ,jurlctions assoc:iated w:ith the base-
diffusions b3 and b~ respectively.
It wi]l be evident that the invention is not limlted to the
structure shown. Many solutions are possible, whilst in respect of the
transistors T5 and T6 it is also possible to use transistor types other
than those shown.
Although the circuit arrangements shown are limited to groups
of two transistors each~ it will be obvious that in a similar way trans-
istors may be added to each group as required. If each group comprises
n transistors~ the circuit arrangement divides the frequency o~ the pu~Lses
by nO
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