Note: Descriptions are shown in the official language in which they were submitted.
~l~5~S~
BACKGROUND OF T~-IE INVENTION
1. Field of the invention
The present invention relates to analog arithmetic circuits.
More specifically, the present invention is directed to arithmetic
circuits on analog input signals to produce an analog output
signal having a predetermined relationship to the combined effect
of a plurality of analog input signals applied to the arithmetic
circuit.
2. Description of the Prior Art ; ~
Examples o-E prior art analog arithmetic circuits may be ~ I
found in U.S. Patent Nos. 2,998,186; 3,016,197; 3,302,807;
3,383,501; 3,634,671 and 3,686,513. Prior art arithmetic cir- ;
cuits of the type shown in the aforesaid examples usually have
had the disadvantage of being limited in one or more aspects
j of their overall operation. Specifically, the prior art
arithmetic circuits have either been limited as to their utility
in performing varied arithmetic operations by being restricted
to a minimum number of arithmetic functions or they have not been
` suitable for use in an electrical signal isolation operating
mode. Further, they have usually employed a precision constant
frequency oscillator for providing a basic signal to be modified
in accordance with input signals to the arithmetic circuits and,
hence, have been dependent on the accuracy of the constant
frequency generator.
SUMMARY OF THE INVENTION~
Accordingly, it is an object of the present invention to ~
provide an improved arithmetic circuit for providing a plurali~y -
of arithmetic operations.
~nother object of the present invention is to provide an
improved arithmetic circuit suitable for use with electrical
isolating elements for providing conductive isolation between
an output of the arithmetic circuit and an input thereof.
--2--
~C~5~
In accomplishing these and other objects, there has been provided,
in accordance with the present invention, an analog signal ar:ithmetic circuit
having a modulating circuit for modulating a first input signal to provide
a variable duty cycle output signal in accordance with the amplitude of a
second input signal to the modulating circuit. The variable duty output
signal is applied to a demodulator circuit to control the modulation of a
third input signal to the ari~hmetic circuit to provide an output signal
having 2namplitude corresponding to the predetermined effect of the three
input signals to the arithmetic circuit. ~ ~
According to the broadest aspect of the invention there is provided -
a signal modulating circuit comprising a signal comparator means having a ;
first input and a second input and arranged to produce an output signal
representative of the difference between input signals applied to the first ;~
and second inputs; a source of a constant reference signal; signal storage
means connected to the second input of said signal comparator means; first
circuit means arranged to apply an input signal applied to said signal
modulating circuit to said first input of said comparator means; first switch
means for selectivel~ connecting an output signal from said constant reference
signal source to said signal storage means; second circuit means arranged to
apply said output signal from said first switch means to said first input of
said comparator means concurrently with said n~nput signal; second switch
means for selectivel~ discharging said storage means; and switch control
means responsive to an output signal from said comparator means for closing
said first switch means in response to a first state of an output signal
from said comparator means while opening said second switch means and for
closing said second switch means in response to a second s~ate of said output
signal of said comparator while opening said first switch means, said first ;~
and second switch means being alternatel~ operated thereby.
~3~
r~
~(~5~15
BRIEF DESCRlPTION OF THE DRAWINGS
A better understanding of the present invention may be had when
the following detailed description is read in connection with the accompan~-
ing drawings, in which:
Figure 1 is a schematic illustration of an arithmetic circuit
embodying the present invention,
Figure 2 is a schematic illustration of a modification of the
circuit shown in Figure 1 and also embodying the present invention, and
Figure 3 is a further modification of the circuits shown in
Figures 1 and 2 and also embodying the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENT ~ ;
DETAILED DESCRIPTION
Referring to Figure 1 in more detail, there is shown an arithmetic
circuit embodying the present invention. A pair of input terminals 2 are
arranged to be connected to a source of an input signal Ein. The input
terminals 2 are connected through an input resistor 4 to the inverting, or
negative, input of signal comparator amplifier 6. The non-inverting, or
positive, input of the comparator amplifier 6 is connected through a
capacitor 8 to a common, or ground, terminal and through a pair of serially
connected feedback resistors 10 and 12 to the inverting input terminal of the
amplifier 6. The amplifier 6 is arranged to
~, _3a-
:, , . . . ~ ,
compare the applied input signals and to operate an output switch
by means Or a relay coil (not shown) energized by an output signal
from the arllpllfier ~ and mec~anically connected to the movable
armature 14 of a sin~le-pole, double throw switch 16. The switches
silown in Figure 1 are shown as mechanical switches for the purpose
of explaining the operation of the circuit. A first stationary
contact 18 of the switch 16 is connected to the positive side
of a constant voltage source shown as a battery 20 while the
negative side of the battery 20 is connected to the ground terminal.
A second stationary contact 22 of the switch 16 is connected to the
ground terminal. The armature 14 of the switch 16 is electrically
connected to the connection between the aforesaid pair of serially
connected feedback resistors 10 and 12. This intermediate
connection point is also connected to the base of an output tran-
15 sistor 24 having its emitter connected through an emitter resistor ~, -
; 26 to the ground terminal and its collector connected through a
:Light emitting diode 28 to a source of energizing potential ~b~
, The light emitted from the light emitting diode 28 is arranged
to affect a photo-diode 30 to produce a change in the resistance
of the photo-diode 30. The light emltting dlode 28 and the photo-
diode 30 are arranged to be enclosed ln ~e light-tight receptacle
32 to form an opto-electric isolator element. One end of the
photo-diode 30 is connected to a source of energizing potential
+Vbb while the other end of the photo-diode 30 is connected to
the ground terminal through a resistor 34 and to a non-inverting ''
input of second amplifier 36. A pair of resistors 38 and 40
are serially connected between the source of potential +Vbb and
the ground terminal while the connection,between the resistors 38
and 40 is connected to the inverting input terminal of the
amplifier 36. The amplifier 36 is arranged to actuate an output
switch by means of a relay coil (not shown) energized by an output ~ ,~
signal from the amplifier 36 and connected to a movable armature
42 of a single-pole, double-throw switch 44.
4 ~
A first stationary con~act 46 of the switch 44 is connected
to the negative terminal Or a second constant voltage source shown
as a second ba'ctery 48 having an output potential equal to the
output potential Or the first battery 20. The positive terminal
of battery 48 is connected to the potential source ~Vbb while a
second statlonary terminal 50 of the switch 44 is also connected
to the energizing source ~Vbb. The movable armature 42 of the switch
44 is electrically connected through a resistor 52 to one of a pair
of output terminals 54 having an output voltage Eout appearing
thereacross. The other one of ~he pair of output terminals 54 is
connected to the potential source ~V while a capacltor 56 is
connected across the pair of outputterminals 54.
In Figure 2, there is s~lown a modification of the circuitry
of the arithmetic circuit shown in Figure 1 while also embodying
the present invention. Specifically, the single-pole, double-throw
switches 16 and 44 shown in Figure 1 are replaced in ~igure 2 by
electronic equivalents employing field effect transistors (FET's)
which perform the switching functions of the relay switches shown
in Figure 1. Also, the batteries 20 and 48 have been replaced by
electronic circuitry (constant voltage units) providing constant
voltage output si~nals. The remaining modifications to the cir-
cuitry ~rom that shown in Figure 1 are necessitated by the aforesaid
basic changes in the circuitry of Figure 1. Slmilar reference
numbers have been utilized in Figure 2 to indicate circuit elements
common to both Figures 1 and 2. Thus, a pair of input terminals 2
are connected through an input resistor 4 to the inverting input
of the first amplifier 6. The non-inverting input of the first
amplifier 6 ~s connected through a serial combination of a resistor
7 and a capacitor 8 to a ground terminal and through a feedback
3 capacitor 9 to an output circuit of the amplifier 6. The connection
between the resistor 7 and the capacitor 8 is connected through
a series combination of a resistor 10 and resistor 12 to the
inverting input of the amplifier 6. The connection between the
~::.`- ' ." ' '"' ~' ~ ' '
~ )5~5~.~
reslstors 10 and 12 is connected to a first input terrnlnal of each
Or a pair o~ ~T's 13 an~ 15. It should be noted that in the
following discussion, the switch, or current flow, terminals of the
F~T's are referred to as first and second input terminals while ln
actual use, of course, one termlnal would be a ~raln and the other
a source.
A second input terminal of the first FET 13 is connected to a
first ground terminal while a second input terminal of the second
FET 15 is connected to a constant voltage source 17 using a Zener
diode for providing a constant voltage reference signal. The output
circuit of the first amplifier 6 is also connected to the control
electrode of the first FET 13 and, through a signal inverter cir-
cuit 19, to the control electrode of the second FET 15. A source of
potential +Vcc is connected through a resistor 21 to the output cir-
cuit of the amplifier 6 to provide a bias signal for applicationto the control electrode of the first FET 13 and to the signal
inverter circuit 19. The connection between the resistors 10 and
12 is also connected to the base electrode of an output transistor
24. The transistor 24 has its emitter electrode connected through
~ a resistor 26 to the first ground terminal. The collector electrode
of the transistor 24 is connected through a light emitting diode 28
to the source of energizing potential tVcc. The light emitting diode
28 is associated with a photo-diode 30 within a light~tight enclo-
sure 32 as previously described. One side of a photo-diode 30 is
connected to the source of energizing potential ~Vbb while the
other side of the photo-diode 30 is connected through a resistor
34 and a diode 39 to the ground terminal and directly to the non-
s~ l~ 3 b ~
inverting input of a second amplifier ~6~. The inverting input
of the amplifier ~3~ is connected to the junction between a pair
3 of serially connected resistors 38 and 40 with the series combina-
tion of the resistors 38 and 40 being connected between the source
of potential +Vbb and a second ground terminal through a diode 39.
t~
An output circuit of ~or amplifier 36 is connected through a
resistor 41 to the second ground terminal and through a feedback
--6--
.. _ _ ,, _, , _ _ . _, . ... .... .. . . .
'~ "' ' ' '`'
~ ~ '
~.~3~sj5~
capacitor Ll3 to the non-inverting input of the amplifier 36.
The output of the amplifier 36 is, also, connected to the input
of a signal inverter circuit 45 and to the control electrode of
a third FET 47. The output of the inverter circuit 45 is
connected to the control electrode of a fourth FET 49 while a
first input electrode of both of the F~T's 47 and 49 is connected
through an output resistor 52 to one of a pair of output terminals
54 having the output signal Eout appearing thereacross. The
~ other one of the output termina~ 54 is connected to the source
of energizing potential +Vbb while a capacitor 56 is connected
across the output terminals 54.
A-second lnput terminal of the fourth FET 49 is connected to
the potential source +Vbb while the second input of the third FET
47 is connected to the output of a constant voltage source 58 using
a Zener diode fcr providing a cons~ant voltage reference signal.
The circuitry shown in Flgure 3 is another modification of the ~-
arithmetic circuit shown in Figure 1 wherein the light emitting
- diode and the photo-diode have been omitted along with their ~ -
associated circuitry. Here again similar reference numbers have
been used for circuit elements common to Figures l and 3. Thus, a
pair of input terminals 2 are provided, one of which is connected
through an input resistor 4 to the inverting input of a first
amplifier 6. The non-inverting input of the first amplifier 6 is
connected through a serial combination of a resistor 7 and a
capacitor 8 to a ground termlnal and through a feedback capacitor
9 to an output circuit of the amplifier 6. The connection between
the series combination of the resistor 7 and the capacitor 8 is
connected through a series combination of a resistor lO and a
resistor 12 to the inverting input of the amplifier 6. The con-
nection between the series combina~lon of the resistors lO and 12is connected to a first input terminal of each of a pair of FET's
13 and 15. A second lnput terminal of the first FET 13 is
. ..
t-j~5t~3
connected to a ground terminal whlle a second lnput terminal Gf
the second FET 15 is connected to the output circuit of a constant
voltage unit 17. The output circuit of the first amplifier 6 is
also connected to the control, or gate, electrode of the flrst F~T
13 and, through a signal inverter circuit 19, to the control
electrode of the second F~T 150 A source of potential ~V is
connected through a resistor 21 to the output of the amplifier 6
to provide a bias signal for application to the control electrode
of the first FET 13 and to the input circuit of the signal inverter
circuit 19. The output circult of the amplifier 6 is also con-
nected to the control electrode of a third FET 60 having one of
its input terminals connected to a ground termlnal. An output
circuit from the signal inverter 19 is also applied through a
resistor 62 to the control electrode of a fourth FET 64. A second
input terminal of the third FE~ 60 and the first input terminal of
the fourth FET 64 are connected together at one end of an output
resistor 65. The other end of the output resistor 65 is connected
to one of a pair of output terminals 66 while the other one of the
: output terminals 66 is connected to a ground terminal. An output
capacltor 68 is connected across the output terminals 66. A ::
second input terminal of the fourth FET 64 is connected to the
output circuit o~ a second amplifler 70. The amplifier 70 has its
non-inverting input connected to a signal input terminal 72 while
its inverting input is connected through a resistor 74 to a ground
terminal and through a feedback resistor 76 to the output clrcult
of the amplifier 70.
MODE OF OP~RATION
Referring initially to the arithmetic circult shown in Figure
: 1~ the input signal applied to the lnput terminals 2 is effective
to control the operation of the movable armature 14 of a switch 16
between the fixed switch terminals 18 and 22 with the switching
~ime of the switch 16 being dependent on the amplitude of the input
~ 5t~
signal applied to the input terminals 2 as more fully described
hereinafter. Thi.s switching action of the switch 16 ls effective
to periodically connect the constant voltage source 20 to the base
electrode of the transistor 24 to control the current flow through
the transistor 24 and, ultimately, the ene~gization of the light
c.~ ~Jt rO o f
f lemittlng diode 28. Since the~modulation is a duty cycle type of
modulation, the control of the light emitting diode 28 by the
transistor 24 is effective to produce an output from the photo-
~io~e 30 which is also a duty cycle modulated signal representative
of the modulation produced by the switching of the switch 16. The
output signal from the photo-diode 30 is applied to the amplifier
36 to produce a corresponding operation of the switch 44.
The operation of the switch 44 is effective to periodically
connect the constant voltage source 48 to the capacitor 56 to charge
the capacitor 56 during one position of the switch 14 and to dis- ~ .
char~e the:capacitor 56 during the other position of the switch 44.
Thus, the charge retained on the capacitor 56 is the average charge
accumulated during the switching action of the switch 44. This
accumulated signal retained on the capacitor 56 is a duplicate of
the input signal applied to the input terminals 2 and is ultimately
applied to the output terminal 54 as an output signal from the
arithmetlc circuit shown in Figure 1. Further, the output signal
on the output terminals 54 is conductively isolated from the input
signal on the input terminals 2 by the optical isolator within the
light-tlght enclosure 32 while providing a reproduction of the
-~ amplitude of the input signal applied to the input terminals 2.
The conversion of the amplitude of the input signal applied to the
: input terminal 2 to a duty cycle modulated signal is performed by
the amplif~er 6 and the circuitry associated therewith. Specifically,
with a given direct current input signal Ein the direct current -.
feedback component of the negative feedback signal through the
feedback resistor 10 must equal Ei because of the closed loop
' ~' ' ' ' ~ -
S'~L5S~
around the amplifier 6. This direct current negative feedback
voltage is developed by generating a rectangular wave form at the
output from the armature 14 of the swltch 16 by operating the
switch 16 between the reference signal from the battery 20 and a
ground terminal, i.e., between switch contacts 18 and 22. This
direct current feedback signal is filtered by a low pass RC filter
including the resistor 10 and the capaci~or 8. The duty cycle Or
the switch 16 is controlled such that: ( t + t rf )V20 ~in.
The duty cycle controlling action can be further understood
by considering the positive feedback voltage to the positive input
Or the amplifier 6 through the resistor 12. This positive feed-
back voltage is added to the input signal to cause a small amount
Or the feedback voltage from the switch 16 to be super-imposed on
Ein . The amplitude of this positive feedback voltage which is
added to Ei~ is determined by the proportion Or the input resistor
4 and the feedback resistor 12 according to ( R 4 R )V2Q~ The
input signal Eln is divided by the proportion of resistor 4 to
resistor 12 when the switch 16 is connected to the ground terminal
so that the net Ein applied to the input of the amplifier 6 is
less than the actual Ein at the input terminals 2. Subsequently,
when the switch 16 applies the aforesaid positive feedback signal,
the net signal applied~the positive input of the amplifier 6
increases by the amou~t of the positive feedback signal from the
~ aforesaid net Ein applied to the ampli~ier 6. Thus, the ~ l~
; 25 representative signal applied to the amplifier 6 is a rectangular
wave signal centered on the actual Ei signal, i.e.~ having equal
~ c~c~s~o~s c~bo~ n
~x~ ~ ~o~ ~nd below the actual Ei signal. Thus, the
amplifier 6 is supplied with this rectangular wave signal rather
than the constant amplitude direct current Ein signal. Since the
3 amplitude of this rectangular wave signal is as stated above, this
signal amplitude is the area of indeclsion by the ampli~ier 6 when
comparing the inputs on the positive and negative input terminals
--10--
iLa~s~
thereof and, hence, .is the so called deadband of the amplifier 6.
If the deadhand is much less -than the ba-ttery level V20, then the
RC filter of -the resistor 10 and the capacitor 8 integrates the
output signal from the sw.itch 16. The output signal from the RC
filter is a triangular waveshape signal that is superimposed on
the Ein component of the feedback voltage applied to the amplifier
6 to the noninverting input thereof.
Since the duty cycle of switch is controlled, as previously
defined, and the ~egative feedback signal has a direct current
component which is equal to Ein, the triangular waveshape signal
is centered on the Ein component and has two slopes depending on
whether the capacitor 8 is charging or discharging. During the
charging of the capacitor 8, the slope is defined by
while the discharge slope is defined ~Y R in si~ce during the ~ .
discharge cycle of the capacitor 8 the battery-20 is disconnected
by the switch 16~. However, since both slopes are controlled by
the amplitude of the input signal, the time required for the ~ ~
triangular waveshape to pass through the deadband of the amplifier .
6 is controlled by the input signal Ein. Whenever the voltage ~:
difference between the inputs of the amplifier 6 crosses the zero
axis, the output signal of the amplifier 6 is arranged to change
state and to operate the switch 16 from one position to the other,
e.g., a zero axis crossing in the positive direction changes the
position of the armature 14 from the switch contact 22 to the switch
contact 18. This change in the position of the switch 16 causes . ;
the voltage at the output of the swit¢h 16 to jump from zero volts
to the voltage leveI of ~20~ ~t the same time~ the difference
--11--
. . . -.. - - . -
. . - , . . .
.. . - , . . . .
L,5~i~
signal at the inputs -to the amplifier 6 jumps in a positive
by (R4 ~ ~12) V20 and then starts down a ramp toward a
zero level. When this decreasing amplifier input siynal difference -
crosses the zero axis in the negative direction, the output of the
amplifier 6 again changes state to operate the switch 16, i.e., to
switch the armature 14 from the switch contact 18 to the switch
contact 22. This position of the switch 16 causes the output
signal from the switch 16 to drop to a Zero level for a repetition
of the aforesaid operation. The slopes of the difference signal -~
at the input to the amplifier 6 are the same as those previously
defined for the triangular waveform applied to the noninverting
input of the amplifier 6.
The duty cycle modulated output signal from the switch 16 is
also used to drive a transistor 24 functioning as a current source,
with a current limiting e~itter resistor 26, to operate a light
emitting diode 28 in the collector circuit of the transistor 24.
The light emitting diode 28 generates light pulses in response to
; the duty cycle modulated energizing signal applied thereto. These
light pulses are applied to a photodiode 30 to produce an increase
in the current flow through the photodiode 30 by changing its
internal impedance. This controlled current flow is used to
generate a rectangular waveform output signal from a bridge circuit
including the resistors 34 38 and 40 with the photodiode 30 forming
one leg of the bridge circuit and an amplifier 36 is connected
across the output, or diagonal, of the bridge circuit. This
rectangular waveform output signal is centered around ~ero volts to
produce the same change in the output of the amplifier 36 as
previously described for the amplifier 6~ i.e., to operate the
switch 44 from one state to the other at the same duty cycle as `
the switch 16. The operation of the switch 44 by the amplifier 44 -
produces a signal which is applied to an RC filter circuit -
including resistor 52 and capacitor 56. The direct current
-12-
~llS~ ~5
component of this switching vol-tage is recovered by this filter
and appears across the output capacitor 56, which capacitor is
connected across the output terminals 54, to produce the output
voltage Eout. The ~irect current component of the operation of
the switch 44 is defined by: ( ton )V4~. If the reference
signal from the battery 48 equals the reference signal from the
battery 20 then ~out equals ~in. Accordingly, this circuit trans-
fers direct current analog signals using an optical coupler and
isolator, and the conversion to duty cycle information does not
require a constant frequency input signal. Further, since it is
duty cycle information that is transferred from one circuit to the
other~the transferred information is not frequency dependent.
The operation and structure of the circuit shown in Figure 2
is the same as that described above for Figure 1 with the exception
that the switch 16 is replaced by a pair of FET's 13, and 15. An
output signal from an amplifier 6A is used to operate the first
FET 13 by a direct connection to the control electrode of the FET
13 thereto while the second FET 15 is operated through a signal
inverter circuit 19 whereby the FET's 13 and 15 are operated by
opposite polarity output signals from the amplifier 6A~ Thus, the
alternate operation of the FET's 13 and 15 represent the switching
of the switch 16 shown in Figure 1 between the contacts 18 and 22.
Additionally, the battery 20 is replaced by a constant voltage
unit, or supply, 17. Similarly, the switch 44 is replaced by a -
pair of FET's 47 and 49 which are operated by an output signal
from the amplifier 36A applied directly and through an inverter
circuit 45, respectively~ Finally, the battery 48 is replaced by
a constant signal source 58 similar to supply 17. ~-
In Figure 3, there is shown another embodiment of the
present invention wherein the si~nal isolating means 32 shown in
Figures 1 and 2 has been replaced by a direct electrical coupling
of the duty cycle modulation section of the amplifier system to
the demodulation section of the amplifier system. Since the optical
-13-
.
1 ~35~ 5
isolator is elimina-ted from the circuit shown in Figure 3, the
control signals from -the FET switches, previously discussed with
respect to Figure 2, are used in common between the first and
second sets of FET switches to provide a synchronized switching
S action between the modulating and demodulating operation of the
circuit. The modulating portion of the circuit shown in Figure 3 ~ ~-
is substantially identical to that shown in Figure 2 and operates
in a similar manner. The demodulating section of the amplifier
circuit shown in Figure 3 is modified from that shown in Figures
1 and 2 to include an amplifier 70 having its inverting, or
negative, input connected in a negative feedback loop with the
output of the amplifier 70 while its non-inverting, or positive,
input is connected to an input terminal 72 arranged to be connected
to a second source o~ input signals. The output signal from the
amplifier 70 is applied to an input of one of the FET switches in
place of the second constant reference signal source shown in
Figures 1 and ~. Thus, the output of the amplifier 70 is switched
into the output capacitor 68 to develop the output signal across
the output terminal 66 in a matter similar to the switching of the
second reference signal source in Figures 1 and 2.
While the circuit in Figure 3 is specifically shown with a
separate second input terminal 72 suitable for connection to a
second source of input signals to the non-inverting input of the
second amplifier 70, this modification is applicable to the circuits ~;
shown in Figures 1 and 2 by replacing the second constant signal
source 7~ or 56 shown in t~e dem~dulating section of the circuits
illustrated in Figures 1 and 2 by a source of a desired input
signal. The basic cireuit shown in ~igure 3 may be arranged to
perform various multiplication arithmetic operatlons by connecting
the input terminals 2 and 72 to deslred input signals. For example,
if the same input signal is applied to the input terminals 2 and
72, the output signal EoUt is the square of the input signal. On.
-14- ;
5~
the other hand, if different input signals are applied to the
input terminals 2 and 72, the output signal EoUt is the product
of the two input signals. Additionally, by using the circuit
shown in Figure 3 in an operative relationship with an operational
amplifier, other arithmetic functions may be obtained. For
example, the basic multiplier shown in Figure 3 may be used in a
negative feedback circuit with an operational amplifier while the
output signal of the operational amplifier is applied to both
inputs of the circuit shown in Figure 3. If the output signal of
the circuit shown in Figure 3 is concurrently applied to the
inverting input of the operational amplifier while another separate
input signal is applied to the non-inverting input of the operational
amplifier, then the output signal of the operational amplifier is
representative of the square root of the input signal applied to
the non-inverting input of the operational amplifier.
Accordingly, it may be seen that there has been provided
; an improved arithemtic circuit for providing a plurality of arith-
metic operations while being suitable for use with a signal isolat-
ing element for electrically isolating the inputs and outputs of
the arithmetic circuit.
'~ '
-15-
.. .
,~ .
