Note: Descriptions are shown in the official language in which they were submitted.
538~L~
1 FIELD OF THE INVENTION
The invention disclosed herein relates to data pro-
cessing devices and more particularly relates to digital
television display systems.
BACKGROUND OF THE INVENTION:
Digital television display systems in the prior
art produced line drawings by storing one video bit for
every element of the picture. In many such prior art systems
the raster assembly storage would have to store as many as
one million video bits for a 1024 X 1024 raster matrix.
The completed picture would then be transferred to a refresh
store. One substantial drawback in such prior art displays
is that any alteration in the displayed picture would ;;~
require either the generation of a new picture or the moving
of all one million bits to the raster assembly storage
for modification and return. Thus to effect a single
erasure of a single vector would require either the reassem~
bly of the entire raster or the transfer of the entire one
million bits out of the storage for alteration and replace- -
ment. In the event that two vectors cross one another, the
process of erasing a first vector, after transfer back to
the assembly store, would remove video bits common to both
vectors, leaving the remaining vector with a gap separating
the components on either side of the erased vector. ~;
Some progress has been made in the prior art
through the implementation of queue memories for the
storage of digitally encoded video data. One example of
~Y~ ~
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1 such a prior art system discloses a video generator for data
2 display which employs a threaded refresh buffer. The use of
3 such a buffer permits a reduction in the size of the raster
4 assembly storage over that of the prior art. However, this
prior art image buffer must be large enough to accommodate
6 the tallest character which is intended to be displaved.
7 According to prior art teachings this would be at least eiqht
8 raster lines which must be stored in the video image buffer.
9 The prior art states that if a vector were to exceed the
vertical height of such a video image buffer, it would have
11 to be generated as separate segments. This, it is disclosed,
12 would be accomplished by returning the contents of vector
13 registers in the vector generator to the threaded list of
14 the data buffer in order that the vector generator may con-
tinue at a later time in the scanning sequence. It is seen
16 that the amount of processing necessarv to access
17 the next component of the vector in the next group of raster
18 lines to be scanned, by accessing the threaded buffer itself,
19 reduces the display capability of the system and increases
its complexity. ; `
21 What the art requires is an improved means of
22 accessing subsequent components of vectors and other data
23 stored in the system so as to enable higher rates for
24 display.
OBJECTS OF THE INVENTION:
~ _ . . . , _ , . . .
26 It is an object of the invention to store graphic
27 and alphanumeric display data so as to be more efficiently
28 accessed than has been capable in the prior art.
29 It is another object of the invention to store
graphic display data so as to retain its identity and
31 special attributes such as color, intensity or blink, in ~`
32 an improved manner.
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1 It is still another ohject of the invention to
2 display deco~posed graphics as vector seqments in an
3 improved manner.
4 It is still a further object of the invention to
store graphic displav words loaded in a random seauence,
6 so as to be sorted into threaded queues of se~uential
7 raster line location, in an improved manner.
8 It is still a further object of the invention to
9 cvclically store displav data which is continually modified
as the raster field is generated.
11 .SUMMAR~r t)F THE INYE~TI~)N:
12 P video generator circuit is disclosed for conver-
13 ting randomlv occurring data signals representing graphical
14 patterns into a time se~uential video signal for use with a
sequential line scan displav device. The improvement of
16 the invention includes a threaded buffer connected to
17 receive the data signals and adapted to sort the data
18 signals into groups ordered bv extremal scan line positions
19 for the pattern represented. An intermediate buffer
having a first input connected to the output of the
21 threaded refresh huffer, stores the ordered data signals
22 once during each displav field before the displav of the
23 pattern represented. The intermediate buffer outputs the
24 ordered data signals in svnchronism with the line scans
of the dis~lay. A graphical or alphanumeric pattern
26 generator is connected to the output of the intermediate
27 buffer for decoding the ordered data signals outputted
28 from the intermediate buffer. The graphical pattern
29 generator generates on a first output line, components
of the pattern to be represented which lie along the
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1 display line or group of lines to be scanned. A partial
2 raster assembly storage is connected to the first output
3 line from the graphical or alphanumeric pattern generator
4 to store the components of the pattern represented which
lie along the display line or lines to be scanned. The
6 graphical pattern generator modifies the decoded, ordered
7 data signals to identify the horizontal coordinates for the
8 intersection of the pattern represented with the next displav
9 line or lines scanned. The graphical br alphanumeric
pattern generator also modifies control data and outputs
11 the modified data siqnals over a second output line to a
12 second input'line in said intermediate buffer for storageO
13 The graphical or alphanumeric pattern generator omits the
14 output of a modified-data signal on the second output line
when no components of the pattern will intersect succeeding
16 display lines to be scanned in the field. The intermediate
17 buffer has a novel memory structure organized into a pre- ; `
18 load area and an active area. In operation, the video ; -'
19 circuit generator invention reduces the amount of processing
necessary to dynamically generate a DTV display.
21 DESCRIPTION OF THE DRAWINGS: -:
.` -.
22 The foregoing and other objects, features, and ,- ,
23 advantages of the invention will be apparent from the
24 following more particular description of the preferred ~' -
embodiment of the invention, as illustrated in the
26 accompanying drawings.
27 Figure 1 depicts the video generator circuit
28 invention,. ',
29 Figure 2 shows the data word format input to the
refresh buffer 28.
31 Figure 3 shows a detailed block diagram of the
32 refresh buffer 28. '
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1 Figure 4 shows a detailed block diagram of the
intermediate buffer 38.
Figure 5 is a block diagram of the symbol genera-
tor 40.
Figure 6 is a detail block diagram of the vector
generator 42.
Figure 7 is a block diagram of the partial raster
assembly store 44.
Figure 8 depicts a system block diagram of a dynamic
10 digital television display system.
Figure 9 shown on the first sheet of drawings is a
block diagram of a graphic display control unit 8.
Figure 10 shows a wiring diagram of the display adap-
ter interface.
Figure 11 shows a threaded list in the refresh
buffer for a first loading.
Figure 12 shows a threaded list in the refresh
buffer for a second loading configuration.
Figure 13 shown on the third sheet of drawings shows
20 the refresh buffer-intermediate buffer interface.
Figure 14 shown on the fourth sheet of drawings is a
block diagram of the addressing logic for the intermediate
buffer.
Figure 15 shows an implementation of the timing for
the intermediate buffer.
Figure 16 shows the preload addressing logic 94.
Figure 17 is a timing diagram for sequential symbols.
Figure 18 is a simplified block diagram of the vector
generator 42.
Figure 19 is an e~ample of the operation of the
vector generator 42.
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1 - Figure 20 gives a detailed illustration of the
2 timing for the refresh cycle in the PRAS.
3 Figure 21a shows the SYNC generator block dia~ram
and Figure 21b~ the resulting raster.
DISCUSSION OF THE PREFERRED EMBODIM:ENT:
6 The dynamic digital TV displav techni~ue can be
7 generally described as follows. Digital TV is a display
8 technology which takes coded data from a computer source
9 and converts it to a TV video signal. This signal drives
one or more TV monitors which present the desired computer -
11 display picture. The logic which converts the coded
12 computer data to a TV signal is all digital, the same as
13 that used in a computer. Thus, digital TV has succeedèd
14 in using the technical advances developed in both the TV
and computer industries to provide a uni~ue computer dis-
16 play capability.
17 A TV display in the context used here is one in
18 which the electron beams (one for each primary color) are
19 repeatedly deflected across the face of the Cathode Rav
Tube (CRT) in a series of closely spaced parallel lines
21 (called a raster). This is repeated a fixed number of
22 times each second (refresh rate). Within a particular
23 display system the number of parallel lines and the
24 refresh rate are usually fixed. A tYpical displav
has 525 lines and is refreshed 30 times per second. Each
26 ~rame is divided into two fields. One field consists of
27 the odd numbered scan lines and the other the even scan
2B lines; this results in an interlaced scan which produces
29 an apparant doubling of the refresh rate. `
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1 Digital TV presents a computer displav in a TV for-
2 mat by reducing the image to a matrix of points or displaY
3 elements. In a display with horizontal scan lines, the
4 number of vertical display elements is e~ual to the number
of visible scan lines. The number of elements within each
6 scan line is somewhat arbitrary but is chosen to be 1.33
7 times the number of scan lines. This conforms to the 4~3
8 aspect ratio of the TV Cathode Rav Tube. Even though the
9 image is made up of elements, it appears continuous because
of the large number of elements used.
11 The invention disclosed herein makes use of the
12 new technique of graphic generation known as "on-the-fly"
13 or "implicit refresh". This is to be contrasted from the
14 "explicit refresh" found in older DTV Systems. The on-the-
fly technique permits all displa~able data to retain its
16 identity in computer coded form up to the final stages of
17 video generation.
18 In use, implicit refresh allows for erasing data
19 on the display without erasing overlaving tintersecting)
data. It permits selective modification of the data.
21 This method of display generation is particularly attrac-
22 tive when blink tflash) and color are desired. The
23 attribute bits for identification of color and flash are
24 contained in computer coded form.
In terms of hardware, implicit refresh can reduce
26 the storage requirements in memory by a factor of 18 to 1
27 for a color graphic display.
28 The video generator circuit invention shown in
29 Figure 1, makes use of the "on-the-fly" refresh technique
to dynamically generate a digital television display. The
.
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1 video generator circuit is composed of the refresh buffer
2 28, the intermediate buffer 38, the vector generator 42 or
3 symbol generator 40, and the partial raster assembly
4 store 44.
The refresh buffer 28 accepts data siqnals re~re-
6 senting picture elements, in a format such as is shown in
7 Figure 2 from a data source such as a computer or program-
8 mable controller. The refresh bu~er 38 reads the data
9 words out, ordered by Y-address, once per field to the
vectors and symbols organized as background and dynamic
11 data. The refresh buffer 28 consists of a control module
12 and two starage modules providing a total of 8K halfwords,
13 each with sixteen ~ata and two parity bits. The major
14 function of the refresh buffer 28 is to store the coded~
data for constructing the visual display. Data, which is
16 received from the digital computer over line 68 in random
17 fashion, is sto~ed in a form ordered by ~-line. ~his allows
18 the refresh buffer 28 to be read on a line-bY-line basis.
19 A detailed block diagram of the refresh buffer is shown in
Figure 3.
2i The data word formats, shown in Figure 2 consist of
22 the Vector Format, the Symbol Format, the Index Format, and
23 the Empty Slot Format. Vectors require a four halfword slot
24 per vector. Symbols require a four halfword slot per set
of up to four sequential symbols. Single symbols also
26 require the same size slot, with space code for the last
27 three symbols. The meaning of the fields is discussed
28 later. Data words are transferred from the digital computer -
29 to the refresh buffer 28 on a shared bi-directional halfword
bus 68.
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1 The intermediate buf~er 38 iq a small, high-
2 speed, memory, which receives data in coded form from the
3 refresh buffer 28, and.transmits the data, in turn to the
4 ~ymbol 40 or vector generator 42, as re~uired. The inter-
mediate buffer 38 receives, from the refresh buffer 28 two
6 32-bit words for each symbol or vector starting on a raster
7 line. This data is requested by the IB 3~ as memory space
8 becomes available, prior to the time the raster line is
9 transmitted to the display 10. A detailed block diagram of
the intermediate buffer is shown in Figure 4.
11 Each pair of coded:data words is transmitted, at
12 high speed, to the-appropriate display generator ~symbol 40
13 or vector 42) where it is-converted into digital video data.
14 Since a vector-or symbol may appear on several raster lines,
the symbol 40 or vector:42 generator modifies the coded data
16 word, and then rewrites it into the intermediate buffer 38,
17 for use in generating the digital video data for the next
18 raster line. I the video data conversion has been completed
19 during the generation.of the currenk raster line, that
particular data word is not re-written-into the intermediate .
21 buffer 38.
22 The intermediate:buffer 38 is organized into a pre~
23 load area-and an-active area, with a total capacity of 256 .~.
24 32-bit wordsData words are transferred from the refresh
buffer 28 to the preload area as room becomes available,
26 and from the preload area to the active area as required -~
27 for display.
28 Th~ symbol generator 40-utilizes a programmable .-
29 memory to conver~ coded:sYmbo~ data from the intermediate
buffer 38 into appropriate sYmbol bit patterns for the ~ :
31 raster line to be displaved. The symbol memory 56 is
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1 loaded from the host processor CapacitY for up to 256
2 symbols can be provided.- The symbol memorv can store any
3 dot matrix pattern within a 16-by-16 format. A detailed
4 block diagram of the symbol generator is shown in Figure 5.
Each pair of words from the intermediate buffer 38 -
6 provides up to four sYmbol codes. The symbol generator 40
7 automatically spaces and positions the symbol in accordance
8 with a space code field in the first word. Spacing between
9 symbols is specified by the host processor.
The sYmbol generator 40 decrements a counter field
11 in the intermediate bufer word pair before causing the
12 data words to be re-written in the intermediate buffer 38.
13 When the count is zero, the words are purged from the
14 intermediate buffer 38.
The vector generator 42 accepts two data words from
16 the intermediate buffer 38 and uses them to determine which
17 elements on each display line compr~se the vector. A11
18 vectors are specified by the host processor as indiuidual
19 vectors starting at the top and running downward on the
screen. A detailed block diagram of the vector generator
21 is shown in Figure ~.
22 Vectors are expressed as X and Y positions, inverse
23 slope (~X/~Y), and number of Y lines on which the-vector
24 appears (Y length~. The XY coordinate origin is the lower
left corner of the displa~, with positive X from-left to ~-
2~ right/ and positive Y from bottom to top. The vector
27 generator-42 uses the-inverse slope to determine the
28 number of elements-on the current line, and updates the X
29 position for use on the next line. It counts down the
number of Y l;nes to determine the vector end. The use of
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~ a modified floating point technique insures that everY
2 point on a vector will be within one display element of
3 the theoretical line specified by the host processor.
4 The partial raster assembly store 44 (PRAS) is a
high-speed memory with capacity for two full display raster
6 lines in explicit (noncoded video dot pattern) form. All
7 vector and symbol dot pattern data are assembled in one
8 line of the PRAS 44 dur,~ng the line time preceding its 7
9 normal display presentation. When the video line is to
be displayed, the PRAS line is read out at video rate
11 while the next line is being assembled in the second PRAS
12 line. A detailed block diagram of the PR~S is shown in
13 Figure 7.
14 The use of a PRAS 44 greatly simplifies the
vector 42 and symbol 40 generators, eliminates restrictions
16 on digital video data intersections, and removes any need
17 for ordering display data by X position in the IB 38 or
18 RB 28. The vector 42 and symbol 40 generators-can drive
19 three PRAS's 44, one for each of the primary colors reauired
to drive a RGB color display mon;tor l0.
21 The digital video output signal from each PRAS 44
22 is routèd to-a vidèo output driver 46, where it is mixed
23 with sync signalsj and converted to a composite video
24 signal for transmission over line 192 to the DTV display.
One output driver-46 is re~uired for each primary color.
26 ~.E .SYS~EM CON~EXT-
27 The DDTV System Context: The operation of the
28 video circuit genèrator invention can best be described
29 in the contèxt-of its use ~n a dynamic digital television
system such as ~s sho~n in Figure 8, for use in applica-
31 tion~ where rapi~ and accurate identification of informa-
32 tion is of prime importance.
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1 An example is given of a particular dynamic digital
television (DDTV) system which employs the video generator
circuit invention. The disclosure o~ this DDTV system for
utilizing the video generator circuit invention should not
be construed as limiting the applicability of the invention
to other display system applications. The example DDTV
system is composed of customized hardware which furnishes
situation display presentations, in color, to a plurality
of independent operators, each at his own integrated dis-
play console where he can interact with the host computer
via trackball and program function keyboard devices. The
DDTV uses a plurality of on-line graphic display control
units to convert computer data into randomly positioned
vectors and symbols which may be representative of dynamic
situations; background graphics with annotation may be
simultaneously generated to support the application.
Novel digital television techniques are utilized to
generate the graphic display presentations. These tech-
niques implemented with the disclosed hardware to provide
the desirable characteristics of flexible configuration,
high availability, autonomous refresh (refresh not in host
computer), independent operation of a plurality of inte-
grated display consoles, small cluster configuration (4
consoles per graphic display control unit), off-line, on-
line and in-line operability and maintainability via pro- -
grammable controller, disk, and support software, solid
state design using monolithic and integrated circuit tech-
niques and IBM* System/370 compatibility.
Among the graphic display features of the system are
307,200 displayable elements on a 480 vertical by 640
horizontal format, color presentations in 7 colors plus
*Registered Trade Mark
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1 black, constant refresh rate o~ 30 frames per second, total
2 display update in less than one second, up to 1700 vectors
3 or 1700 r~ndom symbols per display, selective ùpdate of
4 dynamic and background data, programmable character set of
255 symbols per display (16 X 16 element matr~x), ~ull
6 vector graphics capabilityj high relative accuracy, uniform
7 intensity, data retention ~no eraSIng of data intersections),
8 and blink or flash of individual vectors and sYmbols.
9 The system is comprised of the following major
functional units.
11 The integrated display console (IDC) 16 houses a
12 color graphic display and operator devices for interacting
13 with the system. An independently operating IBM 3277 alpha-
14 numeric display, supported by alphanumeric keyboard and
light pen, is integrated into the console structure. IDCs
16 are connected on-line with unit available for backup or
17 test pruposes.
18 The graphic display control unit (GDCU) 8 comprised
19 of a programmable controller for performing data formatting,
buffering, operator device handling, and control functions;
21 disk attachment for initial program load and internallv
22 generated diagnostic routines, and four independent on-the-
23 fly color graphic/sYmbol video generators 6. Each video
24 generator 6 contains the video generator circuit invention
of Figure 1, modified by the addition of two additional PRAS
26 44 and two additional video mixers or drivers 46 to permit
27 three color RGB display. Active GDCUs furnish an on-line
28 capabilitY for independent displav channels, with an
29 eleventh GDCU available for backup.
~ ' ' .
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1 Graphic patch panel (~PP) ~4 designed to provide
2 reconfigurability and to enhance graphic sYstem availabilitY.
3 This panel permits anY of 44 GDCU color channels ~from 11
4 GDCUs) to be connected ~anually to an~ of up to 44 IDCs with
associated operator devices.
6 Alphanumeric patch panel (ANPP) 26 designed to provide
7 reconfigurabilitv and to enhance IBM 3270 alphanumeric svstem
8 availabilitv. This panel permits anv of 84 alphanumeric dis-
9 plav channels (from IBM 3272 control units) to be connected
manuallv to anv of up to 84 IBM 3277 alphanumeric displavs
11 (39 console mounted units and 45 free standing units) with
12 associated operator devices.
13 A more specific description of the svstem's apparatus
14 follows. Dynamic digital T~7 svstem (DDTV) of-Figure 8 is a
versatile, interactive color display svstem, interfacing with
16 two System/370 Model 158 MP computers through an IBM 2914
17 Switching Unit 2. The DDTV sYstem emplovs high speed, mono- ;
18 lithic refresh buffers, under the control of a programmable
19 controller 4. The technologv is current, usIng high speed,
high density, solid state logic. A programmable controller 4
21 and as manv as four (4) video generators 6 can comprise a
22 graphic displav control unit (GDCU) 8.
23 ~ach video generator 6 within the ~CU 8 provides
24 the necessary graphic signals and controls to drive a 19-
inch, industrial color TV monitor 10 with intèractive
26 capabilitv provided by a program function kevboard 12 and
27 a trackball for graphic cursor control 14. The displav 10,
28 keYboard 12, and trackball 14 are housed in an integrated
29 displa~ console (IDC) 16 together with an IB~ 3277 displaY
station 18, alphanumeric kevboard 20 and light pen 22.
,
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1 The alphanumeric units 18, 20, and 22 while phvsicallY
2 part of the IDC 16, are separately controlled bv an IBM
3 3272 control unit and mav be considered a separate, stand-
4 alone system.
The DDTV svstem consists of 10 ~CUs 8 and IDCs 16
6 with one GDCU 8 and one IDC 16 provided as spares. Each
7 GDCU 8 is capable of driving and controlling 4 IDCs 16.
8 Through the use of a graphic patch panel 24, each GDCU 8 maY
9 be connected to any 4 IDCs 16, providing both flexibilitv
and svstem reliabilitv, through reconfiguration. The 3277
11 display stations may also be reconfigured through a separate
12 alphanumeric patch panel 26.
13 A programmable controller 4 feeds data words
14 representing vectors and svmbols to be displayed, to this
video generator circuit invention contained in the ~DCU 8.
16 The video generator circuit emplovs the graphic/svmbol on-
17 the-flv generation technique to create, in color, displavs
18 of dynamic (rapid update) graphics and sYmbols and static
1~ backgrounds. The on-the-fly technique improves the per-
formance of the sYstem and eliminates the need for extensive
21 raster assembly and refresh storage commonlv associated
22 with DTV svstems.
23 The programmable controller 4 operates with four
24 independent color video generators 6 to service the reauire-
25 ments of four individual displav consoles 16. A disk ~ -
26 attachment to the programmable controller 4 can provide
27 initial program load (IP~) capabilitv an~ storage o~
28 diagnostic routines and test patterns for exercisin~, on
29 an individual basis, each color display channel of the
cluster. Communication with the host computer (~vstem/
.
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I 370) channel and handling of operator-controlled inter-
2 active devices are effected via adapters on the program-
3 mable controller 4.
4 The primary data flow paths in the DDTV system are
between the host computer svstem tthrough the IBM 2914
6 Switching Unit 2) and the GDCUs 8, and between each GDCU 8
7 and its cluster of IDCs 16. Figure 8 illustrates the data
8 flow.
9 There are two levels of control with the DDTV
sYstem: (1) graphic commands issued to the GDCU 8 bv the
11 host processor across the Svstem/370 I/~ interface 2 and
12 (2) internal graphic orders issued hy the programmable
13 controller 4 within the GDCU 8 to each of the four associated
14 video generators 6 and their refresh buffers 28. The GDCU
8 shown in Figure 9 consists of the following functional
16 elements: programmable controller 4, display adapter 30,
17 manual input adapter 32, maintenance panel 34, power svstem
18 36, the video generator circuit invention comprising the
19 refresh buffer (RB) 28, the intermediate buffer (IB) 38,
the svmbol generator (SG) 40, the vector generator tVG) 42,
21 and the partial raster assemblv storage (PRA~) 44, and
22 finally the video output from the video generator circuit `~
23 goes to the video output drivers (VOD) 46.
24 Figure 9 is a block diagram of the GDCU 8, and
shows how the video generator circuit comprisinq elements
26 28, 38, 40, 42, 44 and 46 are replicated four times within
27 each GDCU 8 to control a cluster of up to four IDCs 16.
28 The video generator circuit elements 28, 38, 40, 42, 44
29 and 46 are described on a per-chann~l basis. A detailed
design description is given later.
WA9-74-001 -17~
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The programmable controller 4 (PCj is a stored
2 program processor, incorporating an integrated monolithic
3 memory 48, and an I/O bus 50 for external communication,
4 through appropriate adapters. The PC 4 interfaces with
the host computer (an System/370 Model 158 MP) through
6 an SYstem/370 local channel adapter 52, with a disk file
7 54 through a disk file adapter, and with the GDCU video
8 generators 6 and the IDC's 16 through the displav adapter
9 30,
The control program, loaded into the integrated
11 memory 48 from the disk file 54, allows the controller 4
12 to receive graphic commands and data from the host computer
13 through the S~stem/370 interface 52. The controller 4
14 then interprets the graphic commands, manipulates the data
as required, and transmits graphic ordex and data to the
16 applicable video generator 6. AdditionallY, the controller
17 4 queues manual inputs from the IDCs 16 and transmits them
18 to the host processor on an interrupt basis.
19 In an off-line mode, the controller 4 is capable
of interpreting manual inputs from the IDCs 16 and
21 controlling the video generators 6 through diagnostic
22 routines stored on the disk file 54. This also allows
23 in-line operation, wherebv one IDC 16 in a cluster may
24 be operated off-line in diagnostic mode, without impacting
the operation of the other three IDCs 16.
26 The display adapter 30 allows the programmable
27 controller 4 to provide data and control to four
28 independent video generators 6 on a multiplexed, demand-
29 response basis.
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1 The manual input adapter 32 provides a multiplexed
2 interface between the display adapter 30 and (1~ the track-
3 ball 14 in each IDC 16 for graphic cursor positioning and
4 (2) the program function ka~board 12 in each IDC 16 for
console operator interaction.
6 The maintenance panel 32 contains controls, switches,
7 and indicators to allow the GDCU 8 to be exercised off-line
8 for diaynostic purposes. AdditionallY, controls are provided
9 to put a single video generator 6 into an in-line mode where-
bv it can be exercised in a diagnostic mode independent of
11 the host processor without impacting the operation of the
12 other three displa~ generators Ç.
13 The power system accepts line power to provide
14 the necessary power at required voltages to
operate the GDCU 8 and all its components.
16 The integrated displav console 16, contains the ;~
17 following elements: graphic displav 10, program function
18 keYboard 12, and trackball 14.
19 The graphic displav lO is a standard, indus~rial
l9-inch, 525-line, RGB (red-green-blue) color TV monitor,
21 with 30 frame per second refresh, 2-to-1 interlace. It
22 receives data from the video generator 6 via three video
23 coaxial cables.
24 The program function kevboard 12 provides operator
interactive inputs to the host processor, through the ~.DCU
26 8.
27 The trackball 14 is used by an operator to position ~ -
28 the graphic cursor on the display screen. Moving the ball
29 causes the cursor to move responsively on the color displav,
under control of the GDCU 8. The trackball 14 and the pro-
31 gram function keyboard 12 interface with the GDCU 8 through
32 the manual input adapter 32.
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1 The graphic patch panel 24 is used to interconnect
2 the 38 IDCs 16 with the 10 GDCUs 8, as shown ln Figure 8.
3 It contains, on the input side, 176 connectors which receive
4 the four output cables (3 video, 1 digital) from each of the
video generators 6 in each GDCU 14 video generators per GDCU, ~ .
6 11 GDCUs, including spare). ~n the output side of this patch
7 panel 24, 176 connectors are provid~ed for the 39 IDCs 16 and
8 to allow expansion capability for 5 additional IDCs.
9 Internally, the patch panel provides quick-release
patch cables, for interconnection of anv IDC 16 with any
11 GDCU 8 channel.
12 Although the 3277 displa~ stations 18 are not
13 electrically a part of the color graphic displav svstem, a
14 separate stand alone alphanumeric patch panel 26 is provided
to allow the interconnection and reconfiguration functions
16 to be performed. A 3277 18 requires onlY 1 coaxial cable,
17 therefore, the alphanumeric patch panel 26 provides 84
18 input connectors to accommodate 39-IBM 3277's housed in
19 the IDC 16 and 4~ additional stand-alone 3277s.
The GDCU 8 is a free standing unit which provides
21 the necessarY signals and controls to support four (4)
22 color graphic displaYs and associated operator devicesO
23 ~he GDCU 8 does not require operator attendance during
24 operation.
pro~rammable controller 4: The controller (PC)
26 4 is a 16-bit, general purpose, stored-program machine
27 using two's complement arithmetic. Utilizing high-speed,
28 high density, solid state logic, the machine can be
29 considered a pluggable unit with the GDCU 8. The PC 4
WA9-74-001 -20-
_ ~53B~7
1 also incorporates a high-speed monolithic memory 48,
2 packaged so as to be modular in 8K-bvtes increments up
3 to ~4X-bvtes.
4 The functions to be performed bY the PC 4 are:
direct interface with the host processor, receipt and
6 interpretation of graphic commands from the host, receipt,
7 modification, and ordering of graphic data from the.host,
8 interface with, and control of, the refresh buffer 28 in
9 display updates, deletions and changes, receipt, monitoring :~
and transmission of manual inputs from the IDCs 16, main-
11 tenance of status and sense information for transmission
12 to the host processor, and control of the graphic cursor
13 for each display, in response to manual inputs from the
14 IDC 16.
The PC 4 is interrupt driven, and communicates
16 with attaching units by wav of a 16-bit I/~ bus 50,.
17 through appropriate adapters. Specific adapters incorporated .
18 within the PC 4 are a disk file adapter, a System/370 local
19 channel adapter 52 and a displa~ adapter 30.
The GDCU 8 incorporates a small, read/write disk
21 file 54 which interfaces with the PC I/n bus 50 through the :
22 disk file adapter. Since the PC monolithic memorv 48 is
23 volatilej the PC control program will be resident on.the
24 disk file 54, to be load into the PC memory 48 during
the initial program load (IPL~.
26 Diagnostic programs and test patterns, for use
27 during off-line diagnostic mode checkout of the DDTV
28 system, are also resident on the disk 54.
WA9-74-001 -21- `.
538~L7
1 The PC 4 incorporates a Svstem/370 local channel
2 adapter 52, to allow GDCU 8 communication with the host
3 computer. This adapter presents an 8-bit, System/370
4 interface to the host, and a 16-bit interface to the PC 4
The GDCU 8 will attach to the host processor via
6 a block multiplex channel, and will support a burst mode
7 data rate of up to 700K bytes per second across-the interface.
8 The displav adapter 30 permits the attach~ent of
9 up to four independent video generator channels to the
programmable controller 4. The adapter interfaces with 9
11 devices, four refresh buffers 28, four programmable svmbol
12 stores 56, and the manual input adapter 32J In addition, it
13 receives control signals from the maintenance panel 34 and
14 the sYnc generatOr.
The interface shown in Figure 10 consists of the
16 following lines~ L~ss-A thirteen bit address bus routed
17 to all 9 devices. The progra~mable controller 4 has the
18 ability to load the address and to specifv incrementing bv
19 0, 1, 2 or 4 after each read or write operation; Data Bus-
An eighteen bit bi-directional bus used bv all 9 devices.
21 Sixteen bits are for data, two are paritv bits; ~anual
22 InPut AdaPter Select-Selects the manual input adapter 32
23 for read or write operat~ons~ -Symbol Store-Selects the
24 symbol store 56 designated bv the channel ID bits for
read or write operations; Refre~s~l Buffer-Selects the
26 refresh buffer 28 designated by the channel ID bits for
27 read or write operations; Channel ID Bits 0 and l-Desi~-
28 nates one of four s~mbol stores 56 or refresh buffers 28.
,
WA9-74-001 -22-
?538~7
1 Read Request-Initiates a read operation in the selected
2 device at the address specified. The device selected
3 places data on the data bus; ~Writ~e Re~u~e~st-Initiates a
4 write operation in the selected device at the address
specified. The device uses the data on the data bus;
6 Status Re~Iest-The device places status on the data bus;
. _
7 Read/Write Complete-The device has placed requested data
8 or status on the data bus or has accepted the data to
9 be written; Inhibit/Enable Dis~lav-If a 'il", when a
refresh buffer is selected that display is inhibited. If
11 a "0" the displav is enabled; Channel N ParitY Frror-
12 Indicates a paritv error has occurred while reading the
13 refresh buffer 28. It is reset bv a status re~uest;
14 Channel N ~n/~ff Line-A signal from the maintenance panel
34 indicating a channel is on line or off line for
16 diagnostics. The displaY adapter 30 interrupts the
17 programmable controller 4 whenever a channel goes on or
18 off line; and ~ertical Re't~r'a~ce-A signal from the ~vnc
lg generator, used bY the displaY adapter 30 to cause once
per frame interrupt to the programmable controller 4.
21 This is used to initiate polling of the Manual input
22 adapter 32.
23 DETAILED DE.~CRIP~I~-N ~F THE IN~ ~ TI'~N D
_ _ _ _ . ,, _ _ ,
24 The refresh buffer 28 accepts data from the
programmable controller 4 (PC) via the displav adapter
26 30 and reads-it out, ordered by Y-address, once per field
27 to the intermediate buffer 38 for display. The stored
28 data consists of combinations of vectors^and symbols
29 organized as background and dvnamic data.
WA9-74-001 -23-
538~7
1 The refresh buffer 28 consists of a control module
2 and two storage modules providing.a.total of 8K halfwords,
3 each with sixteen data and two paritY bits. '.
4 The major function of the refresh buffer 28 is to
store the coded data for construct:ing the visual displav.
6 nata, which is received bv the P~.4,in.random fashion, is
7 stored in a form ordered bv Y-line,~This allows the refresh
8 buffer 28 to be read on a line-b,v-line basis.
9 Data is stored in the refresh buffer 28 in four
halfword (16 bit each) slots, which.are ordered bv a method
11 similar to indirect addressing. .Each slot has a pointer
12 field that contains the address of another slot; thus a :-
13 group of slots can he threaded together into a list. Figure
14 11 shows such a list. Slot 4 is.the first in the list. It
points to slot 7, which points to.slot 2,.and so on to slot
16 5, which is the last slot in the.listThis is indicated bv
17 a special control bit designated end.of.thread (E~T). Lists
18 such as this have a verv useful.propertv; s~ots can be '~-
19 added to the head of the list without:disturbing anv slots '
alreadv in the list. In Figure 12,.slot 12 has been added :: :
21 to the head of the list. All that,was necessarv was to
22 known.that slot 4 was ~reviouslY.the head of the list. The
23 PC organizes data in the refresh huffer into threaded lists,
24 using separate lists for the background.and:dvnamic data
on each Y-line. The lists are accessed bY an index that is
26 a table of pointers. Every raster.line has associated
27 with it a pair of index halfwords:.one for background data `.:.
28 and one for dvnamic data. They are stored in fixed memorv
29 locations in the refresh buffer at.addresses which are a
direct function of the V-address.of the.data on the screen. .'
31. When adding slot 12 to the list of Figure 11, all that was .
WA9-74-001 -24-. .
1~5~7
1 necessary to access the index to find out that slot 4 was
2 the previous hsad of the list, to write the 4 in the
3 pointer field of slot 12, and to write l2 into the index
4 so that it will point to the new head of the list.
Just as slot 12 was added to the list and became
6 the slot at the head of the list~ it is apparent that the
7 slot at the head of the list can be readilY removed. The
8 index is read and used to access slot 12. The slot 12
9 pointer contains 4. This is loaded into the index and
slot 12 is no longer in the list and could be threaded
11 to another list. The PC uses this capabilit~ to manage
12 emptv slots. Emptv slots are initiallv threaded together
13 with a special pointer, called the next emptY register (N~R)
14 pointer, pointing to the head of the list of emptv slots.
The NER is located in the PC 4, unlike the index which is
16 in the refresh buffer 28. T~he NER can, however, he located
17 within the refresh buffer 28. When a slot is needed for
18 data, it is removed from the empty list and threaded to the
19 proper Y-line list. ~en a data is cleared, the slot is re-
threaded to the empty slots.
21 To read out for displav refresh, the index halfword
22 for the desired Y-line dvnamic data is accessed, and from it
23 the first slot in the list is entered. This data is used
24 while the pointer field in the slot permits accessing the
next slot. The last slot is recognized bv its EOT bit, and
26 the process is repeated for background data, after which
27 data for the next Y-line is read.
28 The 8K halfwords or memorv are divided into two
29 groups, the indsx and the data slots~ The index consists
of 960 halfwords with the even numbered words pointing to
WA9-74-001 -25-
1l)~3~317
1 the dynamic data and the odd numbered halfwords pointing
2 to the bac~ground data. The remainder of the memory is
3 organized into data slots of four halfwords each. Data
4 slots start on double-word bounda~ies.
The refresh buffer 28 co~nicates with the PC 4
6 via the displav adapter 30 described previouslv. Data
7 words are transferred from the displaY adapter 30 to the
8 refresh buffer 28 on a shaxed bi.directional halfword bus.
9 All update and diagnostic operations are accom-
plished bY se~uences of read and write commands from the
11 display adapter 30. The PC 4 also has the capabilitv of
12 commanding that any displav be inhiblted. Whenever a
13 refresh buffer 28 is selected it senses the inhibit/enable
14 line, and either inhibits or enables refresh according to
its state. This capability permits one-hundred percent of
16 the refresh buffer time to be devoted to update the back-
17 ground data.
18 A complete displav update can be accomplished in
19 less than 42 milliseconds, worst~case, with the average
update requiring less than 33 milliseconds ~one frame
21 time). During an update, the display would be inhibited.
22 The displaY adapter update formats, shown in Figure
23 2 consist of the vector formatr the svmbol format, the
24 index format and the emptv slot ~ormat. The cursor is
generated as a special svmbol positioned bv the PC 4 and
2~ identified b~ the operator through its unigue shape and
27 color. As an alterna~ive, two vectors could be used.
28 Vectors reguire a four halfword slot per vector.
29 S~mbols require a four halfword slot per set of up to
four se~uentia]. symbols. Single svmbols also require
WA9-74-001 -26-
~L0538~7
1 the same size slot, with space code ~or the last three
2 s~mbols. The meaning of the fields.is.next discussed.
3 Refresh buffer data is stored in the refresh
4 buffer 28 as received from the displa~ adapter 30 in
the following formats of Figure 2~
6 The index forma~ contains three fields. l) P.o~inter-
7 The eleven high order bits of the aiddress of th~ first
8 data slot to be read for displav refresh; 2) End of
9 Thread (EOT)-If "1", indicates no data present; 3) End
of Display (EOD)-If "I", indicates last line of displaY.
11 The vector format has eleven fields.- l) Pointer-
12 The eleven high order bits of the address of the next data .
13 slot to be read for display refresh; 2) Horizontal Li-ne (EL)-
14 If ~1", indicates horizontal line; 3) Vector/S~mbol (~/S)-
A "1" indicates vector; 4) Flash (FL)-If "1", the vector
16 flashes at one Hz rate (0.5 seconds, 0.5 seconds off); '.
17 5) End of Thread (EOT)-If "1", indicates that no more data
18 slots are to be read from this list for displav refresh at
19 that Y-address; 6) Slope-If HL= "O", slope is sixteen bit .
inverse slope (~X/Q~). If HL= "1", slope is the length of
21 the line; 7) X-The X position of the start (top) of the
22 vector or the left end of a horizontal line; 8) C.olor- ~.
23 Three bits to specifv one of seven colors; 9) Shift-If
24 "O", slope is interpreted as a six bit integer and 10 bit .
fraction. If "1", slope is interpreted as 10 bit integer
26 and 6 bit fraction; 10) Sign-If hOIl, vector runs from left
27 to right. If ~1: vector runs from right to left. A.ll
28 vectors run from top to bottom: ll) AY-The difference.be-
29 tween the starting ana ending Y-line of the vector. -'
WA9-74-001 -27-
. .'
:~OS381~
1 The svmbol format has twelve fields. l) Pointer-
2 ~ame as a vector format; 2) Lower ~rder S~ace-5ee high order
3 space; 3) Hi~h Order ~S~ace/L-ow ~rde~r S~ace-The high order
4 space and the low order space fields determine the spacing
~0-31 raster elements) between leading edges of the svmbol -~
6 defined bY the slot; 4) Vector/SVmbol (~/5)-~ "0" indicates
7 sYmbol; 5) ~lash (FL)- Same as vector format; 6)- ~nd of
8 Thread (E~T)-Same as vector format, 7) X-The X position of
9 the left edge of the 16 bY 16 arraY containing the first
symbol; 8) Color-Same as vector format; 9-12) Sv~bols (S1
_
11 S4)-Eight bit codes used to specify symbols.
12 The emptY slot format has two defined fields.
13 1) Pointer-The eleven high order bits of the address of the
14 next slot in the list of emptv slots; 2) End-of Thread_(FOT)-
If "1", indicates that the slot is the last in the list of
16 emptv slots. ;
17 The interface with the intermediate buffer 32, shown
18 in Figure 13, consists of five control and sixteen data lines. `'
19 Communication is initiated bv the data reauest line. Data is ''~
then transferred on a demand/response basis, under control of
21 the data present/data accepted lines. The re~uest continue
22 line is used during multiple transfers. An additional line,
23 word one present, ensures that the intermediate buffer 38
24 and the refresh buffer'28 operate in address svnchronism
during multiple transfers. Data is transferred to the
26 intermediate buffer 38 in the same formats in w~ich it is '~
27 stored in the refresh buffer 28, except that the ll-bit
28 pointer field is replaced bY a 9-bit Y-line field. '
WA9-74-001 -28-
`` 1~53~3~iL7
1 Refresh Buffer ~peration: This section describes
2 how read and write commands are used to initialize the
3 refresh buffer 28, add data, delete data and erase back-
4 ground or dvnamic data.
Initiation: Prior to operation, the refresh buffer
6 28 must be initialized. This is accomplished in two steps.
7 First the index is preset bv writing a halfword with EOT =
~ "1" into each index location in the refresh buffer 28 except
9 the last index location which is written with a halword
containing EOD = "1".
11 The data slots are then threaded bv writing into
12 the first word of each slot except the last, a halfword
13 containing EOT = "0" and the eleven high order bits of
14 the address of the irst halfword of the next slot. The
last slot is written with a halfword containing EOT = "1"
16 and the PC loads the address of the first slot into its
17 next empty register pointer (NER), completing the initiali-
18 zation of the refresh buffer 28. Initialization is
19 facilited bY having all write commands specifv inhibit
display.
21 In order to ensure that proper threading of the
22 refresh buffer-28 is maintained, the refresh buffer 28 is
23 not onl~ initialized whenever the PC 4 does initial
24 program load, but is also reinitialized whenever the entire `
display is erased.
26 Add Data: To add a vector or a string of up to
27 four symbols, the PC 4 goes through the following steps:
2~ 1) Read backqround or dYnamic index word, as re~uired for
29 ~-line to which data is to be addressed. 2) If EnT bit in
NER = "0", read first halfword of slot pointed to bY N~R.
31 If EOT = "1", all slots are full. 3~ Using EOT bit and
WA9-74-001 -29-
, : , . . . .
~ 38~7
1 pointer from index word and data from host, assemble four
2 halfwords and write slot of step 20 4) Using pointer from
3 NER (pointer to slot read), write pointer and E~T = "0"
4 in index word of step 1. 5) Load EOT bit and pointer from
halfword read in step 2 into NER.
6 This completes the data addition. The slot at the
7 head of the list of empty slots has been selected and load-
8 ed and the NER now points to the next slot in the list The
9 index points to the newly written slot which now points to
any previously written data.
11 Delete Data: To delete a data item, the PC 4 goes
12 through the following steps: 1) Read background or dvnamic
13 index word, as re~uired, for Y-line from which data item is
14 to be deleted. 2) Using pointer from index, read data slot.
If EOT = "1", PC reports "not found" to host and exits.
16 3) Compare slot contents with data to be deleted. 4à) If
17 match, write EOT bit and pointer from slot in index and go
18 to step 7. 4b~ If no match and slot EOT = "1", report "not
19 found" to host and exit. 4c) If no match and slot EO~ =
0, use pointer from slot to read next slot. S) Compare slot
21 contents with data to be deleted. 6a) If no match and EOT =
22 "1", report "not found" and exit. 6b) If no match and ~OT =
23 "0", use pointer from slot to read next slot and go to step
24 5. 6c) If match, write EOT bit and pointer o~ matching slot -~
in slot which pointed to matching slot. 7) Write FOT bit
26 and pointer from NER into matching slot. 8) Load ~OT = 0 and
27 pointer to matching slot into NER.
'~ ' .
WA9-74-001 -30-
.. . . .
::: .. . - . . . . . .
1~ 3 ~ ~7
l This completes the da-ta deletion. The data has
2 been located and bridged around in its list or, if it ~as
3 the only item in the list, the ~T in the index has been
4 set to "1." The slot which containecl the data has been
added to the head of the list of empty slots.
6 Erase Dynamic Data: To delete all dvnamic data,
7 the PC 4 goes through the following steps: l) Read f~rst
8 dynamic index halfword. 2a) If EOT = "l", go to step 7.
9 2b) If E~T = "0", use index pointer to read first half-
word of data slot. 3a) If EQT = "l", go to step 4. 3b)
ll If EOT = "0", use data slot pointer to read first halfword
12 of next data slot. Repeat step 3. 4) Write NER into first
13 halfword of last data slot. 5) Load EOT = "0" and pointer
14 from index into NER. 6) Write ~OT = "l" into index~ 7a)
If last dynamic index, exit. 7b) If not last dynamic index,
16 read next dvnamic index. 8) ~o to step 2.
17 This completes the erasure. ~ach dynamic index
18 halfword has had its ~T bit set to "l" and all lists of
l9 d~namic data have been threaded to the list of emptv slots.
If the command from the host was erase-add, the new data
21 can now be added. ~;
22 The refresh buffer 28, shown in Figure 3, consists
23 of 8K halfwords of memorv, and addressing and control iogic.
24 It intaraces with the display adapter 30 and the inter-
mediate buffer 38. Simultaneous renuests for service are
,
26 resolved bY the prioritY control 60.
27 When the refresh buffer 28 is selected bv the ~i
28 displav adapter 30, and the prioritv control 60 permits,
39 the control logic 62 gates the display adapter 30 address
~:
~f .
WA9-74-00l -31- ~
::.,: :.
. ".'
`-` 1.~53~7 ~
1 bus through ~he memorv address register multiplexer 64
2 (MAR MUX) to the memorv address register (~AR) 66 and
3 initiates a read or write cycle as required. During
4 write cvcles, the display adapter data bus 68, which is
the only data source for the refresh buffer 28, is
6 loaded into the memory 70. During read cycles, the
7 addressed memory location is loaded into the memorv data
8 register (MDR) 72 and gated onto the displav adapter data ~;
9 bus 68. At the completion of the operation, the control
logic 62 sets the read/write complete line, the display
11 adapter 30 drops its request, and the control logic 62
12 drops read/write complete. The displav adapter 30 then
13 either drops its refresh buffer select line or changes
14 the address and requests another memorY operation.
When the intermediate buffer 38 requests data
16 and the priority control 60 permits, readin~ of the
17 refresh buffer 28 for display contin~es from where it lef~
18 off. For convenience, assume that the first Y-line is about
19 to be read.
The control logic 62 gates the refresh Y counter
21 through the MAR MUX 64 into the MAR 66 and initiates a
22 read c~cle. When the index word is in the ~DAR 77, the ~OT
23 and EOD bits are checked. If EOT = "1", there is no data,
24 the refresh Y counter is incremented and operation repeated. ;
When the last inde~ word is read, the EOD bit is "1" and
26 a status bit is set and the refresh Y counter reset for
27 the next field.
28 When an index word with EOT = "0" is found, the
29 pointer field from the MDR 72 is loaded into ~he 11 high
order bits of the MAR 66 and "0"s are loaded into the
WA9-74-001 -32-
.: . - , : :
~(~5~817
1 two low order bits. The first word of a data slot is then
2 read. The pointer field and EOT bit from this word are
3 read into a temporarv address register (TAR) 76.
4 ~elect ~ates replace the pointer with the Y-line
number and the data present line to the intermediate buffer
6 38 is set. When the intermediate huffer 38 has taken the
7 data, it sets data accepted and data present is dropped.
8 The refresh buffar 2g does not wait, however, but increments
9 the MAR 66, reads the second word, and sends it to the
intermediate buffer 38 which will be able to accept it bv
11 the time it is available. This continues through the
12 fourth word after which the EOT (in the TA~ 76) from the
13 first word is tested. If it is "1", the refresh ~ counter
14 is incremented and the next index word read; if it is "0",
the TAR 76 is gated into the M~R 66 and the next data slot
16 read.
17 Two status bits are provided. The first, which
18 has alreadv been discussed, is set at EOD and reset at
19 vertical retrace. The second retains the displav inhibit/ `~
enable status from the most recent selection bv the
21 programmable controller 4.
22 The prioritv control 60 examines the status ~its
23 and re~uests service. The prioritv scheme is that the
24 intermediate buffer 38 has top prioritv except when dis-
plav is inhibited and during the ~eriod from EOD to
...'. . ..
26 vertical retrace. When the displa~r adapter 30 has been
27 granted service, however, it remains in control untll
28 its refresh ~uffer 28 select line drops.
29 Paritv is checked with each memorv read and
parity errors reported to the displav adapter 28. The ;~ ~
31 PC 4 can re~uest status of the refresh buffer 28, in ` ~`
,,. ~.
WA9-74-001 -33- ~
.: . - . ' , . . .
1053~7
,~, -
1 which case error bits (one for each hal~ of memorv) and
2 an inhibit/enable bit are gated onto the data bus 68.
3 An alternate embodiment of the refresh buffer
4 28 is disclosed in the UnitedhStates'copending application
Serial Number 335,388 by A. A. Schwartz, et al., assigned
6 to the instant assignee. Schwartz discloses the threaded
7 ~ueue buffer 200 in his ~igure 12 which can be emploved ~'
8 as the refresh buffer 28 herein.
g Intermediate Buffer ~peration: The intermediate
buffer 38 serves as a high-speed scratchpad memory for the
11 vector 42 and svmbol 40 generators. It consists of thirtY-
12 two 256 x 1 high-speed random access memorv modules 20,
13 a 32 bit input register 78, and the read and write
14 addressing and control necessar~ for proper operation as
shown in Figure 4. The memorv is divided into two e~ual'
16 areas, an active area and a preload area.
17 Data is initiallv written from the refresh buffer
18 28 into the preload area, se~uentially bY Y-line, until
19 the preload area is full. As each TV raster line is
generated into the PRAS 44, the data words for that line
21 are read from the preload area into the appropriate svmbol
22 40 or vector 42 generator. Reading from the preload
23 area continues until the data for the Y-line being
24 ganerated has been completelv read out, or until the ~re- ''
load area becomes emptv. ~nce a preload location has ~''''
26 been read out, it is available for more data ~rom the '
27 refresh buffer 28. Since the preload area contains 128
28 32 bit locations, no more than 64 vector crossings/4-
29 symbol groups per line mav be accomodated, since each ~"
vector/symbol group requires 64 bits, or two memorv
31 locations.
- '.
WA9-74-001 -~4-
. , . ~ , , .
.
~053!317
,,
1 The active area contains the data whi~h is being
2 displayed at anv given line time. The data is read each
3 line, strobed into the appropriate vector 42 or svmbol
4 40 generator, where it is modi~ied and rewritten back
into the active area. When the vector 42 or svmbol 40 r
6 generators detect an end to the dat:a, it is not written
7 back. The active area is read and written, starting at
8 the same address. The read address is constantlv compared
9 to the last address written on the previous Y-line. When
a compare is made, it indicates that all of the data in
11 the active area has been read and strobed into the vector
12 42 or svmbol 40 generators. At this time, the preload
13 area is tested for a ~-line compare and any data available
14 is read from that area.
Normal ~peration of Active Area: The active area
16 is defined as the memorv locations between the address 000
17 and 177 octal, inclusive. Vector/symbol data is loaded
18 starting at 000 and counting up.
19 Figure 14 is a block diagram of the addressing
~ . .
logic 92 and Figure 15 shows an implementation of the
21 timing. During horizontal blanking, the contents o~ the
22 write counter 82 is strobed into the last address written
23 register 84. The counter 82 is then reset to the starting
24 value (000). ~ -
The vector/svmbol read complete comparator 86 is
26 tested; if this test is negative, a read cvcle is
27 initiated using the vector/svmbol read counter 88 to
28 address the MAR 80. The function code is tested and
29 the data loaded into either the vector 42 or svmbol 40
generator. The sample and read cvcle is repeated until -
31 one of the following occurs:
".
WA9-74-001 -3~- ~
` .
:~OS~ L7
_
1 1. ~ data present signal is received from the
2 refresh buffer 28. This causes the read cvcle in process
3 to be completed, Control is then switched to the preload
4 area, and the refresh buffer 28 data is loaded into the
proper preload address,
6 2. A vector generator busv signal is received
7 from the vector generator 42 and the word bein~ read is a
8 vector word. This causes the intermediate buffer 38 to
9 wait until the vector generator 42 goe~s not busv or until
conditions 1 or 4 occur. ,
11 3. A symbol generator busv signal is received
12 from the symbol generator 40 and the word being read is a
13 svmbol word. This causes the intermediate buffer 38 to
14 wait until the symbol generator 40 goes not busv or until
conditions 1 or 4 occur.
16 4. A write re~uest is received from the svmbol
17 40 or v0ctor 42 generator. This causes the svmbol or -
18 vector data to be loaded into the input buffer register 78. ,'
19 The read c,vcle in progress is completed, and a write
cvcle is initiated using the vector/svmbol write counter
21 82 as the address. This counter 82 is then incremented. ~-
22 ~link ~peration: The blink operation is per-
23 formed at the input to the intermediate buffer 38. The
24 s,vnc and timing generator creates a blink signal which ~'
is a "1" for 1/2 second and 1l0ll for 1/2 second. T^~henever
26 the blink signal is a "1", the blink control logic gn
27 is enabled to sample the data words from the refresh
28 buffer 28. When a blink bit is detected the write cvcle " '
29 is ignored and the sYmbol or vector word associated with '"
the blink bit i~ not loaded into the intermediate buf~er ; ;
..
WA9-74-001 -36-
~3 ~7 t
1 38. When the blink signal is a "0", the blink control
2 is disabled and all words are loaded into the intermediate
3 buffer 38.
4 Normal operation - Preload Area 94: The preload
area is defined as the memorv locations between addresses
6 200 and 377 octal. Figure 16 is a diagram of the read and
7 write address control re~uired. The counters are the same
8 as those in the active area except for the vectorfsvmbol
9 next Y-line registers 96 and comparators 98, 86 and 102.
Writing is initiated bv the refresh buffer 28 with
11 the data word being loaded into the appropriate address of
12 the preload area. The Y-address of the first word written
13 into each sector is loaded into the appropriate next Y-line
14 register 96. As the active section becomes emptv, the Y-
line register is compared to the Y-address of the next line ~-
16 to be displayed (from the sync and timing generator 100).
17 When a compare is made, a read cvcle is initiated and the
18 data is strobed into the appropriate generator 40, 42. The
19 read counter 88 is incremented and another read initiated.
The Y-address of this word is then loaded into the next
21 Y-line register 96 and compared to the Y-address of the
22 next Y-line. The procedure is continued until a Y-code
23 is loaded which does not compare. At this time, the read -;24 counter 88 is not incremented and the read enable line is
dropped until a compare is again detected.
26 The address counters 82 and 88 in the preload
27 area are cYclic. When initialized, they are set to their
28 minimum value. The write counter 82 is incremented after
29 each write from the refresh buffer 28 until it reaches its
maximum value. The next write causes it to be reset to
. ~ . , .
W~9-74-001 -37-
' ."
. "'' ' . ' . .
. . .
B~L7
,~
1 minimum value. The read counter 88 operates in the
2 same manner being incremented after each read operation.
3 Thus the write counter 82 is alwaYs ahead of or e~ual to
4 the read counter 88. Write o~erations from the refresh
buffer 28 are continued until the preload area is fuil
6 which occurs when the write counter 82 is so far ahead of
7 the read counter 88 that one more write would cause data
8 to be overwritten which had not vet been read. This is
9 tested at the end of each write cYcle when the write
address counter 82 is incremented. It is compared to
11 the read address counter 88, and when e~ual, the preload
12 area full signal is enabled. Mo more write operations -
13 are initiated until at least one read operation has been
14completed. -~
15Read operations are continued under control of
16the Y-compare circuitrv 82, 88 and 102 until the preload
17 area is emptv, which occurs when the read counter 88
18 catches up to the write counter 82. This is tested at
19 the end of each read cYcle when the read counter 88 is
incremented. It is compared to the write address counter
21 82, and when equal, the preload area emptv signal is
22 enabled. No more read operations are initiated until
23 at least one write operation has been completed.
24Data Initialization: The intermediate buffer 38 is
initialized during each vertical blanking period bv
26 setting all of the counters 82 and 88 to their initial
27 values. The refresh buffer write is then enabled and
28 the preload area of memor~ 80 in IB 38 is filledSwith all
29 of the data which is to start at the top of the screen
loaded first. The Y-line compare circuitrv 98 is enabled,
WA9-74-001 -38-
- lOS3~
1 and any data which begins at the top of the screen is
2 read from the ~reload area of memorv 80 in IB 38 and
3 strobed via line 200 into the appropriate svmbol 40 or
4 vector 42 generators. A special control signal prevents
the generators 40 or 42 from modifYin~ the data, and it
6 is simplv written back, as received, into the active area
7 of memorY 80 in the IB 38 over line 207. The operation
8 is continued until either the active area of memorv 80
9 in IB 38 is filled or the Y-compare circuitrv g8 out~ut
is low, indicating that there is no more data for that
11 line address. When the vertical blankinq period is over,
12 the active read circuitrY 88 is enabled and operation
13 continues as normal. ;
14 The symbol generator 40 has a repertoire of 256
programmable sYmbols, each defined by a 16 bY 16 matrix.
16 Fonts this size or smaller can be directlv accommodated.
17 Larger fonts can be implemented by combining sYmbols.
18 Symbols are generated in groups of four. The
19 svmbol generator 40 locates svmbols based on the X, Y
address of the top left corner of the 16 bv 16 matrix,
21 accesses the sYmbol one segment at a time, and loads it
22 into the PRAS 44. ~ -
23 The symbol words which are loaded into the
24 refresh buffer 28 contain an X-address, an implicit Y-
address, a color code ~3 bits), and up to four svmbol
26 codes. Another bit is also provided to specifv the
27 blink attribute. When two, three, or four symbols
28 are packed into one data word, the color and blink
29 attributes apply to all.
WA9-74-001 _39_ -
,.
538~7
1 Figure 5 is a block diagram of the symbol qenerator
2 and Figure 17 presents a timing diagram for seauential
3 svmbols. The data, as read from t:he intermediate buffer 38,
4 is in the following form:
32 Bits 4 svmbol codes
6 10 Bits X position of leftmost bit of leftmost svmbol
7 5 Bits spacing
8 1 Bit startinq field
9 4 Bits segment code
3 Bits color
11 These are loaded into the input registers 104, 106, 108, 110,
12 112 and 114 and the first svmbol code is selected for input
13 to the symbol memory 56.
14 ~he spacing is used to generaté ax, which is added
to the X-write register 116 after each sYmbol generation, to
16 provide inter-svmbol spacing for se~uential sYmbols. Up to
17 four sequential symbols mav be generated.
18 The segment code determines which line of the svmbols
19 is to be read from sYmbol storage 56 in symbol generator 40. ~
It is incremented after each line and written back over line ~-
21 202 into the intermediate buffer 38. When the segment code
22 indicates that the sYmbol is complete, the s~mbol word is
23 not rewritten. -
24 Data Format for Vector Generator: Vector data is
transmitted bv the host processor in the format shown in ~-
2~ Figure 2. Each vlector has its own startinn point ~specified .~!
27 as the uppermost point on the vector), a length in the Y-
28 direction (aY) and an inverse slope (~X/~Y, in signed
29 magnitude form).
..
WA9-74-001 -40-
1~538~'~
1 The vector generator 42 uses an algorithm wherebv
2 the length of a horizontal line segment is determined by
3 the value of ~X/~. Adding or subtracting this value to
4 the starting X address gives the starting point for the
next line segment. Figure 18 is a simplified block
6 diagram of this operation.
7 The starting X position, the value of ~X/AY and
8 the value of ~Y are received from the intermediate buffer
9 38 and loaded into the appropriate registers 118, 120
and 122 res~ectivelv. Two transfers are re~uired to
11 collect all the needed data. The X starting address for
12 the first horizontal line segment is transferred to the
13 Xl register 124. ~X/~Y is loaded into the ~Xl register 126.
14 The value of ~Y is decremented by two and if zero detect
128 determines it is not greater than or e~ual to zero,
~X
16 the values of X position ~ 2 ~ X/~Y and ~Y are written
17 back into the intermediate buffer 38 over line 202 as the
18 data needed to generate the next line segment of that
19 field. When ~Y goes negative, the vector is completed
and the data is not written back.
21 Figure 19 shows an exam~le of a vector drawn from
22 coordinates X = 50, ~ = 50 to coordinates X = 70, ~ = 42.
23 In order to obtain the closest approximation to the actual
24 vector, the first and last horizontal line segments are
~X ::
calculated using 1/2 ~ as the addend. Thus on TV line
26 50 a horizontal vector is plotted from X = 50 to X = 51,
27 on line 49 a horizontal vector is plotted from X = 52 to
28 X = 53, on line 48 from X = 54 to X = 56, and so forth. -
29 The last segment is plotted from X = 69 to X = 70.
WA9-74-001 -41-
:
- .. .. . . . . .
- 1~53817
1 Figure 6 is a detailed hlock diagram showing the
' ~X
2 data flow in the vector generator 42. X, ~Y and ~ are
3 loaded into registers 118, 122 and 120 respectivel~, over
~X
4 line 200 from the intermediate buEfer 38. ~ is a 16-bit
word with a shift control bit which determines whether the
6 16-bits are to be added to the 16 most significant bits
7 (MSB) or to the 16 least significant bits (LSB) of the
8 20 bit X-value. This shift bit, along with controls 132
9 which detect that it is the first or last horizontal
segment to be generated, control the MUX shift logic 130
~X
11 to align the value of ~Y at the correct position in the
~X
12 ALU 134, 136. The shift bit e~ual to a "one" causes ~ to
13 be added to the most significant bits of X (the most
~X ,
14 significant bits of ~ is added to the most significant
bit of X) in ALU 136. If the segment to be generated is
16 the first or last segment the value of ~ is shifted one
dX
17 bit right (the most significant bit of ~Y is added to the
18 next most significant bit of X in ALU 136).
19 Whenever the vector starts on the field opposite
to that being displayed, an extra calculation is performed
21 to generate the first segment. Xl register 138 gets loaded
22 with the value of X received from the intermediate buffer `
23 38 plus (or minus for positive slope vectors) l/2 (~X/~Y)
24 + 1. Figure 19 serves as an example. If line 49 is to
be generated, the address register 119 is initially loaded
26 with 50.
27 1/2 ~X/~Y = 1.25
28 Therefore Xl register 138 is loaded with 50 + 1.25 ~ 1 = 52
29 The value 52 is loaded into the Xl register 124
and the ten most significant bits of (~X/~Y) - 1 are loaded
31 into the axl register 126. For vectors with slopes > 45,
WA9-74-001 -42-
38~7
.
1 the aXl register 126 is reset to zero, causing a single
element to be written on each raster line. For the first
element of a positive vector ~45, (1/2) ~X/ ~Y is sub-
tracted from the contents of the X address register 118.
If the sum or difference of the 10 least significant
bits of the X address register 118 and ~X/ ~Y in the 20
bit ALU 136 results in a carry to or borrow from the 10
most significant bits, then ax is just ~X/ AY.
~Y is decremented by ~, and checked for sign.
If it is non-negative, a new starting X address for X
address register 118 must be determined. 2 ~X/ ~Y is added
or subtracted from the value in X address register 118, as
determined by the sign of the slope. This value, along
with aX/ aY and ~Y, is reloaded over line 202 into the
intermediate buffer 38. A negative ~Y count means the
vector is complete and the data is not written back into
the intermediate buffer 38.
The eight most significant bits of the Xl register
124 are sent to the PRAS address register 144 in PRAS 44
and least to significant bit pair 0 and 1 and bit pair 5
and 6 to the X shift control 146. The ~Xl register 126
value is sent to the X length control 142 and zero detect
148. A major and a minor PRAS exist in PRAS 44 to receive
four bits of vector data. For a transfer to the major
PRAS each bit transferred represents 32 bits of data.
Thus, in a four bit transfer to the major PRAS, 128 bits
of data are actually transferred. To the minor PRAS, each
bit transferred represents just one bit. In the case of
a minor PRAS transfer, the two lowest significant bits of
Xl are decoded through the X shift control 146 to pro-
vide a 4 bit word with ones in the bit positions
WA9-74-001 - 43 -
105~1~17
1 corresponding to the starting X address. The QXl value
determines the number of ones to be written. For the
first write to the minor PRAS, ~Xl is compared with the
two lowest significant bits of Xl to determine how many
bits are being written. This number is subtracted from
- dXl to determine the number of bits to go. Thereafter,
- writes of 4 bit words (all ones) are made to the PRAS
44 and the eight most significant bits of aXl decremented
until zero is detected. The two lowest significant bits
of ~X are then decoded to generate the number of "ones"
that remain to be written. Thereafter, another 4 bit
write to PRAS 44 is performed with only those bits set to
1, thus completing the vector generation.
For shallow angle vectors, it is desirable to cut
down the number of 4 bit transfers to the minor PRAS by
performing transfers to major PRAS. During vector genera-
tion, when a 32 bit X address boundary is reached, the
five most significant bits of ~X are checked; if not
zero, the two lowest significant bits of these are direc-
ted into the X length control 142 and the correspondingbits of X are directed into the X shift control 146. The
operation parallels that of a minor PRAS transfer. When
zero is detectecl in the five most significant bits of X,
the transfer mode is switched back to that of the minor
PRAS to finish up the vector.
The PRAS 44 consists essentially of two one-line
buffers 150 and 152 operating in an A-B arrangement. As
one buffer is being read and displayed, the other is
being loaded with the data for the next line. Data is
30 loaded into PRAS 44 from the vector 42 and symbol 40
WA9-74-001 - 44 -
~ ,
- . ~
?- ~enerators in 4-bit words. The ~RA~ memories 150 and
2 152 are controlled so that only ones are written which
3 allows an accumulation of data to occur. Thus, there are
4 no restrictions on vector or svmbol crossings since anv
number of data intersections mav occur at a given point.
6 As has heen previouslv discussed, there are, in realitv,
7 two PRAS's: a major PRA~ 20-bit :Length with ea~h hit
8 representing a string of ~2 bits on the display line and
9 a minor PRAS representing a point-for-point ima~e o~ the
raster display line. The major PRAS is used onlY for
11 vector generation.
12 Refresh Cycle ~peration of the P~AS: The
13 refresh cycle consists of a read cvcle followed bv an
14 erase cvcle. The erase is done to restore the lin`e
buffer 150 or 152 to an all-zero condition so that the
16 next line of datà can be loaded. Figure 7 is a block
17 diagram of the PRAS 44. A buffer-select flip flop 154
18 selects which of the line huffers 150 or 152 is to be
19 in refresh. The address multi~lexers 160 and
162 are then enabled to ~ate the read address counter ~-
21 164 to the correct line buffer 150 or 152. The data
22 lines are set to write zeros and the input data multi-
23 plexers 156 and 158 are set to allow a write enable
24 pulse. The output multiplexer 166 is also set to enable
reading from the correct buffer 150 or 152. Figure 20
26 de~ails the timing of the refresh c~cle. As can be
27 seen, the aata is read into the parallel-to-serial
28 converter 168 and then a write enable pulse is generated.
29 The data lines are held at zero causing all bits to be
~,
WA9-74-001 -45-
. .
- ~ . ,;
. ~ . - . . .. . . . 1 ,
105;~8~7
7 reset. The output of the parallel-to-serial converter
2 168 is a serial digital video stream which contains the
3 vector and svmbol video. The output of the ma}or and
4 minor PRAS are ORed together, such that a 1 from the
major PRAS will generate a serial stream of 32 "ones".
6 The line buffer 150 or 152 which is not in refresh
7 is in a load cvcle. When in this mode the data to be dis-
8 plaved on the next TV line is written. The input data and
9 address multiplexers 156 -162 are set up to select data
from either the vector 42 or symbol 40 generator. The
11 data to be written is strobed into the input re~ister 170,
12 and the address ~o be written is strobed into the write
13 address counter 144. The line buffer data inputs are
14 set to "1" since onlv "ones" are to be written. The data
multiplexers 156, 158 select the output of the data register
16 which is used to set the write enable inputs of the line
17 buffer. In this wav only the locations corresponding to
18 a "1" in the data register receive write enable signals,
19 and a zero in the data word will not erase a previouslv
written "1". The input register 170 continues to be
21 loaded and the write counter 144 incremented until the
22 operation is completed. Since svmbol and vector data are
23 always loaded from left to right, the write address
24 counter 144 need only be an up counter.
Video Output: Video output from the controller
26 8 to the console 16 is provided over three cables. The
27 cables provide the red, green, and blue primarv color
28 signals to the TV monitor 10. One of these also contains
29 synchronization information so that the color monitor
may be properly svnchronized.
WA9-74-001 -46- -
- ` ~053817
1 Sync and Timing: The video waveform can conform to
~ the specifications of El~ standard R~-170. This will provide
3 a 30 Hz refresh, 2-to-1 interlaced raster. The 3.58 MHz
4 color burst is not used. This is because the color signals
are sent to the monitor on 3 separate lines representing the
6 red, blue and green video signals, and not on a single line
7 in composite form as with a encoded color signal. The use of
8 separate RGB signals provides higher bandwidth color (up to
9 7MHz) than is available with encoded color signals. Figure 21a
shows the sync generator block diagram and Figure 21h the
11 resulting raster. The total raster is shown including hlank
12 regions which are not visible. The numbers horizontallY
13 indicate bits per raster line and the numbers verticallY
14 indicate number of raster lines.
A base oscillator 172 of 11.97MHz is used to gener-
16 ate the basic clocking signal bit rate along a raster line.
17 Its divided bv a 380 counter 174 from which are decoded
18 176 blanking, svnc, eaualizing, and vertical sync signals, all
19 at twice the line rate (31,500) The 178 divided bv 525 and
180 divide b~v 525 and 180 divide bv 2 countèrs are decoded bv
21 decoder 302 and used to select these signals such that the
22 even signals are selected for an even display field and the
23 odd signals are selected for are odd display field to pro-
24 vide the horizontal svnc and blanking output signals.
~ecoders 302 are also provided to select the eaualizing and
26 vertical sync pulses at the proper time to generate a
27 composite waveform.
WA9-74-001 -47-
'' .,
. . .
: . . . ~ . . ~, ,
- ~OS3~17
.--
1 Thus it i5 seen that the video qenerator circuit
2 invention stores graphic and alphanumeric dlsplay data so
3 as to be more efficientlv accessed for display than has
4 been capable in the prior art, bv c~clicallv storing the
S display data in a coded form which is sequentiallv modified
6 as the raster field is generated.
7 While the PRAS 44 has been disclosed as storing
8 two raster lines of video output data, the basic svstem can
9 be modified to accommodate a PRAS with a storage of more
raster lines. The numher of raster lines to which data can
11 be sorted in the refresh buffer could also be modified
12 without departing from the spirit of the invention dis- -
13 closed. The disclosure of the particular nDTV svstem in
14 which the video generator circuit invention can be
emplo,ved should not be construed as limiting the
16 applicability of the invention to other display svstems
17 employing on-the-flv refresh techni~ues.
18 While the invention has been particularlv shown
19 and described with reference to preferred embodiments
thereof, it will be understood by those skilled in the
21 art that the foregoing and other changes in form and
22 details may be made therèin without departing from the
23 spirit and the scope of the invention.
24 - We claim: '
WA9-74-001 -48-
