Note: Descriptions are shown in the official language in which they were submitted.
I'l{N 806~
BKs/vo~ /cB
25.5. 197G
lOS9Z40
"5~}icon~c-~r dcvie~.~'
The invention relates to a semi-
conductor device comp:rising a semiconductor body
having at least a bipolar transistor with an
; emitter zone of a first conductivity type
adjoining a surfaGe of the body, a likewise
i surrace-adjoining base zone of the second
~ conductivity type which within the body surrounds
s the emitter zone entirely, and a surface-adjoining
collector zone of the first conductivity type,
~¦ 10 the base zone comprising an active base region
~ and a base contact region which is associated
j therewith and which is deeper ænd more highly
doped than the active base region and, like the
emitter zone, is contacted at the surface, in
which the collector zone comprises a surface- -
adjoining collector contact region of the first
i conductivity type which is contacted at said sur-
3 face and has a higher doping concentratibn than
the adjoining semiconductor material and in which,
viewed in a direc-tion parallel to the surface,
the active base region is present between the
base contact region and the collector contact
3 region, the emitter zone, the active base
~s region, the base contact region and the collector
contact region being provided in and having a
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~059Z4()
diffcrent doping than a surface-adjoining
subst;an~ia].ly homogeneously doped semicondllctor
layer wh:ich surrollnds the collec-tor contact
region and the base regions.
The invention relates in addition
to a particul.arly suitable method of manufac-
turing such a semi-conductor device.
A semiconductor device of the above-
described kind is known, for example, from the
~, ~ ~ ~~e /~73
U.S. Patent Specification 3,766,446'! J
In semiconductor technology, and in
particular in monolithic integrated circuit tech-
nology, it is often endeavoured to produce circuits,
and hence semi-conductor circuits, which can be used
up to very high frequencies, for example., up to
frequencies of one or a few Gigaherz (GHz). In
addition it is in many cases desirable for a mono-
lithic integrated circuit to comprise bipolar
- transistors of both the npn-type and of the
type.
Although reaching such very high
frequencies presents technological problems already
for vertical B -transistors, this is the case in
. particular in monolithic circuits having B-
transistors and ~-transistors in one single
epitaxial layer. The ~-transistors are nearly
always constructed as lateral transistors. Therefore,
PlIN 80/~)
~5. 5. 1~17G
:10~9Z40
it is not on].y substantia]ly impossible to make
said ~llp-transistors suitab].e for very high
frequencies, due to the lateral structure and
due to the low hole mobi]ity, but in general the
_~-transis-tors and pnp-transistors provided in
one single epi-taxial layer in this manner will
show electrically importan-t differences due to
their greatly differing geome-tric structure,
which in general is not desirable.
It has been endeavoured to solve
this problem by giving the npn-translstors and
~-transistors both a vertical structure, while
using two or more epitaxial layers present one on
top of the other, but in additinn to the fact that
the provision of several epitaxial layers yields
a considerable technological complication, further
problems occur due to the out-diffusion of the
1 buried layers present at different levels.
¦ In the described known transistor
structure these problems occur to a far smaller
extent, but an important drawback is that in the
kno~n transistor according to the U.S. Patent
~ ~ Specification 3,7~6,446 the emitter zone is
! present for a large part wi-thin the highly doped
base contact region. The emitter-base junction of
the known transistor thus comprises a considerable
part across which substantially no injection of
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PIIN 80G9
25.5 1976
~59Z~O
minoIi.ty charge carrie.rs into the base occurs,
but wllich due to :i.ts eY.tra surface, does increase
the emi.tter-base capacitance considerably, to
which the high doping of the base contact region
contr:ibutes additionally. In particular at low
currents this has a very adverse infl.uence on the
high-frequency characteristics, such as inter
alia the cut-off` frequency.
One of the objects of the invention
is to avoid or at least considerably reduce the
problems occurring in the said ~nown semiconductor
device.
A further object of the invention is
. to provide a semiconductor device having a new
transistor structure which is suitable for~ery ..
high frequenci.es.
Still another object of the invention
is to provide a lateral high-frequency transistor
which, together with a vertical transistor having a
~ 20 structure which is complementary thereto and has
j corresponding electrical properties, can be used
in one single epitaxial layer in a monolithic inte-
grated circuit.
A further object of the invention is
to provide a self-insulating lateral high-frequency
. transistor which is particularly suitable for use in
monolithic integrdted cirouits.
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P~IN 8069
25.5.1976
lOS9Z40
The invent:ion is based inter alia
on the recognition Or the fact that the high-
frequency behaviour of the transistor can be
considerably improved by suitable choice of the
place of the emitter zone in the base region.
The invention is furthermore based on
the recognition of the fact that it is of advan-
tage to use such a lateral transistor structure
that the charge transport in the active base
region immediately adjoining the emitter zone
takes place mainly in a direction substantially
normal to the semiconductor surface. The invention
is also based on the recognition of the fact that
this canbe achieved by ensuringthat the difference
in transit time through the base zone of minority
charge carriers from several points of the emitter
zone to the collector zone is as small as
possible.
- According to $he invention, a semi-
conductor device of the kind described in the
preamble is therefore characterized in that the
emitter zone is present substantially entirely
within the active base region.
- The semiconductor device according
to the invention comprises a lateral transistor
which is capable of a satisfactory operation at
high frequencies in that the width of the active
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25.5. 1'~7G
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base region, taken from the emitter to the
col]ector, can be made very smal] so that the
difference in transit time of the charge carriers
injected from -the various poin-ts of the emitter
to the collector contact region can be maintained
small. Therefore, the width of the active base
region, measured in the direction of the base
contact region to the collector contact region,
is pr~erably at most equal to the smallest dis-
tance between the active base region and the
collector contact region, and is preferably at
most equal to half said distance. The substan-
tially homogeneously doped semiconductor layer
may be of the first conductivity type. However, a
very important preferred embodiment is characterized
i in that the said semiconductor layer is of the
¦ second conductivity type. In fact, said latter
¦ embodiment enables the provision in the said semi-
¦ conductor layer of both high frequency np_-
transistors and ~- transistors, the semiconduc-
tor layer constituting the collector zone of the
vertical transistor. In order to enable a satis-
factory operation and very high frequencies, it is
furthermore desired that the smallest distance
from the collector contact region to the active
base region be so small that the depletion zone of
the collector-base junction extends over the whole
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PIIN 80Gg
25 5 1~76
lOS9240
intermediate, substantially homogeneously
doped sen~iconductor region. The very small
thickness of the (substantially non-depleted)
active base region then is decisive of the
achievable frequency.
When the semiconductor layer is
present on a substrate of a conductivity type
I opposite to that of the semiconductor layer it
j is desirable, in order to prevent the collecting
i 10 of charge carriers emitted by the emitter of
the latter transistor by the substrate, that a
burried layer of the second conductivity type be
present whlch i9 connected to the base contact
region.
~ 15 The invention also relates to a
5, method by means of which the described device can
¦ be manufactured in a very simple manner. According
~ to the invention, this method is characterized in
3 that a first and a second masking layer are
successively provided on each other on the surface
of a substantially homogeneously doped semiconduc-
i tor layer, which masking layers can be etched
selectively relative to each other, that a first
aperture is provided in the second masking layer
at the area of the base contact region to be
provided and a second aperture is provided in the
second masking layer at the area of the collector
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25.5. 197G
~059~Z40
contact region to be provided, that within the first
aperture the exposed first masking layer is removed
by etching, the first masking layer within the
second aperture bcing masked against said etching
process, after which by introduction of a dopant . :.
i determining the second conductivity type via the
first aperture at least a part of the base contact
region is formed which is then covered with an
electrically insulating layer, and that, pri.or to
the formation of the active base region, within
. the first aperture at least the edge portion of the
~ masking layers nearest to the second aperture is
¦ subjected to an etchant which attacks only-one of
the two said masking layers so that said masking
~ 15 layer is etched away selectively over a lateral
'3 distance which is smaller than half and preferably
is smaller than one third of the shortest distance
~' between the first and the second aperture, the
! etched masking layer being masked on its upper side
against said etching process by a mask extending
i thereon up to the edge of the first aperture,
~ after which, via the surface part present below
.~ _
said etched-away portion, the active base region
is provided by the introduction of a dopant deter-
:
mining the second conductivity type, and the emitter
zone and the collector contact zone are formed
by the introduction of a dopant determining the
;,
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; Pll~ 80~9
25.5. 1~7G
~L~592'~
first conductivity type via the said surface
part and the second aperture.
The invention will now be described
`i in greater detail with reference to a few
examples and the drawing, in which
Figure 1 is a diagrammatic plan
~ view of a deviee according to the invention,
j Figure 2 is a diagrammatic cross-
sectional view taken on the line II-II of the
device shown in Figure 1,
Figures 3 to 9 show the device of
Figures 1 and 2 in successive stages of manu-
facture,
Figures 10 to 19 show successive stages
j 15 of a semiconductor device manufactured by using the
method according to the invention, and
Figures 20 to 24 show successive
stages of a modified embodiment of the method
aceording to the invention.
The Figures are diagrammatie and
not drawn to seale. Corresponding parts are as a
rule referred to by the same reference numerals.
For elarity, the boundary of doped
regions, in particular of diffused regions, is in
most of the eases not in aeeordance with-reality
~ but is shown purely diagrammatically. Notably
-' the lateral diffusion is ignored in the drawings.
.,
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PIIN 80~
25.5. 1976
lO~gZ~O
In the plarl view of Figure 1 the metallisation
is shadecl and the boundaries of doped regions
are shown in solid lines.
Figurc 1 is a diagrammatic plan view
and Figure 2 is a diagrammatic cross-sectional
view taken on the line II-II of a semiconductor
device according to the invention. The device
comprises a semiconductor body 1, in this exam-
ple a si]icon plate, which contains inter alia
a bipolar ~-transistor T1. The transistor T1has
an emit1;or zone 3 of a first conductivity type,
in this example a ~-type zone, adjoining a
surf~ce 2 of the body, a base zone (4,5) of the
second conductivity type, so in this example an
n-type zone, which also adjoins the surface 2 and
which surrounds the emitter zone 3 within the body
entirely, and a collector zone 6 of the first
(~) conductivity type adjoining the surface 2.
The base zone comprises an active base region 4
and an associated base contact region 5 which
is deeper and more highly doped than the active
base region 4 and, ]ike the emitter zone 3, is
contacted at the surface ~.
The collector zone comprises a
collector contact region 6 of the first (~)
conductivity type which adjoins the surface 2
and is contacted at said surface 2 and has a
-
-1 1-
~'IIN 80G~
25.5.197G
~05g2~0
hig~ r ~opin~ conccntratioIl than the adjoining
semiconductor material. Viewed in a direction
parallel to the surface, the active base region
4 is present between the base contact region 5
and the collector contact region 6, while the
emitter zone 3, the base regions ll and 5 and
collector contact region 6 have a different
doping form and are provided in a homogeneously
doped, in this example n-type conductlve,
semiconductor layer 7 which adjoins the surface
2 and has a resistivity of approximately 1 to 2
Ohm.cm and which surrounds the collector contact
region 6 and the base regions ~I and 5. Since the
~ . layer 7 in this example is an n-type layer, the
¦ 15 collector la~er is entirely formed by the collector
contact reginn 6; this need not always be the
case since, as will be explained hereinafter, the
regions 3, 4, 5 and 6 may also be provided in a
~-type layer.
I 20 According to the invention, the
j emitter zone 3 is situated substantially entirely
within the active base region 4. As a result of
this, an emitter-base junction is obtained which
takes part in the injection substantially entirely
and has a minimum capacitance, so that, in parti-
cular with low currents, the high-frequency
-properties are considerably improved and inter alia
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25.5. 197G
,
:~05~ 40
the cut off frequency (fT)is increased.
i The base contact region 5 is connected
through the semiconductor layer 7 to an n-type
conductive buried layer 8 and forms therewith
a coherent n-type conductive region. The buried
layer 8 is present between the layer 7 and an n-
type conductive substrate 9 which adjoins same and
~ has a resistivity of approximately 5 Ohm.cm and
j extends down to below the collector contact region
6, in which, however, the region 6 need not be
¦ present entirely above the layer 8. The said
buried layer serves to prevent holes injected by
7 the emitter zone 3 from being collected partly at
the p-n junction 10 which in the operating condi-
tion is reversely biased. When the substrate 9 is
of the same conductivity type as the layer 7, the
buried layer 8 may be omitted, if desired. This
is the case also when the transistor is provided
in a single homogeneously doped body w~thout an
i 20 epitaxial layer. The regions 3, 5 and 6 are
contacted via windows in an insulating layer 11,
- in this example of silicon oxide, provided on the
semiconductor surface 2.
Since~the dimension, taken in-a
direction from the emitter to the collector, of
the active base region 4 in which the emitter is
present can be maintained very small (in ~igure 1
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,
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:`''t`'~ ".".~,,
P~IN 8069
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~C~592~0
the distance a is 1 micron), the di~ference
in transit time of he holes from any point of
the emitter zone 3 to the collector contact
region 6 may be minimum; this is the case in
particular when, as in the present example, the
width a of the active base region 4, measured
in the direction frorn the base contact region 5
to the collector contact region 6, is at most equal
to half the smallest distance b between the active
base region 4 and the collector contact region 6.
In Figure 1 which, as already said, is not drawn
to scale for reasons of clarity, the distance a
is 1 micron and the distance b is 3 microns. This
latter distance is so small that the depletion
zone of the collector-base junction at normal
values of the collector base voltage extends
throughout the intermediate part of the layer 7.
In these circumstances, the charge transport in
this lateral transistor in the substantially non-
depleted active base region 4 takes place by
diffusing emitted holes mainly in a direction
- substantially normal to the semiconductor
surface 2, which considerably improves the
¦ ~ high-frequency properties of the transistor with
respect to those of the conventional lateral
~-transistors. The region between the active
base region 4 and the collector contact region
,
- 1 Ll.
: ' '
PIIN 80G9
25.5. l~)7G
10591240
G is fully deplcted, as already noted, and
heIIce the effecti~e base thickness is very
small, since the depth of the emitter zone 3
is approximately 0.2 micron and that of the
nctive base region 4 is approximately 0.3
microns.
I In the e~ample described the
3 substantially homogeneously doped n-type
semiconductor layer 7 forms part, besides
of the ~-transistor T1, also of a second
bipolar npn-transistor T2 which is complelnentary
to the transistor T1 and which has an n-type
¦ emltter zone 12 adjoining the surface 2 and a
¦ . p-type base zone 13 which also adjoins the
surface 2 and which surrounds the emitter ~one
12 entirely within the semiconductor body, the
collector zone of the transistor T2being formed
by the layer 7 in which, to reduce the collector
series resistance, an n-type buried layer 14 and
n-type contact zones 15 are also provided. A
resistor R is also provided consisting of a p-
type surface zone 16 havlng ~ contact zones 17
and 18. These three circuit elements are sepa-
~ rated from each other by p-type insulation zones
i 25 19
Since the charge tranSport in the
non-depleted region between the emitter-base
-15
!
- . .
PlIN 806')
25.5.197G
lOS9Z40
junction ancl the col]ector-base junction both
in the transistor T1 and in the transistor T2
¦ takes place mainly in a direction normal to
the surface 2, the difference in the gain
characteristics may be maintained small. So the
invention offers the possibility of providing in
one single epitaxial layer 7 two complementary
transistors the characteristics of which are
~ comparable.
¦ 10 The described device may be manu-
~ factured, for example, as follows. Starting
; material (see Figure 3) is a ~-type silicon
substrate 9 having a resistivity of approximately
5 Ohm.cm. Provided on said substrate by a gene-
rally known photolithographic method is an oxide
mask 21 comprising apertures at the area of the
buried n-type layers 14, 8 and 20 to be provided.
These layers are provided, for example, by an
arsenic diffusion, see Figure 3, after which the
oxide layer 21 is removed and an:n-type silicon
layer 7, for example 3 microns thick, is grown
epitaxially by using conventional methods. The
layer 7 has a resistivity of 1 to 2 ohm.cm; the
¦ buried layers prior to the epitaxial growth have
J, 25 a sheet resistance of 15 to 25 ohm per square. By
¦ a boron diffusion, separating channels 19 are
s
diffused throughout the thickness of the layer 7
,i .
-16_
, s
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~5.5. l976
105~9Z40
down to the substrate 9. A fresh oxide mask 22
is then provided in which apertures are etched
at the area of the contact zones 15 to be pro-
vided of the npn-transistor and of the base contact
zone 5 of the pnp-transistor, see Figure 4.
By a deep n-diffusion, for example
a phosphorus diffusion, the _-type zones 15 and 5
j are then provided after which the mask 22 is
replaced by a fresh oxide mask 23 which, like
~ 10 the preceding masks, is formed by thermal oxida-
¦ tion or by pyrolytic deposltion, in which mask
23, apertures are etched to form the ~-type
zones 13 and 16, see Figure 5. Said zones 13
and 16 are then formed either by diffusion, or by
~ 15 ion implantation of, for example, boron, after
3 which an oxide layer 24 is deposited pyrolytically
¦ over the assembly, in which layer an aperture is
~ etched to provide the emitter zone 12 of the npn_
¦ transistor, see Figure 6.
~ 20 After the formation of the emitter
j zone 12, for example by an arsenic implantation,
succeeded by an annealing treatment by heating
at 1000C in nitrogen, all the apertures necessary
for the further dopings and all the contact windows
are etched. The resulting mask is shown diagram-
matically in a simplified form in Figure 7 and
bears reference numeral 11.
~ 17
. . .. . . . .
, . . . . . . .
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PHN 8~9
25.5. 197-~
i
lO59~Z40
~ photolacquer mask ~ is then provided
wh:ich closes all t}le apertures with the ~o~e~$ion
of those for providing the active base region 4
and the emitter zone 3 and of the base contact
' 5 wi.ndow of the ~ transistor T1, see Figure 7.
i. By the implantation of~ for example, arsenic ions,
J the active base region 4 of the transistor T1 is
then provided, an n+ contact window 26 in the base
contactregion 5 being formed within the base
contact window, see Figure 8. The photolacquer
¦ mask 25 masks against said implantation and need
not be provided very accurately since the oxide
layer 11 also masks against said impIantation.
The photolacquer mask 25 is then replaced by a
¦ 15 fresh photolac~uer mask 27, see Figure 8, which
does not cover only the base contact windows of the
transistors T2, the collector.windows and the
j emitter windows of the ~-transistor T1 and the
¦ contact windows of the resistor R. A.s shown in
¦ 20 Figure 1, the emitter zone 3 of the ~ transistor
.¦ T1 does not entirely surround the base contact
window, but the emitter zone 3 is divided into
two separated zones so as to avoid short-circuit
of the emitter-base junction upon contacting the
emitter and the base.
l The contact diffusions 28 and 29 of
.~ the ~ transistor T2, the collector contact zone 6,
. ~
~ -18-
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PIIN ~Ofi9
25.5. 197G
~059~Z40
the emitter zones 3 of` the ~-transistor T1,
j and the contact zones 17 and l8 of the resis-
tor R are then ~ormed by an implantation of
boron ions, the mask 27 and the oxide layer 11
serving as a mask, see Figure 9. A:~ter removing
the photolacquer mask 27, the metallisation is
then provided in the usua] manner so that the
structure shown in Figures 1 and 2 is
I obtained.
¦ 10 It.will be obvious that~ where
ion implantations are used above, diffusions may
also be used in which it should be taken into
account that during the diffusion oxide masks
or other pyrolytic masks are used instead of
.15 photolacquer masks, for the manufacture of which
the normal photolithographic etching methods may
be used.
In the above-described method of
manufacture some masking windows are difficult
. 20 to realise by using photolacquer masks due to
the very small dimensions; this applies, for
example, to the windows in the oxide layer 11
(Figure 7) which serve for the formation of the
active base region 4 and the emitter zone 3 of
the transistor T1. A method in which said draw-
back is reduced by using an underetching step
will now be described with reference to Figures
; 10 to 19.
_ 19_
.
PlIN 8069
25.5. 197G
lOS9Z~O
Star-ting aterial is the structure
of Figure 10 having a ~-type substrate 9 and an n-
type layer 7 which can be obtained in a manner
analogous to that of` the preceding example.
Only the transistors T1 and T2 are shown in the
figures; further circuit elements may be present
in other places of the disl~. The reference
numerals correspond to those of Figures 1 to 9,
in which the same parts of the device are
referred to by the same reference numerals.
According to the invention, a
silicon nitride layer 31 and a silicon oxide layer
32 are provided successively one on top of the
other on the surface 2. As is known, said layers
can be etched selectively relative to each other
by means of specific etchants. Masking layers
of other materials may also be used, provided
they can be etched selectively relative to each
other.
At the area of the base contact
region 5A including the part 5B thereof still to
be provided, a first aperture 33 i6 provided an~,
at the area of the collector contact region
of the ~ transistor T1 to be provided, a second
aperture 34 is provided in the second masking
layer 32 of silicon oxide. Apertures are simul-
taneously provided at the area of the collector
contact windows of the ~ transis-tor T2 to be
--20--
PIIN 8069
25.5.1~76
~Q59240
forme~ and of the ba.se zone of said transistor,
see Figure 10. Subsequently, the exposed first
masl~ing layer 31 of silicon nitride within the
first aperture 33 i~ removed by etching, the
first masking layer 31 within the second aperture
34 being masked against said etching process,
for example, by means of a photolacquer mask 35
which in this example covers all the apertures
but for 33, see Figures 11 and 12, after which
(see Fi~ure 12) via the aperture 33, the surface-
adjoining part 5B of the base contact region is
further provided by introduction of a donor.
This may be carried out, for example, by
implantation of boron ions, the mask 35 and
the oxide layer 32 serving as a mask, but , if
desired, also by diffusion, in which case the
- mask 35 has first to be removed. When the layer 7
is thin, the base contact region 5 in this stage
may also be provided entirely down to the buried
layer 8, but when the layers are s~ghtly thicker
it is desired to form the region 5 in two steps
as is described in this example.
After removing the photolacquer mask
35 an insulating layer 36 which is approximately
1 micron thick and is partly sunk in the body is
formed on the base contact region by thermal oxi-
dation, -the remaining part of the semiconductor
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P~IN 80Gg
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surface being protected against said oxidation
by the silicon n:itride layer 31, see Figure 13.
Prior to forming thc active base
region 4, at least the edge portion of the
masking layers 31 and 32 nearest to the second
aperture 3ll is exposed to an etchant, in this
case phosphoric acid, at approximately 150C,
which etchant attacks the silicon nitride 31
but leaves the oxide layer 32 substantially
unattacked, see Figure 14. The nitride layer
31 is etched away over a lateral distance which
is smaller than half, and in this example is
smaller than one third of, the shortest dis-
tance between the first and second apertures 33
and 34. During this etching process, the layer
31 is masked on the upper side by a mask exten-
ding thereon up to the edge of the first aperture
33 and formed by the layer 32. Due to under-
etching a part of the layer 31, approximately
1 micron wide, is removed which is denoted in
Figure 14by 37. In this example, the nitride
layer 31 within the second aperture 34 and within
the contact windows and the base window of the
npn-transistor T1 are simultaneously etched
away. Of cou~se, the same underetching occurs
which, however, is not shown in the figure
for clarity and which is taken into account upon
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PIIN 8069
25.5. 197
lOS~240
proportioning the masks. However, it is also
possible first to mask said other apertures
and to etch them free only afterwards in a
second nitride etching s-tep.
Tlle active base region 4 is then
provided by the introduction of an acceptor
via the surface part present below the
etched-away part 37, see Figure 15. In the
present example this is carried out by first
remo-ving the oxide layer 32 entirely, covering
all the apertures except the etched-away part
37 with a photolacquer layer 38, and then
implanting arsenic ions. The doping of the
region 4, however, may also be carried out by
diffusion, in which case, for example, a mask
consisting of a pyrolytically deposited oxide
layer should be used instead of a photolacquer
mask, and the layer 32 may be maintained for the
time being, if desired.
As shown in Figure 16, the base zone
13 of the npn-transistor is then formed by an
implantation of boron ions and the use of the
nitride layer 31 as a mask, the remaining
apertures being covered by a photolacquer mask
39 or in a different manner, after which a
pyrolytically deposited layer 40 of silicon oxide
is provided over the assembly, see Figure 17. Via
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P}~N 80G9
25.5.197
1~59Z40
a window in said layer 40, the n-type
emitter zone 12 of he n~n-transistor Tz
is provided1 for example~ ~y implantation
or diffusion of arsenic. The layer Llo is then
S provided with base contact windows for the
_~-transistor T2 and is removed from the
whole region of the ~-transistor T1, while
a base contact window for the transistor T1
is etched in the oxide layer 36. This base
contact window, the emitter window of
transistor T2 and the part of the active base
region 4 not destined for providing the
emitter zone are then closed with a photo-
lacquer mask 41, see Figure 18, after which
the emitter zones 3 and the collector region 6
of the pnp-transistorTl are formed by the in-
troduction of an acceptor via the surface part
obtained by the above-described underetching and
via the second aperture 34, in this example
by the implantation of boron ions. This doping
also may be carried out, if desired, by dif-
fusion provided a refractory mask is used in-
stead of the photolacquer mask 41. Simulta-
neously with said doping, the base contact zones
28 and 29 of the npn-transistor T2 are formed,
see Figure 18. After removing the mask 41 and
- removing the oxide layer 40 o~ the collector
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I'IIN 80~
25.5, 197G
~O59Z~
contact window of the npn-transistor T2,
the metallisation is ca~ried out and the
device is ready for assembly, see Figure 19.
In -this example, the doping
window for the regions 3 and 4 was obtained
by underetching of the nitride layer 31.
According to a modified embodiment of the
method according to the invention, however,
instead thereof the second masking layer,
that is in the present example the oxide
layer 3Z, may also be used for underetching.
This is shown in Figure 20 to 24 in which for
simplicity only the n-type semiconductor layer
7 and the transistor T2 provided therein are
shown. According to this modified embodiment,
for example, after etching the first and second
apertures 33 and 34 in the oxide layer 32,first
the nitride layer 31 is etched away in the first
aperture 33 at the area of the base.and collector
contact regions to be provided, after which a
photolacquer mas~ 50 is provided which extends
up to the edge of the first aperture 33, and in
this example covers a part of said edge on the
side remote from the aperture 34, see Figure 20.
A part 51 of the masking layer 32 below the
edge of the mask 50 is then etched away, see
Figure 21, after which the mask 50 is removed
PIIN 8069
25.5.1976
1059Z40
and the base contact region 5 is provided, for
example by iOII implantation or diffusion, ln the
aperture 33 while using the silicon nitride layer
31 as a maslc, in which or after which said base
contact region 5 is covered with an insulating
layer 52, for example a silicon oxide layer,
see Figure 22.
The aperture 34 is now covered, for
example, with a photolacquer mask 53, and by
means of a hot phosphoric acid solution the
exposed silicon nitride is etched away after
which (see Figure 233 the active base region 4
is implanted. After removing the mask 53, the
collector contact region 6 and the emitter zone 3
are then provided, see Figure 24, and after metal-
- lisation the device may be assembled.
As in the preceding example, the zones
3 and 6 may in this case also be of the ~~type
and the regions 4 and 5 may be of the n-type
so that a ~ transistor is obtained. It will be
obvious, however, that nn npn-transistor can be
formed in an analogous manner. In general it
holds that in all the examples the conductivity
types of the various semiconductor regions and
zones may all (simultaneously) be varied in the
opposite conductivity type, although this may
sometimes presenttechnological problems in prac-
tice.
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PIIN 80G9
25 5.1976
1~592~0
In thi.s connection it is to be noted
that in the examplcs descri.bed, with otherwise
conductivity types remaining the saMe, the
conductivity type of the layer 7 may moreover be
reversed.For example, the collector-base junction
in the ~-tra~sistors of Figures 2, 19 and 24
is formed between th.e p-type collector contact
region ~ (which in this case forms the whole
collector zone) and the layer 7. When in the said
figures according to a further embodiment the
layer 7 is ~-type conductive instead of n-type
conductive, the ~ junction between the collector .:
zone and the base ~e is formed between the n-type - `
base regions 4 and 5 and the ~-type layer 7.
Upon application of a transistor
structure as that of transistor T1 in a mono-
lithic integrated circuit, the layer 7 will ge-
nerally be of the n-type and the substrate 9 of
the p-type. However, it is also possible that
the layer 7 and the substrate 9 both are of the
same.-eonductivity type or that the layer 7 is -:
formed by a homogeneously doped silicon plate.
In that case the buried:layer 8 is super~luous
as a rule.
It will be obvious that the invention
is not restricted to the embodiments described
but that many variations are possible to those
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Pl-lN 80G9
25.5.1976
lOS924()
skilled in the ar-t without departing from
the scope of this invention. For exarnple,
if desired, semiconductor materials other
than silicon, for example germanium or III-V
compounds such as GaAs, and insulati.ng layers
other than silicon oxide and silicon nitride,
for example aluminium oxide, may be used,
provided the requirements of se]ective
etchability are fulfilled. Also, instead of
~0 photolacquer masks, other masking layers may
be used. The geometry of the resulting device
may be varied withln wide limits as will be
obvious already by comparison of the transis-
tors T1 of Fi~ures 2 and 19 with the transistor
shown in Figure 24 which are both_embodiments
of the device according to the invention.
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