Note: Descriptions are shown in the official language in which they were submitted.
12 Cross P~eferences to Related _ ten's
13 1. Spampinato et al U.S. Patent 3,541,530 issued on
14 November 17, 1970, and assigned to the assigr.ee of the
present invention.
16 2. Sonoda U.S. Patent No. 3,949,385 issued April 6,
17 1976 and comm~nly assigned herew;th.
18 sac~ground of the Invention
19 1. Field of the Invention
This invention relates to a D.C. stable semiconducto-
21 memory array and more particularly to such an array in
22 which each memory cell comprises four field effect
23 transistors.
24 Description of the Prior Art
The above mentioned Spampinato et al patent e~emplifies - -
26 the prior art in memory arrays having memory cells com-
27 prising four field effect transistors. Such four device
28 cells have traditionally not been D.C. stable and therefore
29 required periodic refreshing to prevent loss of the stored
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1 information. A number of different techniques for re-
2 freshing such non-D.C. stable memory cells were developed~
3 however, they all lack the advantageous feature of D.C.
4 stability as described in the present application.
Summary of the Invention
6 Accordingly, it is a primary object of this invention
7 to provide a D.C. stable storage cell with only four field
B effect transistors.
9 It is a further object of this invention to provide
a memory array consisting of such cells;
11 It is a further object of this invention to provide
12 three distinct levels of bias voltage to each of the
13 memory cells.
14 In accordance with the present invention, a semi-
conductor memory array of four device FET cells is provided.
16 Word lines and bit lines are arranged orthogonally in a
17 known manner to permit accessing and sensing of information
18 with an individual desired memory cell. Restoring means for
19 equalizing or precharging the potential on a pair of bit
lines is also provided. In addition to the foregoing,
21 there lS provlded an array biasing means. In accordance
22 with the present invention, the array bias means consists
23 Ln part of several field effect transistors connected in a
24 series feedback path between the word lines and the bit
lines. The array bias means includes further transistor
26 means to provide a bit line and word line bias at a
27 potential level intermediate between the full logical up
28 and down levels. ~-
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1 The foregoing and other objects, features, an'd
2 advantages of this invention will be apparent from th~
3 following more detailed description of a preferred embodi-
4 ment of the invention as illustrated in the accompanying
drawings.
6 ' ": Brief Descriptlon of the Drawings
7 Flg. 1 is a schematic circuit diagram of the pre-
8 ferred embodiment. ,~
9 Fig. 2 is a series of waveform diagrams depicting
the operation of the circuit of Fig. 1.
11 ~ Detailed Description
12 Refer now to Fig. 1 for description of the circuit
13 details. A matrix of four cells is shown for purposes of
14 illustration.,,A~typical cell includes four field effect
transistors such as Ql, Q2, Q3, and Q4. Each of the ,
16 field effect transistors have two gated electrodes and a
17 gating electrode. Transistors Q3 and Q4 have a gated and
. .
18 gating electrode of one respectively connected to a gating
19 and gated electrode of the other forming a cross coupled
pair; the other of the gated electrodes of each of said
21 transistors b'ë~ing connected to a fixed potential such
. ~ , - 1 .. . . .
22 as ground. Devices Q1 and Q2 are load devices connected
23 in series between the internal cell nodes A and B and
24 the associated bit'-line BO and Bl, respectively. A
ZS similar cell is shown consisting of transistors QlA, Q2A,
26 Q3A, and Q4A. Two other cells are illustrated merely as
27 block diagrams to complete the four cell matrix or array.
.
28 Those skilled in the art will understand that in practice
29 numerous such cells compose an array and the number
illustrated here has been limited merely for ease of
31 illustration.,'
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1 The restoring means for equalizing or precharging the
2 ~it lines consists of transistors Q5, Q6, and Q7. The
3 qating electrodes of each of said transistors is connected
4 together and adapted to receive a pulse signal on terminal
phase D. The gated electrodes of Q7 are connected in series
6 between the two bit lines providing equalization of
7 potential. Transistors Q5 and Q6 are connected in a
8 series path with each other between the two bit lines and
9 receive a potential at a common point between them for
application equally to the two bit lines. The potential
11 at this common point designated as node C will either be
. . .
12 a full binary 1 or 0 level or~at a third intermediate
13 level during standby. 'The appropriate desired potential
14 levels are provided by the transistors Q8 through Q13.
The connection of these last mentioned transistors
16 will now be described. Transistor Q10 has its-gated
17 electrodes connected in a series path between a first
18 fixed potential +Vl and node C. In the N channel MOSFET
19 technology assumed for the purposes of the present
illustrative example, +Vl is typically +8.5 volts repre-
21 senting a full logical up level. Transistors Q8, Q9, and
.
22 Qll are connected in series between a second fixed
23 potential ~ground representing a full logical down level)
24 and a third fixed potential +V2 (representing an inter-
mediate potential of +2 to +3 volts)O The interm2diatle
26 point between transistors Q8 and Q9 is also connected to
27 node ~ as illustrated. The common point between Q9 and
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1 Q11 is connected to a plurality of word line isolation
2 transistors such as Q12 and Q12A. Transistor Q13 is
3 connected between the same common point and the third ~ ;
4 fixed potential +V2. Each of the word lines is also
connected to a decoder/word line driver permitting in-
6 dividual accesslng of any one word line. Each of the
7 bit lines is ~urther connected to a ga~ed elèctrode of a
8 field effect trans~stor such as Q14, Q15, Q16, or Q17.
9 The gating electrode of each of said transistors is
connected to a bit decoder output terminal such as BIT
11 1, BIT 2, etc. The other of the gated electrodes of each
12 of said transistors is connected to a data input or a
13 sense amplifier depending on whether a write or read
14 operation is desired. Lastly, a preamplifier is connected
between the two bit lines so that in the read mode,~the
16 difference between the potential on lines B0 and Bl is
17 amplified prior to transmission to the sense amplifier.
18 In operation, the array operates in a D.C. stable
19 mode, in response to the application of various timing
pulses to the various gating electrodes as illustrated ln
21 Figs. 1 and 2. During stand-by the phase A pulse is down,
22 the not phase A pulse is up, the phasë D pulsé is up, the
- , . .
23 phase C pulse is up, the phase B pulse is down and the
24 phase E pulse is down. This provides a series path from
the third fixed potential +V2 through Q8j Q9, and Q12, Q12A,
26 etc., such that the word line is at an intermediate level
27 of two to three volts. Note that Q8 is structurally
28 arranged to have a width to length ratio (W/L) that is
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1 oné.eignth that of ~h`e othar de~icés;iimiting current
2 flow therethrough. Note also that node C is also connected-
3 to +V2 through Q8 and since devices Q5 and Q6 are also
4 on, the load current of the cells is supplied through
the bit lines. This current is sufficient to maintain
6 the appropriate cell node (A or B) at an up level while
7 the other of the two nodes is maintained at a down level.
8 It is a significant feature of this invention that the
9 stand-by power o~ the array is limited by the feedbac~
path including Q9 which joins node C (which is connected
11 to the bit lines through Q5 and Q6) to the word line
12 (through one of transistors Q12, Q12A, etc.). As the
13 potential of one of the word lines rises, the conductance
14 of load devices such as Ql and Q2 is increased drawing
more current from the bit line in the path from +V2
16 through Q8 and Q5 and Q6. As more current is drawn through
I7 Q8, the potential at node C becomes lower, the feedback
18 path thereby clamping the voltage on the word line to the
19 lowered potential. This techni~ue permits information to
be retained in the cells indefinitely with minimum power
21 dissipation.
22 The stand-by bit line voltage, clamped by the above
23 mentioned feedback path~is too low for operating the FET
24 array in the read and write mode. Device 10 is therefore
added to permit raising the bit line voltage prior to
26 either a read or write operation. When a particular
27 word line is selected, Q10 is turned on by the phase B
28 timing pulse. Initially, the phase D timing pulse is also
.
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1 maintained in an up level permitting current through dcvice
2 8 to also charge th~ bit lines. ~lowever, device 10 is
3 designed to be approximately 8 times the width to lenyth
4 (W/L) ratio of device 8 such that the majority of the
S current used in raising the bit line voltage is supplied
6 by device 10.
7 Upon selection of the particular semiconductor chip
8 into which the disc~osed array is formed, all word lines
9 are discharged to ground. This is accomplished by turning
the device Qll on by bringing the phase A pulse to an up
11 level, the not phase A pulse correspondingly turning device
12 Q9 off. The phase C pulse also being on provides a direct
13 path- to ground for all the word lines. The bit line
14 restore devices Q5, Q6, and Q7 are permitted to remain on
for some time to equalize the different potential on the
16 bit lines created by the load current of the cell. After
17 the bit lines are equalized, the bit line restore devices
18 (Q5, Q6, Q7) are switched off by bringing phase D to a
19 down level and the selected word line is raised to the
+Vl potential. Assuming that the word line connected to
21 the illustrated cell including transistors Ql, Q2, Q3,
22 and Q4 is to be selected, the decoder/word line driver
23 will bring the word line to which it is connected to this
24 up level. Devices Ql and Q2 will be turned fully on
providing a differential voltage on bit lines B0 and Bl
26 that is the same relative up and down level as stored on
27 internal nodes A and B. The preamp will accelerate bringing
28 this difference potential to full logic level. At this
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1 point one of a pluralLty of bit switch signals is applied
2 to a terminal such as BIT 1 or BIT 2, and will gate out
3 the information from the cell. For example, in accessing
4 the cell consisting of transistors Ql, Q2, Q3, and Q4,
the BIT 1 bit switch turns on transistors Q14 and Q15
6 permitting the differential potential on lines B0 and Bl
7 to be sensed by the sense amplifier. In the alternative,
8 if it is desired to~alter the information on the cell
9 by writing, then the differential data input is applied
to the bit line through transistors Q14 and Q15 setting
11 the cross coupled transistors Q3 and Q4 lnto the desired
12 one of the possible two binary states. Note that all
13 other word lines such as the word line connected to the
14 cell including transistors QlA, Q2A, Q3A, and Q4A are
clamped to ground by a down level output from the ~-
16 decoder/word line driver. The phase C pulse is also -
11 brought to a down level turning transistors Q12, Q12A,
18 etc., off isolating the word lines from each other.
19 Also note that during select, Q9 is turned off by the
not phase A pulse further isolating the word lines
21 from the bit lines.
22 As a further feature of the present invention note
23 the presence of boostiny transistor Q13 connected between
24 +V2 and the word line through one of transistors Q12, Q12A, ~-
etc. Following every select cycle, the phase E pulse
26 turns transistor Q13 on while phase pulse C turns the
27 corresponding transistor Q12 on. This permits current ~`
28 to flow into the word line permitting load devices such
29 as Ql and Q2 to turn on harder than is possible by the
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l current path through Q8 alone. At substantially the same
2 time, the phase D pulse turns on transistors Q5, Q6, Q7,
3 and Q8 providing a current to replenish the potential of
4 the appropria~e internal cell node (A or B) that might
have leaked away during the time the load devices of the
6 unselected cel?s were completely turned off.
7 The details of the just described timing operations
8 are shown in the waveform diagrams of Fig. 2. These
9 various timing waveforms are generated by field effect
transistor circuits formed on the same semiconductor chip
ll with the memory cells. The details of these timing
12 circuits are not shown since it is well known to provide
13 timing waveforms in any sequence with field effect
14 transistors formed on a semiconductor chip.
While the invention has been shown and particularly
16 described with reference to preferred embodiments, it will
17 be understood by those skilled in the art that various
18 changes in form and detail may be made therein without
l9 depar~ing from the spirit and scope of the invention.
What is claimed is:
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