Note: Descriptions are shown in the official language in which they were submitted.
10f~1006
B.~CKGROUND OF THE INVENTIO~J
This invention relates to data processing systems and
m~ore particularly, to data processing display systems including
one or more display devices each capable of displaying a-desired
image.
Prior art data processing display systems are character-
ized by special purpose memories which in thè aggregate define
a character generator. Typical display devices are of the raster-
scanned type, such as CRT-TV tubes. A character to be formed at
a location on the display screen is defined by a matrix of
selectively energiza~le points arranged in a plurality of verti-
cally oriented scan lines. As is conventional, a scanning beam
scans from left to right, one scan line at a time, until an entire
"page" is displayed, and then returns to the top scan line in
order to "refresh" tne image on the screen. Typically, the image
is refreshed 30 times per second.
It is a characteristic of prior art systems that characters
are definable only in fixed "blocks" on the displa~ screen, each
block containing the requisite matrix of energizable points. As
is conventional, a display list memory contains the character data
2~ to be displayed in the form of a plurality of ASCII coded words each
defining a particular character element. A predetermined number
of words in the display list memory define each text line to be
displayed. Each A5CII coded word from the display list memory is
forwarded to a separate font memory along with a signal indicating
a scan line number. For example, there may be eight scan lines in
the matrix for each character which then could be 8 X 8. ThuS,the
scan line number sisnal could be a 3-bit code. The font memory
contains a plurality of words each representing the desired bit
configuration for each scan line of a particular character. It is
the output of the font memory that is supplied to the display
-- 2 --
1061006
controller for trans~ittal in bit-serial format to the display
device. The words of the font memory are traditionally
supplied directly one at a time to the display controller.
Other prior data processing display systems, such as that
- disclosed in U.S. patent No. 3,895,357, store 2 predetermined
number of the font memory words, such predeter~ined number
defining a small band of the picture to be dis?layed, into a
partial raster assembly store. Again, however, special purpose
memories are employed.
- 10 The main problem with these prior art "character
generator" type display systems is that they are generally
limited to forming characters only, and only on specifically
predetermined portions or "blocks" of the displ~y screen. They
do not have a "graphics" capability, i.e. the ability to draw
relatively high resolution lines and curves unrelated to the
conventional alphanu~eric characters. U.S. patent No. 3,716,842
discloses a data processing di~play systems that does have
a graphics capability However, the system is relatively
complex from a hardware standpoint in requiring, again;
special purpose memories.
It would be desirable, therefore, to provide a data
processing display system having the attributes of simplicity
and generality, i.e. simplicity in a hardware sense such as
by avoiding special purpose memories r and generality in a
display capability sense such as being virtually ùnlimited
as to the nature and location of data displayed on the
display thereby providing a graphics capability.
1061006
SUMMARY OF THE INVENTION
In accordance with one aspect of this invention there
is provided a data processing display system comprising: a
display device capable of displaying a desired image, said
display device including a plurality of points each capable
of being selectively illuminated; a main memory storage
device including a plurality of addressable storage locations
capable of being addressed by predetermined address signals,
each location capable of storing a multi-bit display word
therein, at least some of.said addressable storage locations
including in the aggregate a number of display bits at
least equal to said plurality of points of said display
device whereby a display bit map of said desired image is
capable of being stored and defined in said at least some
addressable storage locations; a display controller
connected to said display device and responsive to predeter-
mined instructions for controlling the illumination of said
plurality of points of said display device; a central process-
ing unit including first means for generating said predeter-
mined instructions for application to said display controller,and second means for generating said predetermined address
signals for application to said main memory storage device;
an address bus connected between said main memory storage
- device and said central processing unit for supplying said
predetermined address signals to said main memory storage
device; a main data transfer bus connected to said main
memory storage device, said central processing unit and
said display controller, said main data transfer bus capable
of supplying to said display controller the display words
addressed from said at least some addressable storage loca-
tions of said memory storage device and said predetermined
instructions; said central processing unit including a data
1061006
section and a control section, said control section including
said first means for generating and means for supplying
instructions to said data section, and said data section includ-
ing said second means for generating and means for executinginstructions supplied it from said control section; and said
display controller including third means for generating at
least one display task request signal, said system further
comprising means for supplying said at least one display task
request signal to said control section, and said control
section including means responsive to said at least one
display task request signal for causing said means for supply-
ing instructions to said data section to supply instructions
relating to the display of said desired image by said display
device.
In accordance with another aspect of this invention
there is provided a data processing display system comprising: a
display device capable of displaying a desired image, said
display device including a plurality of points each capable
of being selectively illuminated; a main memory storage device
including a plurality.of addressable storage locations capable
of being addressed by predetermined address signals, each
location capable of storing a multi-bit display word therein,
at least some of said addressable storage locations including
in the aggregate a number of display bits at least equal to
said plurality of points of said display device whereby a
display bit map of said desired image is capable of being
stored and defined in said at least some addressable storage
locations; a dlsplay controller connected to said display
device and responsive to predetermined instructions for con-
trolling the illumination of said plurality.of points of saiddisplay device; a central processing unit including first
means for generating said predetermined instructions for
~'
--5--
1061006
application to said display controller, and second means for
generating said predetermined address signals for application
to said main memory storage device; an address bus connected
between said main memory storage device and said central
processing unit for supplying said predetermined address
signals to said main memory storage device; a main data trans--
fer bus connected to said main memory storage device, said
central processing unit and said display controller, said
main data transfer bus capable of supplying to said display
controller the display words addressed from said at least
some addressable storage locations of said memory storage
device and said predetèrmined instructions; and said central
processing unit including a data section and a control
section, said control section including said-first means for
generating and means for supplying instructions to said data
section, and said data section including said second means for
generating and means for executing instructions supplied it
from said control section, said means for supplying instruc-
tions and said first means for generating including a micro-
instruction memory device, said instructions and said pre-
determined instructions being microinstructions.
These and other aspects and advantages of the present
invention will be more completely described below with reference
to the accompanying drawings.
1061006
BRIEF DESCRIPTION OF THE DRAWINGS
Figure 1 is a block diagram representation of an
exemplary data proeessing display system of the present invention;
Figure 2 is a schematic bloek diagram representation
of the control section of the CPU depicted in Figure l;
Figure 3 is a more detailed bloek diagram representation
of the instruetion register and decoders depicted in Figure 2.
Figure 4 is a schematic block diagram representation
of the data seetion of the CPU and the main memory depieted in
Figure l;
Figure 5 is a representation of the diLferent storage
seetions of the main memory store depieted in Figure 4;
Figure 6 is a bloek diagram representation of a portion
of the display eontroller depieted in Figure l;
Figure 7 is a block diagram representation of another
portion of the display controller depieted in Figure l;
Figure 8 is a sehematic drawing of logic elements which
constitute portions of the display controller as shown in
Figure 6;
Figure 9 is a sehematic drawing of additional portions
of the display controller as depicted in Figure 6; and
Figure 10 is a sehematie drawing of the eontrol logie
of the display eontroller as shown in Figure 6.
10610(~
DESCRIPTION OE THE PREFERRED EMBODIMENT
Referring to Figure 1, a data processing display
system of the present invention is shown. The system includes
a central processing unit (CPU) 10 that is comprised of a
data section 12 and a control section 14. The system also
includes a main memory 16 to be described below and a
plurality of input-output (I/O) controllers 18, e.g., "M" I/O
controllers designated 18(1) through 18 LM) Each of the I/O
controllers 18 is connected to a respective one of a plurality
of I/O devices 20 for controlling same. At least one of the
I/O controllers 18, e.g. controller 18(1), is a display
`- controller for controlling a display device 20(1). Examples ofother typical I/O devices that may be employed as I/O devices
20 in the system of Figure l-are disk drives, keyboards and cursor
control devices (sometimes each referred to as a "mouse").
The depiction of only one display controller 18(1) and
associated display device 20(1) is, of course, only exemplary.
- Information is transferred to and from the data
section 12 of the CPU 10 by means of a main data transfer bus
22. The information is desirably trans erred in bit-parallel
format. Typical CPU's are designed to operate in 8-bit or 16-bit
format, i.e., 8-bit or 16-bit quantities are transferred to and
from the data section 12 along the bus 22, which would then be
comprised of either at least eight or at least sixteen parallel
lines. Information may be transferred on the data bus 22
between the main memory 16 and the data section 12, between the
I/O controllers 18 and the data section 12, as well as between
each of the I/O controllers 18 and the main memory 16.
lOf~lOOf~
Each of the I/O controllers 18, including the display
controller 18(1) is capable of generating one or more t~sk
request signals in the form of "wake-up" commands whenever
the particular controller 18 requires one or more services to
be performed by the CPU 10. The specific nature of three
wakeup-task request signals that are preferably generated by
the display controller 18(1) will be described in more detail
below. The wakeup-task request signals from the controllers -
18 are applied on respective lines 24(1)-24(N). The three
wakeup-task requests from the display controller 18(1),
arbitrarily designated wakeup-tasks 1-3, are applied on lines
24(1) - 24(3) to the control section 14 of the CPU 10. In
order for each controller 18 to be informed when the CPU 10 is
executing instructions relating to the requested service, the
control section 14 includes means to be described below for
applying a "task-active" status signal back to the controller.
These task active status signals are applied on lines 26 from
the control section 14 to the controllers 18, as shown in Figure
1. There are three task-active lines associated with the
display controller 18(1), i.e. task 1 active on line 26(1), task
2 active on line 26(2) and task 3 active on line 26(3).
Reference is now had to Figure 2 where the control
section 14 of the CPU 10 will be described. At the outset, it
must be stated generally that the control section 14 applies
instructions to the data section for execution thereby. Addi-
tionally instructions are applied to the various I/O controllers
18 for execution thereby. The instructions are forwarded in
accordance with a particular sequence or routine to be carried
10~1006
out and identified with a particular task to be serviced. The
control section 14 includes means to be described below for
determining which of a plurality of wakeup-task request signals
that may have been applied to the control section 14 has the
highest current priority value. More specifically, each of
the plurality of tasks to be serviced is preassigned a unique
priority value. Thus, performing a requested service for the
display controller 18(1~ may be of higher priority than per-
- forming a requested service for I/0 controller 18(M) The
control section 14 then forwards instructions associated with
the highest current task to be serviced to the data section 12
and respective I/0 controller 18 for execution.
Referring now in more detail to Figure 2, the control
section 14 includes a priority encoder 28 which has task
request inputs connected to the N task request lines 24. As
explained above, wakeup-task request signals for task l-N are
provided from the I/0 controllers 18. Additionally, a wakeup-
task request signal for task ~, which requests servicing the
main program, is always present, as will be explained in more
detail below. The priority encoder 28 inclu~es circuitry (not
shown) for generating a multi-bit control signal on a respec-
tive plurality of lines 30 (only one shown) related to the
highest priority wakeup-task request signal currently applied
as an input to the encoder 28. The priority encoder 28 includes
a further input for receiving a RESET signal on a line 32 from
an initialize circuit 34 to be described in more detail below.
Now then, the control signal developed on lines 30
is applied to respective inputs of a current task register 36
which responds to such control signal for generating a multi-
1061006
bit address signal that is applied in bit-parallel format on
a respective plurality of lines 38 from the register 36 to
respective inputs of an address memory 40. The address memory
40 includes a plurality of storage locations, preferably de-
fined by a respective plurality of multi-bit registers (not
shown). There are preferably N such registers included in
the address memory 40, each one being add~essed by a unique
multi-bit code defined by the address signal applied thereto
from the current-task register 36 on lines 38.
Each one of the N registers in the address memory
40 is associated with a respective one of the N tasks to be
performed, as defined above. In actuality, each of the address
memory registers is capable of storing the next address of an
executable microinstruction stored in a microinstruction memory
42. In this respect, each of the N address memory registers
may be thought of as a program counter for its respective
task to be serviced relative to the corresponding microinstruc-
tion routine stored in the instruction memory 42.
Each instruction stored in the memory 42 is accessed
in response to a corresponding address signal applied on address
lines 44 from the address memory 40. Each instruction includes
an instruction field preferably comprised of twenty-two bits,
and a next-address field preferably comprised of ten bits. The
specific constitution of the 22-bit instruction field will be
described in more detail below in connection with Figure 3. The
instruction field is loaded into an instruction register 46
on lines 48 and is then applied through appropriate decoders
52 (also to be described in more detail below in connection
-- 10 --
106~006
~ith Figure 3) to the data section 12 of the CPU. Certain of
these decoded instructions are also forwarded to the display
controller 18(1), as will be discussed below in connection
with Figures 3 and 4. The next-address field is fed back on
lines 50 to the currently addressed register in the address
memory 40. In this manner, each of the N registers in the
memory 40 will always contain the address of the next micro-
instruction stored in the instruction memory 42 to be executed
in accordance with the particular task to be serviced.
A portion of the twenty-two bit instruction field
of each microinstruction may be dedicated to various special
functions, som~ of ~hich are applied on control lines 47 to
respective ones of the I/O controllers 18 for controlling
same, and some of which are applied on control lines 49 to
address modifier circuits 56 (to be described below) for
branching. In accordance with the preferred embodiment, there
is a four-bit special function "sub-field" in the instruction
field of each microinstruction (hereinafter referred to as
the "Fl" sub-field), wherein two of the sixteen four-bit
codes capable of being defined (e.g. Fl=2, Fl=3) are respec-
tively representative of "TASK" and "BLOCK" functions. A
TASK signal component of an accessed instruction, upon being
decoded by an appropriate one of the decoders 52, is applied
on a line 54 to the current task register register 36 for
enabling same to load an address signal, representing the
current highest priority task requesting service. This
- address signal is then applied to the address memory 40. A
decoded BLOCK signal is applied on a line 55 to the current
task register 36 for disabling same.
-- 11 --
106~006
It will be appreciated that a TASK signal can be
presented in any desired microinstruction during any routine
to be executed. Normally, a TASK signal would be generated
at least once during each microinstruction routine in order
to enable any higher priority task awaiting service to
interrupt the current routine in order to be serviced by the
CPU 10. If a particular task to be serviced has a microinstruc-
tion routine that carries out a plurality of different functions
that can be independently serviced, then a TASK signal would
normally be written into the last microinstruction of each
segment of the routine identified with a particular one of
such functions.
Continuing with a description of Figure 2, the control
section 14 of the CPU 10 further includes conventional address
lS modifier circuits 56 which, in a known manner, are responsive
to instructions on control lines 49 for modifying the next-
address signal being fed back on lines 50 from the instruction
memory 42 to the address memory 40. As is conventional, such
~ address modifiers are used for branching. The specific nature
of the address modifier 56 forms no part of the present
invention and thus shall not be described in detail.
The multi-bit address signal developed at the out-
put of the current task register 36, in addition to being
applied to the address memory 40 on lines 38, is also applied
on lines 58 to a task-active decoder 60. The decoder 60
responds to the address signal output of the register 36 and
generates one of the N TASK-ACTIVE signals alluded to earlier
1061006
on its respective line 26, dep~ndent upon the current highest
priority task to be serviced. The decoder 60 includes a
delay circuit for delaying the application of a TASK-ACTIVE
signal to the respective I/O controller 18 by one clock cycle
of the processor. In this manner, the appropriate TAS~-ACTIVE
signal will be generated at a time corresponding to the
execution of instructions related to the task being serviced.
The control section 14 as shown in Figure 2 also
includes a clock generator 62 for generating appropriate CLOCK
signals for application to the current-task register 36 on a
line 64, the tasX-active decoder 60 on a line 66, the address
memory 40 on a line 68, and the initialization circuit 34 on a
line 69.
Still referring to Figure 2, the initialization
circuit 34 is responsive to a START signal generated when the
system is turned on by the operator. Upon receipt of the
- START signal, conventional circuitry in the circuit 34 causes
a RESET signal to be generated which is applied to the priority
encoder 28 on line 32, to the current task register 36 on a
line 70, to the task-active decoder 60 on a line 72, to the
instruction memory 42 on a line 74, to the instruction regis-
ter 46 and decoders 52 on a line 76, and to the address modifier
56 on a line 78. Upon receipt of a RESET signal, these various
components of the control section 14 are reset.
The initialization circuit 14, in response to a
START signal, also generates a multi-bit initialization address
signal on a respective plurality of lines 80. In a preferred
embodiment of the invention, "N" equals sixteen and thus the
initialization address signal is a four-bit signal that is
10~;1006
initially zero, i.e., 0000, and is incremented by one at the
rate of the CLOCK signal pulses applied on line 69. The RESET
signal is maintained for sixteen cycles, i.e. sixteen CLOCK
signal pulses, at which time the initialization address on
lines 80 will increment from zero (0000) to fifteen (1111).
As will be described below, the address signal output of the
current task register 36 during initialization is identical to
the initialization address signal. During initialization, the
address signal output of the current task register 36 is
applied through an AND-gate 82, which is enabled by a RESET
signal from the initialization circuit 34, to the address
memory 40. In this manner, the address signal (0000) will be
loaded into register number zero in the address memory 40,
the address signal one (0000) into register number one, and so
on. This process initializes the address memory by setting
the various registers therein at their respective starting
values.
Further details of the control section 14 of the
CPU 10 may be had through a review of U.S. Patent No. 4,103,330,
Charles P. Thacker.
Referring now to Figure 4, the basic elements of the
data section 12 of the CPU 10 are a register file 102, T
register 106, L register 110, memory address register (MAR)
114, and instruction register 116. The registers 106, 110,
114 and 116 are connected to the register file 102 and to an
arithmetic and
- 14 -
1061006
logic unit (ALU) 120 by means o~ the main data transfer bus
22, which is desirably 16 bits in width.
Data is typically put onto the bus 22 from the
register file 102 which is preferably implemented by a group
of 32 registers whose contents are read or loaded as selected
by a specific microinstruction field. Data may also be entered
on the bus 22 from a constant memory 12g which is preferably
implemented by any commercially available 256-word read only
memory (ROM) which holds arbitrary 16-bit constants. Data may
be available as well from the I/O devices 20, such as the
--- display 20(1). Other data is available from the main memory
16 and portions of instructions are entered on the bus 22 from
the instruction register 116. The main memory 16 will be
described in more detail below.
Data may be transferred from the bus 22 to the I/O
controllers 18, the main memory 16, the instruction register
116, the T register 106, or even the L register 110 through
the ALU 120. Data-transfers are under the control of micro-
instructions which are executed from the instruction memory
42, which is desirably implemented by a conventional 1024 word
X 32-bit programmable read-only-memory (PROM).
The specific nature of the 22-bit instruction field
of a 32-bit microinstruction accessed from the instruction
memory 42 will now be described with reference to Figure 3. As
shown, the 22-bit instruction field loaded into the instruc-
tion register 46 includes seven "sub-fields" as follows:
- 15 -
1061006
BIT(S) SIGNAL MEANING
~-2 A REGISTER (R) SELECT
3,4 B REGISTER (R) SELECT
5-8 C ALU FUNCTION
9-11 D BUS DATA SOURCE
12-15 E FUNCTION 1
16-19 G FUNCTION 2
H LOAD L
21 I LOAD T
The R Select field (bits 0-4, signals A and B)
specifies one of the 32 registers which comprise the register
file 102 to be loaded or read under control of the bus source
field, or, in conjunction with the bus source field (bits 9-11,
signal D), one of the 256 locations to be read from the
constant memory 128. The low order two bits of the R address
(but not the constant memory address) may be taken from fields
in the instruction register 116, i.e. IR (1,2) and/or IR (3,4),
as applied through a conventional multiplexer 125 (Figure 4).
- This enables the main microprogram, i.e. task 0, to address
certain registers in the R file 102 more easily.
The ALU Function field controls the ALU 120. The
ALU 120 can do a total of 48 arithmetic and logical operations.
The 4-bit field is mapped by a PROM 140 into the 16 most use-
ful functions,
The bus data source field (bits 9-11, signal D), upon
being decoded by BS decoder 52a, specifies one of 8 data
sources for the bus 22 as follows:
- 16 -
1061006
OUTPUT
BS DECODER 52a SOURCE OF DATA
0 Read R Register 102
1 Load R Register 102
2 Nothing (-1)
3 Kstat ~assigned to disk controller
if used as one of controllers 18)
4 Kdata (assigned to disk controller
if used as one of controllers 18)
Memory data (from main memory 16)
6 Input device data (4 bits, remain- -
der of word is 1) : MOUSE (if used
as one of controllers 18~
7 Disp (low order 8 bits of
instruction register 116, sign
extended)
Output 1, i.e. Load R, is not logically a source, but
since the register file (R) 102 is gated to the bus 22 during
both reading and writing, it is included in the source specifiers.
The two function fields Fl and F2 specify the address
modifiers, register load signals ~other than those for the
registers 102, 106 and 110) and other special conditions
required. The first eight conditions specified by each field
after being decoded by Fl decoder 52b are interpretated identi-
cally by all tasks, but the interpretation of the second eight
decoded conditions depends on the active task. The first eight
task-independent functions are given below, whereas the latter
eight task-dependent (also referred to as "task~specific")
functions will be described later.
1061006
OUTPUT
Fl DECODER 52b NAME MEANING
~ No activity
1 MAR ~~ : Load MAR 114 from ALU
120 output; start main
memory 16 reference
2 TASK : Switch tasks if higher
priority wakeup pending
3 BLOCK ~ : Disable current task
wakeup until reenabled
by hardware generated
condition
4 ~ L lsh 1 : Left shift L (one place)
f-L rsh 1 : Right shift L (one place)
6 ~-L lcy 8 : Cycle L (8 places)
7 ~~ CONSTANT -: BUS constant ROM loca-
- tion addressed by R
SELECT BUS SOURCE
Outputs 4-6 are modified by function fields F2=11 and
F2=12, such fields to be described in detail later.
OUTPUT
F2 DECODER 52C NAME MEANING
0 ---- No Activity
1 BUS=0 NEXT~NEXT OR (BUS=0)
2 . SH 0 NEXT~-NEXT OR (SHIFTER
OUTPUT 0)
3 SH=0 NEXT~LNEXT OR (SHIFTER
OUTPUT =0)
4 BUS NEXT~-NEXT OR BUS (06)
-BUS (15)
ALUCY NEXT~NEXT OR LALUCO
~THE CARRY USED IS THAT
PRODUCED BY THE ALU
FUNCTION WHICH_LAST
LOADED THE L REGISTER 110.
6 STORE
7 CONSTANT S~-lE AS Fl=7
- 18 -
10f~i1006
The ALU 120 is restricted by the mapping of its
4-bit field by the PROM 140 so that only sixteen arithmetic
and logical functions may be performed. The output of the
ALU 120 is transferred to the L and memory address registers
110 and 114. The T register 106 may also be loaded from the
output of the ALU 120 under certain conditions. The L register
110 is connected to a shifter 144 which is capable of left and
right shifts by one place, and cycles of eight. Double-length
shifts may also be formed. The output of the shifter 144 is
transferable to the register file 102. The output of the MAR
register 114 is decoded by a decode and control unit 148 and
transferred along the address bus 13 to the main memory 16, and
more particularly to a main memory store 17 of the main memory
16. Details of the main memory 16 and its main memory store 17
will be described below.
As indicated above, microinstructions are executed
one at a time in each processing cycle. Generally spea~ing,
-- 19 --
1061006
with respect to the data section 12 of the CPU 10, a micro-
ins~ruction consists of taking a piece of data from a source
resister in the register file 102, operating upon it, and
loading the results into another register. For example, a
microinstruction may dictate that the contents of the 23rd
reg~ster in the register file 102 be transferred by way of
the bus 22 to the T register 106. This microinstruction would
be in the form of having the R select field equalling 23 and
hav~ng the load T bit set. An additional operation may take
as ~any as three microinstructions. If it is desired to add
the contents of the 22nd register of the register file 102 with
the 23rd register and transfer the results to the 30th register,
three microinstructions are, in fact, necessary. The first
microinstruction would read the contents of the 22nd register
in.o the T register 106; the second microinstruction would
read the contents of the 23rd register through the ALU 120 and
in.o the L register 110 and simultaneously would define an
add~tion operation in the ALU function field so that the
AL~ 120 would perform addition (the result stored in the L
register 110 at the end of the second microinstruction would
thus be the sum of the contents of the 22nd register and the
con.ents of the 23rd register); the third microinstruction
wou~d transfer the contents of the L register 110 through the
-shi~.er 144 back into the appropriate destination in the register
file 102.
The microinstruction is structured so that a
parallelism of different operations may be directed by a given
ins.ruction. This segmentation is achieved by the definition
- 20 -
10~100~
of specific fields within the instruction as is represented
in Figure 3. A given instruction is selected from the instruction
memory 42 and is transferred to the microinstruction register
46 where it is stored as shown in Figure 2. In the preferred
embodiment of the invention and as indicated above,: seven
fields comprising an instruction width of 22 bits dictate the
processing operations to be performed. Five bits (signals A
and B) are used to select the location in the register file 102
which are to be involved during a given instruction period.
If the register file 2 is not to be involved within a
particular processing cycle, this RSELECT (RSEL) field has
a value of zero. A 4-bit arithmetic and logic unit function
field ALUF (signal C~ specifies one of 16 logical operations,
including addition and subtraction, which the ALU 120 can perform.
A 3-bit bus source field BS (signal D) determines which of the
previously identified eight possible data sources are gated onto
the 16-bit bus 22 during the particular microinstruction period.
The Read R and Load R bus sources are typically used
in almost every microinstruction. With the value of two, the
BS field specifies that nothing is to be placed on the bus 22.
The Kstat source indicates status bits which would be stored
within a disc controller, if used as one of the I/O controllers
18. Kdata would consider 16 bits of disc data as a source,
again assuming a disc controller were being utilized in the
system. Memory data identifies data which would result from
a fetch from a particular location in the main memory store 17.
The indicator device data could possibly be represented by
four external control bits. Disp would be the lower 8 bits of
10~006
of the instruction register 116, with bits 0-7 made equal
to bit 8 (sign extension). This particular bus source
specification allows for the definition of microcode which
provides fast processing. As has been already mentioned,
the register file 102 is gated to the bus 22 during both the
reading and the writing of the file 102. Thus, Load R source
is included in the source specifiers.
Whenever the register file 102 is selected for
reading or writing, data is necessarily placed on the bus 22.
- 10 Therefore, the bus 22 contains data whenever a write operation
is performed on the files 102, even though some other transfer
in parallel may be made. Writing into the file 102, then, uses
the Load R condition in the BS field. If writing into the
file 102 is not specified with this field, then there would
be no other use for this field during that microinstruction.
~ith this implementation, dur~ng an instruction which writes
data into the register file lQ2, the contents of the bus 22 will
be represented as zero at that time, even though data was
originally on the bus 22. This latter condition is implemented
by the address memory 40 (Figure 2) whose inputs are connected
to the instruction register 116 and the bus 22 under the
control of the signal ZERO BUS. The bus 22 is zero when the
ZERO BUS signal is true, which signal is generated whenever the
microinstruction specifies that the register file 102 be loaded.
The advantages of using special function fields Fl
and F2 can be illustrated by the function of loading the memory
address register (MAR) 114. This is a function that is performed
1061006
moderately often in a microprogram, conceivably every five
microinstructions. This frequency of use is not such that it
would justify a special bit in the instruction, but often
enough so that it should be specified as a task-independent
function. Therefore, Load MAR is in the first set of eight
function Fl's, i.e. Fl=l. Similar rational is applied to the
implementation of the remaining functions within the set of
functions.
The left shift (Fl=4), right shift (Fl=5) and cycle
(Fl=6) functions control the shifter 144 which is responsive
to the output of the L register 110. Sixteen bits of data
are transferred from the L register 110 to the shifter 144
in parallel and 16 bits which are inputted to the shifter 144
can be left shifted, right shifted, or cycled by 8 with the :
result of the operation being transferred to the register file
102 to be stored. By the use of the function Fl, values 4, 5,
or 6, these task independent functions may be specified.
Tasks may be switched to higher priority wake-up
requests by the use of the function 1, value 2 (Fl=2). Current
task wake-up may be disabled by the use of the function 1, value
- 3 (Fl=3). The function l,value 7 instructs that a literal
constant be fetched from the constant memory 128. There are
preferably up to 256 literal constants stored in the constant
memory 128, the addressing of which requires 8 bits. The constant
memory 128, in the preferred embodiment, may be implemented by a
256X16 PROM available from Microsystems International, type
MD6300. The constant memory 128 is gated to the bus 22 by
Fl = 7, F2 = 7 or BS ~ 4 fields. The constant memory 128 is
- 23 -
lO~lOOf~
addressed by the 8-bit concatenation of RSELECT and BS, as
shown in Figure 4. The intent in enabling constants with
BS ~ 4 is to provide a masking facility, particularly for the
input device signal MQUSE and DISP bus source. This is
facilitated because the processor bus 22 is arranged electrically
such that it -"ANDS" if more than one~source is gated to it.
Up to 32 such mask constants can be provided for
each of the 4 bus sources ~ 4. For example, specific locations
in memory are identified by constants representing their
address to enable the microcode to communicate with the main
program. Also, these constants may be used to implement masks,
patterns and bits that the program wishes to contain.
Otherwise, such features would have to be stored in the
instruction memory 42 which would require an extra 16-bit field.
During an instruction, the constant memory 128
appears to be any other register in relation to the bus 22. The
gating of the constant memory 128 onto the bus 22 can occur
simultaneously with the specification of another function by
the other function field which does not enable the gating of
- 24 -
10~1006
the constant to the bus 22. If, for example, the rest of
the instructions dictate that the F2 field be used for a
branch, then the assembler will assign Fl=7. Otherwise, it
will assign F2=7.
The function 2Is are normally branch conditions.
Each of the F2 values specify the condition that must be
satisfied for branches to occur. Specifically, the notation
NEXT indicates the next address bus 50 (Figure 2), which
transfers the address of the next microinstruction. The left
arrow (~f--) means "gets". Therefore, F2=1 indicates that
NEXT gets NEXT or (bus equals 0). This indicates that a branch
will occur if the bus 50 equals ~, or the-output of the shifter
144 is less than ~ or equal to ~, or will branch to the location
specified by the bus 50. An address when generated allows a
jump to the location addressed in the instruction memory 42 or
a branch if the ALU 120 produces a carry out on the last
operation from which it was used.
F2=6 provides for a STORE which says that the data
that is currently on the bus 22 be written into the main
memory store 17 during this microinstruction cycle. Since the
main memory store 17 is much slower than the cycling of the
processor itself, it takes four cycles before a STORE is performed.
In the first cycle, the address register 114 is loaded, on the
next two cycles, operations may be performed elsewhere in the
processor, and in the fourth cycle, data is actually stored in
the main memory store 17.
Task dependent (specific) functions are provided by
function values in the Fl and F2 fields which are greater than 7, i-e-
- 25 -
106~006
between 10 and 17. The following table gives for each of
tasks 0, 1, 2 and 3 a number in the priority scheme and their
specific functions. The remaining tasks 4-N are not set forth
herein since they form no part of the present invention.
Fl (TASK SPECIFIC)
CPU-0 DWT-l DHT-2 DVT-3
10: SWMODE
11: WRTRAM
12: RDRAM
10 13:
14: - - _ _
15:
16:
17: START
F2 (TASK SPECIFIC)
CPU-0DWT-l DHT-2 DVT-3
10: BUSODD DDR ~-- EVENFIELD EVENFIELD
11: MAGIC - SETMODE
12: DNS
20 13: ACEST - - -
14: IR
15: IPISP
16: ACSOURCE
17:
As discussed above, task ~ is the main microprogram
and always is requesting service. Tasks 1-3 are generated by
the display controller 18(1). Task 1 is a display word task
(DWT), task 2 a display horizontal task (DHT), and task 3 a
display vertical task (DVT). As shown in the above tables,
only task 0 has task-specific (dependent) function Fl values,
i.e. Fl = 10, 11, 12 and 17. In the case of function F2,
- 26 -
10610~)6
however, F2 = 10 - 16 designate functions for task 0, F2 = 10
designates a function (DDR ~--) for task 1, F2 = 10, 11 designate
functions (EVENFIELD, SETMORE) for task 2, and F2 = 10 designates
a function (EVENFIELD) for task 3. The three microcoded tasks
1-3 will be described below with reference to the display con-
troller 18(1) and display 20(1)-
The display controller 18(1) handles transfersbetween the main memory 16 and the display 20(1). The display
20(1) may be a standard 875 line raster-scanned CRT-TV monitor,
refreshed at 60 fields per second (30 "pages" per second) from
a "bit map" in main memory 16. More specifically, there are
interlaced even and odd fields, each refreshed 60 times per
second so that the total page display is refreshed 30 times
per second. The display 20(1) preferably contains 606 points
horizontally and 808 points vertically, or 489,648 points
total. Thirty-eight, 16-bit words are required to represent
each scan line and 30,704 words are required to fill the screen.
The bit map in main memory contains a total number of bits
at least equal to 489,648, i.e. the total number of points on
the display. This
- 27 -
1061006
is an important feature of the present invention as will be
made clear below.
A page to be displayed is defined at one or more
display control blocks (DCB's) in the main memory store 17.
DCB's are linked together starting at location DASTART in the
main memory store 17 (see Figure 5). Location DASTART points to
the first DCB word ~, or 0 if the display 20(1) is off. All
DCB's must start on even word boundaries. Location DASTART+l
represents a vertical field interrupt bit mask. Each DCB has
the following format:
DCB word ~: Pointer to next DCB, or ~ if this
is the last.
DCB word 1: Bit 0 ~=high resolution mode
- l=low resolution mode
15Bit 1 ~=black on white back-
ground presentation
l=white on black back-
ground
Bits 2-7: HTAB: On each scan line of
this block, wait HTAB
16 bits before displaying
information from memory.
Bits 8-16: NWRDS:Each scan line in this
block is defined by NWRDS
16 bit words. (NWRDS must
be even).
- 28 -
~061006
DCB word 2: SA: Bit map "starting address"
(this address must be even).
DCB word 3: S~C: This block defines 2 x SLC
scan lines, SLC in each-
field.
At the start of each even and odd field, the display
controller 18(1) inspects DASTART and DASTART+l. An interrupt
is initiated on the channel specified by the ~its in DASTART+l.
The controller 18(1) then executes each DCB sequentially until
the display list or the field ends. At normal resolution, the
first scan line of the flrst (even) field of a block is taken
from location SA tot~A) (NWRDS-l). During each field, the bit
map address is incremented by NWRDS between each scan line. Thus,
although the display is interlaced, its representation in memory
is not. In low resolution mode, the video is generated at half
speed, and each scan line is displayed twice (once in each field).
During each field, the bit map address is not incremented between
the display of adjacent scan lines. This makes the format of
the bit map of the main memory store 17 identical for both
modes--only the size of the presentation is affected by the mode.
The storage of display data in the main memory store 17-will be
described in more detail below with reference to Figure 5.
The display controller 18(1) basically consists of
a main buffer 180, intermediate buffer 184 and serializing
shift register 186 (all shown in Figure 6), a sync generator
196 (Figure 7), and, as indicated above, the three microcode tasks
1-3, i.e. DWT, DHT and DVT, which control data handling and
communicate with the main program. Referring to Figures 6 and 7,
- 29 -
106~006
the 16 word buffer 180 is loaded from the bus 22 with the
DDR~function (F2=10, specific to the display word task DWT).
The purpose of the intermediate data buffer 184 is to
synchronize data transfers between the main buffer 180, which
is synchronous with a 170ns master clock, and the shift
register 186, which is clocked with an asynchronous bit clock~
The sync generator 196 provides the asynchronous bit clock and
the vertical and horizontal synchronization signals required
by the display 20(1), as shown in Figure 7.
The horizontal synchronization signal HSYNC is
generated from timing and state information presented at the
output of a programmable read-only memory 220 which receives
at its input the signals Bl, B2, B4, B8 and ~. The output
signals from the PROM 220 are latched in a latch 222, which
provides the synchronization signal HSYNC along with HBLANK
and the B field. The PROM 220 is preferably of the type 8223
by Signetics and the latch 222 is preferably of the type 74174
by Texas Instruments. The vertical synchronization signal
VSYNC is generated in a remaining portion of the logic constituting
the sync generator 196. A clock signal HLC is generated from the
ANDing from one of the output signals from the PROM 220 with a
clock signal DCLK in order to provide a clock signal to a half-
line counter 226 comprised of counter elements, preferably
type 9316 by Fairchild. The input to the counter 226 is a
hard-wired octal number which determines the number of scan
lines for the display 20 ll) . The half-line counter 226 counts
to the -limit provided by the signal LC which is generated
from a NAND gate 228 which decodes its input provided by the
-- 30 --
106100~i
output of the counter 226 to the signal LC. A PROM 232
processes the output of the counter 226 to generate input
signals to a multiplexer 234 which generates the signals
__
VBLANK and the vertical synchronication signal VSYNC. The
PROM 232 is preferably of the type MD 6300 by Microsystems
International and the multiplexer 134 is desirably of the
type 74298 by Texas Instruments.
The horizontal synchronization signal HSYNC is
inverted by an inverter 237 and then the synchronization
signals HSYNC and VSYNC are ORed by virtue of their
respective signal levels by a NAND gate 236 to provide a
composite synchronization signal. A latch 238 and a NAND
gate 239 provlde for the signal SWAKMRT which may be used
in the event a "MOUSE" cursor device is used as one of the
I/O devices 20.
In Figure 8, the field BUS( ~j-BUS(15) from the
bus 22 is shown loaded into the main buffer 80 under control
of the signal LOADMB. The signals MB~ ~A3 select the word
to be loaded from the bus 22. The main buffer 180 is comprised
of four memory elements, preferably type 3101A by Intel. The
output of the main buffer 180 is loaded into the intermediate
buffer 184 under control of the signal LOADIB. The buffer 184
is implemented by latches, desirably type 3404 by Intel.
Under control of the signal LOADSR, the shift register
186 is loaded by the output of the intermediate buffer 184.
The contents of the shift register 186 are clocked serially
from the register 186 by means of the clocking signal BITCLK.
The shift register 186 is implemented by two 8-bit shift
1061006
register elements, preferably type 74166 by Texas Instruments.
The output of the shift register 186 provides the video
signal which is processed through the video mixer 188 to the
display 20(1). The video mixer 188 is implemented by a NOR
gate 242 which'l"ORs" a curser video signal CVIDEO (assuming a
cursor unit is employed in the system) with the video signal
VIDEO. The output of the NOR gate 242 is further processed
by an exclusive OR gate 246, comprised of a pair of AND-gates
and a NOR-gate, all numbered 246, in order to provide the true
VIDEO signal. A NAND gate 248 allows an external video
signal VID to be provided the display 20(1). Horizontal blanking
of the VIDEO signal is provided by the signals CLR and the
output of a flip-flop 249 under control of the signals CLR and
BITCLK.
Referring to Figures 6 and 9, control over the data
exchange for the buffers 180 and 184 is provided by the
counters 202 and 204, whose outputs are received by-a comparator
210 and a multiplexer 212. The signal UNLOAD increments the
counter 202, while the counter 204 is incremented by DDR~f--
The output of the counters 202 and 204, i.e. R~ bits and WA
bits respectively, are compared by a comparator 210 to indicate
whether or not the main buffer 180 is empty or full. The
output signal STOPWARE indicates that the main buffer 180
is almost full; whereas the signal MBEMPTY in fact indicates
the buffer 180 is full. The comparator 110 is desirably
implemented by a PROM, type MD 6300 by Microsystems International.
The multiplexer 212, under control of the signal DDR~- , selects
whether the signals WA~-3 or RA~-3 are placed on the output
- 32 -
1061006
lines MBA~-MBA3. It has already been mentioned that MBA~-MBA3
select the words from the bus 22 for storage in the buffer 180.
Control logic 190 (Figure 6) is responsive to the output from
the comparator 210 to provide buffer control signals, including
the signal UNLOAD.
As shown in Figure 10, the control logic 190 is
comprised of a counter 255 which is desirably of the type 9316
by Fairchild and which counts to 15. A D-C flip-flop 257,
under control of IBEMPTY Cinte~mediate buffer not empty)
10 generates a load shift register signal LOADSR. Another D-C.
flip-flop 259 is responsive to the output of the flip-flop
257 to provide the signal IBEM~TY ~intermediate buffer empty)
signal at is Q output and the I~EMPTY signal at its ~ output.
A latch 160 latches the Q output of the flip-flop 159 prior
to "ANDingn with the signals I~EMTY unlatched, MBEMP~Y, and
DDR~- by means of the NAND gate 264. The output of the NAND
gate 264 provides the UNLOAD signal which causes transfer of
data from the main buffer 180 to the intermediate buffer 184
upon the conditions defined by the input signals. The UNLOAD
20 signal is also gated..by the NA~D gate 266 under control of a
signal DCARC to provide an output signal which controls the state
of the flip-flop 259. Further shown in Figure 10 is the
gating logic which provides the signals CLR and LOADMB.
Some of the more significant features of the
additional logic provided for the various clocking and control
signals required for the operation of the display controller
20(1) is that the bit clock is
- 33 -
1061006
disabled by vertical and horizontal blanking, and its rate
can be set by the microcode to either 50 or 100 ns, by the
function SETMODE (F2=11, specific to the display horizontal
task DHT). This function examines the two high order bits
of the processor bus 22. If bit ~=1, the bit clock rate
is set to 100ns period (at the start of the next scan line),
and a "1" is merged into the NEXT ADDRESS field. SETMODE
also latches bit 1 of the processor bus 22 and uses the
value to control the polarity of the video output. A third
function, EVENFIELD (F2=10, specific to DHT and to the display
vertical task DVT), merges a "1" into the NEXT ADDRESS field
if the display 20(1)is in the even field.
- As indicated previously, the display controller
18(1~ generates wakeup-task request signals 1-3 to the micro-
processor tasking logic. Task 3, the vertical task DVT, is
! awakened once per field, at the beginning of vertical retrace.
Task 2, the display horizontal task DHT, is awakened once at
the beginning of each field, and thereafter whenever the
display word task DWT (task 1) blocks. DHT can block itself,
in which case neither it nor DWT can be awakened until the
start of the next field. The wakeup-task request signal 1
for the display word task DWT is controlled by the state of
the main buffer 180. If DWT has not executed a BLOCK, if
DWT is not blocked, and if the buffer 180 is not full, DWT
wakeups are generated. The logic sets the buffer 180 empty
and clears the DWT block flip-flop at the beginning of
horizontal retrace for every scan line.
- 34 -
10~100~
The specific constitution of the main memory 16
as shown in figure 4 will now be described in more detail with
reference to Figures 4 and 5. As indicated above, the main
memory 16 includes an addressable main memory store 17 which
is desirably 64,000 words X 16 bits. The main memory 16 further
includes a conventional driver and parity checking circuit 19
connected to the store 17 by a 16-bit memory data bus 21.
Referring to Figure 5, the main memory store 17 is
preferably divided into 3 main storage sections. The first
section has various programs and non-display data stored
therein. The word DASTART, which points to the first DCB as
defined above, is located in this section.
The second section of main memory store 17 has
alphanumeric character fonts stored therein. Each word in
-- this section of the memory corresponds to a distinct scan
line of a distinct character. For example, a character may
require 12 scan lines on the display 20(1). In this event,
that character would be comprised of twelve, 16-bit wordc in the
font section of main memory store 17. The bits in each of these
twelve words that are binary "1" would define corresponding points
to be illuminated on the display when the character is formed
thereon. Under program control, the 12 word font definition of
a character to be displayed would be transferred into a designated
storage location in a third, display data section, of the main
memory store 17 for display at a corresponding location on the
display screen.
1061006
The third, display data section, has both the display
control blocks (DCB's) and the "bit map" to be displayed stored
therein. As indicated previously, each DCB contains the infor-
mation necessary to define the contents of a variable number
of scan lines defining a region on the display screen. The
DCB contains this number, as well as thè address in memory
from which the data for the region described by the DCB is to
be taken. The DCB also contains the address of another DCB
whose contents will be used when the scan lines described by
the first DCB have been displayed. There may thus be any
number of DCB's,each with an associated region of memory to be
displayed (i.e. segment of the bit map). As also indicated
previously, each segment of bit map contains a number of words
at least equal to the total number of displayed points in that
segment divided by 16, i.e. the number of bits per word in
the store 17. There are NWRDS words necessary to define a
complete scan line on the display screen. Each DCB contains
the value of NWRDS for the region it describes.
A memory reference to the main memory 16 is initiated
by executing Fl=6, MAR~t~ The program partially controls
memory timing, and must observe certain rules to insure correct
operation:-
a) There may be a minimum of one and maximum of
three microinstructions executed between start-
ing the memory and the data transfer.
-36-
1061006
b) During the fourth cycle after the
address from memory address register 114
has been loaded, if F2=6, a store of bus
data into the word addressed by register
114 will occur.
c) During the fourth cycle of a reference, if
BS=5, the reference is a fetch to the word
addressed by register 114.
d) During the fifth cycle of a reference, if
BS=5, the odd word of the double word
addressed by register 114 is deliv2red. The
memory cycle is extended by one cycle if both
words of a doubleword are fetched. If MD is
referenced during the fifth cycle, it must
- have also been referenced during the fourth.
e) If MD is referenced before the fourth cycle
of a reference, the processor will be suspended
until a total of 4 cycles have elapsed.
f) If RSELECT = 37B during the instruction which
starts the memory, a refresh cycle is assumed
and all memory cards are activated. This is
used by the refresh task.
g) The memory checks parity on all fetches, unless
the cycle is a refresh cycle, or the address is
177000 in which case an I/O device is being
referenced. Parity errors result in activation
of a task whose purpose is to deal with the
error.
-37-
~061006
The main memory store 17 is connected to the bus
22 through the memory data bus 21 and the drivers and parity
device 19, the latter providing for the transfer of data to
and from the store 17 with a parity check upon the fetching
of data from the store 17.
Exemplary microcode for implementing the data process-
ing display system as described above may further include as
other I/O devices 20 a disk driver, a "MOUSE" cursor unit and
five-finger keyset, an unencoded keyboard, an interfact to a
serial communication line referred to as "Ethernet," and
optionally a serial printer. The main microprogram is
referred to as an "emulator". The microassembler (MU) for
the CPU is preferably implemented in BCPL.
Although the invention has been described with respect
to a presently preferred embodiment, it will be appreciated
by those skilled in the art that various modifications, sub-
stitutions, etc. may be made without departing from the spirit
and scope of the invention as defined in and by the following
claims.
~ 38
