Note: Descriptions are shown in the official language in which they were submitted.
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Field of the Invention
. .
This invention relates to the field of electrical
memory apparatus, and more particularly to memory cells
utilizing a capacitor as the memory storage element.
Background of the Invention
Metal-insulator-semiconductor (MIS), and more
specifically metal-oxide-semiconductor (MOS), capacitor
memory cells are a form of dynamic memory cells. In an
MIS capacitor dynamic memory cell, the information is stored
in the form of the presence-vs-absence of charge in a
capacitor, thereby representing a binary digital state of
information. By "dynamic" is meant that the state of
information is either one or the other (or both) of the two
possible states tends to become degraded and ultimately to
disappear with the passage of time.
An MOS capacitor memory cell can take the form of,
for example, an N-type semiconductor covered with a
silicon-dioxide insulator layer upon which a metal or
metal-like electrical conducting plate is located. This
conducting plate of the MOS capacitor is maintained at a
fixed negative reference voltage while electrical writing
and reading pulses are applied to the semiconductor surface
portion of the capacitor (underlying the plate). A
positive-going voltage or current write-in pulse, applied to
the semiconductor surface portion of the MOS capacitor,
injects positive charges ("hole" minority carriers) into
this semiconductor substrate surface portion, thereby
bringing the MOS capacitor into its binary digital "1"
memory state ("full" of positive charge). On the other
hand, a negative-going voltage or current write-in pulse to
the semiconductor surface portion removes these positive
charges out of the semiconductor substrate surface portion,
thereby sharply reducing the positive charge in the
semiconductor surface portion and bringing the MOS capacitor
into its binary digital "0" memory state ("empty" of positive
charge). However, this binary "0" state tends to become
degraded with the passage of time subsequent to the negative-
going write-in pulse, due to the thermal regeneration of
spurious minority carriers (positively charged holes) in the
N-type semiconductor substrate. This degradation takes
place within the order of the semiconductor's thermal
regeneration time during operation, typically of the order
of a few milliseconds or less. However, even in the face of
this memory degradation, a negative-going write-in voltage
pulse can empty the MOS substrate surface portion of positive
charges and thereby produce the binary "0" state of information
for storage in the MOS capacitor at least for a short period
of time; whereas, the presence of positive charges in the
substrate surface portion due to a positive-going write-in
pulse can produce the binary "1" for storage in the MOS
capacitor.
In much of the prior art, in order to preserve the
binary "0" state, the access network for reading and writing
- was required to devote a substantial por~ion of its operating
time to the reading of the binary state of the capacitor
only for the purpose of refreshing by re-writing the same
state of the capacitor, that is, to read out and re-write
even when it was not desired to read out the binary memory
state of the capacitor for useful external aecess readout
of the information stored in the MOS capacitor. This
resulted in a significant loss of available access time
for reading and writing, which can be an important disadvantage
because system diagnostic testing consumes a substantial
portion of total operating time and thus reduces this
available access time, thereby putting a premium on the
remaining available access time. By reason of this need for
continual refreshing of the memory, not only was the memory
thus not always available for external-use reading and
writing, but the memory also required a substantial amount
of standby power to be expended in the refresh cycles. This
large expenditure of standby power arises from the fact that
the entire amount of charge in the capacitor being refreshed
must be removed, processed and returned during every refresh
cycle. In large scale memory arrays, this standby power can
thereby represent the greater portion of the total power
associated with operation of *he array. Moreover, in order
to minimize the amount of time used for refreshing the MOS
capacitor and hence increase the time available for external
access reading and writing, it was necessary that the
temperature of operation be kept rather low in order to
decrease the required frequency of refresh by increasing the
thermal regeneration time of charge carriers in the MOS
capacitor, since it was the thermal regeneration of charge
carriers which was responsible for the degradation and
disappearance of the binary "0" state. Thus, the heat~sinking
problems are rather serious especially in large scale arrays.
The detection networks for many of the prior art
MOS capacitor memory cell must be able to distinguish
between a fully charged cell and a cell which has been
partially filled by thermally generated carriers, thereby
imposing rather severe requirements on the detection margins
between the two sta~es of binary "0" and "1". Finally, many
of the prior art memory cells suffer from relatively low
64i~; ~
fabrication yield for mass memory arrays, due to localized
high direct-current generation sources in the silicon
substrate which can render any neighboring cells inoperative
after the relatively long times ~etween successive refreshes,
in turn due to the relatively low refresh frequencies used
in much of the prior art, of the order of a kilocycle.
Increasing the frequencies of refreshing in this prior art
would, however, concomitantly increase the required power
and decrease the useful operating memory time available
for external access reading and writing.
In a paper entitled "A Three Transistor MOS Memory
Cell with Internal Refresh", published in the 1972 IEEE
International_Solid-State Circuits Conference, pp. 14-15,
an integrated array of dynamic memory cells is described with
a mass refresh, that is, a refresh of all cells occurs by
means of read and write pulses to every cell. However, this
necessitates the use of a rather complex memory cell. ~ - -
Moreover, these read and write pulses for refresh must be
turned on and applied to the cells during time intervals
during which these cells are again not available for external
read or write access.
In U.S. patent 3,858,184, a peripheral circuit
technique for a purported automatic noninterrupting dynamic
memory refresh is set forth which, however, renders the
memory cells unavailable for external read or write access
during the refresh pulse intervals. While this patent
describes a technique for "aborting" the refresh at command
of the external access; nevertheless, the time required for
such "aborting" will necessarily undesirably increase the
access times themselves.
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In U.S. patent No. 3,795,898, a cross-coupled
transistor static memory cell configuration is disclosed
with an alternating-current (A.C.) charge pumped refresh.
(By "static" memory cell is meant a memory cell in which
the memory states do not become degraded with the passage of
time.) However, the cross-coupled static cell is rather
complex in structure. Moreover, an undesirably large
amount of external standby power is required for maintaining
and refreshing the memory states because, in order to get
rid of a relatively small amount of spurious electrical
eharge, a relatively large amount of eharge must be eontinually
shifted by the A.C. pump.
Accordingly, it would be desirable to have a
memory cell in which the refresh network is independent of the
aeeess reading and writing and whieh requires relatively low
refresh standby power.
Summary of the Invention
In order to provide an independent refresh to a
memory charge storage capaeitor, a first terminal portion of
the eapacitor is eonnected to one of the high current
carrying terminals of a first switching transistor in a
refresh network whieh is separate from a read-write aeeess
network for said eapaeitor. Another high eurrent earrying
terminal of the first switehing transistor is eonneeted to a
suitable voltage souree aeting as a sink for spurious
baekground eleetrieal eharges being aecumulated in the
memory capaeitor. By "high current carrying terminal" is
meant, for example, the source or drain of an insulated gate
field effect transistor (IGFET), or the emitter or colleetor
of a bipolar transistor. A low eurrent earrying terminal of
the first switehing transistor is eonneeted to a high
--5--
current terminal of a second switching transistor thereby
controlling the first switching transistor. Another high
current terminal of the second switching transistor is
connected to the first terminal of the memory capacitor, and
a low current terminal of the second switching transistor is
connected to a different terminal of the capacitor. By "low
current carrying terminal" is meant, for example, the gate
electrode terminal of an IGFET or the base terminal of a
bipolar transistor.
The capacitor has two memory states, one
characterized by an empty or nearly empty capacitor (digital
"0") and the other by a full or nearly full capacitor charge
state (digital "1"). In the digital "0" state, spurious
charge due to background charge generation in the semiconductor,
for example, is continually removed from the capacitor
through the first switching transitor to the voltage source
acting as a sink for spurious charges being generated in the
capacitor. In the digital "1" state, the first switching -
transistor is kept "off" so that the charge is not removed
from the capacitor, and the background charge being generated
in the semiconductor merely acts to maintain this digital
~; "1" state. In this way, the binary digital memory state
of the capacitor is preserved, as previously determined by
the semiconductor portion of the capacitor's being empty
of charge vs. being full of charge; and the capacitor can
be read or written independently of refresh.
In a specific embodiment of the invention, a
transistor memory cell includes an MIS (metal-insulator-
semiconductor) capacitor memory element, more specifically
an MOS capacitor element. The MOS cpacitor is gated for
useful access (reading and writing) by a gating transistor
Tl, typically an insulated gate field effect transistor
(IGFET). A portion of the surface region of a
morlocrystalline semiconductor substrate chip provides the
semiconductor region of the MOS capacitor, and the gating
IGFET is also integrated in another portion of the same
substrate. The semiconductor region of the MOS capacitor is
connected to the source regions of both of a pair of first
and second switching transistors, T2 and T3, both typically
of the IGFET type, also integrated in the same substrate.
One of the switching transistors (T2) has its drain region
connected to an A.C. "refresh line", and its gate electrode
connected to the drain of the other IGFET (T3). The gate
electrode of this other IGFET (T3) is connected to a D.C.
voltage source which advantageously also maintains the same
D.C. voltage potential on the metal plate of the MOS
structure. This D.C. voltage on the metal plate of the
capacitor is of negative polarity for an N-type semiconductor
substrate surface portion in the MOS capacitor,positive
for P-type. The semiconductor surface portion of the MOS
capacitor is thus subjected to a reverse bias voltage (positive
polarity for N-type semiconductor) relative to the metal
plate, thereby ensuring the continued formation of a depletion
layer in the MOS capacitor portion of the surface region of
the semiconductor substrate during operation. The refresh
line, to which the drain of the transistor T2 is connected,
is an electrically conductive line controlled by an A.C.
voltage "refresh" source, such
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that the refresh line voltage varies at an A.C. frequency between
potentials Vl and V2, where Vl is conveniently approximately
equal to the D.C. voltage applied to the plate of the MOS
structure, and V2 is a voltage typically about 5 to 10 volts
different from Vl. More specifically, V2 is electrically more
negative than Vl for an N-type semiconductor surface portion
in the MOS capacitor, and V2 is more positive than Vl for
P-type. Advantageously, the drain to gate electrode electrical
capacitance C2 (ordinarily due to parasitics, for example) of
the first switching transistor (T2) is advantageously greater
than the capacitance (C3) of the second switching transistor
(T3). The larger of these electrical capacitances (C2 of T2)
is itself advantageously less than the capacitance Cs of the
MOS capacitor by a factor of 5 or more. In this way, the
spurious charges in the memory element, such as thermally
generated minority carriers in the semiconductor substrate
of the MOS capacitor, are continually removed by the refresh
line and delivered to the A.C. refresh source acting as a
sink for these spurious charges. Reading and writing through
the gating transistor (Tl) can be performed as ordinarily in
the prior art, but now at any desired moment of time independent
of refresh.
Alternatively, the refresh line of the above
described circuit is held at the D.C. potential while the
metal plate of the MOS capacitor is subjected to an applied
A.C. voltage excursion, the semiconductor substrate being
held at a reverse bias D.C. voltage, thereby reducing the
magnitude of the required A.C. voltage excursion (l~swillg~l)
while maintaining a depletion region in the MOS capacitor
portion of the semiconductor surface operation. In yet
another alternative, both the refresh line and the metal
plate of the MOS capacitor are held at D.C. potentials while
the semiconductor substrate is subjected to an applied A.C.
voltage which swings about an average valve such that a
depletion layer is maintained in the MOS capacitor portion
of the surface of the semiconductor during operation.
An array of these memory cells, each controlled by
separate gating and switching transistors, can be integrated
in the same semiconductor chip together with an A.C.
oscillator for the refresh line pump source, for a large
scale memory in accordance with integrated circuit techniques.
Moreover, it is desirable that the A.C. refresh
voltage, being continuously delivered to all cells on a
single semiconductor chip, be interrupted whenever any cell
on that chip is being accessed for write-in. Thereby, the
possibility of spurious write~in due to the A.C. refresh
voltage is avoided.
The advantages of this invention thus include the
fact that useful access for reading and writing of the MOS
memory cell can be performed at any time (independent of
refresh). Thus, the memory is ready and available for
write-in including erase, as well as readout, at all times.
There is thus also no need in this invention for complicated
program control over external access, otherwise necessitated
by the refresh intervals of much of the prior art. In
addition, the standby power required for refresh is minimized,
since only the undesired thermally generated carriers are
removed from the memory cell. In this invention the entire
charge corresponding to a digital "1" (fully charged MOS
memory cell) does not now have to be
': ' ' ' ~ ' , ~
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shifted during every refresh, contrary to the prior art,
thereby requiring lower standby power. Moreover, since
the frequency of refresh in this invention can be as high
as 100 KHz or more in a dynamic memory configuration, a
higher operating temperature (shorter semiconductor
thermal regeneration time) can be tolerated, thereby
easing the heat-sink problem; or alternatively, by using
the lower range of operating temperatures of the prior art
in conjunction with this invention, localized undesired
high "dark" current background sources (corresponding to
"white video defects" in imaging devices) can be better
tolerated in the practice of this invention. Finally, in
this invention, the memory cell during operation
automatically is either full or empty of electrical
charges; whereas in much of the prior art, the readout
networks must distinguish between a fully charged MOS cell
(digial "1") and a cell which is unavoidably partially
filled (digital "0") due to the thermally generated
carriers in the semiconductor. Yet these carriers can
ordinarily be removed only once every millisecond
(otherwise, the available access time for reading and
writing would be even more curtailed in this prior art).
Thus, such a prior art cell is characterized by lower
detection margins for the same storage capacitor cell size.
In accordance with an aspect of the present invention
there is provided apparatus which comprises: a capacitor
memory element capable of storing electrical charge to
represent binary digital memory states of the element; a
first electrical network means for providing access
reading and writing signals to the element; and a second
electrical network refresh means including first and
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A
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second switching transistors, each having a pair of high
current terminals and a low current terminal, one high
current terminal of the first switching transistor being
ohmically connected to a terminal of the memory element
and the other high current terminal of the first switching
transistor being ohmically connected to an electrically
conductive refresh line, said refresh line having a
refresh terminal means for the connection thereto of
electrical means for acting as an electrical sink for
spurious charges in the memory element during operation,
one high current terminal of the second switching
transistor being ohmically connected to the one high
current terminal of the first switching transistor and the
other high current terminal of the second switching
transistor being ohmically connected to the low current
terminal of the first switching transistor, the low
current terminal of the second switching transistor being
connected to a different terminal of the memory element.
Brief Descr ptio of the Drawing_
This invention together with its features, advantages
and objects can be better understood from the following
detailed description when read in conjunction with the
drawings in which:
FIG. 1 is a schematic circuit diagram of an MOS memory
cell with refresh, in accordance with a specific
- 10a -
d:
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embodiment of the invention;
FIG. 1.1 is a schematic circuit diagram of an MOS
memory cell with refresh in accordance with an alternate
embodiment of the invention;
FIG. 2 is a top view of an integrated circuit
version of the MOS memory cell diagrammed in FIG. l;
FIG. 3 is a top view in cross section of the MOS
memory cell integrated circuit shown in FIG. 2;
FIG. 4 is a plot of refresh line voltage vs. time,
useful in describing the operation of a speGific embodiment
of the invention; and
FIG. 5 is a circuit diagram of a refresh line
voltage source useful for the operation of a specific
embodiment of the invention.
For the sake of clarity only, none of the drawings
is to any scale.
Detailed Description
As shown in the circuit of FIG. 1, an MOS memory
storage capacitor Cs is formed by a metal (or metal-like)
plate 11 separated by an oxide layer 12 from an N-type
semiconductor substrate surface portion 10. The semiconductor
substrate itself is advantageously reversed biased (not
shown in FIG. 1). The metal plate 11 is directly coupled
by ohmic connection to terminal 14 which is advantageously
maintained at a constant negative D.C. voltage, -V, as by
means of an external battery (not shown). This voltage -V
applied to terminal 14, in conjunction with the reverse
bias voltage applied to the semiconductor substrate, produces
a depletion region in the semiconductor region underneath
the metal (or metal-like) plate 11. Write-in of digital
"1" or "0" into the capacitor Cs is controlled by a "P
--11-- -
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channel" access gating IGFET device Tl whose gate terminal
voltage is controlled by a word line W and whose source
terminal voltage is controlled by a bit line B, as known
in the art. Bit line B is normally set at the negative
potential, -V; whereas, the word line W is set normally
at ground.
The write-in of positive charge, i.e., digital
"1", to capacitor Cs is achieved by a positive-going pulse
on bit line B applied to the source of Tl (top side of Tl)
accompanied by a negative-going pulse (turn "on") on the
word line W applied to the gate of Tl, thereby filling the
surface portion of the semiconductor substrate 10 in the
region underneath the metal plate 11 with positive charge
carriers ("holes"), in a quantity given by CsV (where V is
the D.C. supply at terminal 14). Removal of the negative
pulse to the gate of Tl prior to the termination of the
positive pulse to the source of Tl thereby traps these
positive charges in this substrate of capacitor Cs by
turning "off" the transistor Tl. This "off" condition
persists after a return of bit line B to its normally
negative voltage bias condition. Thus, the long-term
nonvolatile trapping and storage of this digital "1" state
in Cs is achieved.
The write-in of a digital "0", i.e., substantially
no charge in MOS capacitor Cs, is accomplished by a
negative-going pulse on word line W to turn "on" Tl while
bit line B remains at its normally negative voltage.
Thereby, the capacitor Cs is emptied of any positive charges
in the surface portion of substrate 10 associated with Cs
(underneath metal plate 11).
Readout of the charge state "1" or "0" of Cs is
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accomplished by a negative turn "on" pulse applied to word
line W with bit line B still in its normally negative bias
condition, thereby transferring positive charge (if any)
from Cs into bit line B for conventional readout and
followed by re-write if desired, as is known in the art.
However, as time passes in the absence of refresh means, the
thermal generation of minority carriers ("holes") would tend
to fill an empty Cs (digital "0") with undesired positive
charge, thereby spuriously converting the memory state to a
full capacitor Cs (digital "l") and completely degrading the
memory state.
The purpose of the auxiliary network of switching
P-channel IGFETs T2, T3, with capacitors C2, C3, C4 and C5,
in combination with an electrical refresh line L controlled
by an A.C. pump power supply source 13 applied to terminal
13.1, is to maintain the empty "0" state, as well as the
full "1" state, of Cs in the absence of any further write-
in voltage pulses on either the word line W or the bit
line B; thereby preventing degradation of the memory state
without need during operation for any tampering with the
word line W or the bit line B for any refresh purpose (as
opposed to the purpose of external access reading or
writing). Ordinarily, the capacitors C2, C3, C4 and C5 are
parasitics, and are therefore indicated in the drawing by
- dotted lines. Advantageously for this refresh purpose, the
A.C. vol-tage source 13 supplies a continuous uninterrupted
(except as described below) alternating voltage, at a
frequency of between about 10 KHz and l MHz, to the refresh
line L, advantageously varying approximately between the
limits of -V an~ -(V+~), where -V is the same voltage as
applied to terminal 14 and ~ is typically in the range of
-13-
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about 5 to 10 volts, advantageously about 8 to 10 volts.
Typically, -V is about -12 volts; however, during "down"
operation (no reading or writing), -V can be reduced to as
low as about -5 volts.
Although, hereinafter the limits of the A.C.
source 13 will thus be described as -V and -(V+~);
nevertheless, it should be remarked that these limits can be
advantageously set at -(V+VT) and -(V+VT+~) where VT (<0) is
the sum of the threshold voltage of T2 and T3 (where T2
usually predominates). These latter limits can be achieved
by means of a free running oscillator which feeds a
bootstrap type integrated driver circuit, as described for
example in a paper by R.E. Joynson et al, IEEE Journal of
Solid State Circuits, Vol. SC-7, No. 3 pp. 217-224 (June
1972) entitled: "Eliminating Threshold Losses in MOS
Circuits by Bootstrapping Using Varactor Coupling". The
upper and lower voltage limits of the A.C. source can both
be simultaneously lowered for a given A.C. excursion ~ (peak
to peak). The output of the A.C. source 13, in any event
need not be in phase with, or synchronized with, any other
voltage sources. The transistor T2 has its drain terminal
(right-hand side of T2) directly D.C. ohmically coupled to
refresh line L by way of a highly conductive ohmic path.
The gate electrode of T2 is directly D.C. ohmically coupled
to the drain terminal of T3. The gate electrode of T3 is
directly D.C. ohmically coupled to the terminal 14 (which
also controls the plate voltage of Cs). The node F (at the
gate electrode of T2) is A.C. coupled by (parasitic capacitances
C2, C3, C4, and C5 associated with this node F as follows:
to the refresh line L through the capacitance C2, to the
gate electrode of T3 through the capacitance C3, to the
source of T2 through the capacitance C4, and the remaining
parasitic to ground through the capacitance C5. Advantageously,
the capacitance C2 is greater than C3 + C4 + C5; however,
capacitance values of C2 somewhat less than this can be
used in conjunction with larger voltage excursions ~. The
capacitance C2 is advantageously significantly less than the
MOS capacitance Cs, advantageously by a factor of 5 or more,
in order to minimize the required value of the voltage
swing Q.
In the following description of operation, it will
be assumed that T3 is designed to have a threshold gate
voltage which is more negative than that of the MOS
capacitor under the same source and drain voltage
conditions. This "higher" threshold condition for T3 is not
essential, however, as will be discussed below. This higher
threshold can be achieved by such known techniques as ion
implantation (of donor impurities for P channel), increased
oxide thickness, or geometrical design effects, as known in
the art. Advantageously, the threshold of T3 is only
slightly more negative than that of the MOS capacitor,
typically by only about 0.5 to 1.0 volts. The peak to peak
swing ~ of the A.C. voltage on the refresh line L is
advantageously equal to or greater than about twice the
threshold voltage of T2. Typically, this swing ~ is in the
range of about 5 to 10 volts or more.
While the refresh line L oscillates in voltage
between -V and -(V+~), the A.C. voltage division produced by
P 2 3 C4 C5 (where C2 > C3 + C4 + C5) is
such that little of the A.C. voltage drop between source 13
and terminal 14 appears across C2. This tends to cause the
gate voltage-of T2 and the drain voltage of T3 to follow
1~3ti~
quite closely the oscillating voltage on L provided that the
transistor T3 is "off", that is, its gate semiconductor
surface region is not inverted from its source to its drain.
In this way, the memory state of Cs is preserved, in terms
either of a fully charged capacitor (with the charge equal
to CsV) or of an empty capacitor, as can be seen from the
following explanation.
Assuming the memory cell is in its digital "0"
state ("empty cell"), then the memory capacitor Cs is empty,
or nearly empty, of charge in the portion of the surface of
the semiconductor substrate under plate 11. Then, thermal
generation of charge in the semiconductor undesirably tends
to increase this charge in the positive sense, thereby
producing spurious charge in the memory capacitor. Moreover,
undesired positive charge on the gate of T2 also tends to
be generated. However, the spurious positive charge being
ge1~erated in a nearly empty capaci~or Cs, as well as any
undesirable charge on the gate of T2, will be drained off
and collected by the refresh line L thereby acting as a
charge sink for the spurious charge as follows. Due to the
fact that Cs is empty or nearly empty of charge, the
transistor T3 is "off", except when the refresh voltage
on the line L goes to -V, i.e., its most positive excursion.
More specifically, T3 then turns "on" at the positive
excursion of refresh line L if there is an undesired
positive charge accumulation on the gate of T2. Thus, on
the positive excursion of L (at and near -V), when T3 is
temporarily "on", any unwanted positive charge which has
accumulated on the gate of T2 is transferred through T3 into
Cs. Thereby, the voltage on the gate of T2 is prevented (on
every cycle of L) from becoming more positive than -V-VT3,
`` :L~ i41~
where VT3 is the (negative) threshold turn-on voltage of T3.
On the negative excursion of the refresh line L (i.e., at or
near -V-Q), the gate of T2 is made more negative by virtue
of the coupling capacitance of capacitor C2. For a
sufficiently large ~, T2 turns "on", thereby enabling the
spurious positive charge (both the previously transferred
charge from the gate of T2 and thermally generated charge)
in the substrate of the memory capacitor Cs to flow into the
line L itself. Summarizing this operation, with Cs empty
or nearly empty (digital "0"), on the positive excursion of
refresh line L any undesired positive charge on the gate of
T2 is transferred through T3 into Cs; whereas on the
negative excursion of L, any of that positive charge which
was just transferred to the substrate of Cs from the gate of
T2 (on the previous positive excursion of L) plus any
spurious positive charge which has been thermally generated
in the substrate of Cs is all transferred through T2 to the
refresh line L (where it is returned ultimately to the power
supply 13). Thus, a nearly empty cell is continually
refreshed to remain an empty cell on each cycle of the power
supply 13.
In the case of a digital "1" ("full cell") i.e.,
the semiconductor substrate surface portion 10 of the
capacitor Cs has a positive charge equal to, or nearly equal
to, CsV; therefore, T3 is always "on" regardless of the
voltage excursion of refresh line L between -V and -V-A.
Accordingly, since T3 is always "on", the gate of T2 is
maintained at the voltage of the positively charged
semiconductor surface portion of the capacitor Cs, so that
T2 is always "off" regardless of the excursion of the
line L. Thereby, the positive charge in the substrate of Cs
-
remains trapped because T2 can never turn "on" during any
portion of the A.C. cycles of the refresh line L.
It should be noted that the transistor T3 controls
the transistor T2; that is, whatever is the state of charge
in the memory cell, T2 is turned "off" whenever T3 turns
"on" and T2 is turned "on" whenever T3 turns "off".
During external access, read or write, the word
line W should normally be held at a potential of about 8 to
10 volts more negative than the threshold of the gating
transistor Tl. Thus, during rewrite the current through T
will be much greater than that through T2. Moreover, the
current through T3 when T2 is "on" tends to turn T2"off",
so that the success of attempted rewriting of the MOS
capacitor will be ensured.
In the above descriptions of operation with a full
and an empty cell, T3 was assumed to have a higher threshold
than both T2 and the semiconductor portion of the MOS
storage capacitor Cs, that is to say, T3 requires a more
negative-going gate voltage for turning "on" than does T2.
If this threshold condition is not satisfied, but the
thresholds of T2 and T3 are about equal, then, when the
refresh line L is on its negative excursion, T3 will turn
"on" even in the case of the empty cell during the same time
that T2 is also "on". The consequent flow of positive
charge through T3 then tends to turn T2 prematurely and
undesirably "off" during this negative excursion of L,
thereby tending to prevent the desired complete emptying of
Cs. This undesirable effect can be mitigated by utilizing a
relatively high frequency of output for the A~C. powers
supply 13, typically of the order of at least 100 KHz to
1 MHz, thereby enabling the transistor T2 to turn "on" more
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frequently, that is, during the more frequent negative
excursions of L, as desired for more efficient and complete
emptying of the positive charge in the capacitor Cs
substrate.
Nondestructive reading access (no rewrite required)
may be achieved by holding the bit line B and word line W
both normally at ground. Then for reading, a negative-
going pulse is applied on W, sufficient to turn "on" T
slightly, but not sufficient for T3 to turn T2 "ff"-
Thereby, during reading, T2 will drain off from the MOS
capacitor Cs to the refresh line L all the reading current
from Tl then being delivered into the MOS capacitor, without
changing the memory state of this MOS capacitor. However,
the reading must then be performed during the negative
phase of the excursion of refresh line L in order to enable
refresh line L to drain off the reading charge continuously.
It can be seen from the circuit diagram of FIG. 1
that the node F undergoes a voltage excursion of but a
fraction of the voltage excursion ~ of the refresh line L,
namely, the fraction ~ = C2/(C2 + C3 4 5
excursion ~ should be larger than the absolute value of
(Vt2/~). In order to increase the fractional excursion of
the node F relative to the applied A.C. source, an
alternative circuit shown in FIG. 1.1 can be employed in
which the refresh line L is held at a fixed D.C. potential
at its terminal 13.1 whereas an ~.C. source 14.1 is applied
via terminal 14 to the plate 11 of the storage capacitor Cs.
In this way, the required excursion ~ of the A.C.
source 14.1 can be made somewhat smaller typically an
excursion as low as about 4 volts, because the parasitic
capacitance C5 now aids C2 in keeping the node F at the
,, --19--
~41~
refresh line's potential. ~lore specifically, in the
circuit of FIG. 1.1, the terminal 13.1 of the refresh line L
is connected to a D.C. source (not shown) of voltage -V, the
same voltage as previously applied to the terminal 14 in the
circuit of FIG. l; whereas an A.C. voltage source 14.1
(FIG. 1.1) supplies a oscillating voltage at terminal 14 to
the metal plate 11 of the storage capacitor Cs. This A.C.
voltage source advantageously provides a voltage which
continuously oscillates between -V and -V +a, where ~ is
0 equal to or larger than the absolute value of VT2/~, where
2 5 /( 2 C3 + C4 + C5). Typically, ~ is about
6 volts. In this case, there is no need for a bootstrap
device in conjunction with the A.C. source, since the A.C.
voltage never need go more negative than -V. Thereby, the
refresh line L in the circuit of FIG. 1.1 again acts as a
sink for spurious memory cell charges as in the circuit of
FIG. 1 while the A.C. voltage source acts as charge-pump
tending to force these spurious charges into the sink.
Alternatively, the terminals 13.1 and 14 can both
be maintained at D.C. voltage -V while the substrate 10 is
connected to an A.C. voltage source, typically having an
A.C. excursion a of about 10 volts (peak to peak) with an
average D.C. level of about +5 volts for ~-type
semiconductor substrate 10. Again the refresh line L will
then collect and act as a charge-sink for spurious charges
accumulating in the storage cell Cs while the A.C. voltage
source acts as a pump tending to force these charges into
the sink; and again the semiconductor surface portion
underneath the metal-like plate 11 will be depleted during
operation while the substrate is thus being A.C. pumped.
A specific integrated circuit embodiment of the
-20-
Lt~'A
invention is shown in FIGS. 2 and 3. FIG. 2 is a top view
of this specific embodiment with both the second level
insulator oxides and "second level" conductor metallizations
removed for the sake of clarity; whereas FIG. 3 is a top
cross-section view of the surface at the semiconductor
substrate of this same specific embodiment. More
specifically, FIG. 2 shows the embodiment during an inter-
mediate stage of its fabrication, at a time when there
is present a relatively thick oxide coating with relatively
thin oxide portlons, plus the subsequently deposited "first
level metallization" of gate electrodes typically of
electrically conductive polycrystalline silicon ("polysilicon").
By " thick oxide" is meant silicon dioxide between about
5,000 Angstroms and about 15,000 Angstroms, typically about
13,000 Angstroms, that is, a suitable thickness for the
higher negative threshold (by about 20 volts) field oxide
of IGFET transistors; whereas by "thin oxide" is meant
between about 500 and about 1500 Angstroms, typically about
1,000 Angstroms, that is, a suitable thickness for the gate
oxide of lower threshold IGFET transistors. The thick oxide
is also advantageously sufficient to act as a mask against
the diffusion of a suitable acceptor impurity to render the
corresponding semiconductor surface portions P type in
those thin oxide regions which are not also masked by the
polysilicon. In FIGS. 2 and 3, a single complete memory cell
with refresh according to the invention is shown, together
with a left-hand portion of a similar reversed mirror image
cell located at the right-hand edge of the drawings, with
similar elements of the mirror image cell labeled with the
same reference numbers as in the completely shown cell plus
100 .
-21-
The semiconductor chip substrate 20 is essentially
a single monocrystalline N-type conductivity silicon chip of
substantially uniform electrical resistivity corresponding
to a uniform doping with 1015 arsenic impurity atoms per
cubic centimeter, except as otherwise indicated in FIG. 3
both where a donor ion-implanted (somewhat more strongly
N-type) surface zone 26.5 is situated and where strongly
P-type zones labeled P are situated. A D.C. battery 15,
typically of about 5 volts, supplies to the substrate 20 a
reverse bias (positive polarity for an N-type semiconductor
substrate). A metallic contact 21 to a P semiconductor
surface zone 22 is connected to the bit line B (FIG. 1) of
the second level metallization to external access circuitry
(not shown in FIGS. 2 and 3 for clarity only), as known in
the art. Thereby, the electrically conductive P surface
zone 22 in a corresponding surface portion of the semi-
conductor is connected to, and controlled by, the bit
line of the second level metallization. The P zone 22 also
serves as the source region of transistor Tl. A word
line 23 (W in FIG. l) is furnished by a metal-like -
polycrystalline silicon ("polysilicon") electrode strip 23.
This electrode strip 23 also overlies a portion of thin
oxide at the right-hand edge of P zone 22, so that the
N-type gate ("P-channel") region of the gating transistor
Tl, located between P+ zones 22 and 24, is controlled by the
potential on this strip 23. At the right-hand edge of this
gate region of Tl is located the P surface zone 24 under
thin oxide. This P+ zone 24 serves the dual role as the
drain region of transistor Tl as well as an electrically
conductive interconnection to the MOS storage capacitor Cs.
An N-type semiconductive surface zone 26 of the capacitor Cs
also lies underneath thin oxide. The left-hand edge of this
N type zone 26 is defined by the contour of a polysilicon
electrode 25 overlying the oxide 20.5. At the lower right-
hand corner of N zone 26 is located a donor ion-implanted
N-type zone 26.5, so that this N zone 26.5 has a somewhat
higher concentration of excess donors and hence a somewhat
more negative threshold voltage than the N zone 26.
Typically, the threshold voltage of zone 26.5 is about
0.5 volts more negative than that of zone 26. It should be
noted that instead of ion implantation, the increased
threshold for zone 26.5 can be achieved alternatively by
means of a slightly (10 percent to 30 percent) thicker oxide
overlying this zone 26.5 than the thin oxide overlying the
surface zone 26. Zone 26.5 serves as the gate region of T3,
while a portion of zone 26 bordering on zone 26.5 serves as
the source region of T3. As discussed previously, this
ion-implanted zone 26.5 is optional, and its location can be
alternatively filled with an extension of the zone 26 under
the polysilicon electrode 25. The right-hand edge of the
polysilicon electrode 25 thus overlies and defines the upper
right-hand edge of zone 26 (that is, the right-hand edge of
zone 26 except where the left-hand edge of the ion-im~lanted
zone 26.5, if any, is located, and except where the left-
hand edge of a thick oxide overlain N-type surface region 27
is located).
The rectangularly shaped N-type surface region 27
underlies a thick oxide region of the layer 20.5 (FIG. 2).
This N region 27 (FIG. 3) is thus characterized by a more
negative threshold voltage, typically by about 20 volts,
than the N zones 26 or 29 or even N zone 26.5O The P
zone 28 serves as the source of T2; whereas the P zone 30
-23-
serves as the drain of T3, and the N zone 29 serves as the
gate region of T2. The N region 27 separates the pair of
N-type surface zones 29 and 32 located underneath a portion
of a polysilicon electrode 33. This electrode 33 serves as
the gate electrode of T2. The N region 27 is located
underneath thick oxide, whereas the N zones 29 and 32 are
located underneath thin oxide; therefore, the N region 27 is
characterized by the higher negative threshold (by about
20 volts) than any of the N zones 26, 26.5, 29 and 32. An
ohmic metallic contact 31 connects the P zone 30 with the
polysilicon electrode 33. Finally, a P surface zone
strip 34, a portion of whose left-hand edge underlies in
advantageous registry with the right-hand edge of the
polysilicon electrode 33, runs in the plane of the drawing -
vertically across FIGS. 2 and 3. This P zone strip 34
serves as the refresh line L, and a portion of the left-hand
extremity of this strip 34, contiguous to the right-hand
edge of P zone 29, serves as the drain of T2.
Even though the oxide thickness underneath the
electrode 33 is the same in N zone 29 as in N zone 32;
nevertheless, during operation the N zone 32 will never have
a conducting surface inversion (channel) layer extending
from the P zone 30 to the refresh line 34, due to the ohmic
contact 31 connecting this P zone 30 with the gate
electrode 33. Capacitor C2 is the parasitic edge capacitance
between the gate electrode 33 and the refresh line 34.
For the sake of simplicity only in the drawings of FIGS. 2 and
3, the left-hand and right-hand edges of the refresh line
34 are straight lines. However advantageously in order to
increase the capacitance C2 relative to C3, the right-hand
extremity of the gate electrode 33 extends somewhat
--24--
1~4~
(typi-cally by 1 micron or more) to the right beyond the
right-hand extremity of the underlying thick oxide.
Moreover, the right-hand edge of the gate electrode 33 is
made serpentine in order to increase the length of the edge
and hence the edge capacitance C2. In this way, C2 can be
made larger than C3 + C4 + C5 as is desired (although not
essential). Thus, the layout just described in FIGS. 2 and
3 represents an integrated circuit version of the schematic
electrical circuit shown in FIG. 1.
It should be understood that the P strip 34 also
serves as the refresh line for the reverse mirror image
device located immediately to the right-hand side of this
strip, as well as serves as the refresh line for many other
similar devices integrated in the same wafer 20 above and
below that shown in FIGS. 2 and 3, in accordance-with "large
scale" integrated circuit technology. The free running
oscillator circuit, together with its bootstrap driver
circuit, associated with the A.C. pump source 13 (not shown
in FIGS. 2 and 3) can also be integrated in the same
wafer 20 in accordance with known integrated circuit technology.
It should be noted that, unless measures to be
discussed are adopted, spurious write-in can occur in the
circuits of FIG. 1 and FIG. 1.1 in case the threshold
voltage of N zone 26.5 (T3) is not sufficiently (by about
one volt) more negative than the threshold voltage of the N
zone 26 (Cs), in the presence of appreciable capacitance C2.
More specifically if the storage capacitor Cs is being
subjected to a write-in of a binary digital "0" (empty cell)
during a time interval tlt2 occurring at or near the most
negative portion of a refresh line cycle, then the storage
-25-
.' . '' , : '
capacitor Cs will draw a spurious charge due to displacement
current in C2 serially through T3, regardless of the desired
write-in. This charge may be sufficient thereafter to cause
T3 to prevent T2 from turning "on", thereby preventing the
storage capacitor Cs from emptying itself of the spurious
charge thereafter (subsequent to tlt2) and thereby enabling
the storage capacitor Cs to become spuriously filled with
thermally generated charge. Thus, the memory cell becomes
spuriously written with and stores a digital "1" (full cell)
even through the desired write-in was a digital "0". In
order to avoid such spurious write-in, as indicated in
FIG. 4, the A.C. refresh line voltage v (being delivered to
the refresh line L in FIG. 1) is suddenly interrupted and
set to the fixed level -V - VT (where VT = VT2 + VT3) for the
whole time interval tlt2 within which the storage cell Cs is
being accessed for write-in. Typically, the write-in access
time is of the order of 200 nanoseconds whereas the period
of the A.C. pump source 13 for refresh is of the order of
tens of microseconds, so that the interval tl to t2 is
ordinarily much less than a single A.C. cycle of the
source 13. Thereby, spurious write-in during access is
prevented.
FIG. 5 illustrates a typical circuit arrangement
for providing the refresh line uoltage characteristic of
FIG. 4. In FIG. 5, the semiconductor chip 20 contains an
array of many of the storage cells, typically about 4,000
cells, each cell of the type shown in FIGS. 2 and 3; and the
chip 20 typically contains the memory refresh line L,
branching out for different columns of cells (not shown).
Whenever any cell on the chip is to be accessed for write-in
(or perhaps read-out too), a chip enable signal source 50
64i~:~
delivers a signal to the chip 20 in order to enable this
chip to be accessed for write-in (or read-out) along a
selected word line and a selected bit line (not shown for
purposes of clarity only). At the same time, this chip
enable signal is also delivered to the gate of an insulated
gate field effect transistor 59 in an electrical network 60
for providing the desired interrupted A.C. refresh line
voltage.
The network 60 also includes an A.C. voltage
source 51, which supplies a continuous A.C. output voltage
sufficient to turn transistors 52 and 58 "on" and "off"
alternately. This A.C. output is delivered to the gate of
the insulated gate field effect transitor 58 and to the
input terminal of an inverter 57. The drain of the
transistor 52 is connected to a terminal 53 at which the
steady D.C. voltage -V is applied, typically -12 volts. The
source of the transistor 52 is connected both to a voltage
level-shifting capacitor 54 and to the drains of insulated
gate field effect transistors 58 and 59. The gate of the
transistor 52 is connected to the output terminal of the
inverter 57. Advantageously, the z/Q ~channel width to
length) ratio of transistor 52 is much less than that of
transistor 59. The level-shifting capacitor 54 couples as
the source of transistor 52 with the source of a clamping
transistor 55. The gate and drain of the transistor 55 are
both connected to a terminal 56 to which the steady D.C.
voltage -V is applied. Thereby, the refresh line L is
maintained at the desired voltage vs. time characteristic
shown in FIG. 4.
The operation of the network 60 may be described as
follows. The A.C. oscillator 51 supplies an A.C. output
- : ' :' ~ .
1~36~
voltage oscillating between about ground to -12 volts. This
A.C. output voltage aternately turns transistor 52 "on" or
"off", while alternately turning transistor 58 "off" and
"on" (due to the inverter 57). At the same time, in the
absence of any chip enable signal, the transistor 59 remains
"off". Thereby, node 53.5 oscillates in voltage between
ground and about -12 volts. By reason of the voltage
level-shifting capacitor 54 and the clamping transistor 55,
the refresh line voltage thus oscilla-tes typically between
about -9 and -17 volts, that is, an excursion which is equal
to ~V where ~ (less than unity) is the ratio CB/(CB + CL),
in which CL is the capacitance of the refresh line load, and
CB is the bootstrap capacitance.- However, if and when a
chip enable signal is forthcoming, then transistor 59 is
turned "on", thereby grounding the node 53.5 regardless of
the state of transistor 52 and thereby forcing the potential
of the refresh line L substantially to -V-VT for the
duration of the chip enable signal, since the resistance of
transistor 52 is much greater than that of transistor 59 (as
determined by the relative z/l ratios). It should be
understood that the A.C. output to the refresh line L
supplied by the circuit shown in FIG. 5 will not necessarily
be of sinusoidal profile, but this does not in any way
adversely affect the performance.
It should also be mentioned that when using the
A.C. refresh pumping in accordance with the circuit shown in
FIG. l.l, or with the above described substrate A.C.
pumping, the A.C. voltage is advantageously interrupted
during write-in access intervals in a similar manner as
indicated in FIG. 4. The network 60 can be integrated into
the chip 20 in ~ccordance with state of the art
-28-
semiconductor integrated circuit fabrication techniques.
In order to fabricate an array of memory cells in
accordance with this invention in a single silicon wafer
substrate, one may proceed as follows. Although the steps
will be described in terms of the fabrication of but a
single memory cell, it should be understood that many such
cells are being formed simultaneously in the single wafer
substrate as in the ordinary integrated circuit art. A
useful starting material is a wafer of monocrystalline
semiconductive silicon oriented (1,1,1) which is uniformly
doped with 1015 arsenic impurities rendering the silicon of
moderately N-type conductivity. The surface of the silicon
wafer is first cleaned and subjected to an oxidation process
at an elevated temperature of about 1050 degrees C for about
310 minutes, to form a thick oxide layer coating of about
13,000 Angstroms. Then a window in the oxide is formed, for
example, by the technique of electron beam lithography
followed by chemical etching, thereby exposing the semi-
conductor substrate in region 26.5. Next, ion
implantation of 30 kev phosphorous ions is carried out
through the window. Thereby, region 26.5 is implanted with
a surface concentration of 2xlOll phosphorous ions per
square centimeter. Next, again the technique of electron
beam lithography for selective masking followed by chemical
etching is used to open windows in the thick oxide in the
region where thin oxide is to be present. It should be
remembered that it is the contour of this thin oxide-thick
oxide boundary intersection which is indicated in FIG. 2.
Thereby, the silicon substrate is exposed in these windows
corresponding to thin oxide to be formed. The exposed
silicon is then oxidized by means of a dry hydrochloric acid
29
1~6~
process at an elevated temperature of about 1100 degrees C
for about 30 minutes, to form a thin oxide of about
1,000 Angstroms in thickness. Next, polysilicon is
deposited all over the top surface of the silicon wafer,
typically at about 760 degrees, to form a polycrystalline
silicon coating of about 8,000 Angstroms in thickness. As
deposited, this polysilicon coating typically does not
necessarily contain any purposeful impurities. In order to
render the polysilicon of sufficiently high electrical
conductivity to minimize electrical losses during operation,
phosphorus diffusion into the polysilicon coating is carried
- out, typically at about 1,000 degrees C for 35 minutes, so
that the polycrystalline silicon becomes of N+ (strongly N)
type conductivity. In order to protect the polysilicon
during further processing, an oxide layer, typically of
about 5,000 Angstroms in thickness is then formed to cover
the polysilicon coating, typically by oxidizing the
polysilicon in steam at about 1050 degrees C for about
50 minutes to form a 5,000-Angstrom-thick oxide layer.
Next, once again the process of electron beam lithography
for selective masking followed by chemical etching is used
to selectively remove both the oxide overlying unwanted
polysilicon and polysilicon itself in accordance with the
desired polysilicon electrode pattern for the electrodes 23,
25 and 33. This etching is continued for sufficient time to
expose the silicon substrate where the polysilicon has been
removed in regions of thin oxide (1,000 Angstroms) but not
thick oxide (13,000 Angstroms). Then a diffusion of boron
impurities into the top surface of substrate produces all
the desired P zones. Next an oxidation of the substrate is
carried out in steam at about 1050 degrees C for about
-30-
3641~.
5 minutes to produce a good quality thin oxide layer of
about 1,000 Angstroms of silicon dioxide. This good quality
oxide advantageously forms an interface with the previously
exposed silicon substrate portion, which is relatively free
of undesired interface states. At this stage in the
proeessing, the appearances of FIG. 2 is obtained, except
for the metallic eontaets 21 and 31. Then a ehemical vapor
deposition of silicon dioxide at a substrate temperature of
about 850 degrees C is earried out to eoat the previously
grown oxide with a silicon dioxide layer of about 11,000
Angstroms; thereby providing a proteetive insulated spaeing
(reduced parasitic capacitance) with respeet to the seeond
level metallization to be formed subsequently. Next, the
baek major surfaee (opposed the top surfaee) of the wafer 20
is stripped of oxide, by chemieal etching, while the top
surfaee with its oxide is proteeted from the etching by an
eteh-resistant mask. Then, an exposure of the baek surfaee
to phosphorous tribromide for about 35 minutes at 1000
degrees C serves to getter impurities, sueh as sodium,
out of the silieon substrate. Next, seleetive masking with
electron beam lithography followed by chemieal etehing on
the top surfaee selectively exposes small portions of the
top surfaee of the silicon substrate thereby produeing
suitable eontaet windows for metallie contaets 21 and 31.
Then a layer of aluminum is deposited, which is selectively
removed/ as by a process of electron beam lithography
followed by chemical etching, in order to provide the
metallic eontacts 21 and 31 as well as the desired second
level metallization pattern. Finally, the silicon wafer 20
is annealed in hydrogen, at a temperature of about
380 degrees C for about 20 minutes.
6~
Typical X and Y dimensions for the various
elements are approximately:
X(microns)Y(microns)
21 7 7
22 7 7
23 7 (extended)
24 7 28
28 (extended)
26.5 14 16
27 21 7
28 7 7
29 7 7
7 14
31 3.5 7
32 7 14
33 7 38
34 7 (extended)
~ hile this invention has been described in terms of
a specific embodiment, various modifications can be made by
those skilled in the art without departing from the scope of
the invention. For example, the A.C. refresh voltage can be
apportioned and applied simultaneously both to the
terminal 14 (as in FIG. 1.1) and to the terminal 13.1 (as in
FIG. 1). Such an apportionment may be required for error-
free operation in case the parasitic coupling between the
read/write circuitry and the metal plate 11 - terminal 14 is
strong enough to necessitate a reduced A.C. refresh voltage
at terminal 14 (which reduced A.C. voltage is not sufficient
by itself to refresh the memory cell). The A.C. refresh
pumping of charge to maintain the memory state of the
-32-
,~
:~3~
storage capacitor is thus determined among other factors, by
the A.C. voltage difference applied across the terminals
13.1 and 14. It should be remarked that the refresh voltage
used in FIG. 4 could be more negative at both upper and
lower limits, while preserving the same A.C. excursion of ~;
and that the network 60 can be integrated into the chip 20
using known semiconductor integrated circuit techniques.
Other semiconductors, and their oxides or other
insulators, such as germanium and its oxide, may be used
instead of silicon and in an integrated circuit version of
the invention. Moreover, the region 26.5 need not be
specially formed out of the region 26, but instead this
region 26.5 can be an extension of region 26; that is,
transistor T3 need not have a higher threshold than
transistor T2 as discussed previously, provided that the
higher indicated frequencies are utilized for the A.C.
source 13 during operation. It may be remarked that the
extra area required by the refresh network in this
invention, as illustrated in FIGS. 2 and 3, amounts only to
about 20 to 30 percent of the area occupied in the
semiconductor wafer by the conventional MOS cell formed by
the MOS capacitor Cs, the gating transistor Tl and the word
and bit lines.
It should be understood that while the invention
has been described in detail using P channel IGFET switching
transistors T2 and T3 in the refresh network, other types of
switching transistors, such as N channel IGFET transistors,
bipolar transistors or junction field effect transistors,
can also be used remembering that transistors generally have
three terminals, two of them being relatively high current
carrying terminals (source and drain in an IGFET, emitter
-33-
iO~ t~.
and collector in a bipolar transistor) and one of them being
relatively low current carrying terminal (gate electrode in
IGFET, base in bipolar). Instead of an MOS capacitor as the
memory element, other types of capacitors can be used, such
as a semiconductor P-N junction capacitor, or a capacitor
formed by a pair of metal plates separated by an insulator,
which also suffers from spurious charging due to electrical
charges çoming from the transistor (semiconductor) control
circuitry.
It should also be understood that although the
substrate surface portion 10 is shown with two separated
terminals for connection, respectively, to Tl and to T2 and
T3; nevertheless a single such terminal to the substrate
portion 10 can be used. Thus, in FIG. 3, the P zone 28 can
alternatively extend through a channel to the P zone 24.
-34-
