DIGITAL TIMEPIECE HAVING MEANS FOR SELECTIVELY OR SIMULTANEOUSLY DISPLAYING BOTH CONVENTIONAL TIME AND REMAINING TIME FUNCTIONS

CHRONOMETRE NUMERIQUE POUVANT AFFICHER SEPAREMENT OU SIMULTANEMENT L'HEURE ET UN COMPTE A REBOURS

English Abstract

Abstract of the Disclosure
The present invention relates to a digital timepiece having
means for selectively or simultaneously displaying both the conventional
elapsed time function and a remaining time function which the timepiece
counts-down to zero from a pre-set value.
Basically, the timepiece comprises a pulse-generator such as a
quartz oscillator generating time-standard pulses and dividing means for
generating pulses at spaced time intervals of seconds or fractions thereof.
Two sets of counters then operate simultaneously to respectively add the
generated pulses to give accumulated seconds, or fractions of seconds,
minutes and hours which are displayed in digital fashion as a conventional
elapsed time display, and to substract the generated pulses from a pre-set
time value to give a remaining time display.
Means are provided for either alternatively and selectively
displaying the elapsed time or remaining time, or simultaneously displaying
both functions. Preferably an audible alarm is provided to audibly indicate
when the remaining time indicated is at zero.

Claims

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE PROPERTY
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A digital electronic timepiece comprising: an oscillator
circuit for producing a relatively high frequency standard time signal;
frequency dividing circuitry arranged to produce a plurality of timing
signals from the standard time signal; digital display means arranged to
be driven by the timing signals and to display the actual time of day;
setting means for pre-setting a predetermined time interval in down-counter
means connected to receive the or some of the timing signals so that, in
operation, the content of the down-counter means is representative of a
remaining time interval, the display means being arranged to display the
remaining time interval.
2. A digital electronic timepiece as claimed in claim 1 including
selecting means for selectively causing the actual time of day and the
remaining time interval to be displayed.
3. A digital electronic timepiece as claimed in claim 2 in which
the selecting means is a manually operable switch.
4. A digital electronic timepiece as claimed in any of claims
1, 2 and 3, including alarm means which are energized when the predetermined
time interval has elapsed.
5. A digital electronic timepiece as claimed in any of claims
1, 2 and 3, in which the display device has a first portion for displaying
the actual time of day, and a second portion for displaying the remaining
time interval.
6. A digital timepiece comprising, in combination:

an oscillator circuit for producing relatively high frequency
time-standard pulses;
dividing means for generating pulses at regular time intervals as
a function of said time-standard pulses;
first counting means for adding said pulses from said dividing
means;
digital display means arranged to be driven by said pulses for
selectively displaying elapsed or remaining time;
first and second serially-connected logic gate means adapted to
selectively pass signals from said first counting means to said display
means whereat elapsed time is displayed as a function of the total pulse
accumulation in said first counting means, said display means being driven
through decoding and driving means for said signals;
second counting means in the form of a down-counter receiving
pulses from said dividing means;
setting means for setting a predetermined time value in said
second counting means;
third logic gate means serially-connected with said second logic
gate means and adapted to selectively pass signals from said second counting
means to said display means whereat remaining time is displayed as a function
of the contents of said second counting means relative to said predetermined
time value;
said first and third logic gate means being in the form of AND
gates and said second logic gate means being in the form of one or more OR
gates;
switch means serially connected to a potential supply source for
selectively applying enabling or disabling signals to a first input upon each
of said AND gates;
inverter means between said switch means and said first input

upon the or each said AND gate of said third logic gate means;
the or each said AND gate of said first logic gate means having
a second input adapted to receive said signals from said first counting
means as enabling signals for the or each said AND gate;
the or each said AND gate of said third logic gate means having
a second input adapted to receive said signals from said second counting
means as enabling signals for the or each said AND gate;
the or each said OR gate of said second logic gate means having
a first input adapted to receive output signals from a respective AND gate
of said first logic gate means and a second input adapted to receive output
signals from a respective AND gate of said third logic gate means.
7. The digital timepiece of claim 6, further comprising alarm
means for signaling when the contents of said down-counter of said second
counting means are at zero, said alarm means being energized by a potential
supply source through an AND gate having first and second inputs, said first
input connected to said potential supply source and said second input
connected to the output of a NOR gate, said NOR gate having a plurality
of inputs respectively connected to the outputs of said AND gates of said
first logic gate means.

Description

~;t;514
The present invention relates to a digltal tlmepiece having means
for selectively or si~ultaneously displaying both the conventional elapsed
time function and a remaining time functlon whlch the timepiece counts-down
to ~ero from a pre-set value.
The invention provides a digital electronlc timeplece comprising:
an oscillator circuit for producing a re.Latlvely hlgh frequency standard tlme
signal; frequency dividing circuitry arrlmged to produce a plurality of
timing signals from the standard time signal; digitial display means arranged
to be driven by the t-lming signals and to display the actual time of day;
setting means for pre-settlng a predetermlned time interval in down-counter
means connected to receive the or some of the timing slgnals so that, in
operation, the content of thè down-counter means is representative of a
remaining time interval, the display means being arranged to display the
remaining time interval.
Means are provided for either alternatively and selectively dis-
playing the elapsed time or remaining time, or simultaneously displaying
both functions. Preferably an audible alarm is provided to audibly in-
dicate when the remaining time indicated is at ~ero.
The invention will now be described further by way of example
only and with reference to the accompanying drawings wherein: ;
Figure 1 is a schematic diagram in logic-form of circuitry for
use in the timepiece according to one embodiment of the present invention;
Figure 2 shows a sequence of display steps of a timepiece
according to the embodiment shown in Figure l; and
Figure 3 shows a sequence of display steps of a timepiece
according to an alternative embodiment of the invention.
Referring to Figure 1, a quartz oscillator 1 feeds a chain
of serially connected counting elements 2, 3, 4 and 5. Counter ~ generates
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"seconds" yulses as a funccion of the input signal from quartz osclllator
1. Counter 3 generates a "minute" pulse for every ~ixty "seconds" pulse8
generated by co~lnter 2. Counter 4 generates an "hour" pulse for every
sixty "minutes" pulses from counter 3 and co-lnter 5 counts the number of
"hours" pulses generated by counter 4. The output from "minute" counter 4
is also applied via serially connected AND gates 9 and OR gates 10 to a
decoder/driver 11 which drives a digital display 13. Slmilarly, the output
from "hours" counter S is also applied via serially connected AND gates
18 and OR gates 19 to a decoder/driver 12 which drives the display 13.
10 The remalning input connections of A~D gates 9 and lô are connected to a
swltch 6a which is switchable bet~een a WATCH position and a TIMER position
for reasons which will hereinafter be explained. The remaining input con-
nections of the OR gates 10 are connected to the output connections of
AND gates 20 and the remaining input connections of OR gates 19 ~re
connected to the output connections of AND gates 21. One set of input
connections on the AND gates 20 and 21 is connected to the switch 6a through
an inverter 8. The remaining input connections to AND gates 20 are connected
to the outputs from a "minutes" count-down element 14 and the remaining
input connections to AND gates 21 are connected to the outputs from an
20 "hours" count-down element 15. The input connection to coùnter 14 is
connected to the output of an OR gate 25 and one input connection to gate
25 is connected to the output from "seconds" counting element 3. The input
connection to counter 15 is connected to tha output of an OR gate 26 and
- one input connection to gate 26 is connected to an output from counter 14.
The remaining inputs of both OR gates 25 and 26 are connected to outputs
from a time setting circuit 22.~
The circuit 22 enables the counters 14 and 15 to be set or reset
to begin counting down from any desired value of hours and minutes. A time- `~
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set output ~rom clrcuit 22 is also applied directly to input colmections
R upon counters 14 and lS. The input to time ~etting circult 22 ls connected
to the output from lnverter 8.
The outputs for counters 14 and 15 are also appl~ed to the input
connections to a NOR gate 23 and the output from gate 23 is applied to one
input of an AND gate 24. The other lnput of AND gate 24 i9 connected to an
output from time setting circuit 22 and the output of gate 24 is connected
to an alarm 17 through a driver circuit 16.
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When switch lever 6a is placed in the WATCH position, enabling
"1" level signal i5 applled through the contact 6 and enables ~ND gates 9.
The output of the "minutes" counter 4 is applied to the decoder/driver 11
via the OR gates 10, and is displayed upon display 13. Similarly AND gates
18 are enabled whereby the output of th~ "hours" counter 5 is applied to
the decoder/driver 12 via OR gates 19, and is displayed upon the display
t .0 ~
13. At this time, the "1" signal is inverted to "O" at the i~ of in~
verter 8, whereby AND gates 20 and 21 are disabled ~ thus preventing ~-
display of the timer function.
When suitch lever 6a ls placed in the TIMER position, a
disabling "O" level signal is applied through the contact 7 and disables
AND gates 9 whereby the "minutes" part of the time display is not dis-
played. The "0" signal goes to "1" level at the output of inverter 8,
whereby AND gates 20 and 21 are enabled and the outputs of counters 14
and 15 are applied to the display 13 via OR gates 10 and 19 and decod~r/
driversll and 12 respec~ively, whereby the "hours" and "minutes" functions
the timer are displayed. ~;
When the switch lever 6a is in the WATCH position, the "1"
signal is inverted to "0" via inverter 8, whereby the timer setting circuit
22 is inoperative. When the switch lever 6a is in the TIM~R posi~ion,
the "O" signal is inverted to "l" via inverter 8, whereby the setting
clrcuit 22 is actuated and can be utilized in conventional manner to
set the counters 14 and I5 to the desired time value as indicated by the
display 13. Once the desired initial time from which the count-down is
to proceed has been set, the counter 14 begins to count "seconds" pulses
from the "seconds" coùnter 3 and generate "minutes" pulses to the counter
15, which then counts these "minutes" pulses and generates "hour" pulses,
these pulses activiating the display 13 via gates 10, 19, 2~ and 21 and
driver/decoders 11 and 12 to show the remaining time. When the contents
of the counters 14 and 15 are completely at "0", NOR-circuit 23 generates
a "1" level signal, whereby the driver circuit 16 is enabled via AND
gate 24, which is also receiving a "1" level signal from circuit 22.

106~A
The driver circuit 16 drives the audible alarm 17 to indicate that the
time period for which the timer was set has elapsed.
The counters 14 and 15 are reset by generating a signal in
the circult 22 and app~ying the signal to counters 14 and 15 to clear the
display 13 of the remaining time display and to apply a "O" level signal
to AND gate 24 to disable gate 24 and turn off the alarm.
Figure 2 shows how the remainlng time display appears after
r ~ c~ l o ~.
switching from the normal SWITCH re&~a~t-. The hour display 31, minute
display 32 and date display 33 of the time display 30 are switched to the
remaining time display 34 having hour display 35 and minute display 36,
the remained time is set and thereafter the reducing condition of the
set time is indicated. The time is reduced minute by minute, until the~
alarm sounds when the hours and minutes remaining are down to zero.
Figure 3 shows a comblned actual time display and remain-ing
time display and is composed of hour display 40 and minute display 41
forming the display portion 38 and hour display 42 and minute display 43
forming the remaining time display 39. If the remained time display was
set to 1 hour 15 minutes, for example,the time is reduced minute by minute
until, at last, the alarm sounds when the remaining time is zero. There-
fore, the timepiece of the present invention is very useful for sports
or other uses where it is advantageous to have an alarmrset and the ability
to continuously monitor the remaining time as desired.
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