Note: Descriptions are shown in the official language in which they were submitted.
10~;'7~i~0
SEQUENTIAL COMP~TING SYSTEM
The present invention relates to data processing and,more particularly, to sequential computing systems. The inven-
tion is applicable in the designing of computing systems.
At present, individual objects are the most effectively
controlled by systems of minicomputers.
There are known minicomputers intended to control dif-
ferent objects; it should be noted, however, that such minicom-
puters are not practicable as far as calculation is concerned.
Calculations are normally done with the aid of calcu-
lators. Calculators of the most sophisticated types can operate
in conjunction with other computers; they are similar to mini-
computers in that they can control peripheral equipment.
These is a growing demand, however, for a computing
system composed of a number of computers. Each of these computers
must be based on the minicomputer principle and, on the other
hand, must be able to operate as a calculator. The major problem
in thls connection is the unification of computers, whereby it
may become possible to minimize the production costs of computers
intended for different purposes, which are employed in a comput-
ing system. The present invention provides a partial solution to
the problem of computer unification. An increase in the range of
functions performed by each computer in such a computing system
involves a substantial increase in the cost of equipment. On the
other hand, the use of the sequential method of data processing
in accordance with the present invention makes it possible to
considerably reduce the cost of equipment.
There is known a sequential computing system comprising
for example, one computer.
The known computer comprises first, second, third and
fourth shift registers, each having an input and an output. The
capacity of the fourth register is four bits.
~.
-- 1 --
~L~ 10f~76Z0
The output of the first register is connected via a
first gate to its input and the input of the second register.
The output of the second register is connected via a second gate
to the input of the third register and the input of the fourth
register. The output of th~ fourth register is connected via a
third gate to the input of the third register.
The computer has an adder with two inputs and an output.
One of the inputs of said adder is connected via a fourth gate to
the output of the second register; the second input of said adder
is connected via a fifth gate to the output of the third register;
the output of said adder is connected via a sixth gate to the
input of the first register. The computer further includes a
seventh gate whose output is connected to the input of the first
register, whereas the input of said seventh gate is connected to
an input bus. The output of the third register is connected via
an eighth gate to the input of the first register.
The computer also includes a microinstruction matrix
with an input decoder whose inputs are connected to outputs of
an address counter. Outputs of the microinstruction matrix are
connected to control inputs of the gates in order to apply control
signals to said gates to carry out operations of addition, as well
as shift and transfer operations.
The high degree of ordering in the structure of known
computing systems, which comprise seriesly connected registers and
matrices, makes it possible to produce computing systems on the
basis of LSI circuits.
The known computer under review operates as follows.
The registers store information entered via the seventh
gate, whereto there has been applied a control signal from the
microinstruction matrix. Circulation of information in the
registers is effected by applying control signals to the second
and eighth gates.
10~i7~;Z'0
Addition is performed with the aid of the adder. As
control signals are applied to the fourth and fifth gates, there
takes place a transfer of the contents of the second and third
registers to the adder which adds up the contents of the second
and third registers. As a control signal is applied to the
sixth gate, the result of the addition is transmitted via the
conduction sixth gate to the first register to be stored there.
The transfer of the contents of one register to another
is effected through the adder by applying control signals to the
fourth and sixth gates.
The transfer of the registers' contents in the opposite
direction, i.e. the transfer of the contents of the first regis-
ter to the second, while preserving the original contents in the
first register, is carried out via the conducting first gate.
A shift operation is effected by applying a control sig-
nal to the third, fourth and sixth gates. As this takes place,
the contents of the third register is transferred to the fourth
register with a shift by one decimal digit.
Addition, shift and transfer operations make it possible
to carry out any calculations.
The sequence of operations is dependent upon the micro-
program. The microprogram is a sequence of microinstructions
stored in the microinstruction matrix.
The sequence of microinstructions is set by the micro-
instruction address counter. Each state of the address counter
corresponds to a microinstruction.
Output signals of the address counter are applied to the
decoder of the microinstruction matrix. The decoder selects one
of the matrixls numerous buses, which bus determines the set of
control signals to be applied to the gates to carry out the pre-
scribed microinstruction.
A change in the state of the address counter is followed
1~67620
by carrying out the next microinstruction. Thus there are
selected the prescribed microinstructions which make up a
specified microprogram.
The computing system under review possesses a limited
set of microinstructions, for which reason it cannot be used to
control peripheral equipment and technological processes. The
connections between individual units of the known computing
system do not make it possible to unitize said system.
It is an object of the present invention to provide a
sequential computing system comprising at least one computer with
an enlarged set of microinstructions, which would be able to
solve mathematical problems and problems of controlling peripheral
equipment and technological processes and which would have a
structure that would make it possible to unitize and reprogram
the computing system, and which structure would be ordered so
that the computing system can be built around a s~ngle LSI crystal.
The foregoing object is attained by providing a sequen-
tial computing system for solving mathematical problems and con-
trolling peripheral equipment andtechnologicalprocesses, compris-
ing at least one sequential computer having an adder to processinformation, seriesly connected registers which are the main
memory of the computer, a direct output of the last register
being connected via a gate to a first input of the adder, an
input of at least one register being connected via respective
gates to an output of the preceding register and a first output
of the adder, a microinstruction matrix to control the gates,
which computer comprises, in accordance with the invention, at
least one additional accumulator registered intended for temporary
storage of a signal applied thereto from the output of the adder,
its input being connected via a respective gate to the first out-
put of the adder and via another gate, to its own direct output,
the direct and inversion outputs of the accumulator register being
~0~762V
connected via respective gates to the second input of the adder,
at least one single-digit Link register to store a transfer sig-
nal and initiate signals to control branching of the program
depending on subproducts of calculations, its input being con-
nected via a gate to its direct output and via another gate, to
the second output of the adder, the input of the first register
of the seriesly connected registers being connected via respec-
tive gates to the direct output of the last register of the
seriesly connected registers, the direct output of the accumu-
lator register and the output of at least one more register ofthe seriesly connected registers, the computer further including
a program matrix with a device for commutation of input signals
of the program matrix and with a device for commutation of output
signals of the program matrix to store and select the program of
problems to be solved, a synchroprogram matrix with a device for
commutation of input signals of the synchroprogram matrix and an
output decoder of the synchroprogram matrix to store and select
synchroprograms, each synchroprogram being a sequence of addresses
of microinstructions, a controlled synchronizer for double-
periodic synchronization of the computer units, comprising atleast three seriesly connected counters to initiate time-
separated clock signals, and at least one control signal forming
unit connected to a respective counter of the controlled synchron-
izer, the device for commutation of input signals of the micro-
instruction matrix being connected to the output decoder of the
synchroprogram matrix, the device for commutation of input sig-
nals of said synchroprogram matrix being connected to a device
for commutation of output signals of the program matrix, making
up a two-level system of data processing control, the device for
commutation of input signals of the synchroprogram matrix being
connected to one aounter of the controlled synchronizer, the
output decoder of the synchroprogram matrix being electrically
10~7~;~0
.
coupled to the control signal forming ullit of the controlled
synchronizer to set a sequence of microinstructions, the inputs
of the device for commutation of input signals of the program
matrix being connected to the outputs of the address counter
whose one group of inputs is connected to respective outputs of
the device for commutation of output signals of the program
matrix, whereas the other group of inputs is connected to the
outputs of the address counter control unit whose one group of
inputs is connected to respective outputs of the device for
commutation of output signals of the program matrix, its other
group of inputs being connected to outputs of a respective
counter of the controlled synchronizer, whereas its separated
input is connected to the output of the single-digit Link
register.
It is expedient that in the proposed sequential com-
puting system, at least one computer should include an additional
gate for carrying out a disjunction operation, said gate being
placed between the direct output of the last register and the
second input of the adder.
It is desirable that in at least one computer of the
proposed sequential computing system, the seriesly connected
registers and the accumulator register should be four-digit
shift registers, all the gates and the adder should be single-
channel circuits, and the first counter of the controlled
synchronizer should be intended for determining the time required
to process four bits of information.
It is desirable that in at least one computer of the
proposed sequential computing system, the accumulator regist~r and
the seriesly connected registers should be multichannel shift
3Q registers, while the adder and all the gates should be multi-
channel circuits, the control inputs of the multichannel gates
being combined and connected to the outputs of the microinstruc-
tion matrix.
() "
It is preferable that in at least one computer of the
proposed computing system, the electric connection between the
output decoder of the synchroprogram matrix and the control
signal forming unit of the controlled synchronizer should be
effected through a synchroprogram commutation unit intended to
change the sequence of selecting microinstructions, which is set
by the synchroprogram matrix, its one group of inputs being
connected to the outputs of the control signal forming unit of
the controlled synchronizer, its other group of inputs being
connected to respective outputs of the device for commutation
of output signals of the program matrix, whereas its outputs are
connected to inputs of the output decoder of the synchroprogram
matrix.
It is expedient that at least one computer of the pro-
posed sequential computing system should include an address
register intended to produce complex branching of the program/
one group of its inputs being connected to respective outputs of
the device for commutation of output signals of the program matrix,
its second group of inputs being connected to outputs of a con-
trol unit of the address counter, its third group of inputs beingconnected to control inputs of the computer, at least one more
input being connected to one of the seriesly connected registers,
whereas outputs of the address register are connected to respec-
tive inputs of the address counter.
It is also expedient that at least one computer of the
proposed sequential computing system should include an output
matrix with a device for commutation of input signals, intended
for output of information, outputs of said matrix being connected
to control outputs of the computer, a code conversion unit, at
least one of its inputs being connected to one register of the
seriesly connected registers, its other input being connected to
one output of the second counter of the controlled synchroni~er,
'- 10~;7~:;Z0
its outputs being connected to inputs of the device for commuta-
tion of input signals of the output matrix whose outputs are
connected to inputs of the output matrix.
It is preferable that in at least one computer of the
pxoposed sequential computing system, the additional control
inputs of all the gates at the inputs of the seriesly connected
registers should be connected to additional outputs of the device
for commutation of output signals of the program matrix.
It is also preferable that at least one computer of the
proposed sequential computing system should include two code
forming circuits and an AND circuit, intended to form constants
required for carrying out operations involving decimal numbers,
inputs of the first code forming circuit being connected to res-
pective outputs of the first counter of the controlled synchron-
izer, an output of the first code forming circuit being connected
via a respective gate $o the second input of the adder, the same
- outputs of the first counter of the controlled synchronizer being
connectea to respective inputs of t~.e second code forming cir-
-` cuit whose output is connected to a first input of the AND cir-
cuit whose second input is connected to the inverting output of
the single-digit Link register, an output of the AND circuit being
connected via a respective gate to the first input of the adder
connected via a respective gate to the inverting output of the
- last register of the seriesly connected registers, the third
input of the adder being connected via a respective gate to the
direct output of the single-digit Link regi~ster.
It is expedient that at least one computer of the pro-
posed sequential computing system should include a flip-flop to
entex digital information from peripheral devices into the com-
` 30 puter/ an input of said flip-flop being connected to an output
of a multiple-input gate whose group of inputs is connected to
respective inputs of the address register, one more of its inputs
-- 8 --
. .
., . . .
~ . . ,
~Oti7ti ~0
being connected to a respective output of the address counter
control unit, an output of said flip-flop being connected to a
respective input of the address counter control unit and, via
a respective gate, to the third input of the adder.
It is also expedient that in order to synchronize the
units of the computing system, at least one computer of said
system should be provided with a synchronization input and a
synchronization output respectively connected to the input of
the first counter and the output of the last counter of the con-
trolled synchronizer, a respective output of the first counterbeing connected via a specified gate to the third input of the
adder.
It is preferable that at least one computer of the pro-
posed sequential computing system should have an additional gate
to connect the direct output of the accumulator register to the
separated output of the computer, and additional seriesly con-
nected registers to expand the main memory of the computer, the
output of the last register of the additional seriesly connected
registers being connected via a respective gate to the separated
2Q output of the computer and via a respective gate, to the first
input of the adder, the input of the first register of the addi-
tional seriesly connected registers being connected to the separ-
ated input of the computer.
It is expedient that the computing system should com-
prise a prescribed number of sequential computers connected so
that the separated input of each preceding computer is connected
to the separated output of the following computer, whereas the
separated input of the last computer is connected to the separated
output of the first computer whose synchronization output as
3Q connected to synchronization inputs of all the following computers.
It is expedient that the computing system should include
at least one external shift register comprising an output buffer
10~7~;Z(~
device to connect the external shift reyister to a respective
computer, an input of the external shift register being connected
to a separated output of the last computer, whereas the output
buffer device is connected to the separate input of the first
computer.
It is also expedient that in the proposed computing
system, the output buffer device of the external shift register
should include two followers, each comprising a first transistor
whose drain is connected to a first clock pulse bus, its gate
being connected to an input of the follower, whereas its source
is connected to an output of the follower and the drain of a
second transistor whose gate is connected to a second clock pulse
bus, its source being connected to a common bus, there being
placed between the gate and source of the first transistor a posi- : :
tive feedback capacitor, the input of the first follower being
connected to an output of an inverter whose input is connected to
an input of a buffer device and the drain of a third transistor
whose gate is connected to the second clock pulse bus, the output
of the first follower being connected to the gate of a fourth
transistor whose drain is connected to a first supply bus, its
source being combined into a common point with the drain of a
fifth transistor whose source is connected to the common bus,
whereas its gate is connected to the output of the second follower
and the gate of a sixth transistor whose source is connected to
the common bus, whereas its drain is combined into a common point
with the source of a seventh transistor whose drain is connected
to the first supply bus, its gate being combined with the source
of the third transistor and the input of the second follower,
there being connected to the common point, formed by the source
of the seventh transistor and the drain of the sixth transistor,
the gate of an eighth transistor whose drain is connected to a
second supply bus, whereas its source is combined with the output
-- 10 --
10~76~0
of the buffer device and the drain of a ninth transistor whose
source is connected to the common bus, its gate being connected
to the common point formed by the source of the fourth transis-
tor, the drain of the fifth transistor and the gate of the sixth
transistor.
It is also expedient that in at least one computex of
the proposed sequential computing system, the instruction address
counter should be a system of flip-flops seriesly connected via
gates, in which systern the output of the penultimate flip-flop
is connected via an inverter and a gate to the input of the first
flip-flop.
It is preferable that in the proposed computing system,
the device for commutation of input signals of the matrices
should include a decoder to provide for conduction between the
common input and one of the outputs of the decoder, depending
upon which code has been applied to the address inputs of the
decoder, first and second exciting circuits of the decoder, an
output of each of said circuits being connected to a respective
address input of the decoder, a discharge device whose inputs are
connected to outputs of the decoder and inputs of a respective
matrix, an inverter whose output is connected to the common input ~:
Q~ the decoder, while its input is connected to a first clock
pulse bus, each of the first exciting circuits of the decoder
including a first transistor whose drain is connected to an add-
ress signal bus, its gate being connected to a second clock pulse
bus, whereas its source is connected to the gate of a second tran-
sistor whose source is connected to a third clock pulse bus, while
its drain is connected to an output of said exciting circuit of
the decoder, there being placed between the drain and gate of the
second transistor a positive feedback capacitor, each of the
second exciking circuits of the decoder including a third tran-
sistor whose source is connected to the second clock pulse bus,
-- 11 --
1~6'~ZO
its gate being connected to the address signal bus, while its
drain is connected to the source of a fourth transistor whose
gate and drain are connected to the second clock pulse bus and
the gate of a fifth transistor whose drain is connected to an
output of said exciting circuit, its source being connected to
the third clock pulse bus, there being placed between the source
and gate of the fifth transistor a switchable capacitor whose
:~ control electrode is connected to the gate of the fifth transistor :
its other electrode being connected to the source of the same ~ `
transistor, the discharge device comprising transistors whose
drains are connected to inputs of the discharge device, their
gates being connected to the first clock pulse bus, while their
sources are connected to the common bus.
It is also preferable that in at least one computer of
the proposed sequential computing system, the device for commuta- ~
tion of output signals of the program matrix should comprise a -
decoder to provide for conduction between its inputs and outputs,
depending upon which code has been applied to the address inputs
of the decoder, first and second exciting circuits of the decoder,
.20 an output of each of said circuits being connected to a respective
address input of the decoder, a charger whose outputs are con-
nected to the inputs of the decoder and outputs of the program
matrix, each of the first exciting circuits of the decoder includ-
ing a first transistor whose drain is connected to an address sig-
. nal bus, its gate being connected to the second clock pulse bus,
~hile its source is connected to the gate of a second transistor
whose source is connected to the third clock pulse bus, its drain
being connected to an output of said exciting circuit, there being
placed between the drain and gate of the second transistor a posi-
tive feedback capacitor, each of the second exciting circuits of
the decoder including a third transistor whose source is connected
to the second clock pulse bus, its gate being connected to the
- 12 -
'7~
address signal bus, whereas its drain is connected to the source
of a fourth transistor whose gate and drain are connected to the
second clock pulse bus and the gate of a fifth transistor whose
drain is connected to an output of said exciting circuit, its
source being connected to the third clock pulse bus, between the
source and gate of the fifth transistor there being placed a
switchable capacitor whose control electrode is connected to the
gate of the fifth transistor, its other electrode being connected
to the source of the same transistor, the charger comprising
transistors whose sources are connected to outputs of the charger,
their gates being connected to the first clock pulse bus, while
their drains are connected to the supply bus.
It is also preferable that each computer of the pro-
f posed sequential computing system should be built around a single
semiconductor substrate.
The present invention substantially reduces the design-
ing and manufacturing costs of computing systems, for computers
incorporated into each system are of the same structure and differ
only in the way their matrices are threaded (which provides for
reprogramming of a computer); the threading of matrices is altered
by replacing only one masking element when manufacturing an LSI
circuit. A masking element is a mask with holes whose location is
determined by the computer's software.
The proposed sequential computing system performs the
functions of a minicomputer, wherefore it can be used to control
pexipheral e~uipment and technological processes, as well as to
solve mathematical problems.
Other objects and advantages of the present invention
will become more apparent from the following detailed description
3Q of preferred embodiments thereof taken in conjunction with the
accompanying drawings, wherein:
Fig. 1 is a functional diagram of a sequential computing
- 13 -
10~76'~0
system comprising one sequential computer, in accordance with the
invention;
Fig. 2 is a block diagram of a sequential computing
system comprising three sequential computers and external regis-
ters, in accordance with the invention;
Fig. 3 is a functional diagram of an instruction add-
ress counter of a sequential computer, in accordance with the
invention;
Fig. 4 is an electric diagram of an output buffer
device of an external register of a sequential computer, in
accordance with the invention;
Fig. 5 is an electric diagram of a device for commuta-
tion of input and output signals of program, synchroprogram,
microinstruction and output matrices of a sequential computer, in
accordance with the invention;
Figs. 6a and 6b are voltage time plots of clock pulses,
illustrating operation of the output buffer device of the exter-
nal register of a sequential computer, in accordance with the
invention;
Figs. 7a, 7b and 7c are voltage time plots of clock
pulses, illustrating operation of the devices for commutation of
input and output signals of the matrices, in accordance with the
invention;
Fig. 8 is a table of alterations of information in the
seriesly connected registers 21, ..., 236 when carrying out cir-
culation microinstructions, in accordance with the invention;
Fig. 9 is a table of alterations of information in the
seriesly connected registers 21, ..., 236 when carrying out the
operation of replacing the word ~ by the word ~ , in accordance
with the invention.
Consider now the embodiment wherein a sequential comput-
ing system for solving mathematical problems and controlling peri-
- 14 -
10~7~0
pheral equipment and technological processes comprises a sequen-
tial computer 1 (Fig. 1). The computer 1 has seriesly connected
registers 21, ..., 2i, 2k~ m n
A direct output 3 of the last register 2 in connected
via a gate 4 to a first input 5 of an adder 6.
An input of the register 2i is connected via respective
gates 7 and 8 to an output of the preceding register 2i 1 (not
shown) and a first output 9 of the adder 6.
The sequential computer 1 also includes a microinstruc-
tion matrix 10 having outputs 101, .. , lOt.
According to the invention, the computer 1 further com-
prises an additional accumulator register 11 whose input is con- :
nected via a gate 12 to the output 9 of the adder 6 and via a
gate 13, to its own direct output 14.
The direct output 14 of the accumulator register 11 is
connected via a gate 15 to a second input 16 of the adder 6. An
inverting output 17 of the accumulator register 11 is connected
via a gate 18 to the second input 16 of the adder 6.
The computer 1 further comprises a single-digit Link
20 register 19 whose input is connected via a gate 20 to its direct
output 21 and via a gate 22, to a second output 23 of the adder 6.
An input of the register 21 is connected via gates 24,
25 and 26 to the direct output 3 of the last register 2n, the
direct output 14 of the accumulator register 11 and an output of
the register 2m, respectively.
The computer 1 includes a program matrix 27 with devices
28 and 29 for commutation of input and output signals, respec-
tively, a synchroprogram matrix 30 with a device 31 for commuta-
tion of input signals and an output decoder 32, and a controlled
30 synchronizer.
The controlled synchronizer comprises three seriesly
connected registers 33, 34 and 35 and a control signal forming
~O~ 7~;~0
unit 36 connected to the counter 35.
A device 37 for commutation of input signals of the
microinstruction matrix 10 is connected to the output decoder
32 of the synchroprogram matrix 30.
The device 31 for commutation of input signals of the
matrix 30 is connected to the device 29 for commutation of output
signals of the program matrix 27.
The device 31 for commutation of input signals is con-
nected to the counter 34. The output decoder 32 is electrically
coupled to the control signal forming unit 36 of the controlled
synchronizer.
Inputs of the device 28 for commutation of input sig-
nals of the program matrix 27 are connected to outputs of an
address counter 38 whose inputs 39 are connected to outputs 40
of the device 29 for commutation of output signals of the program
matrix 27, its other inputs being connected to outputs 41 of an
address counter control unit 42.
: Inputs 43 of the unit 42 are connected to respective
outputs of the device 29 for commutation of output signals of the
program matrix 27. Inputs 44 of the unit 42 are connected to
respective outputs of the counter 35 of the controlled synchroni-
zer; its separated input 45 is connected to the output 21 of the
single-digit Link register 19.
: The input of the first counter 33 is connected to a
synchronization input 46 of the computer 1. Outputs of the
counter 35 are connected to synchronization outputs 47 and 48 of
the computer 1. ..
~n output 49 of the counter 33 is connected via a gate
50 to a third input 51 of the adder 6.
Other outputs 52 of the counter 33 are connected to
inputs of a code forming circuit 53 whose output is connected via
a gate 54 to the second input 16 of the adder 6.
0
The same outputs 52 of the counter 33 are connected to
inputs of another code forming circuit 55 whose output is con-
nected to an input 56 of an AND circuit 57. Another input 58 of
said AND circuit 57 is connected to the inverting output of the
single-digit Link register 19. An output of the AND circuit 57
is connected via a gate 59 to the first input 5 of the adder 6.
The first input 5 of the adder 6 is also connected via
a gate 60 to an inverting output 3' of the register 2n.
The third input 51 of the adder 6 is connected via a
gate 61 to the direct output 21 of the single-digit Link register
19 .
According to the invention, the computer 1 has an addi-
tional gate 62 whose input 63 is connected to the direct output
3 of the register 2n and the second input 16 of the adder 6.
According to the invention, the computer 1 includes an
additional gate 64 which connects the direct output 14 of the
accumulator register 11 to a separated output 65 of the computer 1
which also includes seriesly connected additional registers 661,
..., 66p. An output of the register 66p is connected via a gate
67 to the same separated output 65 of the computer 1 and via a
gate 68, to the first input 5 of the adder 6.
An input of the register 661 is connected to a separated
input 69 of the computer 1.
According to the invention, in the embodiment of the
't computer 1 under review, all the registers 21, ... , 2i, 2j, 2k~
..., 2n, as well as 11 and 661, ..., 66p, are four-digit registers
the adder 6 and all the gates 4, 7, 8, 12, 13, 15, lB, 20, 22,
24, 25, 26, 50, 54, 59, 60, 61, 62, 64, 67 and 68 are single-
channel.
According to an alternative embodiment of the computer
1, all the registers 21, ..., 2n, 11 and 661, ..~., 66p, the
adder 6 and all the gates 4, 12, 13, 20, 22, 64, 67, 24, 25, 26,
10~7~j~0
60, 68, 59, 15, 18, 54, 61, 50, 62 and 8 may be multichannel.
The control inputs of each multichannel gate are combined and
connected to the outputs of the microinstruction matrix.
According to the invention, the computer 1 includes a
synchroprogram commutation unit 70 whose inputs 71 are directly
connected to the outputs of the control signal forming unit 36
of the controlled synchronizer. Inputs 72 of the unit 70 are
connected to respective outputs of the device 29 for commutation
of output signals of the program matrix 27. Outputs 73 of the
unit 70 are connected to inputs of the output decoder 32 of the
synchroprogram matrix 30.
- According to the invention, the computer 1 has an add-
ress register 74 whose group of inputs 75 is connected to respec-
tive outputs of the address counter control unit 42; its other
group of inputs is connected to the outputs 40 of the device 29
for commutation of output signals of the program matrix 27; a
~roup of inputs 76 is connected to control inputs 77 of the com-
puter l; an input 78 is connected to an output of the register
2k. Outputs 79 of the address register 74 are connected to res-
pective inputs of the address counter 38.
According to the invention, the computer 1 comprises an
output matrix 80 whose outputs are connected to control outputs
81 of the computer 1.
The computer 1 still further comprises a code conversion
unit 82 whose inputs 83 are connected to outputs of the register
2j. ~n input 84 of the unit 82 is connected to an output 85 of
the counter 34 of the controlled synchronizer. Outputs of the
unit 82 are connected to inputs of a device 86 for commutation of
input signals, whose outputs are connected to inputs of the out-
put matrix 80.
According to the invention, the additional control in-
puts of the gates 7, 8, 24, 25 and 26 are connected to additional
- 18 -
outputs 87 of the device 29 for commutation of output signals of
the program matrix 27, which inputs 87 are also connected to an
input 88 of the code conversion unit 82.
According to the invention, the computer 1 includes a
flip-flop 89 whose input is connected to a multiple-input gate
90 whose group of inputs is connected to the inputs 76 of the
address register 74; an input 91 of said gate 90 is connected to
the output of the address counter control unit 42.
An output 92 of the flip-flop 89 is connected to an
input 93 of the address counter control unit 42 and via a gate
94, to the third input 51 of the adder 6.
Fig. 2 shows an embodiment of a computing system which
comprises, according to the invention, three sequential computers,
1, 1' and 1 n ~ each constructed as shown in Fig. 1.
The three computers 1, 1' and 1" are connected so that
the separated input 69 of the first computer 1 is connected to
the separated output 65 of the second computer 1' whose separated
input 69 is connected to the separated output 65 of the third
computer 1" whose separated input 69 is connected to the output
65 of the first co~puter 1, whereas the synchronization inputs 46
of the second and third computers 1l and 1" are connected to the
synchronization output 48 of the first computer 1.
~ccording to the invention, this computing system
includes additional external shift registers 951~ ~ 95q, an
input of the shift register 951 being connected to the separated
output 65 of the computer 1; an output buffer device 96 of the
external shift register 95q is connected to the separated input
69 of the last computer 1".
The synchronization inputs 46 of the second and third
computers 1' and 1" are connected to the external synchronization
output 48 of the first computer 1.
The address counter 38 (Fig. 3) comprises a system of
19
~0f~76Z~
flip-flops 981, ..., 98S seriesly connected via gates 971~ '
97s-1 An output of the flip-flop 98S 1 is connected via an
inverter 99 and a gate 100 to an input of the first flip-flop 981.
Control inputs of the gates 971~ ' 97s 1 and 100
are combined and connected to one of the inputs of the counter
38, which input is connected to the output 41 (Fig. 1) of the
counter control unit 42. The flip-flops 981, ..., 98S (Fig. 3)
are connected via gates 100' and 97'1' ' 97's 1 to the respec-
tive inputs 39 of said counter 38. Control inputs of the gates
100' and 97'1~ .... 97's 1 are combined and connected to another
input of the counter 38, which input is connected to the output
41 (Fig. 1) of the counter control unit 42.
The flip-flops 981, ~ 98S (Fig. 3) are connected
yia gates 100" and 97"1~ ' 97"s 1 to respective inputs of the
counter 38, which inputs are connected to the outputs 79 (Fig.
1) of the address register 74.
Control inputs of the gates 100" and 97"1~ ~ 97"s 1
LFig. 3) are combined and connected to the third input of the
counter 38, which input is connected to the output 41 (Fig. 1)
of the counter control unit 42.
According to the invention, the computing system
includes the output buffer device 96 (Fig. 2).
The output buffer device 96 ~Fig. 4) comprises identical
followers 101 and 102. Consider now the follower 101. It com-
prises a first transistor 103 whose drain is connected to a first
clock pulse bus 104, its gate being connected to an input 105 of
the follower 101, whereas its source is connected to an output
106 of the follower 101 and the drain of a second transistor 107.
The gate of the second transistor 107 is connected to a second
clock pulse bus 108, while its source is connected to a common
bus 109. Between the gate and source of the first transistor
103, there is placed a positive feedback capacitor 110. The
- 20 -
10~i7~;20
input 105 of the first follower 101 is connected to an output
of an inverter 111 whose input is connected to an output 112 of
the buffer device 96 and the drain of a third transistor 113.
The gate of the third transistor 113 is connected to the second
clock pulse bus 108. The output 106 of the first follower 101 is
connected to the gate of a fourth transistor 114 whose drain is
connected to a first supply bus 115, whereas its source is com-
bined into a common point 116 with the drain of a fifth tran-
sistor 117. The source of the fifth transistor 117 is connected
to the common bus 109, whereas its gate is connected to an out-
put 118 of the second follower 102. To the common point 116,
there is also connected the gate of a sixth transistor 119 whose
source is connected to the common bus 109, while its drain is
combined into a common point 120 with the source of a seventh ::
transistor 121. The drain of the seventh transistor 121 is con-
nected to the first supply bus 115j its gate being combined with
: the source of the third transistor 113 and an input 122 of the
second follower 102. To the common point 120, there is connected
the gate of an eighth transistor 123 whose drain is connected to
a second supply bus 124, whereas its source is combined with an
output 125 of the buffer device 96 and the drain of a ninth tran-
sistor 126 whose source is connected to the common bus 109, while
its gate is connected to khe common point 116.
According to the invention, the computer 1 (Fig. 1)
includes the devices 28, 31, 37 and 86 for commutation of inputs
signals of the matrices 27, 30, 10 and 80.
The commutation device, for example, the device 28
(Fig. 5) for commutation of input signals of the matrix 27, com-
prises a decoder 127 which ensures conduction between a common
: 30 input 128 and one of outputs 129 of the decoder 127, depending
upon which code has been applied to address inputs 130 of the
decoder 127. The commutation device 28 also comprises first
- 21 -
,
106~
exciting circuits 131 and second exciting circuits 132 of the
decoder 127, a discharge device 133 and an inverter 134.
Each of the first exciting circuits 131 of the decoder
127 comprises a first transistor 135 whose drain i5 connected to
an address signal bus 136, its gate being connected to a second
clock pulse bus 137, whereas its source is connected to the
gate of a second transistor 138. The source of the second tran-
sistor 138 is connected to a third clock pulse bus 139, its drain
being connected to an output 140 of the exciting circuit 131 of
the decoder 127. Between the drain and gate of the second tran-
sistor 138 there is placed a positive feedback capacitor 141.
Each of the outputs 140 of the first exciting circuits 131 of
the decoder 127 is connected to the respective address inputs 130
of the decoder 127. Each of the second exciting circuits 132 of
the decoder 127 comprises a third transistor 142 whose source is
connected to the second clock pulse bus 137, its gate being con-
nected to the address signal bus 136, whereas its drain is con-
nected to the source of a fourth transistor 143. The drain and
gate of the fourth transistor 14~ are connected to the second
2Q clock pulse bus 137. The drain of the third transistor 142 is
: also connected to the gate of a fifth transistor 144 whose drain
is connected to an output 145 of the exciting circuit 132, whereas
its source is connected to the third clock pulse bus 139. Between
the source and gate of the fifth transistor 144, there is placed
a switchable capacitor 146 whose control electrode is connected
to the gate of the fifth transistor 144, other electrode being
connected to the source of the same transistor. Each of the out-
puts 145 of the second exciting circuits 132 of the decoder 127
is connected to the respective inputs 130 of the decoder 127.
3Q An output of the inverter 134 is connected to the common
input 128 of the decoder 127; an input of said inverter 134 is
connected to a first clock pulse bus 147.
- 22 -
10ti7~Z0
The discharge device 133 comprises transistors 148
whose drains are connected to inputs 149 of the discharge device
133, their gates being connected to the first clock pulse bus
147, whereas their sources are connected to a common bus 150.
The inputs 149 ofthe discharge device 133 are connected to the
outputs 129 of the decoder 127 and the inputs of the matrix 27.
The device 29 for commutation of output signals of the
matrix 27 comprises a decoder 151 which ensures conduction bet-
ween inputs 152 and outputs 153 of the decoder 151, depending
upon which code has been applied to address inputs 154 of the
decoder 151, as well as the first and second exciting circuits
131 and 132 of the decoder 151 and a charger 155.
Each of the outputs 140 of the first exciting circuits
131 of the decoder 151 is connected to the respective address
inputs 154 of the coder 151. Each of the outputs 145 of the
second exciting circuits 132 of the decoder 151 is connected to
the respective address inputs 154 of the decoder 151.
The charger 155 comprises transistors 156 whose sources
are connected to outputs 157 of the charger 155, their gates
being connected to the first clock pulse bus 147, whi,e their
drains are connected to a supply bus 158. The outputs 157 of
the charger 155 are connected to the inputs 152 of the decoder
151 and the outputs of the matrix 27. The outputs 153 of the
decoder 151 are connected to those of the device 29 for commuta-
tion of output signals of the matrix 27.
Figs. 6a and 6b show voltage time plots of clock pulses,
which illustrate operation of the output buffer device 96.
Fig. 6a shows a first clock pulse 159 and a second clock
pulse lbO.
Fig. 6b shows a third clock pulse 161 and a fourth clock
pulse 162.
Fig. 7a, 7b and 7c show voltage time plDts of clock
- 23 -
10~7~ZO
pulses, which illustrate operation of the devices for commutation
of input and output signals of the matrices.
Fig. 7a shows clock pulses 163, 164 and 165.
Fig. 7b shows clock pulses 166, 167 and 168.
Fig. 7c shows clock pulses 169, 170 and 171.
Consider now operation of the sequential computing
system comprising at least one sequential computer 1 (Fig. 1).
First of all, it must be noted that the computer 1 comprises
"n" v-digit registers 21, ..., 2n, which are placed in series,
the accumulator register 11. having v digits, the adder 6, and
the counters 33, 34 and 35 of the controlled synchronizer, whose
division factors are v, ~ and ~.
Clock generator signals are simultaneously applied to
the input of the counter 33 of the controlled synchronizer and the
s control inputs of the registers 21, ...... , 2n (the clock generator
and control inputs of the registers 21, .. ...., 2n are not shown in
Fig. 1).
From the output of the counter 33, the signals are
applied to the counter 34 from whose output they are applied to
the inputs of the counter 35.
The common division factor "k" of the counters 33, 34
and 35 of the controlled synchronizer is: k = v, ~, ~; the
common number M of the digits of the seriesly connected registers
21/ -., 2n is: M = v . n.
In the computing system under review, the period of
circulation of information in the registers 21, ..., 2n, as
control signals are applied from the outputs 101, ..., 10t f
the matrix 10 to the gates 24 and 7, is equal to the repetition
period of output signals of the counter 35 of the controlled
synchronizer, i.e. k = M. This makes it possible to unambiguously
establish the information layout in the registers 21, ..., 2n at
any moment of time in order to convert said informationO
- 24 -
1067620
Information in the registers 21, ..., 2n is converted
with the aid of control signals applied from the outputs 101,
~ 10t of the matrix 10 at moments of time when information to
be converted is passing through the gates 4, 7, 8, 24, 25 and 60.
The combination of the control signals applied from the
outputs 101, ..., 10t of the microinstruction matrix 10 at a
specified moment of time is a microinstruction of the computer
1. Each microinstruction lasts for a period of time required to
process v bits of information. The microinstruction matrix 10
has a set of microinstructions required to solve a certain range
of problems, for example, mathematical problems.
The necessary microinstruction is selected with the
aid of the device 37 for commutation of input signals of the
microinstruction matrix 10.
For this purpose, codes of the address of the required
microinstruction are applied from the output decoder 32 of the
synchroprogram matrix 30 to the inputs of the device 37 for
commutation of input signals of the microinstruction matrix 10.
A synchroprogram is a sequence of a microinstruction
carried out within a time interval equal to one operating cycle
- of the computer 1. The operating cycle of the computer 1 is
equal to the period of circulation of information in the registers
''''" 21~ , 2n-
- The moments for selecting a required microinstruction
-` are set by the control signal forming unit 36 of the controlled
~; synchronizer. Thus, a synchroprogram determines both the sequence
; of microinstructions carried out during one operating cycle of
, the computer 1 and the moments for selecting these microinstruc-
tions within one operating cycle of the computer 1.
The synchroprogram matrix 30 has a set of synchropro-
grams required to solve a given range of problems.
A necessary synchroprogram is selected with the aid of
- 25 -
., .
- ~, --. .. . ~ .
10~i'7~V
the device 29 for commutation of output signals of the pxogram
matrix 27 and the device 31 for commutation of input signals of
the synchroprogram matrix 30. For this purpose, a respective
code of the address of a synchroprogram is applied from the
device 29 for commutation of input signals of the program matrix
27 to the inputs of the device 31 for commutation of input sig-
nals of the synchroprogram matrix 30. The address code of a
synchroprogram is set for a period of time equal to one operating
cycle of the computer 1.
A program of solving a specified range of problems is
a sequence of instructions of the computer 1 which ensure con-
trol over the problem solving process. A set of such programs
is contained in the program matrix 27. An instruction contains
a synchroprogram address code, a new instruction address code,
a code of a condition of a jump to a new instruction, a synchro-
program modification code, and a microinstruction modification
code.
An instruction required for calculation is selected
with the aid of the device 28 for commutation of input signals of
the program matrix 27.
For this purpose, a respective instruction address code
is applied from the output of the address counter 38 to the inputs
of the device for commutation of input signals of the program
matrix 27. The instruction address code is set in the address
counter 38 for a period of time required to carry out the instruc-
; tion~ which period is equal to one operating cycle of the com-
puter 1. A change in the state of the code of the address counter
38 is effected by signals arriving from the output 41 of the
address counter control unit 42, which signals correspond to a
code of the condition of a jump to a new instruction.
An address of new instructions is entered into the
counter 38 when a control signal is applied from the outputs 41
of the unit 42 to the control inputs of the gates 100' and 97'1
- 26 -
10~7~i~0
' 97's 1 (Fig. 3) and/or the inputs of the gates 100" and 97"1
' 97"s 1 (Fig. 3), when signals from the outputs 40 of the
device 29 are applied to the inputs 39 of the counter 38, and/or
when a signal from the outputs 79 of the address register 74 is
applied to the respective inputs of the counter 38.
The address of the next instruction is entered into
the counter 38 when a signal from the respective output 41 of
- the unit 42 is applied to the control inputs of the gates 100 and
971~ ' 97s 1 As this takes place, the contents of the first
digit of the counter 38 is transferred to the second digit, the
contents of the second digit is transferred to the third digit,
etc. The contents of the s-l digit is transferred through the
inverter 99 and gate 100 to the first digit, so that the address
code of the next instruction is fixed in the counter 38.
The code state of the counter 38 is changed at a moment
of time set by the counter 35 of the controlled synchronizer.
For this purpose, a signal from the output of the coun-
ter 35 of the controlled synchronizer is applied to the input 44
of the address counter control unit 42.
The signal, which corresponds to the code of a condition
` of a jump to a new instruction, is applied to the input 43 of the
address counter control unit 42 from the output of the device 29
for commutation of output signals of the program matrix 27. This
ensures at least the following types of jumps to a new instruction
and transmission of an instruction address code:
an unconditional jump to carrying out a new instruction
whose address code is indicated in the given instruction;
a jump to carrying out a new instruction whose address
code is indicated in the given instruction, as a "1" signal is
applied from the output 21 of the Link register 19 to the input
` 45 o~ the counter control unit 42, or a jump to carrying out the
next instruction as a 10ll signal is applied from the output 21 of
,
1067~20
the Link register l9;
a jump to c~rrying out a new instruction whose address
code is indicated in the given instruction, as a "O" signal is
applied from the output 21 of the Link register l9 to the input
45 of the counter control unit 42, or a jump to carrying out the
next instruction, as a "l" signal arrives from the output 21 of
the Link register 19;
a jump to carrying out a new instruction whose address
code is formed by way of disjunction (conjunction) of the code of
the address counter 74 and of the address code indicated in the
given instruction; signals, corresponding to the address code
incidated in the given instruction, are applied to the inputs 39
of the address counter 38 from the outputs 40 of the device 29;
transmission of the instruction address code indicated
in the given instruction from the output 40 of the device 29 for
~ commutation of output signals of the matrix 27 to the input of
: the address register 74;
transmission of an instruction address code from the
output of the register 2k to the input 78 of the address register
: 20 74.
There may be entered into the address register 74 the
address code of a new instruction, which code is indicated in the
instruction set in the matrix 27, or the code of the register 2k
read therefrom at a specified moment of time, or an address code
applied from peripheral devices to the control inputs 77 of the
computer 1. The branching of the calculation program is effected
~ by means of disjunction or conjunction of the code of the address
register 74 and the new address code specified in the given
~ instruction.
A signal, which corresponds to the synchroprogram
modification Gode contained in the given instruction, is applied
`::
: from the output of the device 29 for commutation of output signals
- 28 -
10f~7f~V
of the program matrix 27 to the inputs 72 of the synchroprogram
commutation unit 70, which provides for different modifications
of synchroprograms for example, successively performing all the
microinstructions of a synchroprogram, partially performing micro-
instructions of a synchroprograms, and altering the sequence in
which microinstructions are carried out within the limits of one
synchroprogram. This makes it possible to produce new synchro-
programs out of the existing synchroprograms with only insignifi-
cant expendituresin connection with the necessary equipment.
A signal, corresponding to the microinstruction modifi-
cation code contained in the given instruction, is applied from
the output 87 of the device 29 for commutation of output signals
~: of the program matrix 27 to the additional control inputs of the- gates 8, 7, 26, 27 and 25. This makes it possible to check the
contents of the registers 21, ..., 2n without erasing information
in said registers 21, ..., 2n.
The proposed embodiment of a sequential computing
system comprising at least one computer 1 operates as follows.
Suppose the computer 1 is operating in the waiting
mode. This mode is characterized by that the information in the
registers 21, ..., 2n, the accumulator register 11 and the Link
i register 19 remains intact and by that it is possible to carry
out a selected program by an instruction from a peripheral
device. The program of each problem to be solved by the computer
1 ends up by bringing the computer l~into the waiting mode.
Corresponding to the waiting mode is one of the multi-
tude of codes of the address counter 38. This mode is ensured
by a specified transfer condition code contained in the instruc-
- tion which corresponds to the code of the address counter 38.
` 30 In this case, the counter control unit 42 applies to
the address counter 38 a signal to receive the new address code
incidated in the program that has been selected, as well as
.'
~ - 29 -
;, ' ' , .
~Ot~7~ZO
a signal to receive the initial a~dress code from the peripheral
device via the register 74.
The address code of a new instruction, which is pro-
duced as a result of receiving the new and/or initial address, is
the address code of the instruction which is the first to be
executed in the program of the problem being solved set by the
peripheral device.
In the waiting mode, a new address code of an instruc-
tion must correspond to the code of the address counter 38, which
corresponds to the waiting mode; this means that the same instruc-
tion of the program matrix 27 is selected prior to the arrival of
the initial address from the peripheral device.
The new address code of the instruction is applied to
the input 39 of the address counter 38 from the output of the
device 29 for commutation of output signals of the program matrix
27; this code is entered into the address counter 38, which is
::
done once during the operating cycle of the computer 1, by a
signal from the output of the counter 35 of the controlled
synchronizer.
{20 In the waiting mode, the same microinstruction is carried
out during each working step of the computer. The duration of
the working step of the computer 1 is l/n of the duration of the
operating cycle of said computer 1.
Control signals are applied from the respective outputs
101, ..., 10t Of the microinstruction matrix 10 to the gates 24,
7, 13 and 20, which initiates transmission of information in the
registers 21, ..., 2n, the accumulator register 11 and the Link
register 19. In order to provide for circulation of information
in all the above-mentioned registers in the waiting mode, the
synchroprogram must contain "n" identical microinstructions.
Fig. 8 is a table of the location and stepwise change of infor-
mation in the seriesly connected registers 21, ..., 236 in the
' .
10676Z0
waiting mode during one operating cycle of the computer 1 for
the case when information circulates in the registers 21, ....
236 of three twelve-digit words ~ , ~ , ~ , where each word
digit is designated as ~ , ~ , ~ (1 = 1, 2, ..., 12).
Column T (time step) lists the serial numbers of time steps;
column MK (microinstruction) lists microinstruction codes (00);
the columns related to the registers 21, ..., 236 list designa-
tions of word digits circulating in said registers; each line
of the table lists the contents of the registers 21, ..., 236
recorded as a result of carrying out the microinstruction indi-
cated in the preceding line.
; Fig. 8 shows that after 36 time steps which make up one
complete operating cycle of the computer 1 and after crrying out
the respective microinstructions, the information contained in
the registers 21, ..., 236 is fully restored.
Consider now operation of the computer 1 in the infor-
mation processing conditions. Any program carried out by the
computer 1 begins with applying an initial address code of the
selected program from the peripheral device to the inputs 77
-; 20 (Fig. 1) of the computer 1 and then, to the inputs 76 of the
address register 74.
To the input 75 of the address register 74, there is
applied a signal to receive the initial address code, which code
is recorded in the register 74.
In the waiting mode, which precedes the information
~ processing mode, there is initiated a signal to receive the
; initial address code, so at a moment of time which coincides
~i with the start of the operating cycle of the computer 1, the
initial address code of the selected program is derived from
the address register 74 and recorded in the address counter 38.
According to the initial address code, the program matrix 27
-~ selects the first instruction of the program. This instruction
,
- 31 -
1(~7~;~0
contains a code of a condition of a jump to the next instruction,
a new address code of the instruction to be carried out during
the following operating cycle of the computer 1, and the address
code of a synchroprogram which determines, with due regard for
the microinstruction matrix 10, the sequence of operations to be
carried out, which involve the contents of the registers 21,
~ 2n, during the operating cycle of the computer 1. This
sequence of operations is determined by a set of microinstructions
which are selected in accordance with the addresses contained in
the synchroprogram. During each time step of the computer 1,
there is selected one microinstruction of the entire set of
microinstructions of the computer 1, which set is stored in the
microinstruction matrix 10.
Let it be assumed that while processing three twelve-
digit words ~ , it is necessary to replace, by a given
: instruction of the program, the word ~ by the word ~ in the
registerS 21~ 236 ( g
The synchroprogram, whose address code is indicated in
the given instruction, contains a sequence of microinstructions
required to carry out the operation of replacing the word ~
by the word ~ . -
For the information processing mode, the sequence of
microinstructions is composed, unlike in the waiting mode, of
two microinstructions (00), (01). The microinstruction (01) is
carried out during specified time steps of the operating cycle
: of the computer 1.
.:.
During the remaining time steps of the operating cycle,
there is c'arried out the microinstruction aimed at preserving
the information in the registers 21, ..., 236.
In order to replace the word ~ by the word ~ , the
microinstruction (01) must ensure application of control signals
to the gates 24, 4 and 8 (Fig. 1) at moments of time when to the
- 32 -
10676Z0
inputs of these gates there are applied signals corresponding to
the digits of the word ~ ; the microinstruction (01) must also
ensure the absence of control signals at the gates 4, 7, 15, 18,
25, 26, 50, 54, 60, 61, 68 and 94 in order to preser~e the infor-
mation in the registers 21, ..., 2n.
The signals corresponding to the digits of the word
are applied from the output 3 of the register 2n via the gate
24 to the input of the register 2l, and via the gate 4, the
adder 6 and gate 8, to the input of the register 2i. In the
present case, in the registers 2l and 2i there are entered the
digits of the word ~ . Thus, an operation of replacement ta~es
place in the register 2i, and the digits of the word ~ replace
those of the word ~
For greater brevity, the subsequent description of the
microinstructions will only incidate the gates to whose control
inputs there is applied a control signal.
. ~ ,
Fig. 9 shows the location and stepwise alteration of
information in the seriesly connected registers 2l, ..., 236
when carrying out the operation of substituting the word ~ for
the word ~ . In order to carry out this operation, during
, steps 2, 5, 8, ll, 14, 17, 20, 23, 25, 29, 32, 35, in the course
;; of one operating cycle of the computer l, there are carried out
the microinstructions (01) of replacing the digit of the word
-. by the respective digit of the word ~ ; during the other time
steps, there are carried out the microinstructions (00) of cir-
culation of information in the registers 2l, ...! 236.
As is seen from Fig. 9, after the second time step
(see the line of step 3), in the register 22 there is the first
digit ~ of the word ~ instead of the first digit ~ of
` 30 the word ~ ; after step 36 (see the line of step 37), in all
the digits of the word ~ there are the respective digits of
the word ~ .
- 33 -
10~'7~;~0
By a signal of the beginning of the next operating
cycle of the computer 1, in the address counter 38 there is
entered the code of a new address indicated in the preceding
instruction.
Let it be assumed that the conditions of the transfer
to the next instruction of the program is the presence of a sig-
nal "1" at the output 21 of the Link register 19.
The next instruction of the program contains the add-
ress code of a synchroprogram, according to which the micro-
; 10 instruction matrix 10 performs the following operations on thecontents of the registers 21, ..., 236;
O is entered in the first digit ~ of the word ~ ;
O is entered in the ninth digit ~ of the word ~ ;
~:O is entered in the ninth digit ~ of the word ~ ;
the word ~ is shifted one digit to the right;
the digits ~ through ~ of the word ~ are shifted
one digit to the left;
the tenth digit ~ of the word ~ is added to the
:eleventh digit ~ of the word ~ ; the result is assigned to
the eleventh digit ~ of the word ~ ;
:the twelfth digit ~ of the word ~ is added to the
twelfth digit ~ of the word ~ ; the carry signal is recorded
in the Link register 19 while performing the adding operation.
The microinstruction matrix 10 applies control signals
to the respective gates, whereby the above-mentioned operations
,... .
are carried out.
Suppose that by the start of the first time step (the
beginning of the operating cycle of the computer 1), information
; in the registers 21, ... , 236 is laid out as shown in the line of
step 1 of Fig. 8.
Zero is entered in the first digit of the word ~ and
the ninth digits of the words ~ and ~ by applying a control
''~
:~ - 34 -
,
~Oti'7f~'~0
signalto the input of the gate 7 (Fig. 1) during time steps 1,
25, 27 (Fig. 8).
The control signals are initiated when a corresponding
microinstruction of the matrix 10 (Fig. 1) is performed. The
absence within the above-mentioned time steps of a control signal
across the input of the gate 24 disconnects the registers 236
and 21, so zero is entered in the first digit of the word
and the ninth digits of the words G and ~ .
The word ~ is shifted one digit to the right by
applying control signals to the inputs of the gates 26 and 7
(Fig. 1) during time steps 1, 4r 7, 10, 13~ 16~ 19~ 221 251 28
31, 34 (Fig. 8).
; Control signals are also initiated as a corresponding
microinstruction of the matrix 10 (Fig. 1) is performed.
As this takes place, the information from the output
of the register 2n is entered via the gate 26 into the register
21; as a result, the information is shifted one digit to the
right.
A shift by one digit to the left of the digits two
through eight of the word ~ is effected with the aid of the
adder 6 by a number of different microinstructions. In the
fourth time step, the microinstruction matrix 10 applies control
signals to the inputs of the gates 4, 12 and 7, whereby the
second digit of the word ~ is transferred from the adder 6 to
the accumulator register 11. In the fifth and sixth time steps,
the microinstruction matrix 10 applies control signals to the
inputs of the gates 7, 13 and 24~ which ensures circulation of
.; . .
the second digit of the word ~ in the accumulator register 11.
~` In the seventh time stop, the microinstruction matrix 10 applies
. . ~
control signals to the inputs of the gates 4~ 7~ 12 and 25,
whereby the third digit of the word ~ is replaced by the second t
` and the third digit of the word ~ is entered in the accumulator
:
~ _ 35 _ i
10~7~
register 11. The remaining digits of the word ~ are shifted
to the left in a similar manner.
The adding of the tenth digit of the word ~ to the
eleventh digit of the word ~ , the entering of the result in
the eleventh digit of the word ~ , and the recording of the
carry signal on the Link register 19 are performed by several
microinstructions.
In the time step 23, the microinstruction matrix 10
applies control signals to the inputs of the gates 4, 7, 12 and
24 to store the tenth digit of the word ~ in the accumulator
register 11.
In the time steps 29, 30 and 31, the microinstruction
matrix 10 applies control signals to the inputs of the gates 7,
13 and 24 to store the tenth digit of the word ~ in the accumu-
lator register 11.
In the step 32, the microinstruction matrix 10 applies
control signals to the inputs of the gates 4, 7, 12, 15, 22 and
24 to add the tenth digit of the word ~ to the eleventh dlgit
of the word ~ and enter the result in the accumulator register
11; simultaneously, 1 is entered in the Link register 19 if the
addition results in a carry; zero is entered in the Link register
; 19 if there is no carry.
, In the step 33, the microinstruction matrix 10 applies
control signals to the inputs of the gates 7, 13 and 20, which
provides for circulation of information in the accumulator regi-
ster 11 and Link register 19.
In the step 34, the microinstruction matrix 10 applies
- control signals to the inputs of the gates 8, 15 and 24, whereby
,~
the result of the addition is transferred from the accumulator
register 11 to the eleventh digit of the word ~ , etc.
The result of the processing is applied from the output
matrix 80 to the control inputs 81 of the computer 1 and proceeds
-- 36 --
io~
to the peripheral device. As this takes place, the information
from the outputs of the register 2j is applied to the inputs 83
of the unit 82. As control signals are applied to the inputs 88
and 84 of said unit 82 from the outputs of the device 29 and
counter 34, respectively, this information is converted into a
parallel code and is applied via the commutation device 86 to
the output matrix 80. The reprogrammable output matrix 80 makes
it possible to modify the output code, for example, for different
types of indication, as well as to send control signals to the
peripheral devices (not shown). -
The input of external information to the computer 1 is
effected by a microinstruction, whereby there is initiated a :
control signal applied to the gate 68, and with the aid of the
., flip-flop 89 which initiates a control signal, whereby the adder
.~ 6 calculates the pulses arriving from the output 49 of the
: counter 33 of ~he controlled synchronizer.
The duration of the control signal from the flip-flop
: 89 is determined by the input digit; said flip-flop 89 is set
and reset by output signals of the multiple-input gate 90; to
: 20 inputs of said flip-flop 89 there is applied the code of the
input digit, whereas applied to the input 91 of the gate 90 is
an enabling signals arriving from the output of the address
:.
: counter control unit 42. In many cases, especially when process-
ing digitial information represented in the computer 1 as the
;: mantissa of a number and its exponent, the same microinstructions
are used for a group of word digits, for example, to shift the
whole mantissa of a number by one digit to add the whole mantissa
~: of a number to that of another number, etc. Such use of groups
:: of microinstructions that are repreated within one cycle makes
it possible to substantially reduce the amount of equipment (the
- capacity of the synchroprogram matrix), which is due to the fact
that the address of only one microinstruction is indicated in the
- 37 -
10f~71~;~0
synchroprogram for this group of microinstructions. During
several time steps, the control signal forming unit 36 of the
controlled synchronizer produces the addresses of the same micro-
instructions, which provides for double-periodic synchronization
of the computer 1.
As is seen from the present disclosure, a program for
solving a problem comprises a sequence of synchroprogram whose
addresses are stored in the program matrix 27. For a specific
computer 1, synchroprograms are selected while evolving the
computer's software, taking into account the versatility factor,
i.e. the possibility to multiply use synchroprograms to solve
different problems.
A synchroprogram of the computer 1 accounts for the
time sequence of microinstruction addresses; hence, the formation
of different sequences of microinstructions is possible through
the use of the same microinstructions. Thus, with a limited cap-
acity of the microinstruction matrix 10, it is possible to pro-
duce a great number of different sequences of microinstructions
~synchroprograms) required for problem solving.
In addition, the number of different synchroprograms
of the computer 1 may be increased by introducing the synchro-
program commutation unit 70 which makes it possible to produce
new synchroprograms out of the elements of the existing synchro-
programs by providing different modifications, as has been shown
above, without increasing the capacity of the matrix 30.
Thus, the computer 1 under review has a two-level
programming system.
The first programming level with branching of programs
and a jump to subroutines is effected with the aid of the programs
3~ matrix 27, the devices 28 and 29 for commutation of input and
output signals, respectively, the counter 38, and the address
counter control unit 42.
- 38 -
.
. .
101~7~V
~1
The second programming level is effected with the aid
of the synchroprogram matrix 30 and microinstruction matrix 10.
Control signals arriving from the matrix 10 effect conversion
of information in the registers 21, ..., 2n.
The two programming levels make it possible to combine
in one instruction a number of indications as regards processing,
checking, transmitting operands and results of processing, as well
as the address of the next instruction, which reduces equipment
costs per capacity unit of the program matrix 27.
The use in the computer 1 of the two-level programming
system in combination with the proposed connections between the
units of said computer 1, for example, the connections between
the registers 21, ..., 2n, between the registers 21, ..., 2
and the adder, between the adder and the accumulator register 11,
etc. provides for a high degree of compactness in combination
with an extremely flexible system of instructions. This makes
it possible to use computers intended for different purposes both
~^ to control peripheral equipment (as in the case of a minicomputer
.
and perform mathematical calculations (as in the case of a calcu-
lator).
"
The computer 1 of the proposed computing system con-
sists in the main of the matrices 10, 30, 27, and 80, the devices
` 37, 32, 31, 29 and 28, and the registers 21, ... , 2n and 661,
` ... , 66p. It can be inferred that the matrices 10, 30, 27 and 80,
the devices 37, 32, 31, 29 and 28 for commutation of input and
- output signals, having a regular structure of connections, as well
as seriesly connected registers 21, ..., 2n and 661, ..., 66 ,
comprising a large num~er of uniform elements (register digits)
connected in series, all meet the requirements involved in the
3Q task of producing a computer 1 in the form of an LSI circuit.
In order to perform calculations with decimal numbers,
the number of digits in the accumulator register 11 and each
- 39 -
.
"'' ' ' , , .
10~7~Z0
of the registers 21, ..., 2n is selected to be equal to 4(v = 4);
for thepurposes of correction, while adding binary-decimal numbers
there are introduced constants 0110 and 1010, the constant 1010
being applied to the input 5 of the adder 6 with the aid of the
AND circuit 57if there is a signal across the inverting output
of the Link register 19.
The constants 0110 and 1010 are formed by the code form-
ing circuits 53 and 55 to whose inputs there are applied signals
from the outputs of the counter 33 of the controlled synchronizer.
Besides, in order to raise the operating speed of the
computer 1, several digits, for example, four digits, are pro-
cessed simultaneously due to the fact that the registers 21, ....
2n, all the gates, the adder 6 and the accumulator register 11
are multichannel, each channel comprising the registers 21, ....
2n, the gates, the adder 6 and the accumulator register 11, all
the gates being controlled simultaneously by signals applied
from the output of the microinstruction matrix 10 via the gates;
a carry signal is applied from the output of the adder 6 of the
first channel to the input of the adder 6 of the next channel,
etc., whereas a carry signal from the output of the adder 6 of
the last channel is applied via the controlled gate to the input
of the Link register 19.
The embodiment of the computer 1, wherein the registers
21, ..., 2n, the accumulator register 11, the adder 6 and all the
gates are multichannel, is not shown in the drawings.
It is clear from the foregoing that in the computer 1
under review, the transfer from the sequential principle of
information processing to the parallel-sequential principle is
only effected through an increase in the number of channels,
without any changes in the other units.
In case of an increase in the range of problems to be
solved, the computers 1 are combined into a computing system
- 40 -
... . . .
la~ 20
comprising several computers which are synchronized by signals
applied from the output 48 of one of the computers 1 to the inputs
46 of the rest of the computers 1; exchange of information is
carried out through the registers 661, ..., 66p. The computers
- 1 incorporated in the computing system can operate both simul-
taneously and one after another.
Consider now a computing system composed of three com-
puters 1, 1' and 1". Apart from said computers 1, 1' and 1",
the system includes the external registers 951~ ~ 95q and the
buffer device 96.
The connection of the computers 1, 1' and 1", the
registers 951~ ~ 95q and the buffer device 96 is shown in
Fig. 2.
Each of the computers 1, 1' and 1" operates as the one
described above.
The registers 661, ..., 66p of all the computers 1, 1'
and 1", the gate 67, the external registers 951' ~ 95q and the
buffer device 96 are all placed in series and form a single
:
closed circuit.
A jump to calculations according to a program recorded
in the computer 1' is performed with the aid of said closed cir-
cuit.
Let it be assumed that the first computer 1 has finished
calculations according to its program, and that it is necessary
to continue calculations according to a program of the third com-
puter 1". For this purpose, the first computer 1 forms and
- enters into the closed circuit, via the gate 64 of the first
computer 1, the number code of the computer which is to continue
calculations (in the present case, this is the third computer 1").
Apart from the code number of the computer 1", the first computer
1 enters into the closed circuit the initial address of the pro-
gram according to which the third computer 1" is to continue cal-
- 41 -
1~;76ZO
culations; if necessary, the computer 1 enters the intermediary
results of its own calculations.
The information entered into said closed circuit circu-
lates in this circuit, i.e. it successively passes through all
the computers 1, 1' and 1".
In order to enable any computer of the system to con-
tinue calculations, it is necessary that all the computers 1, 1'
and 1" of the computing system should be capable of interruption.
In the course of an interruption, there is carried out the check-
ing of the contents of the closed circuit and established thenumber code of the computer 1, which coincides with the number
code previously assigned to said computer 1. In case of simul-
taneous operation of all the computers 1, 1' and 1" of the com-
puting system, the interruption program is inserted at specified
points in the calculation program; if the computers 1, 1' and
1" operate sequentially, all the calculation programs of each of
the computers 1, 1' and 1" are to end with an interruption program
which is matched, if necessary, with the waiting mode.
If in the course of an interruption, the computer 1
finds its number code in the closed circuit, said computer 1
transfers the initial address code from the closed circuit to its
:.
registers 21, ..., 2n, and from the output of the register 2k to
the address counter 38 to continue calculations according to the
program selected according to the given initial address.
Consider now a programmable computing system, wherein
one of the computers 1 is programmed as a computer 1 which con-
trols all the other computers of the system.
Such a computiny system is programmed at the level of
programs of the controlled computers 1 by presetting the initial
- 30 address codes of these programs in the control program. The
control program is entered into the closed circuit via the gate
64 of the control computer 1 from the peripheral device. The
- 42 -
10~;7t~0
control computer 1 selects the initial address codes of the
required programs from the control program and turns over the
control of the calculation process to the controlled computers
1 containing these programs. After the controlled computer 1
has finished a certain program, there is a comeback to the control
program in order to determine the next initial address code with
the aid of the control computer 1 and continue calculations.
The proposed output buffer device 96 (Fig. 4) operates
as follows. During the action of the clock pulse 159 (Fig. 6a)
applied to the second clock pulse bus 108 (Fig. 4), the transistor
113 is driven into conduction, so that information, which has
been applied to the input 112 of the buffer device 96, is sent
to the input 122 of the follower 102. Simultaneously, the input
information is applied via the inverter 111 to the input 105 of
the follower 101. If in the course of the duration of the clock
pulse 159 (Fig. 6a) there is applied high voltage to the input
112 (Fig. 4) of the buffer device 96, at the input 105 of the
follower 101 there i5 low voltage, and the positive feedback
capacitor 110 discharges through the output resistor of the
inverter 111 and the transistor 107 (Fig. 4) which is conducting
during the action of the clock pulse 159 (Fig. 6a). At the out-
` put 106 of the follower 101, there is set low voltage. The posi-
tive feedback capacitor 110 remains discharged until the arrival
of the next pulse 160 (Fig. 6a) at the second clock pulse bus
108 (Fig. 4); the transistor 103 remains non-conducting, and low
voltage is maintained across the output 106 of the follower 101.
If during the action of the clock pulse 159 (Fig. 6a) there is
applied low voltage to the input 112 (Fig. 4) of the buffer
~! device 96, there is observed high voltage across the input 105
of the follower 101, and the positive feedback capacitor 110
~` is charged through the output resistor of the inverter 111 and
the transistor 107 (Fig. 4) which is in the conducting state
- 43 -
.~
lot~ o
during the action of the clock pulse 159 (Fig. 6a). There is
now low voltage at the output 106 of the follower 101. I'he posi-
tive feedback capacitor 110 remains charged until the arrival of
the next pulse 160 (Fig. 6a) at the second clock pulse bus 108
(Fig. 4), whereby the transistor 103 is maintained in the state
of conduction. As a result, the clock pulse 161 (Fig. 6b), which
is applied to the first clock pulse bus 104 (Fig. 4) via the
transistor 103, passes to the output 106 of the follower 101. If
during the action of the clock pulse 159 (Fig. 6a) high voltage
is applied to the input 112 (Fig. 4) of the buffer device 96,
there is high voltage across the input 122 of the follower 102,
and the clock pulse 161 (Fig. 6b) is applied to the output 118
- (Fig. 4) of the follower 102, because the circuitry of the
follower 102is similarto that of the follower 101. If duringthe action
of theclock pulse159 (Fig. 6a) thereis applied low voltage to theinput
112 (Fig.4) of the buffer device 96,there is]ow voltageacross theinput
122 of the follower 102, and low voltage is maintained across
~ the output 118. Each of the positive feedback capacitors 110
`~ serves for maximum transmission of the voltage of the clock
;~ 20 pulses 161 and 162 (Fig. 6b) to the outputs 106 and 118 (Fig. 4),
.~
since the voltage of the charged positive feedback capacitor 110
is added at the gate of the transistor 103 to the source voltage
of the transistor 103, whereby the transistor 103 is driven into
conduction more effectively during the action of the clock pulses
` 161 and 162 (Fig. 6b). Thus, if low voltage is applied to the
input 112 (Fig. 4) of the buffer device 96, the transistor 114
is driven into conduction by the clock pulse 161 (Fig. 6b)
applied from the output 106 (Fig. 4) of the follower 101, so
that high voltage is applied from the first supply bus 115 to
the common point 116 and the gates of the transistors 119 and
126. The transistors 119 and 126 are snapped into conduction.
The conducting transistor 119 passes low voltage of the common
.'` .
- 44 -
10~ 0
bus 109 to the common point 120 and the gate of the transistor
123. The transistor 123 is rendered non-conducting, and the
output 125 of the buffer device 96 gets connected to the common
bus 109 via the conducting transistor 126. The transistors 121
and 117 are rendered non-conducting by low voltage across the
input 122 and the output 118 of the follower 102.
If high voltage is applied to the input 112 of the
buffer device 96, the transistor 117 is driven into conduction
by the clock pulse 161 (Fig. 6b) applied from the output 118
(Fig. 4) of the follower 102,so that low voltage is applied from
the common bus 109 to the common point 116 and the gates of the
transistors 119 and 126. The transistors 119 and 126 are rendered
non-conducting. The transistor 114 is rendered non-conducting by
low voltage at the output 106 of the follower 101. The transis-
tor 121 is driven into conduction by high voltage at the input
122 of the follower 102, so that high voltage of the first supply
; bus 115 is applied to the common point 120 and the gate of the
transistor 123. The transistor 123 is driven into conduction,
and high voltage is applied from the second supply bus 124 to the
output 125 of the buffer device 96. The state of the output 125
`~ of the buffer device 96 remains unchanged until the arrival of the
next clock pulse 162 (Fig. 6b) applied to the first clock pulse
bus 104 (Fig. 4)~ because the transistors 114 and 117 are non-
i conducting during the period of time between the clock pulses 161
and 162 (Fig. 6b), so that information is maintained at the
capacitances of the gates of the transistors 119 and 126 (Fig. 4).
The proposed devices 28 and 29 (Fig. 5) for commutation
; of input and output signals of the matrix 27 operate as follows.
During the action of the clock pulse 163 (FigO 7a) applied to the
second clock pulse bus 137 (Fig. 5), the transistor 134 is driven
into conducticn, and information is applied to the gate of the
transistor 138. Simultaneously, the switchable capacitor 146 is
- 45 -
.,
~0~7~V
char~ed through the transistor 143 which has been driven into
conduction by the clock pulse 163 (Fiy. 7a). The transistor 144
is snapped into conduction, and low voltage is applied to the
output 145 of the second exciting circuit 132 of the decoder 127.
If high voltage is applied to the address input 136 of the commu-
tation device 28, the positive feedback capacitor 141 is charged
through the conducting transistors 135 and 138 to the third clock
pulse bus 139 at which there is low voltage during the action of
the clock pulse 163 (Fig. 7a). Upon the end of the action of the
clock pulse 163 and prior to the arrival of the clock pulse 165
(Fig. 7b), the switchable capacitor 146 (Fig. 5) discharges
through the conducting transistor 142. During the action of the
clock pulse 166 (Fig. 7b) applied to the third clock pulse bus
139 (Fig. 5), the clock pulse 166 (Fig. 7b) is transmitted via the
conducting transistor 138 (Fig. 5) to the output 140 of the first
exciting circuit 131 of the decoder 127. As this takes place,
low voltage is maintained across the output 145 of the second
exciting circuit 132 of the decoder 127, since the transistor 144
remains non-conducting. If low voltage is applied to the address
input 136 of the commutation device 26, the positive feedback
capacitor 141 discharges, the transistor 142 is non-conducting,
and high voltage is maintained at the gate of the transistor 144.
During the action of the clock pulse 166 (Fig. 7b), the clock
pulse 166 is transmitted via the conducting transistor 144 (Fig.
5) tothe output 145 of the second exciting circuit 132 of the
decoder 127. As this takes place, low voltage is maintained
across the output 140 of the first exciting circuit 131 of the
decode~ 127, since the transistor 138 remains non-conducting.
The positive feedback capacitor 141 serves to more fully
transmit the voltage of the clock pulses 166, 167 and 168 (Fig.
7b) and increase the load capacity of the output 140 (Fig. 5) of
- the first exciting circuits 131 of the decoder 127, because the
- 46 -
.~ .
10~17~0
voltage of the charged positive feedback capacitor 141 is added
at the gate of the transistor 138 to the drain voltage of the
transistor 138, whereby the transistor 138 is driven into con-
duction more effectively during the action of the clock pulses
166, 167 and 168 (Fig. 7b).
The switchable capacitor 146 ~Fig. 5) also serves to
more fully transmit the voltage of the clock pulses 166, 167 and
168 (Fig. 7b) and raise the load capacity of the output 145 (Fig.
5) of the second exciting circuits 132 of the decoder 127,
because the voltage of the charged switchable capacitor 146 is
added at the gate of the transistor 144 to the voltage of the
clock pulses 166, 167 and 168 (Fig. 7b), whereby the transistor
144 (Fig. 5) is driven into conduction more effectively during
the action of the clock pulses 166, 167 and 168 (Fig. 7b). The
capacity of the discharged switchable capacitor 146 (Fig. 5) is
at a minimum, so the voltage of the clock pulses 166, 167 and
168 (Fig. 7b) is not transmitted to the gate of the transistor
144 (Fig. 5) during the action of these pulses.
Hence, information applied to the address inputs 136
of the commutation device 28 during the action of clock pulses at
the third clock pulse bus 139 is transmitted in the direct form
to the outputs 140 of the first exciting circuits 131 of the
decoder 127, and in the inverted form, to the outputs 145 of the
second exciting circuits 132 of the decoder 127. During the
~`~ periods of time between adjacent clock pulses applied to the
third clock pulse bus 139, there is low voltage at the outputs
140 and 145 ofthe first and second exciting circuits 131 and 132,
respec~ively, of the decoder 127.
During the action of the clock pulse 169 (Fig. 7c)
applied to the first bus 147 (Fig. 5), the commutation devices
28 and 29 are prepared for subsequent operation. Low voltage
is set at the common input 128 of the decoder 127. The capaci-
; - 47 -
10t;7~;~0
tances of the internal units of the decoder 127 are discharged
through the output resistor of the inverter 134 and the conduct-
ing transistors 148 of the discharge device 133. The capacitances
of the outputs 129 of the decoder 127 are discharged through the
same circuit, including the selected output, because at the add-
ress inputs 130 of the decoder 127 thereis found the information
applied from the outputs 140 and 145 of the first and second
exciting circuits 131 and 132, respectively, of the decoder 127
during the action of the clock pulse 166 (Fig. 7b). Simultan-
eously, the capacitances of the inputs 152 of the decoder 151
and the capacitances of the outputs 153 of the decoder 151 are
charged through the conducting transistors 156 of the charger
155 from the supply bus 158, because at the address inputs 154
o~ the decoder 151 there isinformation applied from the outputs
140 and 145 of the first and second exciting circuits 131 and 132,
respectively, of the decoder 151 during the action of the clock
pulse 166 (Fig. 7b).
Upon the end of the action of the clock pulse 169 (Fig.
7c) and during the action of the clock pulse 166 (Fig. 7b), high
voltage is set across the input 128 (Fig. 5) of the decoder 127,
which high voltage is applied to one of the outputs 129 of the
decoder 127. The matrix 27 selects the information, and the out-
put information of the matrix 27, which is applied to specified
outputs of the matrix 27 as low voltage, is transmitted to the
outputs 153 of the decoder 151 and, accordingly, to the outputs
- of the device 29 for commutation of output signals of the matrix
27.
:. .
In the period between the clock pulses 166 and 167
(Fig. 7b), there is applied low voltage to the inputs 130 and
~54 (Fig. 5) of the decoders 127 and 151, and upon the end of
the clock pulse 169 (Fig. 7c) and during the action of the clock
pulse 166 (Fig. 7b), the information applied to the outputs of
- 48 -
:1 Oti7tiZO
the device 29 for commutation of output signals of the matrix
27 is maintained at the output capacitance of these outputs until
the arrival cf the following clock pulses 170 (Fig. 7c) and 167
(Fig. 7b).
The commutation devices 28 and 29 of the matrix 27
operate in a similar way during the action of the pulses 164,
165 5Fig~ 7a), 167, 168 (Fig. 7b), and 170, 171 (Fig. 7c).
The proposed sequential computing system makes it pos-
sible to use the computer 1 as the basis for different computing
systems which may include one computer 1 to solve simple problems,
or several computers 1 to solve complicated mathematical problems,
problems of management and problems involved in developing pro-
grammable systems.
In such computing systems, the computers 1 only differ
in the type of threading of the matrices 10, 30, 27 and 80 (i.e.
in the software). If a computer 1 is based on an LSI circuit,
it is enough to replace one masking element (mask) to provide
computers for different purposes.
.;
,.
~ 30
.~
- 49 -
