Note: Descriptions are shown in the official language in which they were submitted.
~683~
This invention relate~ in general to machine opera-
tion control systems and, more specifically, to a method
of and apparatus for monitoring and eontrolling the oper-
ation of preselected functions of individual machines in
a plurality of machines.
More particularly, this invention relates to a
digltal communications system wherein speeifie operational
funetions of each maehine in a series of maehines are
monitored and eontrolled from a single eontrol sub-
system or controller to assure individual maehine per-
formanee in aecordanee with a predetermined program.
In all manufacturing and produetion operations,
it is neeessary to monitor and eontrol the operation
of the equipment used in the produetion and manufae-
turing proeesses. In eertain applieations this moni-
toring and eontrolling funetion is performed by the
individual maehine operator who may eontrol more than
one maehine, depending upon the number of operations
whieh must be monitored, and the frequeney with whieh
ehanges occur in these eonditions and operations.
However, the eapabilities of an individual machine
operator to eontrol and monitor the equipment whieh is `
being utilized are limited. Therefore, it has been
attempted to monitor the operation of these maehines
25 and to control their functioning through the use of a
predetermined control program which monitors the various
funetions and conditions of a machine and controls the
operation of the machine in response to these moni-
tored eonditions to insure satisfactory operation.
One attempt to provid~ such a solution to this
,~
10~8381
problem has been the use of a controller which is pro-
grammed to couple predetermined control or command
signals to the machines in the event a predetermined
condition is detected thereby causing the command or con-
trol signal to be generated. In certain of these appli-
cations the detector or sensor which monitors the condi-
tion or operation, and the programmer or controller which
generates the responding command signal, are each electri-
cally coupled one to the other by wire pairs. This
coupling or hard wiring necessitates a substantial
expenditure of money for labor costs as well as the ;,
materials utilized in hard wiring the machine to the
controller. Such a system obviously requires a
controller to be in close proximity to the machine from
a physical standpoint due to the large number of wire
pair connections which must be made between the units.
Another attempt to provide a satisfactory solution
to this problem has been the use of various multi-
plexing systems using a common transmission line or
2~ signal carrier between the machine and the controller
wherein each of the individual functions of the machine
which are monitored and the responding control signal
generated to control proper machine operation are all
transmitted by the common signal carrier. Such systems
25 overcome the difficulties associated with hard wiring
each monitor or sensor to its respective controller
since they utilize a common transmission line, but
they are limited as to the number of conditions which
can be monitored within a given time frame.
3~ In such a system each of the functions is
--3--
iO6~38~
sequentially monitored and the corresponding control
signal coupled to the sensor. Such a system not only
controls changes in the state of the sensed condition
in response to the programmed control, but also insures
S that the correct state is maintained. These systems
address each sensor and generate a command or control
signal to the machine at every address regardless of a
change of state in the controlled function or operation.
Such a redundant system is satisfactory in applications
where the ~umber of monitored conditions is such that the
entire system may be monitored or addressed within the
limits of a predetermined maximum time frame. However,
such systems are not satisfactory for use in monitoring
a large number of inputs, or in smaller systems wherein
the maximum time period within which a condition must be
monitored or addressed is less than the time period
required for the multiplexing system to complete its
entire address cycle monitoring all terminals. In such
systems if a monitored function were to change state
immediately after the sensor has been addressed, the
condition could not be changed until the next cycle -
after all of the other machine functions or operations
had been addressed and the corresponding command signal
transmitted to each receptor. In many applications such
a time or cycle period is too great.
In monitoring or controlling machine operations
where the "redundant" type of multiplexing systems,
such as previously discussed, are not suitable due to
the cycle time delay inherent in this system, a prior-
ity system has been utilized. In such systems the func-
~06838~
tions or conditions are arranged in priority of impor-
tance and sequentially addressed in synchronism, but
no command signal is transmitted unless a change of state
has been detected. The individual sensors or detectors
of each group are addressed, and, upon a change being
detected, a command signal is generated to correct or
change the condition or function. At the end of the
transmission cycle to that particular receptor, the en-
tire functions or controls series are again addressed
beginning with the highest priority function or control,
and the addressing of the entire cycle restarted to con-
tinue until a change is detected. Such a system requires
that each of the functions or controls which are to be
monitored must be ranked according to their importance,
and presents the problem that the lower ranked prior-
ities may never be monitored.
In another type of priority system the monitored
functions or controls are electrically coupled into
two groups. The first group comprises a small number of
high priority terminals and the second group contains
the remaining monitored terminals. The high priority
group is sequentially addressed and a command signal is
generated for each of the functions in this group in the
manner previously described with reference to the
"redundant" type of multiplexing system. The remaining
functions or controls are addressed, but no command signal
is generated unless the sensor for these controls or func-
tions has indicated that a change or a command signal is
necessary.
~nother type of priority multiple.xing system utilizes
--5--
33~
a random access memory and a two-speed addressing rate
which addresses all of the monitored conditions to
determine a change of state requiring a response, but
only transmits data through the comrnon signal carrier
upon the occurrence o~ a monitored event or the sensing
that a response-requiring change has occured. While
this system eliminates the problems incurred by delay
time due to the transminnsion of command signals to
functions or controls which do not need a command signal
for proper operation, they require further and more
sophisticated electronics in that the individual moni-
tors or detectors must be provided with additional
informational data identifying the receptor to insure
correct correspondence between the function monitored
and the command signal generated in response since there
cannot be any synchronization between the controller
and the receiver. The resulting random transmission of
control or command signals to the monitored receptors
must, therefore, be accompanied by informational data
which correlates the particular function or control which
is being monitored and the command signal directed to
change the state of a particular operation or function
to insure that the command signal is coupled to the
appropriate receptor. Such a system requires highly
sophisticated electronics and is, therefore, expensive.
With all of the various types of priority
systerns which have been utilized, each of these systems
is burdened with the inherent problem that, in order to
give certain machine functions priority, other monitored
functions must of necessity yield to these priorities.
~0~33~
Therefore, the secondary or non-priority functions may
become critical through lack of a command response being
directed to the receiver because of the continued utiliza-
tion of the common signal carrier or transmission line by
the higher priorit-y informational data. Even though the
various multiplexing systems discussed above are of bene-
fit in minimizing the expenses incurred in monitoring and
controlling the operations of a machine, such systems in-
herently present fu~ther problems which must be minimized
~0 in order to obtain an economical and co~nercially accept-
able system.
It is therefore, an object of this invention to
improve systems for monitoring and controlling the opera-
tion of production machinery.
It is another object of this invention to moni-
tor the operational functioning and controls of a machine
and to control its operation in accordance with a prede-
termined program.
A further object of this invention is to moni-
tor and control the operational functions of individualmaehines through a probramable controller used to control
the operations of a plurality of machines.
Still another object of this invention is to
control multiple operations and functions of machinery
through a controller coupled to the various monitoring
stations by a eommon signal carrier.
Yet another object of this invention is to min-
imize hard wiring between programably controlled machinery
and the programmed controller by utilizing a common signal
carrier.
3~
These and other objecrs are attained in accord-
ance with the present invention wherein there is provided
an information directing system coupling condition-defin-
ing signals generated by monitoring the operation of each
of a series of multi-functioning machines to a program-
able controller wherein each of the monitored operations
is controlled in accordance with a preselected program.
The system monitors and controls individual machine opera-
tions of a series of machines by means of the prepro-
grammed command signals generated to control the monitored
operations and couples the various condition-defining !?
signals and responding command signals through a common
signal carrier or transmission line.
Basically, the system comprises a controller-
machine combination involving a programmable controller
having groups of output lines which carry the machine
command signals as updated by information obtained from
the machinés, and groups of input lines to which the
corresponding information from the machine is routed so
20 as to update the controller. A multiplexing transmitter/ ~,
receiver assembly connected to the input and output lines
of the controller and driven by a free-running clock
simultaneously transmits the command signals information
in multiplexed format and receives the groups of machine
7~5 information for demultiplexed routing to the appropriate
groups of controller input lines. A similar multiplex-
ing transmitter/receiver assembly is connected to the
machine and is likewise driven by a free-running clock
simultaneously to receive/demultiplex the transmitted
3~ command signals for appropriate application
--8--
~068381
to the maehine eontrols and to transmit the machine data
in multiplexed format baek to the controller-associated
assembly. Eaeh transmission cyele is charaeterized by
the sueeessive transmission of the individual groups of
command or machine-information signals, followed by a
"dead" time whereafter the eyele repeats. The maehine-
assoeiated reeeiver utilizes this "dead" time not only
to maintain its transmitter and receiver in synehronism
but also to slave/synehronize the maehine assembly to
1~ the eontroller assembly despite the faet that each is
driven by a separate free-running eloek system. The
transmission from the two assemblies of each controller/
maehine eombination oeeur eoneurrently but it is the
transmission from the controller-asso:icated assembly
whieh eontrols the system beeause the event marked by
the ending of its transmission eyele is that whieh is
employed to eontrol or synehronize the maehine-assoeiated
assembly.
Further objects of this invention, together
2~ with additional features eontributing thereto and advan-
tages accuring therefrom will beeome apparent from the
following detailed deseription of one embodiment of the
present invention when read in conjunction with the
aeeompanying drawings, wherein:
2~ Figure 1 is a block diagram of a machine con-
trol system which may be eonstrueted aeeording to this
invention;
Figure 2 is a bloek diagram illustrating certain
prineiples of each basie controller/maehine system;
3~ Figure 3 is a eircuit diayram illustrating a
la~683l~L
machine multiplexer terminal;
Figure 4 is a circuit diagram of a machine-
associated transmitter multiplexer matrix;
Figure 5 is a circuit diagram of a machine-
associated receiver receiver demultiplexer matrix;
Figure 6 is a circuit diagram illustrating
a unit in the controller multiplexer terminal;
Figure 7 is a circuit diagram of a controller-
associated receiver demultiplexer matrix;
Figure 8 is a circuit diagram of a controller-
associated transmitter multiplexer matrix; and -
Figure 9 is a block diagram illustrating
the principle of machine serializing.
As is well known, certain operation character-
istics of machinery are capable of being determinedthrough the use of, for example, microswitches, limit
~switches, photo-sensors, or other suitable condition
responsive devices. These operating funcitons or char-
acteristics indicate normal operation as well as mal-
functions of the machine, and in many instances theoperations are interdependent such that a change in one
operation requires a coordinate response in another
operation to insure continuous satisfactory production.
There is in the logic block diagram plurality
of multi-functioning machines, Ml - MX individually
coupled to a centrally located programrning controller
12, by rneans of transmission lines Tl-~8. The pro-
grammable controller 12 is programmed with a program
compatible with -the controller's programming panel to
control a number of machines or processes. Since the
~10-
i83~ilL
speed of operation of the controller is so much faster
than that of the parallel coupled machines, the control-
ler can communicate with and thus operate one or more
of the machines concurrently and essentially independent
of the other machines. The programming controller 12
receives the information from various sensors in each of
the machines, the information is correlated by the control-
ler and data in response to the information from the
sensors is coupled to each of the individual machines
to control its operation. The controller 12 is a solid-
state modularized system designed to control operations
or processes that can be logically arranged into a number
of discrete steps of logical expressions, each with just
two states; i.e., status inputs are either on or off,
and the control operation selects outputs and turns them
on or off. This type of control sequence is used in mass-
production equipment and materials handling systems as
found in such varied industries as automotive, steel
and food processing and is commercially available as
2~ Model ~EC 14/30 Industrial Control System Model 14/30
manufactured by the Digital Equipment Corporation, May-
nard, Massachusetts. The DEC 14/30 System uses a replace-
able memory to direct specific control operations. Con-
venient computer programming techniques allow the user
2~ to design a memory to suit his unique control needs, and
the entire control process can be redefined by changing
the memory.
The DEC 14/30 System is designed to operate
independently or with cornputer monitoring or control.
3~ Since the DEC 14/30 can access all control inputs and
~0683~31
outputs, the monitoring components may be a general
purpose computer and a suitable interface device.
Further, a group of DEC 14/30 Systems can be monitored
by a single computer using a multiplexer to provide
status and malfunction reports for a large control
complex.
As shown in E'igure 1, controller 12 provides a
multitude of condition-responsive command signals through
a multiplexer controller terminal 15 and the transmission
lines labeled Tl, T2 - T8 to respective Multiplexer
Machine Terminals MTl, M~2 - MTX. Each of the
Multiplexer Machine Terminals MTl, MT2 - MTX is coupled
to respective input and output converters labeled I01, I02-
IOX to respective machines Ml, M2 - MX.
Conversely, the Multiplexer Machine Terminals MTl,
MT2 - MT X couples a multitude of condition-defining
information signal outputs indicative of the respective
machine Ml, M2 - MX throu~h transmission lines Tl, T2 -
T8 to the Controller terminal 15. More specifically,
and as will be explained further hereinbelow, when a
machine, for example, Machine Ml,- changes its status or
position, converter I01 converts the new status or
position information to logic level data which Multi-
plexer Machine Terminal Ml translates to binary data
which is coupl~d back through transmission line Tl and
controller terminal 15 to the controller 12. Controller
12 compares this new machine data with the pertinent
programmed or control information to continue the
operation in progress, to initiate a new operation as
required, or change the opera~ion.
-12-
The basic operation of the system is illustrated
in Figure 2 ~hich diagrammatically illustrates one
multiplexer machine terminal system MTN and the corres-
ponding portion of the multiplexer controller terminal
S syste~ . The t:wo systems include the respecti.ve free-
running clocks A and A', which drlve the receiver demul-
tiplexer sequencers B and B' and the transmitter multi-
plexing sequencers C and C' at a relatively slow byte
rate while dxi.ving the respective UAR/T transmitters
74 and 74' and the UAR/T receivers 74A and 74A' at a
relatively rapid rate. The units 74 and 74' (and also
74A and 74A') contain intern~l divide-by-sixteen counters
so that the bit rate of the system is one-sixteenth
that provided by the inputs of the clocks to these units.
The transmitters 74 and 74' accept parallel bi.t inputs
and transmit them serially, toyether with start, stop
and parity bits to the receivers 74A and 74A' respec--
tively, wherea~ the receivers accept the serialized bytes
and output them i.n paxallel. The demultiplexers D and
20 D', under control of the sequencers B and B' sequent.ially ~;
step the byte information to the groups of controll~d
devlces Fl FN and to the controller over the input
llnes Gl - GN. Dependent upon the controller program
as influenced by t.he inputs at Gl -GN, the controller
25 outputs the command signals at the lines Hl - HN. These
cor~lands are multiplexed by the multiplexer I, serialized
by the transmitter 74', received by the rece:Lver 74A
and provided as parallel outputs thereby to the demulti--
plexer D where they are sequenced to the appropriate yroups
of controlled devices Fl - FN. The groups of sensors
-:l3-
831~
Kl - KN monitor the corresponding controlled devices
Fl - FN and provide the inputs to the multiplexer I'
which are applied in se~uence to the transmitter 74,
serialized thereby, and which ultimately appear as the
updating data at the controller input lines Gl - GN.
The two sequencers B and C are controlled by an
end-of-transmission detector L to be reset simultaneously
thereby. The sequencers operate, in principle, as if
there are N+l states, N being the number of the groups
~t~ Fl - FN or groups Kl - KN, etc., with there being
only N transmissions (and corresponding receptions) per
cycle. In this way, there is a "dead" byte period
separating successive cycles whlch is used to detect
end-of-transmission by the controller assembly. Since
; the two sequencers A and C are reset simultaneously,
they remain synchronized so that each cycle starts with
the reception of the first group of command signals
applicable to the controlled device group Fl and the
transmission of the first group of data signals from
2(' the sensor group Kl. The detector L effectively slaves
each machine terminal system to the controller terminal
system and allows all of the clocks to be free-running.
The only constraint on the clocks is that they all be
su~ficiently accurate as to avoid such gross misphasing
:-~ during any one cycle as would defeat the effect of the
slave-inducing detector L.
Fiyure 1 illustrates a possible arrangement of
controlled machines. The controller 12 is connected
to the multiplexer controller terminal 15 which
-~ comprises eigllt of the transmitter/receiver systems
~0~83~
.
illustrated at the left-hand side of Figure 2 connected
respectively to the multiplexer machine terminals MTl -
MT8 each of which comprises a transmitter/receiver sys-
tem as illustrated at the right-hand side of Figure 2.
Each group of sensors K1 - KN and controlled devices
Fl - FN is- associated with a corresponding machine Ml -
M8 and are interfaced therewith by means of the input
and output converters I01 - I08. Additionally, there are
the two multiplexer machine terminals ~T9 and MTX serially
connected from the terminal MT8, as detailed herein-
after, and their corresponding input and output converters
I09 and IOX and machines M9 and MX.
One of the Multiplexer Machine Terminals is shown
in Figure 3 and comprises a transmitter section and a
receiving section. The transmitter section includes a
clock 61, which is of any suitable known design and
includes 1 MHZ oscillator 627 a 4-bit binary counter 63
and a NAND buffer gate 64. The counter 63 divides the 1
MHZ output from the clock 62 by two, four, eight or sixteen.
In the embodiment shown, a jumper wire 65 is connected
to counter 63 to divide by two and provide a 500 KHZ out-
put. The clock 61 provides clock or timing pulses for the
system, and particularly, to the units labeled UAR/T 74
and UAR/T 74A, as is well known in the art (units UAR/T
74A will be described hereinbelow).
The output from the clock 61 is coupled through
lead 66 to another 4-bit binary counter 67, connected
to divide by 16, and a divide-by-12 counter 69. The
oscillator 62 and counters 63, 67 and 69 comprise the
clock A of ~'igure 2, the Ot1tpUt of the counter 69 being
8:~81
the byte rate clock output of that Figure. The output
from counter 69 is coupled through a monostable multi-
vibrator 70 and lead 68 to provide pulses to another 4-
bit binary counter 71 which is the sequencer B of Figure
2, to the NAND buffer gate 73 and to the multivibrator
152 for purposes to be hereinafter explained.
The counter or sequencer 71 is connected to provide
a 4-bit binary output to a binary-to-decimal decoder 72.
The decoder 72 is arranged to provide an output for
the first 9 of the sixteen available states of the
counter 71, the sequencer being then reset and the ,
cycle repeats. To illustrate, assuming the sequencer 71
initially to be set to its initial state, output El
will be low correspondingly to control the multiplexer
matrix (I' of Figure 2) as hereinafter described and
each of the outputs E2 - E9I will be high. The gate 73
is thus enabled and the input from the inverter 151 will
be low to the multivibrator 152. A positive byte rate
clock pulse at the line 68 will thus provide an inverted
palse output frorn the gate 63, the leading edge of
which will cause the transmitter 74 to latch the parallel
input signals at D1 - D8, as dictated by the multiplexer
matrix, and the trailing edge of this pulse will initiate
serialization o~ these signals from the unit 74.At the
same time, the trailing edge of the clock pulse on line
68 will cause the counter 71 to increment, returning El
to its normal high state and causing E2 to go low corres-
pondingly to index the multiplexer matrix. This sequence
continues, driving the lines E3 - E8 successively low.
The eighth byte rate clock pulse on the line 68 will
-16-
~06~331~1
initiate transmission of the eighth by-te and will also
drive the line E9I low, thus disabling the gate 73.
The low state of the line E9I also enables the multi-
vibrator 152 by providing a high input thereto through
the inverter 151. The multivibrator 152 will produce
an output pulse only when both inputs thereto are
high with one of them negative-going. Thus, the multi-
vibrator 152 will produce an output pulse at the trailing
edge of the ninth byte rate pulse at line 68 and this
will condition the gate 141 so that a coincidental reset
pulse on the line 128 (as hereinafter described) will
produce a negative pulse output from the gate 141 which,
inverted by the gate 143 will reset the counter 71 to
its initial state in which only the line El is low and
the line E9I returns to its normal high state. Thus,
it will be seen that every ninth byte rate pulse will be
blocked by the gate 73 to provide a byte period "dead"
time between successive cycles. It will also be noted
that the reset signal on the line 128 also resets the
counters 67 and 69 so as to syncrhonize the sequencer
71'with the receiver 74A from whence this reset signal is
initiated and with the receiver sequencer 90 which is
simultaneously reset.' The delay or idle time corres-
ponding to the ninth state of the decoder 72 is used
as a marker for identifying and synchronizing the
initiation of the scan cycles, as will be explained.
The transmitter/receiver units 74, 74A and 74',
74A' are one package solid state Universal Asynchronous
Receiver/Transmitter devices (hereinafter also referred
to as UAR/T) manufactured by General Instrument Corporation,
-17-
~0683B~
Micro Electronics Division, 600 West John Street, Hicks-
ville, New York, 11802. Each UAR/T unit includes a
receiver section 74 or 74' which accepts asynchronous
serialized characters and converts them to a parallel
format. Each UAR/T unit also includes a transmitter
section 74A or ur~' which independently accepts parallel
binary characters and converts then to a serlal asynchron-
ous output with start, stop and parity bits added.
The UAR/T is relatively versatile with the baud
rate, bits per character, parity mode, and number of stop
bits being externally selectable, and the unit will inter-
nally synchronize the start bits with the clock input.
In the embodiment shown, the UAR/T units process eight
data bits, a parity bit and the start and stop bits.
It should be noted that the data transmission rate
capability of the UAR/T is quite high as compared to the
relatively low operating speed of machines Ml etc. The
UAR/T has tha capability of transmitting approximately
40,000 baud or 4000 eight bit transmissions per second.
~ As mentioned above, the counter 71 and the binary-
to-decimal decoder 72 generate the group-select address
pulse. The decoder 72 transforms the binary output of
counter 71 into one of eight mutually exclusive group-
select pulses which is coupled to terminals El-E8 to pro-
~5 vide a group-select address. The terminals or leads El-E8
are coupled to the like numbered terminals in Figure 4 to
apply the sequentially selected one out of eight groups
of data bits which is applied to the UAR/T transmitter
section 74.
When a strobe pulse is applied to the transmitter
~3~
74, strobing of eight bits enabled by the decoaer 72
occurs. A clock pulse from dividers 67 and 69 and
the multi-vibrator 70 is coupled through NAND gate 73
to UAR/T 74 to function as a strobe pulse.
With the beginning of a~strobe pulse applied to
UAR/T 74, the strobing o~ eight bits selected by the
decoder 72 occurs. The trailing edge of the strobe pulse
will cause the bits in the particular group to be serially
coupled out of the transmitter 74 through the line driver
75 and the transmission line.
The data bits Dl - D8 are coupled to UAR/T
transmission section 74 in parallel and are transmitted
through the transmission line in serial fashion as
will now be discussed. Figure 4 shows the multiplexer
circuit assembly or matrix 77 for entering the data bits
in parallel to the section 74. Circui~ assembly 77 i~
comprises eight identical switching circuits labeled
GlA-GlB through G8A-G8B, each circuit including two
buffer gates labeled generally A and s, which gates are
20 enabled or inhibited by the respective enabling lines ~,!`
labeled El-E8. In Figure 4 for simplicity in the drawing,
only four of the eight identical circuits are shown with
the associated buffer gates. The enable lines El-E8 will
be driven low or enabled in a sequence from 1 through 8
as the decoder 72 (Figure 3) is incremented. The enabling
lines numbered El-E8 are connected to the similarly
numbered terminals of the decimal decoder 72 of Figure 3.
As mentioned, decoder 72 selects and sequentially
couples each of the mutually exclusive groups of eight
bits through matrix 77 to the UAR/T transmitter section
--19--
~61~38~
74. Thus, one of the eight lines El-E8 is enabled
during a given period and the remaining lines remain
disabled. For example, when enable line El is low,
the eight input lines or leads ISl, IS2 - IS8, which are
connected to the input side of the two buffer gates GlA
and GlB, are effectively coupled through the matrix 77
to the output lines Dl-D8. Output lines Dl-D8 couple
the bits in parallel to the similarly numbered terminals
of the UAR/T transmitter section 74 of Figure 3.
The input leads ISl-IS8 are connected to respective
converters which will convert a relatively high 60 HZ
voltage to selected logic levels. As is well known, such
could be obtained, for example, by means of either a
transtormer or photo-optic system whereby a switch opening
1~ or closing in a 60 HZ line would be converted through a
suitable component, such as a D.C. bridge, to a distinc~
logic level. The foregoing would provide condition-
defining binary data information or signals to the
circuitry of Figures 3 and 4 relating to the occurrence
20 of an event in the associated machine. These condition-
defining information signals received from the machine are
converted through the Input/Output Converters I01-I09 and
coupled as parallel bits (Dl-D8) to the transmitter
section 74. The UAR/T section 74 serializes the data
25 bits and then couples the data through the line driver
75 and the transmission line Tl to the Controller
Multiplexer Terminal 15.
The receiver section of Figure 3 provides a means
of receiving condition-responsive cornmand signals from
30 the Multiplexer Controller Terminal 15 through the
-20-
~0683Bl
respective associated transmission lines Tl-T8 and couples
or conveys this information through the associated input/
output converter I01-I09 to the respective machine Ml-
M9 to affect its operation.
Serialized data from the Controller Terminal 15 is
received from the transmission lines Tl through input
gating and shaping circuits 83 and 84 which reshape and
square the data bit pulses before they are coupled to
the input of the UAR/T receiver 74A. The receiver
74A restructures the serialized data D9-D16 into an
eight bit output (D9-D16) havlng a parallel format and
the parallel eight bits are coupled out through two
Quad-input AND gates 85 and 86.
Concurrently, the designation as to where each
particular group of eight bits is to be delivered is
controlled by one of the eight outputs of a binary to
decimal decoder 72A; decoder 72A being similar to decoder
72.~At the beginning of each cycle, the multiplexer
controller terminal commences transmission of the
eight successive bytes-which contain the command signals
from the controller 12. At the end of each byte, a
high signal is produced on the output terminal 89 of the
receiver 74A. This signal is used either to increment
or to reset the address counter or sequencer 90 as
explained hereinafer, and to provide an input to the
decoder 72A. Strobe pulses from the decimal decoder
72A determine which one of the eight output lines E9 -
E16 will go low and strobe the group of eight bits
received by the receiver 74A. The decimal decoder
72A thus determines where each group of eight data
-21-
33~3~
blts applied to the receiver 74A and available at the
output of AND gates 85 and 86 will be coupled to the
machine. The demultiplexer matrix 80 is illustrated
in Figure 5 and its operation will be evident due to
its similarity to Figure 4.
Returning to Figure 3, the end of a byte is
signalled by a high signal at the output line 89 and
this signal toggles the multivibrator 91 connected to
operate as a flip-flop having a Q output to the gate
130 and a Q output to the gate 128. The Q output is also
connected to the receiver 74A to reset the internal
flip~flop which produced the high signal at the line 89.
The two NOR gates 130 and 131 are cross-coupled as shown
and when the Q output from the device 91 goes high,
lS the normally low output of the gate 131 goes high and will
remain so until the two counters 135 and 134 provide a
clock pulse input to the gate 131. Normally, the counters
134 and 135 are held reset by virtue of the normally high
output ~rom the inverter 132. When the counters 134 and
135 have counted exactly thirty-two pulses from the ~.
counter 63, an input will be provided to the gate 131
This time delay (thirty-two pulses) corresponds to
two bit periods, the UAR/T devices having internal
divide-by-sixteen counters so that a bit period is
equal to sixteen clock pulse outputs from the counter 63.
When the gate 131 receives the input from the counter 134,
the output of the gate 132 returns to high state, resetting
the counters 134 and 135 and causing the one-shot 133 to
~ire, producing a negative-going pulse output which is
applied to the two NOR gates 92 and 93. Since this signal
-22-
~0~ 38~L
is delayed by two bits at the end of one byte, it will
coincide with the first bit (the "start" bit) at the
beginning of the next byte unless there is no next
byte because the cycle has completed and the "dead" time
is present at the input to ~e unit 74A. It will be noted
that each byte consists of eleven pulse time slots,
the first and last of which are assigned to the "start"
and "stop" bits wllereas the remalnder are assigned to the
eight data bits and a parity bit. Since each byte
1~ period contains twel~e time slots, the aforementioned
two bit period delay is necessary to assure that the -~
delayed pulse will coincide with the "next byte"
"start" bit. If there is a "next byte", its "start"
bit will cause the signal at the input 97 to be low when
the two gates 92 and 93 are enabled by the one-shot 133
and both inputs to the gate 93 will be low so that it
produces a positive output at the line 98 which incre-
ments the counter 90. The low signal on the line 97
will cause a high input, through the inverter 95, to the
,~D gate 92 so as to disable it. If, on the otner hand, there ~j,
is no "next byte", indicating that the multiplexer con-
toller terminal 15 (see Figure 2) has completed a cycle,
the signal at the line 97 will be high disabling the gate
93 while enabling the gate 92. Thus, the output from the
25 one-shot 133 will produce an output from the gate 92
to reset the counter or sequencer 90, reset the counters
67 and 69 and reset the counter or sequencer 71 through
the gate 141. Thus, the cycles of the machine terminals
are slaved to the controller terminal transmissions.
The two gates 128 and 129 and their output at the
-23-
~L06838~
line 99 to the decoder 72A are employed for parity pur-
poses. As a byte is received and parity check indicates
an improper bit, the output line to the gate 128 goes high.
This prevents any output from the gate 128 when the
normally high Q input to the ga~e 128 goes low at the end
of a byte and the output from the inverter 129 will remain
high so that when the counter 90 is incremented, a low
signal will not appear at the corresponding line E9-E16
and the defective byte will not be demultiplexed to the
machine. Thus, the output of the gate 129 constitutes
an enable signal to the decoder 72A which, if parity
checks, will go low in response to the output from the
device 91.
It is necessary to insure that the Multiplexer
Controller Terminal 15 and the Multiplexer Machine
Terminal MTl-MT9 generate waveforms at essentially the
same rate. Accordingly, clocks (labeled 61 in Figure 3)
are provided at the various terminals which run at fre-
quencies which match within approximately one per cent.
At each terminal phase synchronization is done internally
by the UAR/T units 74 and 74A.
As noted, Figure 5 shows a demultiplexer matrlx
system generally labeled 80 for connecting the
eight bit parallel outputs from UAR/T 74A to the assoc-
iated input and output converter. The output of UAR/T74A of Figure 3 is coupled to the exclusive OR gates 161
and 163 of Figure 6. Depending upon which of the enab]e
lines E9-E16 are enabled by decimal decoder 72A,
two each of the respective flip-flop circuits generally
labeled G9-G18 are activatcd.
-2~
3~
For example, C,9A and G9B pass the data through
output of lines D9B-D16B to the input and output termina]s
of the machine to which these lines are coupled.
In systems such as described herein, there are
generally two types of command situations in the control
process of the system. In the first situation, action
has to be taken to change the control or status of the
machine. Such new command will be applied by the
controller 12 to the Multiplexer Controller Terminal
15 where it will be placed into a signal format compatible
with the circuitry of a Machine Terminal MTl-MTX. In
the embodiment of the invention groups of eight data
bits each will be serialized and coupled through the
transmission llnes Tl-T8 to the machine terminals MT1-
MT9. The receiver section of the respective Machine
Terminal MTl-MTX will receive these commands, and these
new commands will be applied to the machine actuators ;
which will cause certain action.
In the other situation no action or change in an
actuator has to be made and, normally, no data need be
transmitted. However, in the present system, the
Controller 12 will determine that the machine should
remain in its current state, and a command to that
effect will be transmitted to the machine to confirm the
25 condition. While such transmittal of information is re-
dundant, it also insures a reliable system.
It wi]l be noted from Figure 1 that the trans-
mission line T8 serves the three machine terminals MT8,
MT9 and MTX. This serial connection arrangement will now
bè described, but it will be understood that any one of the
-25-
33~
transmission lines may be used to serve two or
more machine terminals if so desired.
The basic principle of the serial arrangement
is shown in Figure 9 wherein it will be seen that
transmissions from the controller terminal 15 are
connected in parallel to the receiver sections of
all three of the machine terminals MT8, MT9 and MTX.
In this way, the controller terminal slaves each of the
machine terminals to it, as described previously. The
transmission output lines 0 from the several transmitter
sections, however, are connected so that only one
of them may be connected back to the con-troller terminal
15 during any particular byte period. For this purpose,
the logic gates L are employed each under control of an
input line 121' as shown. The details of a logic gate
and the manner of Gontrol thereof are shown in Figure 3.
In Figure 3, the switch or jumper assembly 120
selectively connects one or more of the outputs ~2-E9
of the decoder 72 to the NAND gate 121. Each of the
2~ inputs to the gate 121 normally is maintained high by
connection to a positive voltage source through a suit-
able resistor, one of which is indicated at R in
Figure 3. If any one of the switches 120 is closed,
the corresponding input to the gate 121 will go low when
the corresponding output of the decoder 72 goes Low,
producing a high output at the normally low line 121'.
A high signal on the line 121' will enable the NAND
gate 127 and, because of the inverter 122, will inhiblt
the N~ND gate 123. The inhibition of the gate 123 will
maintain its output to the NAND gate 12~ high so as to
-26-
~0~i838~
enable it. Thus, during any byte period corresponding to
an open switch condition at the switch 120, the transmitter
74 of Figure 3 will be connected through the transmission
line to the controller terminal 15. If, on the other hand,
the switch connected to the decoder line E4 for example
is closed, then the gate 127 will be enabled and the gate
122 will be inhibited during the corresponding byte period
and the transmitter of the machine terminal MT9 will
then be connected back to the controller terminal 15.
Thus, by programming the switch assembly 120, the
machines MT8 an~ MT9 are connected in the time shared
fashion to the controller terminal 15 during each cycle.
If a third machine such as MTX is desired also to share the
common controller terminal transmitter/receiver system,
then the machine terminal 9 is provided with a switch
assembly 120 and logic gate arrangement cooperating
with the machine terminal MTX as shown in Figure 9.
In each case, the last machine terminal of the series
(MT9 in Figure 3~ does not require the switching
assemhly 120 or the logic gate arrangement 122, 123,
124, 126, 127.
To provide a specific example , suppose the
machine M9 is to transmit its condition-defining
signals during the fourth byte period, the machine
MTX is to transmit its condition-defining signals during
the fifth byte period and the machine MT8 is to transmit
its signals during the remaining byte periods. Then,
only the switches of E4 and E5 of the transmitter section
associated with the machine MT8 will be closed, and
only the switch of E5 of the transmitter section assoc-
-27~
~06838~
iated with the machine MT9 will be closed.
The re~e.iYer .section of each machine terminal
~Tl~MTX as well as the corresponding'receiver sections
- of the'controller terminal 15 contain safety circuits
.5 which monitor or check whether the transmission of data
is pr.oceeding properly and, if not, to disenable the
rec'eiver .demultiplexers to block the reception of
. data.
. , Figure.5 illustrates the control associated
with each machine terminal receiver demultiplexer matrix
wh~reas Figure 7 illustrates the control associated'with
each control.le~ terminal receiver demultiplexer matrix.
In Figure.5, the safety signal is provided at the.line
101 and will toggle the flip-flop formed by the cross-
15: coupled NOR gates 157 and 158 to drive the normally
high'output.of,.the gate low and corxespondingly to provide
a low input to the NAND gate 119, the other input of which
normally is high. In consequence the output at the line
117 goes high and this signal disables all of the
.20 switching devices G9A-G18A and G9B-G18B, thereby
to disable the demultiplexing matrix. Thus, no command .
signals appearing at the group of input conductors D9 - .
. D16 from the receiver 74A can be applied to any group of
output lines D9B- D16B.
Once the high safety signal appears at the line
101,.the system must be reset manually in order to toggle
the gates 157,.158 to their normal state. The manual
switch MS is provided for this purpose. Normally, the
inputs to the inver.ter 162 are high so that the corresponding
input to thé NOR gate 115 is low, its other input also
-28-
338~
normally being low. Thus, the output from the gate 155
normally is high, independent of the state of the safety
signal at the line 101. However, by depressing the
reset switch MS, the output of the gate 162 goes high
and that of the gate 155 goes low~ thereby resetting the
flip-~lop 157,158. This allows the matrix of Figure 5
to operate normally.
The flip-flop 157,15~ also controls the transistor
T120 through the buffer gates 159, 160 to cause it to
conduct and energize the relay Rll9 when the output of the
gate 158 goes low. The relay R119 is used to provide a
visual or other signal that the demultiplexer matrix
has been disabled.
The circuit of Figure 5 also provides a power-up
~5 delay to prevent matrix operation for a short period
until the circuits have "settled" incident to power being
turned on. This is achieved by the R-C circuit R76,
C75. When power is first turned on, a finite time will
be required to charge the capacitor C75 and, until it
does, the output from the multivibrator 114 to the
gate 115 will remain high. When this input to the gate
155 goes low, the flip-flop 157,158 will be toggled to
its normal state.
Figure 7 shows the safety circuit control arrange-
'5 ment for a controller terminal receiver demultiplexermatrix. The condltion-defining signals from the corres-
ponding machine terminal transmitter come in over the
transmission line and the controller receiver outputs
them in parallel at the lines D9'-D]6'. The controller
12 handles sixteen of these signals at a time and for
-29-
106~3~1
this reason the latches G9AC - G16AC and G9BC - G16BC
are separated into groups of four. The four inputs
to the buffer 102A are enabling signals from the controller
L2 and appear one at a time and are applied to the switching
circuit 102. If the input from the NOR gate 107 to the
circuit 102 is high, the switch 102 will pasa the
appropriate enabling signal to one of the groups of
four latches of the matrix, allowing them to latch their
inputs in accord with the addresses E9' - ~16'. Any
two of these enabling inputs are NANDed as shown so that
- if either one or both of them are low, a low input
will be applied to the NOR gate 107. The other input to
this gate is the safety signal on ~e line 101' which,
as described before, normally is low. Either the presence
1~ of a high signal on the line 101' or the presence of a
high signal at the other input to the gate 107 will cause
the switch 102 to open and block the enabling signals.
The manner of generating a safety signal will be
seen from Figure 3. The multivibrator 112 will produce
a high output pulse at the line 101 whenever its input
is low. During normal operation the capacitor C104 will
be charged, maintaining the input to the device 112
high so that its output is low and the safety signal
therefore will not be present on the line 101. The
device 110 is an eight bit serial shift register which
is cleared at the byte rate from the multivibrator 133
of the delay circuit 94 if transmission is proceeding
normally. Under these conditions, the counter 69 clocks
the shift register at the byte rate and the output of
3~ the shift register continuously remains low. In
-30-
~06~38~
consequence, the output of the multivibrator 111 remains
high and the capacitor C104 remains charged. If trans-
mission is interrupted to the receiver 74A, the multi-
vibrator 133 ceases to clear the shift register 110 and
if this condition persists ~or enough byte periods, the
shift register will then produce a continuous high out-
put, triggering the device 111 rapidly to discharge the
capacitor C104. The multivibrator 112 is thus triggered
so that its normally low output goes high, producing
the-safety signal at the line 101. When the fault is
repalred and transmission resumes, the capacitor C104
will recharge slowly enough to allow the system to
stabilize before the signal on the line 101 goes low
to permit resumption of the data exchange. The capacitor
C104 thus acts as a power-up delay device under actual
power-up conditions as well as under a condition in which
power remains on while a broken transmission line, for
example, is repaired. In either case, the relatively
slow rate of capacitor charging allows time for the
system to "settle" or synchronize.
A similar circuitry is employed at the controller
terminal units as shown in Figure 6 where the components
described in conjunction with Figure 3 are identified
by corresponding primed reference characters.
The principles of transmitter multiplexing at the
controller terminal lS are illustrated in Figure 8.
The controller 12 used in the embodiment of the
invention shown and described herein is capable of
providing two hundred and fifty-six command signal
outputs and of accepting five hundred and twelve
-31-
3~
inputs. Therefore, whereas there are thirty-two inputs
available for each controller demultiplexer there are
only sixteen outputs available for each controller
multiplexer, these command signal outputs for the
multiplexer being indicated as CSl - CS16 in Figure 8.
As will be described later, the output gates 200' and
201l are enabled by a signal on the line 199' to output
the relevant command signals during the first four byte
periods of each cycle and to provide high outputs (0
logic level) during byte periods five-eight, the ninth
byte period being the dead time dictated by blocking
of the gate 73' (Figure 6?.
In the matrix of Figure 8, there are four buffer
gates 175' - 178', each having four command signal
inputs and corresponding output terminals. There are
two sets of four coincidence gating circuits 179' - `
186'. Every such gate has four inputs from one of the
devices 175l - 178' and the outputs of each device
175' - 178' are connected to two of the coincidence
gating circuits 179' - 186'. Enabling signals to each
group of four devices are provided by the controller 12
and these are the sequential signals at the lines 171' and
172' of the four lines 171' - 174' in Figure 6. The con-
troller 12 outputs sixteen command signals simultaneously
(also inputing sixteen condition responsive signals simul-
taneously) so that the enabling signals at the lines 171' -
174' are maintained for two byte periods. In Figure 8,
the signal at the line 171' enables the four gates 179' -
182' so that their sixteen command signal outputs are
~(~ applied to the corresponding latches 191' - 194'. The
-32-
~6838i
enabling signal at the line 171' drives the inputs to the
NAND gate 187' high so that the inputs to the NAND gate
188' go low to produce the high enabling signal.
The output sof the groups of gates 179' -
182' and 183' - 186' are connected to the corresponding
inputs to the groups of gates 191' - 194' and 195' -
198', through pulse-shaping circuits, one of which is
illustrated in detail in Figure 8. As shown, the pulse-
shaping circuit comprises a Schmitt trigger device
189', the input voltage level to which at the junction
J' is controlled by charging of the capacitor 190'
through the resistor Rl' from the +5V source and dis-
charge of the capacitor 190' through the resistor R2'
in response to a command signal pulse passed by the
gate 179'.
Each set of four gates 179' - 182', 183' - 186' is
enabled by a signal 171' or 172' for a period equal to
two byte periods. During this period, two address signals
will appear sequentially from the decoder 72' of Figure 6.
Thus, while the gates 179' - 182' are enabled, first the
two output gates 191' and 192' will be enabled by the sig-
nal El' and then the output gates 193' an 194' will be
enabled by the signal E2', and so on for the gates 195'
and 196', 197' and 198' during the first four byte per-
iods of each cycle. Each pair of the output gates iscoupled to the command signal inputs Dl' - D8' to the
transmitter 74' through the ga-tes 200' and 201'.
These latter gates are enabled by the signal at the ter-
minal 199' for only the first four OUtpllt states of the
counter 71' (Figure 6) and, for this purpose, the NAND
-33-
~)683~
gate 170' is connected to that output line of the counter
71' which remains high during these first four states.
At the fifth output state of the counter 71', the signal at
the terminal 199' goes low to disable the gates 200'
and 201' and this condition prevails until the counter
71' is reset.
When the signal at the terminal 199' is low during
the fifth through the eighth byte periods of each cycle,
all of the outputs Dl'- D8' to the transmitter 74' are
high so that all command signal bits transmitted during
these periods are of O logic level (high) to the machine
terminal receiver 74A. It will be appreciated that the
controller receiver demultiplexer, Figure 7, receives
condition-defining signals from the machine terminal
i5 transmitter 74 during each of the eight byte periods of
each cycle but, as is the case with the matrix of Figure
8, the demultiplexer matrix outputs sixteen condition-
responsive signals simultaneously to the controller 12,
corresponding to signals lSl - lS16 of Figure 7. It
should be understood, of course, that one set of sixteen
signals is produced by the set of four gates G9AC,
G9BC, GlOAC and GlOBC, and so on for all sixteen
of these gates , and each set of four gates being
enabled in turn by the lines 103, 104, 105 and 106.
2~ To illustrate one embodiment of the invention, the
following circuit components are listed:
Reference character Component
102 DM740ON National
92,93,95,107,128-132,141,143 DM7402N "
3~ 17S'-178' DM7404N
-34-
10~;83~
Reference Character Component
85,86 DM7408N National
110 DM7416~ "
121 DM7430N
64,73,119,122-124,126,127,159,160 DM7437N "
162,179'-188',200',201'
72,72A DM7442N "
69 DM7492~ n
63,67,71,90,134,135 DM7493N "
GlA-G8A,GlB-G8B,l91'-I98' DM8093N a
G9A-G16~,G9B-G16B,G9AC-G16AC, DM8551N "
G9BC-G16BC
70,91,133,152 DM74121N "
84,111,112,114,189' NE555V Signetics
102A 206-004 CTS
120 260-8 CTS
83,125 MCL610 Monsanto
While the invention has been described with reference
to a preferred embodiment, it will be understood by those
skilled in the art that various changes may be made and equi-
valents may be substituted for elements thereof without departing
from the scope of the invention. ~arious individual components
or devices shown in the various figures are known in the art.
The specific description of their individual structure and
operation can be found, for example, in the book entitled
Diqital Inte~rated Circuits, published by National SemiConductor
Corp., Santa Clara, Californ}a, and copyrighted 1974. In addi-
tion, many modifications may be made to adapt a particular situ-
ation or material to the teachings of the invention without
departing from the essential scope thereof. Therefore, it is
intended that the invention not be limited to the particular
- 35 -
10~;~3381
embodiment disclosed as the best mode contemplated -for carrying
out this invention, but that the invention will include all
embodiments falling within the scope of the appended claims.
- 36 -
, ~
