Note: Descriptions are shown in the official language in which they were submitted.
C17~t;7
Background of the Invention
The present invention relates in general to
communicating over power lines and more particularly concerns
novel techniques and apparatus for exchanging digital data over
distribution power lines between a central control unit and
remote meter or control modules. The invention is especially
useful in facilitating automatically monitoring and controlling
the power distribution system and reading meters at remote
locations with good reliability. It accomplishes this using
the existing power distribution system between a substation
where a typical central control unit is located and each remote
meter or control module not only as a transmission path, but
also as a synchronization source. The invention advantageously
incorporates fewer components at the remote meter and control
modules than at the central control unit to help keep system
costs down.
Utility meters are typically read periodically by a
meter reader at the location of each customer who manually
records each meter reading and returns the in-formation concerning
the date, location and reading to a central office. At -the
central ofice a keypuncher or other cperator manually converts
this data into a form for automatic processing by billing com-
puters.
When meters are inside a building and no one is
available to admit the meter reader, the meter reader does not
record the reading for that period. The meter reader may leave
a post card addressed to the utility instructing the customer to
read the meter himself, write the reading on the postcard and
mail the reading to the utility. Alternatively, the utility may
es~imate the use for that period based on past history. Both
of these approaches are subjec-t to inaccuracy. Moreover, e~en
in systems where the meter is located outside and the meter
;7
reader always has access to it, manually obtainlng and converting
these readings for automatic processing is costly, time consuming
and subject to error in each step between initial reading by the
meter reader and automatic data processing for billing by the
computer.
A number of automatic meter reading systems have been
proposed. One approach involves the use of telephone lines to
carry the data. Another contemplates transceivers at each
customer location with an aircra-Et flying over the area to in-
terrogate transponders at each customer location through thetransceivers. Still another approach contemplates the use of
power lines for communicating data, but with costly links by-
passing each distribution transformer. A disadvantage common
to all these systems is high cost.
Utilities presently monitor the power flow on
distribution lines at very few locations because of the high cost
of telephone lines or limited radio-frequency channel allocation.
Control elements such as switches are manually operated while
power factor correction capacitors are operated by a clock
rather than in response to load demands. When power outages
occur because of breaks in the distribution line, utilities wait
for customer telephone complaints to inform them of the aEfected
area because they have no method of monitoring or controlling the
distribution system in real-time.
Utilities also have to provide generating capacity to
meet the peak load demands, rather than the average or essential
load. The present method of peak load shaving is to lower the
distribution voltage, which is harmful to items such as computers
and air conditioners, or in the extreme, to black out sections
of their franchised area by interrupting service. It is a far
better practice to shave peak load by interrupting service to
non-essential power loads such as hot water heaters. This is
:
--3--
7~ '7
presently accomplished by using time clocks, which lose time
during power outages and therefore eventually do not remove the
load during periods of maximum power consumption, or by general
appeals to the public to turn off non essential loads.
Summary of the Invention
An important object of this invention is to provide
an improved power line communication system.
It is another object of the invention to achieve the
preceding object with a relatively economical digital data
transmission system in which the existing power transmission
system is used not only as transmission paths but also as a
source of synchronizing signals locally available at each station.
It is another object of the invention to achieve one
or more of the preceding objects in a system where equipment
specifications at the numerous meter or control module locations
may be relaxed relative to those at the many fewer central control
units to keep system costs down while maintaining a reliable ex-
change of data at reasonable transmission rates.
It is a further object of the invention to achieve one
or more of the preceding objects with a system capable of
discriminating between desired and undesired signals.
It is still a urther object of the invention to
achieve one or more of the preceding objects with a system
incorporating a logic arrangement facilitating reliable
communication at relatively low costs.
It is another object of the invention to achieve one
or more of the preceding objects while automatically reading
meters at many remote locations and accurately transmitting
these readings to a central billing location.
It is another object of the invention to achieve one
or more of the preceding objects while automatically controlling
elements of the power distribution system at many locations and
--4--
~7`~7~
accurately transmitting the status o~ -these elements to a central
operations control location.
It is another object of the inventi.on to achieve one
or more of the preceding objects while providing a means o-f
rapid peak load shaving by interrupting service to non-essential
loads.
It is another object of the invent:ion to achieve one
or more of the preceding objects while provid:ing a means for
metering power consumption during peak demand hours.
In accordance with the foregoing objects and other
10 features and advantages, there is provided:- -
in apparatus for communicating from a central station
to a plurality of remote stations over power lines that may also
carry electrical power at power frequency, wherein the apparatus :
comprises transmitter means at the central station and receiver
means at each remote station, the transmitter means and each
receiver means being coupled to the power lines to transmit and
receive signals thereover, respectively, wherein said trans-
mitter means comprises a source of a carrier signal, a source ~ ~.
of a digital data signal and modulation means for modulating
said carrier signal with said digital data signal, and wherein
each receiver means comprises demodulation means for demodulating
the modulated carrier signal to recover the digital data signal
carried by the modulated carrier signal,
the improvement wherein,
said source of a carrier signal has a frequency that
is a harmonic of one-half said power frequency and is within the
range of 500 Hz. to 30 kEIz,
the data bit rate of transmission is a sub-harmonic
of, or the same as, said power frequency,
the transmitter means further comprises means
synchronizing the modulation means with the electrical power
~37~7~7
frequency carried by said power lines, and
each receiver means further comprises means syn-
chroniziny the demodulation means with the electrical power
frequency carried by said power lines.
There is also provided:-
synchronous power communicating apparatus for
communication between a central station and remote stations
over power lines that may also carry electrical power at power
frequency comprising:
a source of a carrier signal at each o~ said central
and remote stations, of frequency that is a harmonic of half
said power frequency in the frequency range between 500 and 30
kHz., for carrying digital data,
a source oE a digital data signal at said central
station and each of said remote stations,
means for establishing synchronism between each
digital data signal and the electrical power frequency carried
by said power lines,
means for modulating a carrier signal with an
0 associated digital data signal,
means for coupling the modulated carrier signal to
said power lines to transmit the modulated carrier signal over
the power lines, a receiving means at each station including
demodulating means for demodulating the modulated carrier
signal to recover the digital data signal carried by the modulated
carrier,
means at each station coupling the modulated carrier
signal from the power lines to said demodulating means,
means for synchronizing the demodulating means with
the electrical power carried by said power lines for demodulating
the modulated carrier signal received at -the receiving station
to recover the digital data carried by the modulated carrier signal.
~L~707~7
Brief Description of the Drawin~
Numerous other features, objects and advantages of
the invention will become apparent from the following specification :
when read in connection with the accompanying drawing in which:
FIG. 1 is a block diagram illustrating the logical
arrangement of a system according to the invention;
FIG. 2 is a block diagram illustrating the logical
arrangement of a system according to the invention having a
number of central control units at intervals along a power
distribution network; :~ ~
FIGS. 3A-3G graphically represent the composition of ~ ~:
messages for transferring data between the data acquisition
computer and central control unit and between the central control ~ :
unit and the transponders;
FIG. 4 is a block diagram illustrating the logical
arrangement of a central control unit;
FIG. 5 is a block diagram illustrating the logical
arrangement of a transponder;
FIG. 6 is a block diagram illustrating the logical
arrangement of a meter encoder;
FIG. 7 is a graphical representation of spectral
noise as a function of frequency typically encountered on a 120
volt power line;
FIGS. 8A and 8B are graphical representations of
i transmission as a function of frequency in an actual installation
according to the invention;
FIGS. 9A and 9B are schematic circuit diagrams of
power factor correction capacitors with series and parallel
isolation networks, respectively;
FIG. 10 shows the specific interconnections among
integrated circuits forming ~he modulator, demodulator and
timing control for the central control unit;
~37~ 7
FIG. 11 is a timing diagram illustrating typical
modulator and demodulator timing signals provided by the system
of FIG. lOB;
FIG. 12 is a timing diagrarn helpful in understanding
how data transmitted by the data acquisition computer is
processed by the central control unit;
FIG. 13 is a timing diagram showins command cycle
timing signal waveorms of the central control unit;
FIG. 14 is a timing diagram showing interxoga-tion
cycle timing signal waveforms of the central control unit;
FIG. 15 is a timing diagram showing interrogation
cycle signal waveforms related to data transfer from the
central unit to the data acquisition computer;
FIG. 16 shows central control unit demodulator phase
scan timing signal waveforms;
FIG. 17 shows specific circuit connections among
integrated circuits forming the input register and sync code
register;
FIG. 18 shows specific interconnec-tions among
integrated circuits forming the central control unit command
register;
FIG. 19 shows the specific interconnections among
components formin~ central control unit status register;
FIG. 20 shows specific circuit interconnections among
integrated circuits forrlling the central control unit output
register;
FIG. 21 shows specific interconnections among com-
ponents forming the demodulator, modulator and timing control
for the transponder;
FIG. 22 shows timing signal waveforms of the trans-
ponder of FIG. 21; and
FIG. 23 is a schematic circuit diagram of an exemplary
transponder transmitter.
~70~7
Description o the_Preferred Embodiments
With reference now to the drawings and more
particularly FIG. 1 thereof, there is shown a block diagram
illustrating the logical arrangement of a sys-tem according to
the invention. Where appropriate, corresponding elements are
identified by the same reference symbol throughout the drawing.
A central billing computer 1, which may be an IBM 360/g5,
prepares a data file containing information pertaining to each
meter to be read or item to be controlled, with the data file
sorted in a hierarchy according to data acquisi-tion and control
branch identification, central control unit identification,
distribution feeder and phase identification, meter module
identification, clock polarity identification, and meter type
identification. The data file is then transmitted by high speed
data link 18, which may be an interconnecting cable, to a
communication dispatch computer 2, which may be a Data General
NOVA 840. The communication dispatch computer 2 transmits the
pertinent parts of the data file to a multiplicity of data-
acquisition and control branches, such as 3A through 3T, via
high speed data lines, l9A through l9T, respectively, which
may be telephone lines or microwave links. The data file is
loaded into the data-acquisition computer controlling each
branch, such as item 4 of branch 3A, which may be a Data
General NOVA 2/10. ~'
The data-acquisition and control branches, such as
3A, interface with a multiplicity of power distribution and
metering systems, such as 6A through 6R, via a multiplicity of
central control units, such as 5A through 5R, which receive data
from data acquisition computer 4 via data links 20A through 20R,
respectively. Based on the data file received from communication
dispatch computer 2, data acquisition computer 4 sends data to a
central control unit, such as 5A, via data link 20A, which may
_g_
: '
~7~
be a telephone line, micro~ave link or cable TV cable, identify-
ing the distribution feeder and phase 2IA that central control
unit 5A should impress its output signal onto. Distribution
feeder and phase 21A forms part of distribution network 7. ~ `
Central control unit 5A signals data acquisition computer 4
when it has completed switching i-ts output signal to the in-
dicated distribution power feeder ~lA. Data acquisition
computer 4 then sends data to central control unit 5A instructing
it which meter module, such as llA, and meter type, such as 15,
to interrogate, the clock polarity to be used -Eor interrogation,
and at what data rate meter module llA should reply. Central
control unit 5A impresses a modulated audio-frequency signal
containing meter module address, meter type and reply data
rate inormation on distribution eeder 21A. The signal travels
along power distribution network 7, comprising power distribution
feeder 21A, which may be a 3-phase, 12, 4 kilovolt feeder, and
a multiplicity of distribution transformers, lOA through lOM,
to a multiplicity of metering groups, 8A through 8M. The
multiplicity of all the meter modules, such as llA through llP,
attached to the 240 or 120 volt, 60-Hz, distribution trans-
former secondaries, such as line 24 of distribution transformer
lOA, receive the central control unit signal and their trans-
ponders, such as 12, demodulate and decode the signal. The
transponder 12 whose locally-stored identification code matches
that of the decoded signal obtains the meter reading of the
designated meter, such as the electric meter 15, fxom a meter
encoder, such as 13, via line 26. The transponder 12 then
impresses on power distribution networ~ 7, via line 24 and
distribution transformer lOA, a modulated audio-frequency signal
identifying the meter module (llA in example) and meter type
(15 in the example), specifying the reply data rate, and giving
the meter reading. The signal travels along power dis-tribution
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~ c~7~37~ :
network 7 to central control unit 5A, which demodulates the
signal and sends the data to data acquisition computer 4 via
data link 20A. Data acquisition computer 4 checks the data for
errors and i-E any are found repeats the interrogation cycle at
a lower reply baud rate. If no errors are found, data
acquisition computer 4 stores the meter reading in a data file.
After all assigned meters have been interrogated, it transmits
the meter reading data to central billing computer 1 via data
link 19, communication dispatch computer 2 and cable 18. In a
similar manner, the system can also read gas meters, such as
16, and water meters, such as 17, by using meter encoders :L3'
and 13", respectively.
Another feature of the invention is the ability to
control the configuration of distribution network 7 by connecting
or disconnecting power factor correction capacitors, such as
23, to or from distribution feeders, such as 21A, and by
connecting or disconnecting distribution feeder switches, such
as part of 9N. Operation center 28 signals a data acquisition
and control branch, such as 3A, via data link 29, communication
dispatch computer 2 and data lin~ l9A, to connect or disconnect
power factor correction capacitors, such as 23, to or from
distribution feeder 21A. Data acquisition computer 4 selects
the proper central control unit, such as 5A, and then sends
data to it identifying the distribution feeder and phase, such
as 21A, central control 5A should impress its output signal onto.
Data acquisition computer 4 then sends data to central control ~-
unit SA instructing it which control module, such as 9A, to
command, the clock polarity to be used for interrogation, and
at what baud rate control module 9A should reply with switch
status. Central control unit 5A impresses a modulated audio
frequency signal containing control module address, switch
command and reply data rate information on distribution feeder
.
21A. The signal travels along power distribution network 7,
through a multiplicity of distribution transformers, such as
10A through 10M, to a multiplicity of control modules, 9A through
9N, which receive the central control unit signal. Their
transponders demodulate and decode the signal and the trans-
ponder, such as 12', whose identification code matches that of
the decoded signal commands switch 22, which may be a General
~lectric Catalogue #178L793G51, to the desired state, thereby
connecting or disconnecting power factor correction capacitor
23 to or from distribution feeder 21A. Transponder 12' then
impresses a modulated audio-frequency signal containing the
identification code of control module 9A, reply data rate and
switch status on power distribution network 7, via line 24 and
distribution transformer 10A. The si~nal travels along power
distribution network 7 to central control unit 5A, which
demodulates the signal and sends the data to data-acquisition
computer 4 via data link 20A. Data acquisition computer 4
checks the data for errors and, if any are found, repeats the
command cycle at a lower reply baud rate. If no errors are
found, data acquisition computer 4 transmits the power factor
correction capacitor switch status to operation center 28 via
data link l9A, communication dispatch computer 2 and data link 29.
Another feature of the invention is the ability to
shave peak load by disconnecting high-power-consumption devices
such as electric hot-water heaters. Operation center 28 signals
a data acquisition and control branch, such as 3A, via data link
29, communication dispatch computer 2 and data link l9A, to
disconnect hot watex heaters. Data acquisition computer 4 sends
data to central control units 5A through 5R instructing them to
interrogate all meter modules, such as llA and llB, by means of
a given clock polarity, hot water heater identification code and
command code. Central control units 5A through 5R impress a
-12-
~ ~7~7~7
modulated audio-frequency signal containing the hot water heater
identification code and command code on distribution networks,
such as 7. The signal travels along power distribution feeders,
such as 21A, through a multiplicity of distribution transformers,
such as lOA through lOM, to a multiplicity of meter modules, such
as llA through llP. All the meter modules receive the central
control unit signal, and the transponders, such as 12, using the
same clock polarity as the transmitted signal correctly demodulate
and decode the signal. All transponders contain the hot water
identification code and command their associated hot water heaters,
such as 14, to the state indicated by the command code. No reply
is sent to the central control units in response to this message.
In a similar manner data acquisition computer 4 then interrogates
the meter modules using the inverse clock polarity. rrhus, the
peak load is shaved by a considerable amount in a very short
period. The high power consumption devices such as hot water
heaters, can be reconnected in a like manner. Alternatively,
these devices can be reconnected after a preset interval by
using a time-delay relay or similar device.
In a similar manner, the invention can be used for ~
metering power consumption during the peak demand hours between ~;
4 and 8 P.M. A second meter encoder, or similar device, is
provided at each metering location. At the start of the peak
demand period the hot water identification code is transmitted
to all meter modules, along with function code indicating the ~ '
start of peak demand metering. The transponders, such as 12,
receive the signal and command the peak demand me~er encoder to
log the power being consumed. At the end of the peak demand
period the hot water identification code is transmitted to all
meter modules~ along with a function code indicating the end of
peak demand metering. The transponders, such as 12, receive the
signal and command the peak demand meter encoders to stop logging
~Ci7~7
the power being consumed. Alternatively, the peak dcmand meter
encoders can be commanded to stop logging power consumption by
using a timer, time-delay relay or similar device. Each peak
demand meter encoder can then be read monthly or bi-monthly as
previously described.
Another feature of the invention is the ability to
monitor the power distribution system operating parameters, such
as current flow, voltage amplitude and switch status. A trans-
ducer, such as current transducer 30, produ~es a digital si.gnal
that is proportional to the current flow through distribution
feeder 21~. When a measurement of the current flow in distri-
bution feeder 21A is desired, operations center 28 signals data
acquisition computer 4 via data link 29, communication dispatch
computer 2 and data link l9A. Data acquisition computer 4 sends
data to central control unit 5A instructing it to impress its
output signal onto power distribution feeder 21A. Data
acquisition computer 4 then sends data to central control unit
5A instructing it to interrogate status module 31, the clock
polarity to be used for interrogation, and at what baud rate
status module 31 should reply. Central control unit 5A impresses
a modulated audio-frequency signal containing status module
address and reply baud rate information on distribution network
7, through a multiplicity of distribution transformers, such
as lOA through lOM, to status module 31, where transponder 12l'
demodulates and decodes the signal. Since the address of
transponder 12" matches the demodulated and decoded signal, it ; .:
obtains the digital signal representing the current flow from
current transducer 30. Transponder 12ll then impresses a .
modulated audio-frequency signal con-taining the identification .
code of the status module 31, reply baud rate and current flow
information on power distribution feeder 21A via line 24' and ~ .
distribution transformer lOM. The signal travels along power
:~7~7~
distribution network 7 to central control unit 5A which
demodulates the signal and sends the data to data acquisition
computer ~ via data link 20A. Data acquisition computer 4
checks the data for errors and if any are found, repeats the
interrogation cycle with a lower reply baud rate. If no errors
are ~ound, data acquisition computer 4 transmits the current
flow data to operation center 28 via data link l9A,communication
dispatch computer 2 and data link 29~ ;
Thesubstations of the power distribution system are
advantageous locations for central control units 5A through 5R.
At this location the central control unit, such as 5A, has
direct access to all distribution feeders and phases, such
as 21A through 21R, emanating from transmission trans~ormers,
such as 27A thxough 27R, respectively, thereby allowing a
single cenkral control unit, such as 5A, to communicate with all
meter modules, such as llA through llP, powered by the sub~
station.
With reference to FIG. 2, it is also within the
principles of the invention to locate central control units at
intervals along distribution network 7'. ~ith this arrangement
data acquisition computer 4' communicates with all central
control units, such as 5C through SF, simultaneously on a party
line basis via data link 20C, which may be a telephone line.
The data acquisition computer message contains a central control
unit address code and only the central control unit that is
addressed, such as 5C, responds to the message. Fach central
control unit such as 5C through 5F has to communicate with only
one metering group, such as 8C through 8F, respectively, thereby
reducing the output signal power requirements of the central
control units~ Communications with a con-trol module, such as
9B, is assigned to a single central control unit, such as 5D.
Having briefly described the physical arrangement of
- 15 -
7~7
the system, its operational techniques will not be described.
Referring to FIGS. 3~-3G, there is shown the composition of the
messages used to transfer data between da-ta acquisition
computer 4 and central control unit 5, and central control unit
5 and meter transponder 12. Data is transferred between data
acquisition computer 4 and central control 5 at 285 baud using
the 11 bit byte message format o FIG. 3A. Other baud rates
and message formats may be used without departing from the
principles of the invention. The signal is normally in the
stop (logic 1) state and the start of a byte is delineated by a
start (logic 0) bit. Eight bits of data are then transmitted
with the end of a byte denoted bytwo stop bits.
Data acquisition computer 4 sends command messages to
central control unit 5 controlling its configuration. These
messages consist of three bytes as shown in FIG. 3B. The first
byte contains the central control unit address bits A16, and A17,
the message mode indicator bit K, the command execute enable bit
P and four of the command bits C0, Cl, C2 and C3. The next
two bytes contain the remainder of the command bits, C~ through
Clg. The central control unit address bits are used to insure
that only the proper central control unit responds to a command
message, particularly when using the party line arrangement of
FIG. 2. The message mode bit K is used to delineate between
command and interrogation messages from data acquisition compu-ter
4. When the message from data acquisition computer 4 is a
command, bit P is interpreted as a command execute enable bit.
If bit P is logic 1, the command message is executed while if
bit P is logic 0, the command message is not executed, thereby
enabling data acquisition computer 4 to obtain the configuration
status of central control unit 5O FIG. 3B illustrates a message
wherein bit K is logic 0, and bit P is logic l; therefore,
the message is a command to central control unit 5 and the
- 16 -
~.~7~7~
command bits, C0 through Clgl control the central control unit
transmitter power and distribution feeder selection relays
according to e~emplary Table I.
TABLE I
Command Action
C0 Transmitter Power On
Cl Transmitter Power Off
C2 Feeder 1 Phase A Selector Relay On
C3 Feeder 1 Phase A Selector Relay Off
10 C4 Feeder 1 Phase B Selector Relay On
c5 Feeder 1 Phase B Selector Relay Off
C6 Feeder 1 Phase C Selector Relay On
C7 Feeder 1 Phase C Selector Relay Off
C8 Feeder 2 Phase A Selector Relay On
Cg Feeder 2 Phase A Selectur Relay Off
C10 Feeder 2 Phase B Selector Relay On
Cll Feeder 2 Phase B Selector Relay Off
C12 Feeder 2 Phase C Selector Relay On
C13 Feeder 2 Phase C Selector Relay Off
20 C14 Feeder 3 Phase A Selector Relay On
C15 Feeder 3 Phase A Selector Relay Off
C16 Feeder 3 Phase B Selector Relay On
C17 Feeder 3 Phase B Selector Relay Off
C18 ~'eeder 3 Phase C Selector Relay On
Clg Feeder 3 Phase C Selector Relay Off
When the party line arrangement of FIG. 2 is used,
it is ad~antageous to increase the number of central control
unit address bits to allow more central control units to be used.
The command bit field can be decreased correspondingly since the
central conlrol unit will only be switching among the three
phases of a single distribution feeder.
- 17 _
7~7&j7
After accomplishing the desired command central control
unit 5 transmits its status to data acquisition computer 4 using
the ~-byte message shown in Fig. 3C. Byte 1 contains status
indicator bits S0 through S7, byte 2 contains status indicator
bits S8 through Sll, the central control unit address bits A16
and A17, the message mode indicator bit K, which is logic 0, and
command execute bit P, and byte 3 contains the remaining status
indicator bits S12 through Slg. Bytes 4 and 7 repea~ byte 1,
bytes 5 and 8 repeat byte 2, and byte 6 repeats byte 3. Thus,
the message is eight bytes in length, with the central control -
unit address and message mode indicator bits appearing at the
end of the eighth byte. This makes central control unit 5
command reply message to data acquisition computer ~ compatible
in byte count with that o an interrogation reply which will be
discussed shortly.
Data acquisition computer 4 sends the three-byte mes-
sage shown in FIG. 3D to central control unit 5 to initiate an -
interrogation cycle. The first byte contains the central control
unit address bits A16 and A17, the message mode indicator bit K,
which is a logic 1 denoting an interrogation messaye, bit P
which controls the bit clock phase during an interrogation cycle,
and the transponder function code bits, Fo through F3. The next
two bytes contain the meter module, control module or hot water
identification code bits, Ao through A15. The function code bits
determine the control action and reply data rate. Table II below
provides an exemplary meaning of each bit.
- 18 -
- '
~37~76~
TABLE II
Interrogation Type Function sit State Control ~ction
Meter Fo 1 Reply at 30 Baud
Meter Fo Reply at 15 Baud
Meter Fl 1 ~ead Electric Meter
Meter F2 1 ~ead Gas Meter :~
Meter F3 1 ~ead Water Meter ~
Hot Water Fo 1 Time out at 30 Baud ~ , -.
10 Hot Water Fo 0 Time Out at 15 Baud
Hot Water Fl 1 Hot Water Heater On ~.
~ot Water Fl 0 Hot Water Heater Off ~ ;
Hot Water F2 1 Start Peak Demand Meter
Hot Water F2 0 Stop Peak Demand Meter
Control Fo 1 Reply at 30 Baud
Control Fo 0 Reply at 15 Baud ~ -
Control Fl 1 Connect Capacitor ~ ~ -
Control Fl 0 Disconnect Capacitor .
Central control unit 5 sends the message shown in
20 FIG. 3E to meter modules llA through llP, ox control modules .:
9A through 9N, at 30 baud. The first eight bits are a fixed
synchronization code which the transponders such as 12, detect
and use to synchronize their data decoding. The next four bits
are the function code, Fo through F3 and the last sixteen bits
are the meter module identification code, Ao through A15. The
designated meter or control module replies at the rate indicated
by function code bit Fo with the message format of FIG. 3F.
Synchronization bits are not required since this message starts
immediately after the completion of the central control unit 5
messag~, shown in FIG. 3E. The reply message repeats the four
function code bits, Fo through F3, and the sixteen module
identification code bits, Ao through A15, and includes twenty
19 -
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bits of meter data or control status, Mo through Mlg, and twenty
bits of the one's complement of this daka, Mo through Mlg. Other
error detecting or correcting codes may be used for the data
fields Mo through Mlg and Mo through Mlg without departing from
the principles of the invention. The function code and module
identification code bits are repeated to verify that the central
control unit message of FIG. 3F was correctly received by the
desired module while the meter or status data is repeated for
transmission error detection since data accuracy is of the utmost
importance.
Central control unit 5 then transmits the module reply
to data acquisition computer 4 as eight bytes of data with the
central control unit address bits, A16 and A17, message mode
indicator bit K, which is logic 1 for this message and clock phase
bit P added to the end o the message, as shown in FIG. 3G. When
the party line arrangement of FIG. 2 is used, it is advantageous -
to increase the number o central control unit address bits. The
number of module identification code bits can be correspondingly
reduced since the number of meter and control modules each central -~
control unit will have to interrogate will be reduced in propor-
tion to the quantity of central control units that are used.
With reference to FIG. 4, the basic timing signal of
the central control unit 5 is the nominal 120 volt, 60-Hz power
line frequency obtained from the distribution feeder such as three
phase feeder 21, via transformer 34 and line 62 or reply contacts
63, 63' or 63" and line 61. Initially relay contacts 63, 63'
and 63" are open and timing control 47 utilizes the nominal 60-Hz
power line frequency on line 62 to derive the 285 baud clock for
communicating with data acquisition computer 4 and other clock
and timing signals that will become apparent as the in~ention is
further described. Central control unit 5 in-terfaces with modem
35, which may be a Bell System 103A data set, for communication
_ ~0~
~L~7~17~'7 ~
with data acquisition computer 4 over 285 baud data link 20. The
digital data xeceived by modem 35 from data acquisition computer
4 is sent to data receiver 36, which may be part of asynchronous
data interface TMS 6011 by Texas Instruments, which strlps out the :
8 da-ta bits from the ll-bit byte of FIG. 3A and signals timing :
control 47, via line 66, that a byte has been received. Timing ~.
control 47 issues a signal via line 70 that loads the data from
data receiver 36 into input register 37 and a reset signal to data
receiver 36 via line 65. After timing control 47 counts three
signals from line 66, it interrogates the first five bits of
input register 37, via line 69. If the central control unit
address bits A16 and A17 are correct, message mode indicator bit
K indicates the contents of input register 37 are a command and
bit P indicates the command should be executed, timing control
47 issues a signal, via line 78, that loads the command bits C0
through Clg of input register 37 into command register 43, which
enables the commanded relay driver, part of 46, which in turn
energizes the co~mandedrelay coil and indicator, part of 45,
thereby closing relay contacts 63, 63' or 63", which automatically
switches the 60-Hz power line frequency source used by timing
control 47 from line 62 to line 61. The status indicators, part
of 45, send a signal to the status register 44, via line 82,
indicating which relay is energized. Bit P is also loaded into
status register 44 via line 68. Timing control 47 waits a
preset interval after strobing the data into command register
43 for relay switching and status indication to take place and
then loads the contents of status register 44 into data ~rans-
mitter 55 via line 83, using shift mode, shift clock and transmit
data control signals on lines 81, 99 and 85, respectively. Data
transmitter 55 which may be part of asynchronous data interface
TMS 6011 by Texas Instruments, inserts the start and stop bits
to form the ll-bit byte, shown in FIG. 3A, which is then sent to
- 21 -
~7~37~7
data acquisition computer 4 via modem 35 and data l.ink 20. If
bit P indicates command executi.on should not take place, command
bits C0 through C19 of input reyister 37 are not loaded into
command register 43 and the command cycle times out as prev.iously
explained, thereby transmitting the pre-existi.ng configuration -~
of central control unit 5 to data ac~uisition computer 4.
If the message mode indicator bit K is logic 1,
indicating the contents of input register 37 are interrogation
data, timing control 47 loads the preset synchronization code
into sync code register 38 using a control signal on line 72,
selects the correct clock phase using bit P, and then shifts the
contents of sync code register 38 and input register 37 to
modulator 39 using the shift clock on line 70. The input to
modulator 39 modulates a carrier received from timing control
47 on line 73. The output of modulator 39 is amplified by power
amplifier 40, which may be a Bogen model NTB-250, and is
impressed on 120V, 60-~z line 61 by coupling network 41, which
is a series capacitor and inductor tuned to resonate with the
impedance of line 61 at the communication carrier frequency.
The transmitted signal then flows through relay contacts 63, 63',
or 63" and distribution transformer 34 to distribution feeder 21
and then to all the meter and control modules, 11 and 9,
respectively, attached to the distribution feeder 21. During
this interval modulator 39 is enabled, and receive switch 51
is inhibited by the transmit enable signal from timing control
47 on line 75.
At the completion of the central control unit 5
transmission period, modulator 39 is inhibited, and receive
switch 51 is enabled, by the transmit enable signal from timing
control 47 on line 75. The me-ter or control module reply signal
on distribution feeder 21 flows through distribution transformer
3~, relay contacts 63, 63' or 63", line 62, bandpass ilter 50,
~L~7~37~7 ~ ~:
which may have a Q of 20, receive switch 51, which may be an RCA `
CD4066A, and video amplifier 52, which may be a Fairchild Semi-
conductor 741 operational amplifier, to demodulator 53.
Demodulator 53 uses a reference frequency and function
code bit Fo received from timing control 47 on lines 73 and 91,
respectively, to obtain the data contained in the received signal.
Timing control 47 uses the meter ox control module reply baud
rate information contained in function code bit Fo to determine
the baud rate at which data is being receivecl by central control
unit 5. At the end of each baud interval the output of de-
modulator 53 is shifted into output register 54 by a shift clock
on line 89, generated by timing control 47. After the entire
reply message is received, the first eight bits of output
register 54 are transferred to data transmitter 55, and the
central control unit address bits A16 and A17, message mode
indicator bit K and clock phase bit P are loaded into output
register 54 by control signals from timing control 47 on lines
85 and 95, respectively. Data transmitter 55 inserts the start
and stop bits to form the 11 bit byte shown in FIG. 3A and
transmits the byte to data acquisition computer 4 at 285 baud,
via mcdem 35 and data link 20. Timing control 47 continues to
shift the data in output register 54 and transfer the data from
output register 54 into data transmitter 55 until the entire
meter or control module reply message contained in output
register 54 is transmitted to data acquisition computer 4.
The central control units, such as 5, and transponders,
such as 12, both use the 60-Hz power distribution frequency to
clock their timing control circuits. Eowever, due to the
random phasing of the distribution transformers, such as lOA
through lOM, the 60-Hz polarity at any transponder may be
inverted with respect to the 60-Hz polarity at central control
unit 5. The phasing of the 60-Hz signal in each transponder
- 23 -
~7~7~'7
can be adjusted at time of installation but this is a time
consuming and, therefore, prohibitively expensive process to be
performed at each transponder. The preferred method is to
install each transponder without adjustment and then use the
data acquisition computers, such as 4I to interrogate each
transponder while adjusting the 60-Hz polarity at central control
unit 5. When the 60-~z polarity used for interrogation timing
by central control unit 5 is identical with that at the trans-
ponder being interrogated, the transponder will reply correctly.
In this manner the correct 60-Hz polarity to be used for
interrogating each transponder can be found and stored in -the
master data files at central billing computer 1. The correct
60-Hz polarity is then transmitted to each data acquisition
computer, such as 4, as bit P whenever a transponder, such as
12, is to be interrogated.
With reference to FIG. 5, there is shown a block
diagram illustrating the logical arrangement of transponder 12.
The basic timing signal of transponder 12 is the nominal 120
volt,.60-Hz power distribution frequency obtained from dis-
tribution transformer secondary, line 24. Timing control 110
utilizes the nominal 60-Hz power distribution frequency on line
24 to derive the various clocks and control signals needed to
control the flow of data in transponder 12. The siynal from ...
central control unit 5 flows through bandpass filter 101 which
has a Q of about 5, receive switch 102, which maybe Rc~CD4066A.
video amplifier 103, which may be a Fairchild Semiconductor 741
operational amplifier, to demodulator 104. Demodulator 104 uses
the reference frequency from timing control 110, on line 119, to
obtai.n the data contained in the signal received from central
control unit 5. The demodulator output on line 135 is used by :~
timing control 110 to control the phase of the reference
frequency on line 119.
- 24 -
~ o7~7 :~ :
~t the end of each data inte~yal timin~ contxol 110
uses the shift clock on line 118 to shift the received data
bit from demodulator 104 into data register 106 via data con-
trol 105. At the beginning of each bit period the first
eight bits of data register 106, carried by part of line 132,
are compared to the preset synchronization code by synchron-
ization code comparator 111. When these are identical, a
signal is sent to timing control 110, via l:ine 121, which
starts a bit counter. After twanty more bits have been ;
received and shifted into data register 106, the first six-
teen bits of data register, carried by part of line 132, are ;
compared to the preset meter module address and hot water
control address by comparators 113 and 112, respectively, the
last four bits of data register 106, carried by part of line
132, are transferred to function code register 11~, and re-
ceive switch 102 is inhibited. The shit clock on line 118 assu~es the
~! .
fre~cy indicate~ by function code bit Fo on line 124.
If meter module address comparator 113 detects a
match, function decoder 115, modulator 107 and the meter
data input to data control 105 are all enabled via line 126.
The meter module address and function code contents of data
register lC6 are shifted to distribution transformer second-
ary 24 via line 128, modulator 107, transmitter lOa and
coupling network 109, while the contents of the meter encoder
that is enabled by function decoder 115, such as the electric
meter encoder via line 26, are shifted into data register
106 via line 129 and data control 105. After the twenty
meter data bits, are shifted into data register 106, its
contents are recirculated via line 133 and data control 105,
which logically inverts the meter data. Data recirculation
- 25 -
~Ci 7~)7~7
: '
through data control 105 is en~bled by timing control 110
enable signal on line 120. After the 60-bit reply message
has been transmitted, receive s~itch 102 is enabled via line
117~ and sync code and meter module address comparators,
111 and 113, respectively, are reset via line 123, thereby
inhibiting modulator 107, meter data inputs to data control
105 and resetting function decoder 115. Transponder 12 then
resumes searching the received data for a synchronization
code match. ~ -
If hot water control address comparator 112 de-
tects a match after a synchronization code match is detected,
the function code bits carried by line 127 are strobed into
hot water control 116, thereby turning the hot water heater
on via line 134 or off via line 134l, or controlling the peak
demand meter via lines 140 and 140'. Modulator 107 is not ;
enabled since no reply message is to be transmitted. After
a period of time equal to that needed for a reply at the
rate indicated by function code bit Fo on line 124, receive
switch 102 is enabled via line 117, and synchronization code
comparator 111 is reset via line 123. Hot water control 116
is not reset, thereby enabling the control function to be
maintained until a further hot water control instruction is
received. Transponder 12 then resumes searching the received
data for a synchronization code match.
If neither a meter module address nor hot water
control address i5 detected by comparators 113 and 112, re-
spectively, after a synchronization code match is detected
by comparator 111, no control action is initiated nor reply
transmitted. Timing control 110 waits a period of time
equal to that needed for a repl~ at the rate indicated by
- 2~ -
~ ~37~7 ti7 ~
function code hit Fo on line 124, then enables receive switch
102, via line 117, and resets synchronization code comparator
111 via line 123.
An exemplary electric meter 15 and encoder 13
are shown in FIG. 6. The electric watt-howr meter 15, such
as General Electric Co. Model No. 150S, drives revolution
contactor, such as General Electric Co. Model R12/125, which
drives relay 176, such as General Electric Co. Model 731X2G6,
whose contacts close for a short period of time after each
100 watt-hours of consumption has been logged by watt-hour
meter 175. The relay contact closure increments counter
177, which may consist of 4 binary coded decimal counter
stages, such as Hayden Switch Model 42410-10. The parallel
outputs of counter 177 are connected to the parallel inputs
of shift register 178, which may consist of parallel input
serial output shift register stages such as RCA CD4034A.
When a meter transponder is not being interrogated the meter
select signal, line 26, inhibits the A bus and serial oper-
ation of shift register 178, thereby allowing the parallel
outputs of counter 177 to continuously update the contents
of shift register 178. During a meter transponder interro-
gation the meter select signal, line 26, enables the A bus
and serial mode of operation, thereby allowing the contents
of shift register 178 to be shifted to meter transponder 12,
via line 129, in a serial manner in response to the shift
clock transistions on line 118. It is preferred that en-
coder 13 include a non-volatile memory element, such as
Hayden Switch Moael 42410-10, to avoid the loss of meter
data in the event of a power failure. Furthermore, while
the Hayden Switch Model 42410-10 has 4 BCD stages it is
obvious that a fifth stage can be added; that is preferably,
- 27 -
~ ~37~7~7
since many utilities are up-gr~ding their meter equipment to
5 dial meters.
When peak demand metering is desired, another meter
encoder, such as 13"', can be connected to the same power
meter with the signal from watt-hour meter 15 connected to
meter encoder 13" " through relay 32 which is con-trolled by ;~
transponder 12. When it is desired to log power consumption
on the peak demand meter encoder, relay 32 contacts are
commanded closed via line 140 from transponder 12. When it
is desired to stop logging power consumption on -the peak
demand meter relay 32, contacts are commanded open via line -~
140' from transponder 12.
FIG. 7 illustrates the typical noise that is
present on a power distribution feeder, such as 21 of FIG. 1,
and shows that the amplitude envelope o the 60-Hz power
distribution frequency harmonics is about 1000 times larger
than random noise between 1 and 10 kHz. This would suggest
a communication carrier frequency selection in the low noise
region above lOkHz.
However, most distribution feeders have power
factor correction capacitors connected to them to enable the
utility to meet economic ànd quality-of~service constraints.
Furthermore, the distribution feeders have series inductance
and stray capacitance to ground, the exact values of which
depend on distribution feeder construction and length. There-
fore, distribution feeders have a low pass transmission
characteristic as a result of these reactive components. A
network analysis, confirmed by distribution feeder signal
transmission measurements, shows the half-power cutoff frequ-
ency to lie at about lkHz when the power factor correction
capacitors are connected to a typical distribution feeder;
- 28 -
:, . .. ~,. ;.
~7~7
this is illustrated in FIG. 8A. ~hen the po~er factor
correction capacitors are disconnected ~xom the distribution
feeder, the half~power cutoff frequency is determined by
the distribution feeder series inductance and stray capacitance
to ground and lies between 10 and 20 kHz as illustrated in
FIG. 8B. Furthermore, a remote meter reading and control
system will consist of a large quantity of meter and control
modules located throughout a power utility's franchised
service area, and it is impera~ive that these units be low
cost. Economic factors preclude the use of high-power,
high-frequency transistors and highly selective filters.
Therefore, it is advantageous to select a communication
carrier frequency in the range between 5 and lO kHz so the
system will operate in the region of low harmonic noise
and low signal transmission loss, and to utilize a technique
for communicating between central control unit 5 and meter
module 11 or control module 9 that will discriminate against
the 60Hz power distribution frequency harmonics.
In order to operate the system in range between 5 -
and 10 kHz, it is necessary to overcome the deleterious
effects of the power factor correction capacitors. The
preferred method is to insert a capacitor isolation network
in series with each power factor correction capacitor as
shown in FI5. 9A, or in parallel with each power factor correc-
tion capacitor as shown in FIG. 9B. ~ith reference to FIG. 9A,
the capacitor isolation network, consistlng of inductor 32 and
capacitor 33, in inserted in series with power factor correc-
tion capacitor 23'. Inductor 32 and capacitor 33 are tuned to
anti-resonance at the communication carrier frequency. Line
21A' is the high voltage distribution feeder, and line 21A" is
- 29 -
.~
7~7
the distribution feeder neutral.
~ith ~eference to FIG. 9B, the capacitor isolation
network, consisting of inductor 32' and capacitor 33', is
installed in parallel with power factor correction capacitor
23". Inductor 32' is tuned to anti-resonance with the par-
allel combination of capacitors 33' and 23" at the communic
ation carrier frequency.
An alternative method of overcoming the effects of
power factor correction capacitors on signal transmission
consists of signalling the control modules, such as 9A, to
disconnect the capacitor.
An advantageous communication technique is phase
shift keying since a unique choice of parameters enables this
method to act as a highly-selective filter and discriminate
against the 60Hz power distribution frequency harmonics.
This techinique is incorporated in the preferred embodiment,
wherein the received communication carrier signal is demodul-
ated by a phase detector whose output is integrated for a
period of time T corresponding to one baud and then reset.
The integrator output Eo at the end of the in-
tegration period T represents the received energy detected
by the system during the period T and can be written as:
~O SO ein(t) eref(t) dt (1)
where the demodulator reference signal eref(t) can be written
as:
eref(t) = Ar sin wr
The phase detector input ei (t) consists of the communication
carrier signal eC(t), each power distribution frequency har-
- 30 -
~C~7~7~7
monic ehp(t) and random noise en~t~ of uniform ener~y spectxal
density No~2 watts per Hz where each o~ these can be written
as:
eC(t) = Ac sin ( wct + ~c ) (2)
ehp(t) = Ahp sin ( whpt ~ ~h )
The demodulator reference frequency is identical to the
communciation carrier, so the detected energy for this signal
is written as:
Eoc = A Ar c ~c (4)
By phase locking the reference frequency to the received commNnication car-
rier signal the phase difference between the ~o signals ~ can be made
arbitrarily small, and the detected energy can be made to approach the max-
imum value of ArACT/2. The detected ener~y in response to a power distrib-
ution frequency harmDnlc ehp(t) can be written as-
ohp ~ ~sin[(wr-whp)T ~ ~hp~ + sin ~hp -
sin[(Wr + Whp)T ~ ~hp~ sin ~hp l (5)
~Wr + whp)T _
where Whp = 2 ~(60P) and P is an integer defining the power
distribution frequency harmonic under consideration. In
the preferred embodiment the communication carrier frequency
is selected to be an odd multiple of 30-~Iz, half the power
distribution frequency. The demodulator reference frequency
~ 31 -
~7~37~7
can then be written as:
Wr = 2~r(2m -~ 1)30 (6)
where m is an integer defining thP odd multiple of 30-Hz used
for data communication. It is also advantageous to select
baud rates that are sub-multiples of the power distribution
frequency, such as 30 or 15-baud, corresponding to integration
periods T of 1/30 or 1/15 seconds, respectively. For this
unique selection of parameters the detected energy Eohp is
exactly equal to zero for any value of P and ~hP~ thereby
discriminating against the 60-Hz power distribution frequency
harmonics. If a 60-baud rate is selected, corresponding to
an integration period T of 1/60 second, the detected energy
E hp can be written as:
EOhp = ~ p hp [1 _( 2P )2 ~ 1 (7)
For this case the phase detector-integrator demodulator acts
as a bandpass filter centered on the communication carrier
frequency discriminating against the 60-F~z harmonics to the
extent each harmonic is separated from the communication
carrier; i.e., that 2P is greater than 2m + 1, and can to-
tally discriminate against a harmonic if ~hp is an integral
multiple of ~ radians.
With respect to the random noise en(t) the integr-
ator acts as a low-pass filter and discriminates against the
random noise components that are outside the signal bandwidth.
Therefore, the average detected power due to random noise
can be written as:
- 32 -
. . .
! ~
,' , ' ,' ' ' " " ' ' ; ~"
.
~ ~7~17~7
.
P = ~on A N
on T 2T (8)
The signal-to-noise ratio at the integrator output for
data rates that are sub-multiples of 60-baud, such as 30
or 15-baud, is obtained by comparing the signal power to
noise power and can be written as:
SNR ACT cos ~c (9
No
Which increases as the baud rate decreases, thereby de-
creasing the probability of bit error. For a 60-baud data
rate the 60Hz harmonic noise power is much larger than the
random noise power and the signal to noise ratio can be
written as:
SNR [ A cos ~c ~ (10)
~ ~ (2m + 1)
P=PL
where Pu and PL are defined by the upper and lower cutoff
frequencies of the frequency selective filter that precedes
the demodulator.
While expression 10 is smaller than expression 9,
a 60-baud data rate is advantageous to use in situations
where a 60-baud data throughput is desired and the resulting
bit error probabilities are acceptable.
The odd harmonics of the power distribution fre-
quency have been measured -to be 10 to 100 times larger in
amplitude than the even harmonics, thus another advantagous
- 33 -
~7~7~7 : :~
selection o~ communication carrier frequency is an even har~
monic of the po~er distribution frequency. The demodulator
reference frequency can then be written as:
Wr = 21~(2Q)60 (11)
where Q is an integer defining the even multiple of 60 Hz
used for data communication. The detected energy in response
to the communication carrier is identical with expression 4.
The power distribution frequency harmonic at the communlcation
carrier frequency can be written as:
EhC (t) = Ahc sin (Wrt + ~hc) (12) ~ '
and the detected energy in response to this harmonic can be
written as:
Eohc = r hc _ cos ~hc (13)
The detected energy Eohp in response to any other harmonic of
the power distribution frequency is given by expression (6)
and is exactly equal to zero for any value of P and ~hp'
thereby discriminating against these harmonics. Since the
signal power of the power distribution harmonic at the comm-
unication caxrier ~req~ency is much larger than the random
noise power, the signal to noise ratio can be written as:
SNR _ AcCs ~ c (1~)
hc hc
;;
and is independent of ~aud rate. Expression 14 may be small-
er than expression 9, thereby yielding a higher probability
of bit error. However, the se-t of parameters defined by
expressions 11 through 14 are advantageous to use in situat-
ions where a 60 baud data throughput is desired and the re-
sulting bit error probabilities are acceptable. -~
- 3
~7~7t;7
It is also within the principles of the invention
to use other communication techniques such as frequency shift
keying or amplitude modulation.
In the preferred embodiment of the invention central
control unit 5 transmits data to meter module 11 and control
module 9 at 30 baud, and the modules reply at 30 or 15 baud.
However in situations where higher bit error probabilities
are acceptable and higher date throughputs are desired, it is a~-
vantageous to have central control unit 5 transmit data to
meter module 11 and control module 9 at 60 baud, and the mod-
ules reply at 60, 30 or 15 baud. For this situation central
control unit 5 transmitter output power may have to be in-
creased to obtain acceptable error rates and an odd harmonic
of 30-Hz, defined by expression 6, should be used for the
communication carrier frequency, thereby permitting central
control unit 5 demodulator to discriminate against the power
frequency harmonics when the modules are replying at 30 or
15 baud.
Measurements on power distribution feeders have
shown the power line frequency has variations as large as 3
from the nomir~al 60-Hz. Therefore, it is advantageous to
derive the transmitter communlcation carrier, demodulation
reference carrier and data bit timing from the power distrib-
ution frequency so the previously defined relationships bet-
ween parameters remain constant and the demodulation results ~:
remain valid. Measurements on power distribution feeders
have also shown the communication carrier phase can varymore than 50 in a six minute period. Therefore, it is
advantageous to phase lock the ~arious demodulator reference
- 35 -
~L~7~7~7
oscillators to a signal obtained from the unit that is trans~
mittin~.
The preferred embodiment incorporates the prin-
ciples developed above to eliminate the neecl for costly items,
such as highly selective filters and high power transmitters
in the transponders. Referring again to
FIG. 1, between interrogations of meter module 11 or control
module 9 central control unit 5 transmits a pilot tone,an
unmodulated communication carrier, with sufficient signal
strength to be detected by all transponders 12 connected to
distribution feeder 21 being driven by the central control
unit 5 transmitter. The transponders 12 connected to distri-
bution feeder 21 receive the pilot tone and phase lock their
reference carrier oscillators to this central control unit 5
signal, thereby making the previously defined phase angle ~c
arbitrarily small. ~fter a period of time, sufficient for
all transponder 12 reference oscillators to have achieved
phase lock, central control unit 5 transmits data to trans-
ponders 12 at a fixed rate of 30 baud by phase-shift modul-
ating the communication carrier. It is advantageous to usea modulation deviation of ~90 degrees to represent a logic
one and -90 degrees to represent a logic zero as this devia-
tion provides the least probability of bit error for a given
signal-to-noise ratio. The transponder 12 that is interrog- ;
ated replies at the instructed data rate, such as 30 or 15
bits per second. Transponders 12 do not transmit a pilot
tone to central control unit 5, which instead demodulates
the transponder transmission by using four parallel phase
sensitive demodulators that have their reference carriers
separated in phase by 45 degrees. After receiving the first
- 36 -
' ''' ' ' : ' '' '
~7~7~7
bit o~ transmission ~rom transponder 12, central control unit
5 scans the ~our demodulator outputs and selects the demodul-
ator output with the maximum absolute amplitude, and there-
fore, minimum phase angle separation ~c from transponder 12
communication carrier. The demodulator polarity is obtained
by comparing the received bit polarity with the expected
polarity of the ~irst bit, which is function code bi-t Fo~
This demodulator polarity is used for detec-tion of the re-
mainder of the transponder transmission.
The ability to use different transponder bit rates
permits the system to use low-power transponder transmitters
and automatically adapt the transponder kransmission commun-
ication channel to varying a signal-to-noise ratios while ob-
taining maximum system data throughput.
Exemplary embodiments of central control unit mod-
ulator 39, demodulator 53 and timing control 47 are shown in
FIG. lO using logic elements of the RCA CD4000A series with
key timing relationships presented in FIGS. ll through 16.
The central control unit communication and reference carriers,
and a synchr~nous data interface clock are developed in a
phase-lock loop using the 60 Hz power distribution frequency
as the source via the utility bus, line 62, or the switched
bus, line 61. The sinusoidal signals on lines 61 and 62 are
squared using zero crossing detectors 200 and 201 which are
National Semiconductor LM139 voltage comparators. If a
signal is present at the output of zero-crossing detector 201,
such as when relay contact 63, 63' or 63" is closed, retrig-
gerable monostable multivibrator 202, which is a CD~047A, is
continuously triggered enabling NAND gate 204 and inhibiting
- 37 -
:: ;
~i7~7~7
NAND gate 204', thereby selectiny the switched ~us signal as
the timing reference for the central control unit. If no
signal is present on the switched bus, line 61, such as when
relay contacts 63, 63' and 63" are all open, retriggerable
monostable multivibrator 202 remains in its stable state, in-
hibiting N~ND gate 204 and enabling N~ND gate 204', thereby
selecting the utility bus signal as the timing reference
for the central control unit. The basic 30-Hz baud rate
clock is obtained from the 60-Hz output o OR gate 205 via
exclusive OR gate 239 and divider 208. The polarity of the
60 Hz signal used to click divider 208 is selected by clock
phase bit P on line 69''' via flip-flop 219 and exclusive OR
g~te 2 39.
The communication and reference carriers and ~~
synchronous data interface clock are developed in a phase- ~
locked loop oscillator circuit consisting of phase-locked ;
oscillator 206, which is a CD 4046A, dividers 207, 207' and
207", which are CD4029A, and various NAND gates, shift reg-
ister 210 which is a CD4015A and inverter 209. The output
frequency of phase-locked oscillator 206 is 50,160--Hz,which
is eight times 6270-Hz, an odd multiple of 30-Hz. The 50,160-
Hz signal is divided down by the appropriate factors in di-
viders 207, 207' and 207", in this instance the division is by
11, 4 and 9, repectively. The output frequency of divider
2û7, is 4560-Hz, which is sixteen times the 285 baud data
transmission rate between central control unit 5 and data
asquisition computer 4, while the output of divider 203 is
the data transmission rate, 285-~Iz. This method of develop-
ing the asynchronous data interface clock avoids the necess-
ity of using a crystal stabilized oscillator in each central
control unit. The output of divider 207" is fed back to
- 38 -
7~317~7
phase-locked oscillator 206 for compa~ison W.ith the selected
60-Hz power distribution frequency signal ~rom OR gate 205,
thereby closiny the phase-locked loop. The output of phase-
locked oscillator 206 clocks shift register 210 to develop
four 6270-Hz signals separated in phase by 45 degrees. The
timing relationship between the phase-locked loop oscillator
output and the four shift register output signals is illust-
rated in FIGS. llA through llE, which shows that the shift
register third stage output, FIG. llD, lags the first stage
output, FIG. llB, by 90 degrees. Therefore, the third stage
output is used for the unmodulated communication carrier, and
the first stage output or its inverse is used for the modulated
carrier.
As previously mentioned, after a byte of data is
received by data receiver 36, it sets a Data Ready flag, FIG.
12~, to the timing control 47 via line 66. The signal on
line 66 is clocked into shi~t register 211, which consists
of CD4013A flip-flops, by the asynchronous data interface
clock on line 64, shown in FIG. 12A. The first clock trans
ition on line 64 after the Data Ready flag is set changes
the state of the first stage of shift register 211, FIG. 12C,
which triggers monostable multivibrator 214, which is a
CD4047~, whose output, FIG. 12J, was resetting shift register
212, which consists of CD4013A flip~flops, to the 100 state
as shown in FIGS. 12E, 12F, and 12G. Before the next clock
transition on line 64 the output of the first stage of shift
register 212, FIG. 12E enables the A bus of the first eight
bits of input register 37 via line 71, thereby transferring
data from data receiver 36 to input register 37.
The second clock transition on line 64 after the
- 39 -
~L~7~7~7
Data Ready flag is set changes the $tate o~ the secQnd stage
of shift register 211, FIG~ 12D, which resets the Data Ready
~lag via inverter 213 and line 65, and clocks shift register
212 to the 010 state,thereby clocking -the b:it P on line 69'''
into flip-flop 219, which is a CD4013A. The next two clock
transitions on line 64 return shift register 211 to its or-
iginal state. The second byte of data from data receiver 36
is loaded into the second eight bits of input register 37 by
the second Data Ready flag and the A bus enable signal from ;
the second stage of shift register 212 via line 71', FIG. 12F,
and the third data byte is loaded into the third eight bits
of input register 37 by the third Data Ready flag and the A
bus enable signal from the third stage of shift register ~ :
212 via line 71", FIG. 12G. After the third data byte is ~.
loaded into input register 37, NOR gate 215 output, FIG- 12HI ~ .
enables NAND ga~es 217 and 217', thereby permitting second
stage of shift register 211 to issue a cycle-initiate strobe
signal, FIG. 12I, on either line 220 or 221, depending on .
contents of the command mode control bit on line 69 and
central control unit address bits A16 and A17 on line 69'.
If the central control unit address bits from in-
put register 37 on line 69' match the preselected central
control unit address, decoder 216, which is a CD4051A, enables
NAND gates 217 and 217'. If the mode control bit on line 69
is a logic 1, indicating a meter transponder interrogation
cycle is desired, NAND gate 217 is enabled, thereby yielding
an interrogation cycle initiate strobe on line 220. If the
mode control bit on line 69 is a logic 0, indicating a com-
mand cycle is desired, NAND gate 217' is enabled via inverter
218, thereby yielding a command cycle initiate strobe on
line 221.
-- ~0 --
~L~7~7~7
At the end of a preset interval, long enough fox
three data bytes to be received from data ac~uisition computer
4, monostable multivibrator 214 returns to its stable state,
resetting shift register 212 to the 100 state. Thus, mono-
stable multivibrator 214 returns the central control unit to
a known state at periodic intervals, thereby overcoming the
problems associated with false data loading due to a noisy
communication line, such as 10, or Data Ready line 66.
If the mode control bit on line 69 is logic 0,
indicating a command cycle is desired, the cycle intiate
strobe from NAND gate 217' on line 221, FIG. 13A, triggers
monostable multivibrator 224, which is a CD4047A. If the
command execute enable bit P, stored in flip-flop 219, is
logic 1 AND gate 223 is enabled, and the signal from NAND
gate 217' on line 221 enables the A bus of command register
43 via line 78, thereby loading the command bits from input
register 37 into command register 43. If bit P, stored in
flip-flop 219, is logic 0, AND gate 223 is inhibited and
the contents of input register 37 are not loaded into com-
mand register 43. After a period of about 1 second, mono-
stable multivibrator 224 returns to its stable state, FIG. 13B,
thereby clocking flip-flop 225, which is a CD4013A. At the
next 285-Hz clock transition on line 99, FIG. 13D, flip-flop
226, which is a CD4013A, changes state, thereby removing
the reset level from counters 227, 227' and flip-flop 232,
enabling the statusregister A bus outputs and serial mode of
operation via line 81, FIG. 13E, and enabling NAND gate 229
via line 233. The command cycle is therefore synchronized to
the 285-Hz clock on line 99 by the output of flip-flop 225,
FIG. 13C, controlling the state of ~lip-flop 226. Counters
- 41 --
~1137~7~7 ~
227 and 227', which are CD4029A~ are incre~ented b~ the 285-
Hz clock on line 99, and the outpu-ts of ~counter 227 are
sampled by decoder 228, which is a CD4028A. When counter
227 is in the 0 state, decoder 228 enables NAND gate 229,
thereby sending a transmit strobel FIG. 13F, to data trans- -
mitter 55 via OR gate 230, inverter 231 and line 85. Since
the 285-Hz clock on line 99 is also shifting the contents
of status register 44 during this period, the status register
contents are transmitted to data-acquisition computer 3 as
eight data bytes. After the sixty-fourth transition of the `
285~Hz clock on line 99, the output of counter 227' clocks
flip-1Op 232, which is a CD4013A, thereby setting flip-flops
225 and 22~, via line 234, FIG. 13G, to their original
state, which inhibits the status register A bus outputs and
returns the status register to the parallel mode of operation,
all via line ~1, FIG. 13E, terminating the command cycle.
The signal on line 81 also resets counters 227 and 227' and
flip-flop 232, while the transmit strobe on line ~5, FIG. 13F,
is inhibited by the signal from flip-flop 226 on line 233.
If the mode control bit on line 69 is a logic 1,
indicating an interrogation cycle is desired, the cycle in-
itiate strobe from NAND gate 217 on line 220, FIG. 14A, clocks
function code bit Fo on line 69" into flip-flop 222, which
is a CD4013A, and also clocks flip-flop 240, which is a CD4013A,
whose output, FIG. 14B, is clocked into flip-flop 241, which
is a CD4013A, by the next transition of the 30-~z clock on
line 70, FIG. 14D, thereby synchronizing the interrogation
cycle to the 30-Hz. clock. The change in state of fIi~flop
241 on line 242, FIG. 14C, removes the reset from counter 243
and the set from flip-flop 244, inhibits the pilot-tone enable
on line 74, FIG. 14G, via line 246 and NAND gate 245, and
~ - ~2 -
~7~7~7
changes input register 37 and sync code xegister 33 to the
serial mode of operation via line 72. The data contained in
input register 37 and sync code register 38 is then shifted
to modulato~ 39 at the rate of 30 bits per second by the 30-Hz
clock on line 70, FIG. 14D. After the 28 bits of data, re-
presenting the sync code, the function code and module address
are transmitted to the meter or control modules, coun-ter 243,
which is CD4029A, and ~arious NAND gates, clocks flip~flop 244,
which is a CD4013A, thereby inhibiting the transmit enable
signal and removing the demodulator phase scan reset signal
via line 75, FIG. 14E, removing the demodulator integrator
reset signal via line 247, OR ga-te 264 and line 93, enabling
the output register clock output from OR gate 248 and A bus
enable gate, line 88 via line 75 and inverter 2~9, and enab-
ling the demodulator reset strobe via line 247. The signal ;~
on line 75, FIG. 14E, also serves to synchronize the 15-Hz
clock from divider 250, which is a CD4013A, to the 30-Hz clock
since its reset signal on line 75 changes state on a 30-~Iz
clock transition. The output register clock frequency is
selected by flip-flop 222. If the function code signal on
line 69" indicated the module is to reply at 15 baud, NAND
gate Z52 is enabled and NAND gate 253 is inhibited. If
the function code signal on line 69" indicated the module
is to reply at 30 baud, NAND gate 252 is inhibited and NAND
gate 253 is enabled. At this -time NAND gates 252 and 253
are also enabled by the signal from flip-flop 254, which is
a CD4013A, via inverter 255 and line 256, while NAND gate
257 is inhibi~ed by the signal on line 256. The output re-
gister clock from OR gate 248, line 258, FIC-. 14F, triggers
monostable multivibrator 259. The first pulse from monostable
- 43 -
~7~7
multivibrator 259, line 89, FIG. 14H, initiates the demodula~
tor phase scan via N~ND gate 261 and line 92~ The trailing .
edge of the signal from monostable multivibrator 259, line ~:
89, FIG. 14H, increments counter 262, shifts the contents of ; .
output register 54 one bit position, and triggers monostable .
multivibrator 263, which is a CD4047A, whose output resets
the demodulator integrator via OR gate 264 and line 93. The
trailing edge of the signal from monostable multivibrator
259 on line 89, FIG. 14H, also clocks flip flop 260, thereby
inhibiting NAND gate 261 and preventing further demodulator ~;
phase scans during the remainderof this interrogation cycle.
The output pulses from monostable multivibrator 259 on line
89, FIG. 14H, shift the contents of output register 54 and
reset the demodulator integrator until counter 265l which is
a CD4~29A, overflows, indicating 64 bits of data have been
received from the interrogated module and loaded in output
register 54. The overflow signal from counter 265 clocks
flip-flop 254 thereby inhibiting the 30-or 15-Hz clock from
NAND gates 252 or 253, enabling the 285-Hz clock from NAND
gate 257, all via line 256, FIG. 14K, enabling NAND gate 266,
and strobing the mode control and central control unit address
bits into output register 54"" via monostable multivibrator
269 and line 95. This corrects the contents of output reg-
ister 54, since the last four bits received by the demodula-
tor represent noise rather than data from the interrogated
module. At this point counters 262 and 265 are in the zero
count state, so decoder 267, which is a CD4028A, also enables
NAND gate 266, allowing the next pulse from multivibrator
259 on line 268 to send a transmit strobe to data t:ransmitter
55 via NAND gate 260, OR gate 230, lnverter 231 and line 85,
FIG. 14L.
- 44 -
~7~7~7
Counters 262 and 265 are incremented b~ the trai
ing edge o~ the pulses from monostable multivibrator 259 on
line 89 t FIG. 14H. Each time counter 262 is incremented to
-the 000 state a transmit strobe is sent -to data transmitter
55. When counter 265 overflows, indicating eight transmit
strobes have been sent, and the 64 bits of data in output
register 54 have been transmitted to data-acquisition computer
4, flip-flop 270, ~hich is a CD4013A, is clocked, FIG. 14M,
thereby resetting ~lip-flops 240 and 241, returning items 243,
244, 262, 265, 254, 270 and 260 to their original sta~e and
terminating the interrogation cycle.
When data is not being transmitted to, or received
from, a meter or control module, modulator 39 transmits an
unmodulated carrier to power ampli~ier 40. During this period
NAND gate 287 is enabled by the transmit enable signal on
line 75, NAND gate 280 is enabled by the pilot-tone-enable
signal on line 74, and NAND gates 281 and 282 are inhibited
by inverter 283 and the signal on line 74. Thus, the signal
on line 73", the unmodulated 6270-Hz carrier, is sent to
power amplifier 40 via NAND gates 280 and 287 and OR gate 286.
When data is to be transmitted, NAND gate 280 is inhibited
by the signal on line 75, and N~ND gates 281 and 282 are en-
abled by inverter 283 and the signal on line 75. If the data
to be transmitted on line 58 is logic 1, NAND gate 281 is
enabled and NAND gate 282 is inhibited by inverter 287, there-
by sending the 6270-Hz signal (that leads the 6270--Hz signal
on line 72" by 90 degrees) on line 73 to power amplifler 40
via NAND gates 281 and 287 and OR gate 286 I~ the data to
be transmitted on line 58 is logic 0, NAND gate 281 is inhib-
ited and NAND gate 282 is enabled by inverter 287. The
- 45 -
~C~7 ~ 7 ~7
signal on line 73~ inverted by inverter 284, becomes a 6270-Hz signal that
lags the 6270-Hz signal on line 73" by 90 degrees and is sent to power
amplifier 40 via NAND gates 282 and 287, and OR gate 286.
When data is to be received, -the modulator is inhibited by the
transmit enable signal, line 75, and NAND gate 287.
The video signal from video amplifier 52 on line
96 is sampled in parallel by four phase detectors 300, 300',
300" and 300'''. Each phase detector uses a receive carrier,
on line 73, 73', 73", and 73''', respectively, that is sep-
arated by 45 degrees to demodulate the video signal on l:ine
96. Item 300' is a typical phase detector and comprises
amplifier 315, which is a Fairchild Semiconductor 741, resis-
tors 316, 316', 316", 316''' and 316'' ", switches 314 and
314', which are CD4066A and are driven 180 degrees out of
phase w.ith each other by the 6270-Hz carrier on line 73', and
inverter 313. The operation of this phase detector is de-
scribed by J. N. Giles, Linear Integrated Circuits Applications
Handbook, Library o:E Congress Catalog 57-27446.
The outputs of the phase detectors are integrated
by integrators 301, 301', 301", and 301'''. Item 301' is a
typical integrator and comprises amplifier 318, which is a
Fairchild semiconductor 741, resistor 317, capacitor 319 and
switch 320, which is a CD4066A. At the end of each bit period
capacitor 319 is discharged by switch 320, via the integrator
reset signal on line 93. The integrator outputs are connect-
ed to signal bus 324 by switches 302, 302', 302" and 302'''
and to signal bus 325 by switches 303, 303', 303" and 303'l'.
Switches 302 ana 303 are CD4066A. Switches 302, 302', 302''
and 302'l' are controlled by shift register 311 via lines 327l -
327', 327'' and 327''', respectively, while switches 303, 303'
and 303'' are cont.rolled by shift register 310 via lines 326, 326',
~ ~6 _
~7~ 7
and 326'', respectivel~. The absolute ma~nitude of the signals
on lines 324 and 325 is produced by absolute magnitude cir-
cuits 304 and 304', respectively. ~ typical absolute magni-
tude circuit 304 comprises amplifier 321, which is a Fairchild
semiconductor 741, diodes 322, which are IN914, and resistors
323, 323', 323'' and 323''l. While data is being transmitted
from central control unit 5 to a meter transponder, integra-
tors 301, 301', 301'' and 301''' are reset by line 93, FIGS. 16W
and 14I, while shift registers 310 and 311, which are CD4034A,
are held in the parallel mode and flip-flop 312, which is a
CD4013A, is set by line 75, FIGS. 16A and 14E. This loads
1000 into shift register 310 as shown in FIGS. 16I, 16J,'16K
and 16L, and enables the A bus of shift register 311, via
line 328, FIG. 16G, thereby allowing the contents of shi~t
register 310 to be loaded into shift register 311 via lines
326~ 326', 326'' and 326'''. The shift register 311 assumes
the 1000 state as shown in FIGS. 16M, 16N, 16P and 16Q.
After data is transmitted to the meter transponders,
the phase scan reset on line 95, FIG. 16A, and the integrator
reset on line 93, FIG. 16W, are removed and integrators 301,
301', 301'' and 301''' integrate the signals from phase de-
tectors 300, 300', 300'' and 300''', respectively. At the end
of the received data bit period flip-flop 306, which is a
CD4013A, is clocked, FIG. 16C, by the phase-scan-initiate
signal on line 92, FIG. 16B. The next transition of the 6~70-
Hz clock on line 73''', FIG. 16D, clocks flip-flop 307, which
is a CD4013A, thereby synchronizing the phase scan to the
6270-Hz clock. Flip-flop 307 output, FIG. 16E, enables NAND gate
308, whose output clocks shift register 310 via line 329,
FIG. 16F, and flip-flop 312, which is a CD4013A, via invert-
er 309.
- ~7 -
~7~7~7
The a~gorithim used fox the phase sca~n is to
load shift registe~ 311 with the contents o~ shift ~egister
310 if the magn~tude of the signal on line 324 is less than
the ma~nitude of the signal on line 325 and to freeze the
contents of shift register 311 if the reverse is true, all
the while shifting shift register 310. At the start of the
phase scan shift registers 310 and 311 each contain 1000,
thereby enabling switch 302 via line 327, FIG. 16M, and
switch 303 via line 326, E`IG. 16I.
FIG. 16 illustrates the case where the signal mag-
nitude from inte~rator 301 on line 324 is less than -that from
integrator 301', on line 325, thus the output of differential
comparator 305, which is a National Semiconductor LM139, is
high as shown in FIG. 16H, and the negative-going transition
on line 329, FIG. 16F, clocks an A bus enable signal into
flip-flop 312, as shown in FIG. 16G, thereby allowing shift
register 311 to be loaded from shift register 310.
The positive going transition on line 329, FIG. 16F,
shifts the contents of shift registers 310 and 311 to the
0100 state enabling switch 302' via line 327', FIG. 16N, and
switch 303' via line 326, FIG. 16J. FIG. 16 illustrates the
case where the signal magnitude from integrator 301l on line
324 is greater than that from integrator 301'' on line 325,
so comparator 305 output, FIG. 16H, is low and the next neg-
ative-going transition on line 329, FIG. 16F, clocks an A
bus inhibit signal into fiip-flop 312 as shown in FIG. 16G,
thereby freezing the contents of shift register 311.
The positive-going transition on line 329, FIG.
16F, shifts the contents of shift register 310 to the 0010
state, while shift register 311 remains in the 0100 state,
thus, switch 302' remains enabled via line 327', FIG. I6N,
- ~8 -
~7i[~7~
and switch 303" is enabled Via line 326"~ FIG.. 16K. FIG. 16 . ~ :
illustrates the case where the $i~nal magnitude from inte- .
grator 301' on line 324 is less than that from integrator 301'''
on line 325, so comparator 305 output, FIG. 16H, is high and
the next negative-going transition on line 329, FIG. 16F,
clocks an A bus enable signal into flip-flop 312 as shown in
FIG. 16G, thereby allowing shift register 311 to be loaded
from shift register 310.
The positive going transition on line 329, FIG. 16F,
shifts the contents of shift registers 310 and 311 to the 0001
state, thereby enabling switch 302''' via line 327''', FIG.
16Q, and setting ~lip-flops 306 and 307 which terminates the
phase scan, and triggering monostable multivibrator 330, which
is a CD4047A, both vial line 326, FIG. 16L. The output of in-
tegrator 301''', via switch 302''' and line 324, is compared
to ground by differential comparator 331, which is a National
Semiconductor LM139, whose output is logic 0 if the signal on
line 324 is negative and logic 1 if the signal on line 324 is .~ :
positive.
Exclusive OR gate 333 compares the logic level out- .
put of differential comparator 331, FIG. 16S, to the logic
level o the first expected bit, which is function code bit
F~, via line 91. If the inputs to exclusive OR gate 331 are .
identical, logic 0 is clocked into flip-flop 332 by monostable
multivibrator 330, FIG. 16R. If the inputs to exclusive OR
gate 333 are opposite, a logic 1 is clocked into flip-flop
332, which is a CD4013A.
The polarity level from flip-flop 332, FIG. 16T,
is compared to the signal from differential comparator 331
by exclusive OR gate 334 and sent to output register 54 via
line 90, FIG. 16U. The selected integrator and polarity
- 49 -
~Ot7~7~
level are used to receive the rem~inder of the inte~xogated
module message until reset by the phase scan ~eset si~nal,
line 75, FIGS. 16A and 14E, and polarity clock pulse, FIG. :
16R, during the next interrogation cycle. The output reg-
ister shift clock and demodula-tor integrator lines 89 and
93, FIGS. 14H and 14I, respectively, are shown for reference
as FIGS. 16V and 16W, respectively.
~ xemplary embodiments of input register 37 and sync code
register 38, command register 43, status register 44 and output reyister
54 using logic elements of the RCA CD4000A series are shown
in FIGS. 17, 18, 19 and 20, respectively. With reference to
FIG. 17, the input register and sync code register comprises
CD~034A eight-bit registers, operated in the asynchronous
mode with A bus data input and B bus data output and are
normally operated in the parallel mode. The first data byte,
on line 56, from data receiver 36 is loaded into register 37
by the A bus enable gate signal from timing control 47 on
line 71; the second data byte, on line 56', is loaded into
register 37' by the A bus enable signal on line 71' and the
third data byte, on line 36", are loaded into register 37" by
the A bus enable signal on line 71". The A bus of sync code
register 38 is always enabled, thereby continuously loading
the preset eight bit synchronization code. The contents of
registers 37, 37' and 37" are available for transfer to timing
; control 47 or command register 43 via the B bus outputs.
During an interrogation cycle, registers 37, 37', 37" and
38 are transferred to the serial mode of operation by the
serial enable signal on line 72, and the register contents
axe shifted to modulator 39 by -the shift clock on line 70,
both si~nals from timing control 47.
3a With reference to FIG. 18, the command register
- 50 -
~7~7~7
comprises CD4034A eight bit registers ope~ted in the a~
synchronous~ parallel mode, with A bus data input and B bus
data output. Data from input register 37 is continuously
available on lines 67, 67' and 67". When the message mode
indicator bit K indicates the contents of input register
37 is a command, the data on lines 67, 67' and 67" are
loaded into registers 43, 43' and 43", respectively, by the
A bus enable signal on line 78 from timing control 47. The
contents of command registers 43, 43' and 43" are available
on B bus lines 79, 79' and 79", respectively.
With reference to FIG. 19, the status register
comprises CD4034A eight-bit registers operated in the a-
synchronous mode with B bus data input and A bus data out-
put. Status data is continuously available on lines 82, 82'
and 82", while the preset message mode indicator bit K (preset
to logic 0) preset central control unit address bits Al6 and
A17, and command execute enable bit P on line 68 are contin-
uously available as inputs Bl through B4 of register 44'.
When the status register contents are to be sent to data -trans-
mitter 55 via line 83, the A bus outputs of register 44 are
enabled and registers 44, 44' and 44" are operated in the
serial mode by the serial enable signal rom -timing control
47 on line 81, and inverter 80, respectively. The conten-ts
of registers 44, 44' and 44" are shiEted by the clock on line
99 from timing control 47.
~ith reference to FIG. 20, the 64-bit output reg-
ister comprises eight-bit register 54 and four-bit register
54"", which are CD4034A, two 18-bit registers 54' and 54",
which are CD4006A, and a 16-bit register 54 " ', which is
CD4006A. Registers 54, 54', 54" and 54''' are always operated
in the parallel mode, while -the A bus of register 54 is used
~L~7~7~7
to transfer data, via line 87~ to data~ txan~ itter 55. ~hile
receiving data ~rom demodulator 53, via line 90, data is
shifted from register 54"" to register 54 by the shift clock,
on line 89, from timing control 47. After the meter module
reply message has been received, the 60-bit reply message
resides in registers 54, 54', 54" and 54"~. Timin~ control
47 then enables the A bus output of register 54 via line 88.
Simultaneously, register 54"" is transferred to asynchronous
paralle:L mode for a short period of time, via timing con-trol
47 strobe signal on line 95, thereby loading the message
mode indicator bit K, preset to logic 1, preset central con- ..
trol unit address bits, A16 and A17, and clock phase bit P
on line 68 into register 54"" via A bus inputs Al through A4,
respectively. The contents of registers 54', 54", 54''' and
54"" are then shifted to register 54 for transfer to data
transmitter 55.
Exemplary embodiments of -transponder demodulator
104, data control 105, data register 106, modulator 107,
timing control 110, synchronization code comparator 111, hot
water control address comparator 112, meter module address
comparator 113, function code register 114, function decoder
115 and hot water control 116 are shown in FIG. 21, using
logic elements of the RCA CD4000A series, with key timing
relationships shown in FIG. 22.
The transponder 30--Hzbasic timing clock, line
424, FIG. 22A, is derived from the nominal 60-Hz power dis-
tribution frequency via: line 24, differential amplifier 401,
which is a National Semiconductor LM139, and divider 423,
which is a CD4013A. The phasing of the 30-Hz clock output of
exclusive OR gate 431, line 445, FIG. 22C, is controlled by
-- 52 --
~7~)7~;7
dividers 427 and 428l which are CD404QA and CD4013A/ respect-
ively, an~ monostable multivibrator 426/ which is a CD4047A. :
Each time the synchronization code is received, monostable
multivibrator 426 ;s triggered by the sync flag signal, on
line 121~ FIG. 22F~ thereby resettiny divicLer 427. If a
synchronization code match is not detected during a duration .
Of 2048 successi~e 30-Hz clock periods, about 68.3 seconds,
divider 428 is toggled, FIG. 22B~ thereby inverting the phase
of the 30-Hz clock on line 445. While interrogating meters
or controlling hot water heaters, central control unit 5 will
be transmitting a message, including the synchronization
code, about e~ery five seconds. Thus, once 30-Hz clock phase
synchronization is obtained, divider 428 Will remain quies-
cent. The shift clock on line 118, FIG. 22DI is developed
from the 30-Hz clock on line 445 via NAND gate 434~ which is
normally enabled by line 124, OR gate 435 and monostable mul-
tivibrator 436~ which is a CD4047A.
The reference frequency for demodulator 104 and ~ .
modulator 107 are developed in a phase-locked loop oscillator
which uses the 60-HZ power distribution frequency, via dif-
ferential ampli~ier 401~ as the source reference frequency.
The output frequency of phase-locked oscillator 402~ which
is a CD4046A~ is 100~320-Hz~ which is sixteen times the
communication carrier frequency, 6270-Hz~ and is divided by
eight in divider 404l which is a CD4029A~ and by 209 in di~
vider405, which is a CD4029A~ to produce a 60-Hz signal that
is fed back to phase-locked oscillator 402l thereby closing
the phase-locked loop. The 100 r320-~Iz output of phase-locked ~:
oscillator 402 is also divided by sixteen by divider
403l which is a CD402sA, to obtain the 6270-H2 reference
frequency, on line 119, used by demodulator 104 and ~lodulator
~7~7
107. The phase of the reference fre~uency on line 119 is con~
trolled by the data received from demodula~or 104 via line
135 and inverter 425.
While central control unit 5 transmits an unmodul-
ated carrier, up~down counters 407 and 408, which are CD4029A,
are clocked by the 30-HZ signal on line 445, FIG. 22C, via
NAND gate 410 and in~erter 409. If demodulator 104 output
is a logic 0, counters 407 and 408 are incremented upward.
If the signal on line 135 is a logic 1, they are decremented
downward. The output of counter 407 is compared to the out-
put of divider 404 by digital comparator 406, which is a
CD4063A. When the outputs match, divider 403 is reset. Thus,
an excess of logic O's from demodulator 104 will advance
the 6270-Hz reference frequency on line 119, while an excess
of logic l's will retard the phase, thereby phase locking the
6270-Hz reference frequency on line 119 to the unmo~-
ulated carrier received from central control unit 5.
Counter 408 has a scale factor of sixteen; there-
fore, an accumulated excess of sixteen logic l's or logic O's
is requiredbefore the phase of the 6270-HZ reference frequency
on line 119 is advanced or retarded, thereby making the
circuit insensitive to short term variations. When the syn-
chronization code, which has a balanced quantity of logic l's
and O's, is received and detected, the phase shift circuits
are inhibited via the sync flag signal on line 121, FIG. 22F,
and NAND gate 410. This pre~ents the phase control circuits
from acting on function bits, Fo through F3, and address bits,
Ao through A15 of the interrogation message from central con-
trol unit 5. After the meter transponder interrogation cycle
is complete, the sync flag signal on line 121, FIG. 22F, again
- 54 -
7~ :
enables the phase control circuit~
Data is obtained from ~ideo amplifier 103 signal,
on line 131, by demodulator 104 which comprises transformerless
phase detector 411 and integrator 416. Phase detector 411
comprises resistors 412, 412', 412", 412 " l, 412"" and 412""',
operational amplifier 413, which is a Fairchild Semiconductor
741, and s~itches 414 and 414', which are CD4066A, driven 180
out of phase by inverter 415 and the 6270-IIz reference frequen-
cy on line 119. Phase detector 411 output is integrated
by integrator 416, which comprises resistor 417, opera-tional
amplifier 418, which is a Fairchild Semiconductor 741, capaci- :
tor 419, switch 420, which is a CD4066A, monostable multivibra-
tor 421, which is a CD4047A, and differential amplifier 422,
which is a National Semiconductor LM139. When the output of
operational amplifier 418 is positive, the output of differ-
ential amplifier 422, on lines 130 and 135,is logic 1. When
the output of amplifier 418 is negative, the output o~ ampli- `
ier 422 is logic 0. At the end of each bit period the neg-
ative going transition of the shift clock on line 118, FIG.
22D, triggers monostable multivibrator 421, thereby discharg- .
ing capacitor 419 via switch 420 and resetting integrator ..
416.
Before the synchronization code is received, the
sync flag signal on line 121, FIG. 22F, continuously re-
sets counters 437 and 438, which are CD4029A, to the zero ;~.
state, thereby developing an enable signal on lines 117 and
120, FIG. 22G, from decoder 439, which is a CD4028A. Thus,
receive switch 102 is enabled and data from demodulator 104
is cloc]~ed into data register 106, consisting of shift re-
gisters106 and 106', which are CD4034A, and 106", which is
a CD4015A, by the 30-Hz shift clock on line 118, FIG~. 22D,
- 55 -
1(371~7ti~7
via OR ~ate 443 and NAND gate 442 r which i5 enabled by the
control signal on line 120. The data register input signal
is shown In FIG. 22E. OR gate 443 and NAND gate 442 form
part of data control 105, the remainder of which comprises
NAND gates 440 and 441, and inverter 424. The first eight
bits of data register 106 are compared to t:he preset synchron~
ization code by digital comparator 111, which is two CD4063A,
via line 132. When a synchronization code match is detected,
sync flag flip-flop 111', which is a CD4013A, is clocked, re- ~
moving the reset from counters 437 and 438, tri~gering mono- . ~:
stable multivibrator 426 and inhibiting NAND gate 410, via
line 121, FIG. 22F.
Twenty bit periods after the synchronization code .
match is detected, decoder 439 inhibits receive switch 102,
via line 117, demodulator 104 data flow through data control
105, via the control signal on line 120, FIG. 22G, triggers
monostable multivibrator 449, and clocks function code bit
Fo~, on line 132 " ' from data register 106'l, into reply rate
register 114 and function code bits Fl, F2, F3, on line 132" :.
from data register 106", into function register 114', via the
control signal on line 122, FIG. 22H, and enables meter data
~low through data control 105 via the control signal on line
120', FIG. 22H. The reply data rate is determined by func-
tion code bit Fo in reply rate register 114, which is a
CD4013A. If the Fo bit is logic 1, the reply rate is 30 baud,
and NAND gate 434 is enabled via line 124. If the Fo bit is
loglc 0, the reply rate is 15 baud and divider 432, which is
CD4013A, is enabled by the signal on line 124, thereby syn-
chronizing the 15-Hz clock to the 30-Hz clock, while NAND gate
433 is enabled by the signal on line 124l. Thus, the shift
clock frequency on line 118, FIG. 22D, is determined by the
- 56 -
~ 7~7~7
contents of repl~ register 114 t
The preset meter module address and hot watex con-
trol address codes are simultaneousl~ compared to address
bits Ao through ~15~ from data registers 106' and 106 by
digital comparators 113 and 112, respectively, which are
CD~063A, via lines 132 and 132'. Monostable multivibrator
449, which is a CD4047A, enables comparators 113 and 112 via
line 444, FIG. 22K, to detect a meter module address match,
a hot water control address match, or no match.
If comparator 113 detects a meter module address
was received, meter module address flag flip-flop 113', which
is a CD4013A, is clocked, thereby enabling function decoder
115, via line 126', and meter data 1Ow through data control
105, and modulator 107, via meter module address flag on line
126, FIG. 22~. Function code bits Fl, F2, F3 are held in
function register 114', which is a CD4042A, and are decoded by ~ -
function decoder 115, which is a CD4028A, via line 127. Only
one meter enco~er is enabled by function decoder 115, such ;
as electric meter encoder via line 26.
During the 20-bit periods immediately following
meter module address detection, function code and address
data is shifted to modulator 107 from data register 106, via
line 128, FIG. 22M, while meter reading data bits Mo through
Mlg from the selected meter encoder are shifted into data
register 106 via line 129 and data control 105, which is en-
abled by decoder 439 control signal on line 120', FIG. 22H.
During the second 20-bit period following meter module add-
ress detection the meter reading data contents of data reg-
ister 106 are shif~ed to modulator 107 via line 12~, FIGo 22M,
while inverted meter data bits Mo through Mlg are shifted
into data register 106, FIG. 22E, via line 133 and clata con-
- 57 -
~7~7~7
trol 105, ~hich is enabled by decodex 439 cont~ol sign~l on
line 120", FIG. 22I During the third 2Q~bit period follo~
ing meter module address detection the 1nverted meter data
in data register 106 is shifted to modulator 107 via line
128, FIG. 22M, and data register 106 is loaded with logic
O's, as shown in FIG. 22E, since data control 105 is inhibit~
ed by decoder 439.
At the end of this period decoder 439 control sig~
nal on line 123, FIG. 22J, sets sync flag flip-flop 111',
meter module address flag flip-flop 113', and reply rate reg-
ister 114 and resets function register 114', thereby resetting
bit counters 437 and ~3~ to the zero state and enabling NAND
gate 410 via line 121, FIG. 22F, inhibiting function decoder
115, via line 126, meter data entry to data control 105 and
modulator 107, via line 126, FIG. 22L, setting the shift clock
on line 118 to 30 Hz via line 124, and enabling receive
switch 102, via line 117, FIG. 22G. The txansponder now re-
sumes searching the received data or the next synchronization
code transmission from central control unit 5.
If comparator 112 detects a hot water control ad-
dress, function code bits, on line 127, is clocked into hotwater control register 116, which is a CD4042A, by the strobe
from comparator 112 on line 125, FIG. 22N. This performs
the desired control function, such as turning the hot water
heater control relay on, via line 134, or peak demand meter
control relay on, via line 140, FIG. 22P. The meter trans-
ponder then idles for 60-bit periods, since modulator 107,
function decoder 115 and data control 105 are not enabled by
meter module address flag signal on~line 126. At the end of
60-bit periods, whose duration is determined by function code
bit Fo of reply rate register 114, receive sync flag flip-
- 58 -
. ,
~ (~7~7~7
flop 111' and reply rate register 114 are reset b~ decoder
439 control signal on line 123, FIG. 22~, thereby resetting
bit counters 437 and 438 to the zero state and enabling NAND
gate 410 via line 121, FIG. 22F, setting the shift clock on
line 118 to 30 Hz via line 124, and enabling receive switch
102, via line 117, FIG. 22G.
If no address match is detected by comparators
112 and 113, transponder 12 performs no control function and
idles for 60 bit periods, whose duration is determined by
function code bit Fo of reply rate register 114, and then re-
sets as in the hot water control cycle.
The signal from da-ta register 106, on line 128, FIG.
22M and 22Q, modulates the phase of the 6270 Hz reference
frequency, on line 119, in e~clusive OR gate 446 r thereby
producing the desired 180-degree phase shift between commun-
ication carrier outputs representing logic 1 and logic 0. The
modulated signal, and its inverse via inverter 447, are enab-
led in NAND gates 450 and 451 by meter module address flag
signal on line 126, FIG. 22L, which drive transmitter 108 via
inverters 452 and 453, and lines 136 and 136', respectively.
With reference to FIG. 23, there is shown an
exemplary embodiment of transponder transmitter 108. Trans-
former 500, which is a Stancor P-8605, steps down the 120V,
60 Hz power line voltage from electric service entrance 24
and 24'. The reduced voltage is rectified by diodes 501 and
502, which are Motorola MR751, and filtered by capacitor 503.
Transistors 504 and 505, which are 2N2222A, are normally
turned off b~ the modulator signals on lines 136 and 136',
via resistors 506 and 507, repsectively. When modulator 107
is enabled, transistors 504 and 505 are switched 180 degrees
out of phase. When transistor 504 is switched on, current
- 59 -
~7~7~7 :~
flows thxough resistors 508 ~nd 5a9~ cha~gl.ng capacitor 510,
thereby slowly switching on txan$~stor 511 r which is a 2N2905,
whose collector curxent is limited by resistor 523, and trans- ;
istor 512, which is a 2N6111 whose emitter current is limited
by resistor 513. ~his raises the voltage on line 525 to that
on line 526, thereby charging capacitor 528 through resistor
527. The voltage drop across resistor 527 causes triac 529
to conduct. When the modulator signal on line 136 switches
off transistor 504, capacitor 510 discharges through:resistor
508, slowly switching off transistors 511 and 512, while
diode 514, which is a Motorola MR751, clips the spike created
by the inductance of electric service entrance 24 and distri-
bution transformer 10. When transistor 505 is switched on by
modul~tor signal 136', transistor 515, which is a 2N2905, is
switched on via resistors 516 and 517. Current then flows
through resistor 518, charging capacitor 519, thereby slowly
turning on transistor 520, which is a 2N6386, whose emitter
current is limited by resistor 524. This lowers the voltage :
on line 525 to that on line 24l, the service entrance neutral,
thereby discharging capacitor 528 through resistor 527. The
voltage drop across resistor 527 causes triac 529 to conduct.
When the modulator signal on line 136' switches off transis- .
tor 505, capacitor 519 discharges through resistor 521, slow-
ly switching off transistor 520, while diode 522, which is
a Moto~ola MR751, clips the spike created by the inductance
of electric service entrance 24 and distribution transformer
10. The voltaye transistors on line 525 are coupled to the
electric service entrance, lines 24 and 24', by coupling :
capacitor 109.
The circuitry just described comprises a source
of unipolar potential on line 26 derived from the electrical
- 60 -
.
~7~;7
power and having ripple at the power line fxe~uency~ The
transistor c~rcuitry comprises means fox interXuptin~ the
unipolar potential at a rate corresponding -to the carrier
frequency in response to the means for moclulating applied to
the bases of transistors 50~ and 505 to in-~errupt the uni-
polar potential at a rate corresponding to the carrier frequ-
ency. The triac 529 comprises means for coupling the inter-
rupted unipolar potential to the power lines -to provide a
carrier signal on the power linesO
There has been described novel apparatus and tech-
niques for effectively communicating over power lines with
numerous advantages and features described above. Xt is
apparent that those skilled in the art may now make numerous
uses and modifications of and departures from the specific
embodiments describad herein without departing from the inven-
tive concepts. Consequently, the invention- is to be const-
rued as embracing each and every novel feature and novel com-
bination of features present in or possessed by the apparatus
and techniques herein disclosed and limited solely by the
spirit and scope of the appended claims.
- 61 -
