Note: Descriptions are shown in the official language in which they were submitted.
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E~ackground of the Invention
A. Field of the Invention
This invention relates to semiconductor devices
and in particular to a sealing coating for protecting the
device from contamination.
B. Prior Art
In the fabrication of integrated circuits, a
wafer of monocrystalline siIicon is variously etched and
subjected to diffusion or implantation of controlled
concentrations of impurities to establish desired topology
and various N-type, P-type and insulating regions which form
the multiplicity of active and passive semiconductor
structures. A final step in fabricating an operating device
is the laying on of an aluminum film pattern to establish
metallic interconnections between the structures such that
a desired circuit is produced. Portions of this pattern
are terminated at bonding pads to which wires are later
, attached; the wires extending to terminal pins of the
`~ completed package.
The device at this stage of fabrication is func-
tionally complete and could, with appropriate mechanical
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support and termination, operate as part of an electronic
assembly such as a television receiver, calculator, etc.
Its usefulness would be shortli~ed, however, because
environmental contamination would profoundly affect the
character of the semiconductor junctions and the regions
abutting them. Specifically, sodium ions and moisture
present in the atmosphere would easily diffuse into the
silicon and radically change the electrical characteristics
of the device. Such influences would cause the demise of
the device in only hours at ordinary temperatures.
It is, therefore, common practice to deposit a
layer of silicon dioxide ~SiO2) which in its amorphous form
i8 essentially glass. This layer protects the underlying
silicon from contact with atmospheric gases and vapor.
Furthermore, it protects the wafer surface and its metal-
; ization against abrasion and gross contaminants such as dust
particles which might be introduced during the cutting of
the wafer into individual chips.
If the chip is then housed in an hermetic seal,
the SiO2 passivating layer has usually been sufficient. Thechip has remained protected against residual contamination within
the enclosure which i8 in turn protected against further
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cantamLnation by the seal. However, hermetic sealing is
relatively costly and thus for most consumer and industrial
products, the completed glass sealed chips are encapsulated
in plastic following the bonding of the wire leads. The
plastic offers adequate mechanical protection and serves to
exclude gross contaminants. However, the plastic is semi- -
permeable and moisture has diffused through it over periods
of time. The moisture has also transported metallic ions,
typically sodium. The layer of passivating glass has
protected the device as described above against these
contaminants over a period ranging from weeks to years
; depending on temperature, electrical biases and the thick-
ness and constitution of the glass itself.
Glass containing about 3 to 10 per cent, typically 5% to ~/0,
of phosphorous has been enhanced in its ability to trap
sodium ions. However, these ions over a lengthy period have
diffused through the glass in sufficient numbers to alter the
electrical characteristics of a device. Such diffusion rates
are enhanced at higher chip temperatures and by electric
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Accordingly, an object of the present invention is
protecting the major surface of a semiconductor device from
moisture and metallic ions present in the atmosphere.
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Summ~ry of the Invention
A seal for a semiconductor device and a method
therefor in which the semiconductor device has a major
surface. A passive sealing silicon layer is formed overlying
S the ma;or surface of the semiconductor body thereby to pro-
tect the device from contamination.
rief Description of the Drawings
,j.
Fig. 1 is a cross-section of a portion of a
semiconductor device having a layer of passivating glass
and a sealing layer of silicon over the glass in accord-
ance with one embodiment of the invention;
Fig. 2 is a plan view of the elements shown in
the cross-section of Fig. l;
Fig. 3 is a schematic diagram of a diffusion
furnace in which the sealing layer of silicon is formed
on the semiconductor device of Figs. 1 and 2;
Fig. 4 is a cross-sectional view of another
; embodiment of the invention in which a second layer of
glass is applied over the sealing layer of silicon; and
- 20 Fig. 5 is a cross-section of a third embodiment
of the invention.
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~etailed Description
Referring now to Fig. 1, there is shown a cross-
section of a portion of a ~S se~iconductor device or integrated
circuit 10. Using well known processes, a circuit is
fabricated starting with a body of silicon 11 having a
major surface lla and having a specified concentration of
N-type impurities. The break shown in the representation
of the wafer thickness is presen~ because the thickness is
very large compared to the dimensions of the diffused and
deposited regions which constitute the active portion of
the circuit.
Using standard photolithographic techniques,
various masking, etching and oxidation steps follow which
lead, for example, to the production of a P-type region
12 into which further diffusions resulting in N-type
regions 13a-b are produced. It will be understood that many
discrete regions may be formed and provided with other
- various circuit elements such as resisters, diodes, tran-
sistors, etc. Additional oxidation and etching steps follow
which provides an insulating layer of silicon dioxide 14
having windows through which a subsequently applied film
of a suitable metal such as aluminum 15 extends to make
contact with the silicon substrate. In conventional
manner, aluminum deposition is effected by evaporation of the
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~07~53
metal onto substrates which are at room temperature or
up to about 300C in a high vacuum. Under these conditions,
the aluminum 15 interacts very little with silicon in the
areas not protected by oxide layer 14.
In the subsequent masking and etching step, the
aluminum film 15 is divided into many individual traces
that interconnect specific regions. For circuit nodes
which are to be connected externally, these traces lead to
extended metallization areas such as indicated by 15a in
Figs. 1 and 2.
Following the metal pattern definition, the aluminum
is "sintered" or "alloyed". In a conventional example,
sintering takes place ranging from about 400C to 500C for
from abou~ 20 to 40 minutes. In these examples, the ambient
is nitrogen or hydrogen or a mixture of nitrogen and hydrogen.
The foregoing results in alloyed regions 16a-c where the
silicon is not protected by oxide layer 14. It will be
understood that higher alloying temperatures much above about
500C, for example, would result in rapid spreading of the
alloyed regions to the point where regions 16a-c would
extend completely through the N-regions 13a,b to thereby
contact the underlying P-region 12. This would result in
an undesirable shorting of the P-~ junctions.
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For the next step, an insulating layer is then
dleposited over the entire oxide layer 14 and aluminum layer
15 as well as metallized areas 15a. A passivating layer of
amorphous glass, (SiO2) has been used as the insulating layer
5 17 where the amorphous glass has a phosphorous content, as
previously described, in the range of about 3 to 10 per cent,
; as operative limits, and about 5-7 per cer~t preferred limits.
A^, The glass cannot be deposited at a temperature much above
about 500C or there results the above described undesirable
- 10 shorting of the P-N junctions. In other examples, the
insulating layer is formed of glass without phosphorous
and is also formed of silicon nitride (Si3N4)
Following deposition of insulating layer 17, a
passive sealing or protective layer 18 is deposited over
15 the entire layer 17 by placing chip 10 in a diffusion
furnace shown in Fig. 3. Diffusion furnace 30 comprises
a chamber 30a surrounded by refactory 30b within which
thermostatically controlled electric heating coils 30c
are embedded. The atmosphere within chamber 30a is
20 supplied with a mixture of silane (SiH4) and nitrogen (N2)
gases. A tank 25 containing nitrogen 25a and'a tank 26
containing 3% silarle in nitrogen 26a are attached to a mani-
fold 29 which leads to the furnace chamber 30a. The flow
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rates of the nitrogen and silane as lndicated by flow meters
27a, 28a are controlled by valves 27 and 28 respectively
and commensurate with the desired deposition rate. One or
more wafer~ 10 may be supported in an upright position on a
quartz or silicon carrier 31 which is inserted into or
removed from ~he furnace by a conventional manually or
automatic or machine operated rod 32. Wafer 10 is heated
in furnace 30 for the growth of a silicon layer. The
temperature of furnace 30 is in a range of 450C to 525C,
approximately, where a temperature of about 475C is a
preferred temperature. The rate of growth of silicon layer
18 goes up sharply with temperature and thus for temperatures
below about 450C in furnace 30 a useful silicon layer may
be deposited but the growth process is uneconomically long.
For temperatures below about 425C, from run to run, the
silicon in some wafers 10 in some runs does not deposit at all.
The degree of silicon aluminum alloying also
increases sh~rply with temperature. Thus, at the upper
limit of the temperature range at about 525C, from run to
run, some of the wafers 10 in some runs may have their
P-N junction regions near the aluminum-silicon contact points
destroyed. Above about 525C, there is an increase in the
destruction of the wafers with temperature in furnace 30.
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At the preferred temperature of about 475C,
depositions of passive sealing silicon layers have been made
in the range of 500-1000 A, approximately. This range has
been found to be a preferred range of silicon thickness and
provides contamination protection with a compromise between '
a more costly thicker silicon layer while at the thinner
-- limit, a lower device reliability. For silicon layers
thinner than 500 A, the saving is only a relatively shorter
duration of deposition time. In addition, for these layers
thinner than 500 A, during fabrication the plus or minus
variation in thickness from run to run may result in some
undesirably thin silicon thicknesses on some of the wafers.
In other examples, the silicon is formed in the
range of 50~3000 A, approximately. The silicon film is
-- 15 desirably not very conductive and provides a high electrical
resistivity of approximately .25 megohm-centimeter. Thus,
a relatively thin passive silicon layer 18 provides a very
high resistance but as the film becomes thicker, the resis-
tance decreases. If the silicon layer is of such a thickness
that the resistance has substantially decreased, a problem
may arise if wire 20 would accidentally touch the silicon layer.
Examples of silicon layer deposition rates in
furnace 30 at temperatures ranging from 450C to 525C at
the indicated silane nitrogen flow rates in a 100 mm.
diameter tube are set forth in the following table.
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Table 1
Furnace 3% Silane in NitrogenRate of Silicon
Temperature Nitro~en Rate Rate Layer Growth
C liter7min. liter/min. A/hr
450 2.7 6.8 1,600
475 2.7 6.8 5,000
500 2.7 6.8 8,500
525 2.7 6.8 13,000
Examination of wafers fabricated in the foregoing
examples of TabLe l show silicon layer 18 to be poly- -
crystalline.
By the selective etching of silicon layer 18
and insulating layer 17, a window 19 as shown in Figs. 1, 2
is formed through layers 18 and 17 to allow passage of
terminal wire 20 for connecting to node 15a.
In this manner, there is produced a semiconductor
device 10 having a silicon layer 18 for protecting
the device from contamination from moisture and
metallic ions. While device 10 is shown as a portion
of a CMOS device, it will be understood that silicon
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layer 18 may be used in connection with other semiconductor
de~ices requiring such protection from contamination.
Fig 4 illustrates another embodiment of the
invention in a CMOS semiconductor device lOa. All of the
fabrication steps up to and including the selective etching
of a window in silicon layer 18 and insulating SiO2 layer 17
are the same as those described previously. In this embodi-
ment, before terminal wire 20 is attached, an additional
layer 35 of amorphous glass is deposited over the top
of the device such that the edges of this layer at window l9a
flow down to coat the sides of the window thus protecting
silicon layer 18 from contact with wire 20. By sele~tive
etching, layer 35 must be opened over the aluminum pad to
allow wire 20 to be attached. Alternatively, the vertical
section of layer 35 within window l9a may aLso be etched
away leaving the edges of layers 17, 18 and 35 extending
within window l9a. In this alternative, layer 35no longer completely
protects layer 18 from contact with wire 20. By enclsoing
the silicon 18 in a glass "sandwich" between layers 17 and
35, the silicon is further protected against abrasion and
chemical attack which might occur during and after installa-
tion within the encapsulating plastic.
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Fig. 5 illustrates yet another embodiment of the
invention in CMOS device 10b. Fabrication of this embodiment
is similar to that of the embodiment illustrated in Figs. 1
and 2. However, in conventional manner, a thin film 36 of
nichrome is disposed during the fabrication of the device,
as illustrated in Fig. 5, on top of the active silicon
regions 11, 12, and 13 prior to the deposition of aluminum
layer 15. During the "sintering" or "alloying" process,
trimetallic alloy regions 37a-c are formed where the aluminum
meets the silicon due to the presence of the nichrome film 36.
ThiE inhibits the alloying of aluminum into the silicon and
allows the wafer to be subjected to higher temperatures,
for example over about 525C, which would allow the silicon
layer to be deposited to the preferred thickness of 500
to 1,000 A units in a shorter time thus greatly increasing
the manufacturing through put.
Alloying can also be inhibited by depositing aluminum
silicon instead of pure aluminum for the interconnects. In
this case, regions 15 in Fig. 1 would be of an aluminum
silicon composition as deposited. The aluminum now being
partially saturated with silicon will not consume as much
silicon from the device contact areas when alloyed. This in
turn would allow a higher deposition temperature for silicon
layer 18.
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In the embodiment of Fig. 5, it will be noted
that window l9b has been etched wider in area 19c which is
defined by silicon layer 18. In this manner, there is
substantially decreased any possibility of contact between
terminal wire 20 and layer 18.
It is understood that the above described arrange-
ments and embodiments are merely illustrative of the many
specific embodiments which can be devised to represent
application of the principles of the invention. For example,
passive silicon layer 18 can also be deposited by means of
evaporation techniques, sputtering techniques and RF plasma
methods. In these examples, the wafer is maintained at
about room temperature or slightly higher and the silicon
layer also results in a polycrystalline structure.
However, the grain size can become so small so as to
characterize the polycrystalline structure as amorphous.
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