Note: Descriptions are shown in the official language in which they were submitted.
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Field of the Invention
The present invention relates to improvements in demodula-
tion circuits and more particularly improvements in coherent or
synchronous demodulation circuits which recreate a carrier in
order to perform the demodulation process. More particularly,
the present invention concerns an improved phase-locked loop
which prevents the loop from being side locked to a side band
frequency of the desired lock frequency.
Background of the Invention
For quite some time now, the art has been aware of the
advantages of modulation techniques in which the carrier is not
transmitted. With the advent of phase locked loops and techni-
ques associated therewith the demodulation of suppressed carrier
signals has been greatly simplified.
Briefly, a conventional phase-locked loop may include a
phase detector, a low pass filter and voltage controlled oscilla-
tor. The controlled oscillator phase makes it capable of locking
or synchronizing with an incoming signal. If the phase relation-
ship changes, indicating the incoming frequency is changing, the
phase detector output voltage increases or decreases just enough
to keep the oscillator frequency the same as the incoming fre-
quency, preserving the locked condition.
In many cases in suppressed carrier applications the
suppressed carrier frequency actually changes due to phase shifts,
downward shifts or other effects and the loop provides the demod-
ulator with an excellent means for tracking this change in fre-
quency to provide effective demodulation.
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However, under certain circumstances the loop can be side
locked. Side lock is an anomalous locking mode in which the
phase-locked loop output frequency is not the desired lock fre-
quency. For the conventional phase-locked loop, side lock is a
stable condition. The difficulty is, of course, that in side
lock the voltage controlled oscillator is not oscillating at
the correct frequency to perform the necessary demodulation.
A discussion of side lock is found in Burst Synchronization
of Phase-Locked Loops, by Leonard Schiff, found in IEEE Trans-
actions on Communications, Volume COM-21 No. 10, October 1973 at
pp. 1091 through 1099. This article teaches that side lock may
be prevented by reducing the allowable offset between the carrier
frequency and the voltage controlled oscillator natural frequency
to be less than half the burst synchronizing rate. Of course,
due to frequency uncertainty in long distance transmissions,
carrier frequency drifts and the like this may not be a practical
alternative. As a further alternative the author employs a
frequency discriminator to provide a voltage proportional to the
difference between the carrier frequency and the lock frequency,
where a carrier frequency is available. Again, depending upon
the application this may or may not be practical.
A severe test of the phase-locked loop capabilities is
found in demodulating PSK signals especially where there are
plural phases. The prior art teaches that the carrier may be
recreated by first multiplying the received signal, in fre-
quency, by a number equal to the number of phases of modulation.
The resulting signal is then applied to a phase-locked loop
whose voltage controlled oscillator has natural frequency of N
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times the carried (NFc). The output of the phase-locked loop
is desirably then N times the carrier frequency (NFc) which,
after division by N can be used for synchronous detection
purposes.
The difficulty with this approach is that, at the
phase locked loop, the input signal has a spectral energy
distribution which includes a strong component at the frequency
NFc and also energy at a plurality of sidebands spaced from
either the carrier or another side band by the modulation rate
Rs. If the modulation rate, Rs is relatively small, compared
to the frequency uncertainty of the received carrier it may
be difficult, or impossible, to design a phase-locked loop
to avoid side lock.
Summary of the Invention
:
The invention provides a method of preventing a
phase locked loop including a phase detector and voltage
controlled oscillator from achieving sidelock in response to
an input signal comprising components at a desired lock
frequency and sideband components spaced from said desired
lock frequency at multiples of a rate Rs, comprising the steps
of, detecting energy at the output of said phase detector
at a frequency R , and inhibiting loop lock when such energy
is detected.
The present invention also provides a side lock
detector which cooperates with the conventional phase-locked
loop to detect the side lock condition and energize a lock
inhibit means to inhibit the phase-locked loop from remaining
in the locked condition. In this fashion, the voltage
controlled oscillator, of the phase-locked loop is driven to
another locked condition. If the side band lock detector
again detects a side lock, the voltage controlled oscillator
is again driven out of the locked condition. In this fashion,
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the voltage controlled oscillator is quickly driven to the
desired locked condition.
: In order to detect the side lock a band pass filter
is provided whose center frequency is equal to the modulation
rate Rs and whose pass band is very narrow compared to the
center fre~uency. In the locked condition, that is with
the voltage
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` 107Z189
controlled oscillator oscillating at the desired lock frequency
the phase detector output at the modulation rate frequency which
is the only frequency that the band pass filter can pass, will be
essentially zero. Only noise will contribute to the output of
the band pass filter and, if the pass band is sufficiently narrow
the noise will be insignificant. A detector is provided to -
detect energy in the band pass filter output. The detector may
be connected to a lock inhibit means which, cooperates with the
voltage controlled oscillator to inhibit the phase-locked loop
from remaining in a side lock condition.
In one embodiment, the lock inhibit means may merely com-
prise a relay which is connected to be energized by the output
of the detector. As a result, the relay will only be energized
in the presence of a side lock condition. Relay contacts may be
arranged to ground the output or the input of the phase detector.
When either of these locations is grounded the voltage controlled
oscillator no longer receives an input and a locked condition is
inhibited. As a further alternative, a sweep voltage may be added
to the output of the low pass filter and provided as the controll-
ing voltage to the voltage controlled oscillator. With such an
arrangement, a lock detector de-energizes the sweep voltage
during a locked condition. However, the detector output, in a
side lock condition, energizes the sweep voltage to again drive
the voltage controlled oscillator out of the locked condition.
By providing the detector with a relatively long time
constant the lock inhibit means will remain effective until the
oscillator has changed in frequency a sufficient amount to pre-
vent the circuit from oscillating into and out of side lock.
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Brief DescriPtion of Drawinqs
The characteristics and features of the present invention
` will become clear from a reading of this description taken in
~ conjunction with the attached drawings in which like reference
. characters identify identical apparatus and in which:
Figure 1 is a block diagram of a prior art coherent demod-
ulation arrangement,
Figures 2A, 2B, and 2C are representation of frequency
spectra at various points in the circuit of Figure 1 under
various conditions:
Figure 3 is a block diagram of an improved phase lock loop
- which incorporates the inventive side lock detector;
Figure 4 is a block diagram illustrating a number of alter-
. native implementations of the apparatus of Figure 3;
. Figure 5 is still a further implementation of the apparatus
of Figure 3.
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.- Detailed DescriPtion of the Invention
.
~ Although side lock is a condition which can be generated -
from a number of causes we will here explore the side lock re-
sulting from an N phase PSK signal modulated at a rate Rs.
~, ,
Figure 1 illustrates a prior art demodulation arrangement for
such a signal in which the received signal is provided to a
frequency multiplier 10. For an N phase PSK signal a frequency
multiplier 10 multiplies the received signal, in frequency, by
N (where ~ equals the number of phases of modulation). If we
assume an idealized PSK signal the frequency spectrum of the
output of the multiplier 10, at point A in the circuit, would
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be that shown in Figure 2A. The intermodulation terms result in
a carrier at the frequency NFC as the original carrier, and side
bands, spaced from the multiplied carrier an amount equal to Rs
where Rs is the modulation rate. Ideally, the phase lock loop 11
locks onto the multiplied carrier NFC which is a continuous wave
without modulation. After frequency division in divider 12 the
frequency spectrum at point B in the circuit comprises a pure
signal at frequency fc~ This, when applied to the coherent de-
~' tector 13 enables the orig~nal modulation to be derived from the
10 received signal. So long as the frequency uncertainty of fc were
small enough compared to the modulation rate Rs, so that the off-
set between the natural frequency of the voltage controlled
~- oscillator of phase lock loop 11 and the desired lock frequency
i were small enough the phase lock loop would lock properly. However
if the frequency uncertainty was large in comparison with Rs then
a side lock condition is possible. To illustrate the problem we
can refer now to Figure 3.
Figure 3 illustrates a conventional phase lock loop within
P the dotted lines 11. This includes a phase detector lla, a low
20 pass filter llb, and a voltage controlled oscillator llc whose
- output is provided to the divider 12 (Figure 1). The phase
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detector lla campares the received signal with the output of the
voltage controlled oscillator and provides a signal to the low
pass filter llb which is indicitive of the phase difference there
between. The phase detector output includes high frequency com-
ponents which are filtered out by the low pass filter. Thus,
the phase difference drives the voltage controlled oscillator to
a locked condition where its output frequency is equal to a
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desired locked frequency as determined by the input to the pha~e
detector. When the phase detector is operating properly on a
signal whose frequency spectra is of the type illustrated in
Figure 2A, the frequency spectra of the output of the phase
detector lla will be of the type shown in Figure 2B. In particu-
lar, there will be a DC amplitude or error voltage. The contri-
bution from each of the side bands will be cancelled out by the
mirror image side band. ~owever, the side lock condition is
characterized by the frequency spectra of Figure 2C. There we
see at least one side band is present at a frequency of Rs.
In order to prevent side lock a band pass filter 20, detector
21, and lock inhibit means 22 is connected between the output of
the phase detector and the voltage controlled oscillator.
The band pass filter 20 has a center frequency which is
equal to Rs and a very narrow pass band. The pass band may be
on the order of 60 hertz when the center frequency is on the
order of 60 kilohertz. Such filters can be fabricated with
crystal tuned circuits. -
The output of band pass filter 20 is provided as an input
to detector 21 which provides a low frequency or DC signal to
lock inhibit means 22. Lock inhibit means 22 is connected to
the voltage controlled oscillator llc.
In operation, if the phase lock loop 11 side locks, the
phase detector output will include a significant component at a
frequency of Rs. This will be passed by band pass filter 20 and
detected by detector 21 initiating lock inhibit means 22. Lock
inhibit means 22 prevents the voltage controlled oscillator llc
from locking to this frequency in a manner which will be explained
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hereinafter.
The foregoing explanation has, of course, ignored the noice
problem. The use of a multiplier, such as a multiplier 10 en-
-; hances noise levels and makes signal to noise ratio threshold
~ significant. To that end, the detector 21 may include a com-
;~ parator such that only signal levels above a reference will be
~ considered to indicate side lock. Signal levels below such a
,
reference will be considered noise generated.
A further problem to be overcome exists if the voltage
controlled oscillator can drift back to the side lock frequency
after the lock inhibit means 22 is de-energized. Of course, this
could cause the loop to oscillate between a particular side lock
. and unlocked condition. This would prevent the loop from locking
to the desired lock frequency. This condition can be prevented
~ by providing the detector with a suitably long time constant such
i that by the time lock inhibit means 22 is de-energized the voltage
controlled oscillator will have drifted or have been driven
sufficiently far from the detected side lock to prevent its return.
One embodiment of the invention is illustrated in Figure 4a
which shows the phase detector lla, low pass filter llb and
-~ voltage controlled oscillator llc much in the same manner as that
of Figure 3. The band pass filter 20 is shown as being connected
to a diode detector 23. A comparator 24 is provided with the
output of diode detector 23 and a reference level. When the diode
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detector output excedes the reference level comparator 24 provides
,;~ a signal to relay 25. In order to prevent the loop from oscillat-
-- ing between a side lock and unlocked condition, relay 25 may be
made slow drop away. Alternatively, as has been suggested, the
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diode detector 23 or comparator 24 may be provided with a long
time constant. Relay 25 has a contact 25a which is connected
between the phase detector and the low pass filter. When the
relay is de-energized the contact has no effect on the circuit.
However, when the relay is energized, in response to detection
of side lock, the output of the phase detector is grounded. In
this condition the loop is inhibited from being locked and the
- oscillator slowly changes frequency. After a sufficient inter-
val, to ensure that the loop does not return to the side lock
condition, relay 25 drops out allowing normal loop operation.
Instead of connecting relay contact 25a at the output of phase
detector lla it may be connected to the input, as illustrated
; in dotted portion contact 25b. The location of the relay con-
tact in either location will inhibit the loop from locking when
the relay is energized.
In some applications it may be necessary to provide a sweep --
voltage to the voltage controlled oscillator to ensure that the
; oscillator sweeps in a preferred direction. Figure 5 illustrates
in the inventive apparatus in combination with such a feature.
Figure 5 illustrates the phase detector, low pass filter and
voltage controlled oscillator as shown in Figure 3 although an
amplifier 30 connects the output of low pass filter llb to the
voltage controlled oscillator llc. A sweep voltage generator
provides an additional input to the amplifier 30. Thus, the
output of the sweep voltage generator 27 ensures the voltage
controlled oscillator will sweep in a preferred direction. The
lock detector 28, when a locked condition is detected de-energizes
- the sweep voltage generatox 27 to allow the loop to lock. A
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lock detector such as lock detector 28 are well known in the art.
one example of such a lock detector 28 is illustrated on p.52 of
Phase Lock Technique by F. M. Gardner (Wiley, 1966).
The apparatus of Figure 5 also includes a side lock detector
` including band pass filter 20, detector 23, and comparator 24.
However, in contrast to Figure 4, comparator 24 provides an in-
put to a side lock detector 26. Side lock detector 26 controls
sweep voltage generator 27. In operation, when the loop is out
of lock the low pass filter llb provides an error voltage through
amplifier 30 to cause voltage controlled oscillator to approach
the desired lock frequency, as detected in the phase detector lla.
The sweep voltage generator 27 ensures that the voltage controlled
oscillator sweepsin a preferred direction, or at a preferred rate.
When lock is detected lock detector 28 inhibits sweep voltage
generator 27 and thus allows the loop to lock. However, if side
~ lock is detected by band pass filter 20, detector 23 and compar-
- ator 24, side lock detector 26 again energized the sweep voltage
generator 27 to inhibit the loop from locking up. The circuit
of Figure 5 may well include the long time constant for detector
23 as discussed with-respect to Figure 4.
Those of ordinary skill in the art will understand that
although a diode detector has been disclosed any AC to DC con-
verter could be used with equal facility. In addition, the
particular reference level for comparator 25 will depend upon
the other parameters of the circuit such as the band width of
filter 20 and noise levels at the output of the phase detector
lla. Other changes and modifications may be made without de-
parting from the spirit and scope of the present invention and
the embodiments illustrated herein should not be construed to
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limit the scope of the invention which is defined by the claims
appended hereto.
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