Note: Descriptions are shown in the official language in which they were submitted.
11 BAC~GROU~ OF THE INVrNTION
i2 The s?eed of lzrge scale integrated (LSI) circuics ls
13 limited to a great extent by the package trans~ission delay. This
14 is so, since the s~-itchirg delay of the active devices beco~es rela-
tively insignificant with respect to the interconnection or propagation
16 delay in the LSI package. The propagation ~elay is due, to a great
17 e~tent, to the large dielectric constant of the insulating ~aterial
18 between the res?ective layers o' the pac~age. The dielectric constant
19 of the insula,ir,g ~aterial is greater thPn one, and when operat.ng in
a cer2~ic environment is or. the order of nine. The higher the
21 dieiectric constant, the lower the signal propaga~ion speed.
22 According to the ?resent invention, the dielec ric between
23 respective layer is air, which has a dielectric constant of one.
~4 AccordinOly, the signal propagation speed is sigr.ificar.tly increased.
SU~ RY OF T~lE I~VENIION
26 According to the present invention, a ~ultila-yer interconnect
27 syste~ for a lar~e scale integra~ed circuit is set forth. Tne inter-
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1 connect system includes at least one signalilayer and one reference
2 layer affixed to one another in a face-to-face relationship by means
3 of spacers which maintain a predetermined air gap therebetween. The
4 one signal line pattern on each face thereof, including conductors at
predetermined locations in said substrate for connecting signal lines
6 on one face to signal lines on the other face, or to the reference
7 layer. The one reference layer is comprised of another substrate, with
8 each face thereof being coated with a conductive material, and including
9 a plurality of conductors extending therethrough. The conductors are
selectively connected to or insulated from the conductive material. The
11 conductors in the ~eference layer are also selectively connected to
12 conductors in the one signal layer.
13 BRI~F DESCRIPTION OF THE DRAWINGS
14 Fig. 1 is a schematic diagram representation of a multilayer
15 interconnect system according to the present invention;
16 Fig. 2 is a schematic diagram representation illustrating
17 the spacing between a signal plane layer and a reference plane layer,
18 including the spacing between respective layers, and the dimensions of
19 strip lines on a given layer;
Fig. 3 is a schematic diagram representation illustrating how
21 masking layers are applied to each face of an insulating substrate,
22 which is subsequently processed to form either a signal plane layer or
23 a reference plane layer;
24 Figs. 4A-4F represent sequential side views of an insulating
25 substrate processed in accordance with the present inventlon for form-
26 ing a reference plane layer;
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1 Fig. S is a top view of a reference plane layer;
2 Figs. 6A-6D represent sequential side views of an insulating
3 substrate processed in accordance with the present invention for forming
4 a signal plane layer;
Fig. 7 is a top view of a signal plane layer; and
6 Fig. 8 is a schematic diagram representation illustrating
7 how a plurality of reference plane layers and signat plane layers a~e
8 joined and fused together for forming a multilayer interconnect system
9 DETAILED DESCRIPTION OF THE INVENTION
Fig. 1 illustrates generally at 2 a multilayer interconnect
11 system according to the present invention. A plurality of signal plane
.: . . .
12 layers 3, 5, 7 and 9 are alternated with and spaced from reference plane
13 layers 4, 6, 8, and 10 by spacers such as the spacers 11 and 12. ~he
14 signal plane layers are known in the art as X-Y plane layers and the
reference plane layers are known in the art as ground or voltage plane
16 layers. The signal plane layers have X lines on one face thereof and
17 Y lines, which are orthogonal to the X lines, on the other face thereof,
18 with the lines being selectively connected to one another or to an
19 ad;acent reference plane layer by conductors which extend through and
protrude from the respective faces of the signal plane layer The
21 respective reference plane layers have a plurality of conductors which
22 extent therethrough and protrude from the respective faces thereof, with a
23 conductive ground or voltage plane layer being formed on each of the
24 faces of the substrate with the conductive layers being selectively
connected to or insulated from the conductors. The conductors in adjacent
26 reference plane layers and signal plane layers are in substantial align-
27 ment with one another, and may be ~oined by fusing of the respective
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1 conductors. An air dielectric is maintained between respective layers
2 1 by means of the spacers 11 and 12 as well as the conductors of the
3 respective layers which are fused to one another. Integrated circuit
4 chips 13, 14 and 15 are connected to signal plane layer 3 in a known
manner, as are integrated circuit chips 16, 17 and 18 to signal plane
6 layer 7. Interconnection of the respective chips to one another and
7 to selected signal plane layers and reference plane layers is accomp-
8 lished in accordance with the techniques set forth in the present
9 invention.
Refer now to Fig. 2, which illustrates the spacing between a
11 given reference plane layer and a given signal plane layer. A signal
12 plane layer 19 is spaced from a reference plane layer 20 by means of
13 spacers 21 and 22. Generally, the spacers are formed on the-signal
14 plane layer and the ground plane layer, with the spacers on the respective
layers being fused to one another. The signal plane layer has a plurality
16 of X lines 23 formed on the top surface thereof, and a plurality of Y
17 lines 24 and 25 ~ormed on the b~ttom surface thereof. The reference plane
18 20 has metal films 26 and 27 formed on the top and bottom surfaces,
19 respectively thereof. The line width of a strip line on the signal plane
layer is illustrated by the dimension W, and the line gap between ehe
21 respective layers is illustrated by the dimension d. The interconnection
22 of lines on the signal plane layer, and interconnection of lines on the
23 signal plane layer to the reference plane layer is omitted to more clearly
24 show the air dielectric gap between the respective layers and the
spacing between the conductors.
26 The ge'ometry of the interconnection structure of the inter-
~7 connect pacXage is determined in terms of the characteristic impedance.
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1 If the fringing field is neglected, the characteristic impedance of
2 a strip line is approximately:
3 (1) Zo ~ ~ (d/w)
4 where:
u = the magnetic permeability;
6 e z the dielectric constant;
7 d = the line GP gap; and
8 W = the line width.
9 If the fringing field i5 taken into consideration, the characteristic
impedance of a strip line is:
11 (2) Zo = 60 log 5.89 d
h~ ,
12 where:
13 r = the dielectric constant;
14 d = the line GP gap;
W = the line width; and
16 t ~ the line thickness.
17 Since the dielectric in the gap is alr, the effective dieleccr~c
18 constant (~r eff) depends upon the dielectric constant (er sub) of the
19 layer substrate material and the spacing between à signal line and the
reference plane.
21 (3) e sub > ~ eff > 1
22 By way o~ example, as set forth below, if the substrate material is
23 ceramic:,
24 t4) ~r sub ~ 9.0
(5) ~r eff ~ 3.8
26 The signal propagation delay is:
27 i ; where C is the velocity of light.
C '.
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1 Thus, ID = 121 pico seconds/cm when thé signal lines are
2 buried in alumina ceramic, whereas ~D = 65 pico seconds/cm when the
3 ~. signal lines are coupled with a reference plane through an air gap,
4 even though the respective substrates are formed from alumina ceramic.
For a semiconductor circuit, Z is typically on the order of
6 50 ohms, thus for a line having a cross-section of approximately
7 3xl mil , a d of approximately 3 mils is easily achieved in accord-
8 ance with the interconnect fabricating technique which is described
9 shortly.
For cross-talk prevention via fringing fields of transmission
11 lines, a line separation in the range of 2d-5d is generally required,
12 depending on geometry and the specific integrated circuit application.
13 Thus, a single row line segment per channel in a 20 mil via grid, or a
14 double row per channel in a 50 mil grid, keeps the mutual capacitive -
and inductive coupling among the lines in the same layer to about lO~o.
16 Accordingly, there is negligible noise due to cross-talk.
17 A signal plane layer and reference plane layer are each formed
18 on an insulating substrate, with the substrate having a masking layer
19 applied to a selected area of each surface thereof. The masking layer
is applied under pressure to each selected area such that the surface of
21 the masking layer becomes coextensive with the surface of the substrate.
22 Accordingly, when the masking layer is removet a depression is formed
23 in the surface of the substrate. The depression serves as a portion of
24 the air gap between a signal plane layer and a reference plane layer when
they are interconnected in accordance with the present invention.
26 Fig. 3 illustrates one technique of applying masking layers
27 to the selected areas of the respective surfaces of an insulating material.
~ .
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1 An insulating substrate 28, which for example, may be green cera-
mic, has sheets of masking material 29 and 30 applied to a selected
area of the front and back surfaces thereof, with the substrate and
the masking sheets being inserted in a parallel plate press having
an upper plate 31 and a lower plate 32. Pressure is applied to
the upper and lower plate of the press in the direction of the
arrows 33 and 34, respectively, such that the masking sheets 29
and 30 are pressed into the surfaces of the insulating layer 28,
such that the surface of the respective masking layers are co-
extensive with the respective surfaces of the insulating sub-
strate. Accordingly, when the masking layers are stripped from
the insulating substrate, depressions are formed in the substrate
having a thickness corresponding to the thickness of the respective
masking layers. The masking layers, for example, may be comprised
of sheets of polyethylene terephthalate available under the trade
mark Mylar, from the Minnesota Mining and Manufacturing Co., each
being on the order of 1 mil thick.
FIGS. 4A-4F illustrate an exemplary process for forming a
reference plane layer in accordance with the present invention.
FIG. 4A illustrates an insulating substrate 35 having masking
layers 36 and 37 pressed into the upper and lower surfaces, respect-
ively, utilizing the technique described relative to FIG. 3. As
previously stated, the substrate 35 may be comprised of green cera-
mic and the layers 36 and 37 may be comprised of polyethylene
terephthalate. It is to be appreciated, that other insulating
substrates and masking layers may be utilized in the practice of
the present invention, and that other techniques may be utilized
to apply the masking layers to the substrate. A plurality of
through holes or via holes are formed in the substrate 35 by known
techn$ques. For example, with reference to FIG. 4B, through
holes 38-43 are formed in the substrate by the use of electron
beam (E-beam drilling). Other
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1 suitable techniques such as mechanical punching or drilling may
be used to form the through holes.
As shown in Fig. 4C, through holes 39-42 are filled with a
conductive material to form conductors 44-47 therein. Any number
of metals may be utilized as the conductive material, one such metal
being copper paste. Through holes 38 and 43 are left empty and are
utilized as index holes for aligning a reference plane layer with a
signal plane layer when the respective layers are stacked to form
a multilevel interconnect system.
As illustrated in Fig. 4D, after the metal paste has dried,
the masking layers are stripped from the substrate utilizing known
techniques to form depressions 48 and 49 in the respective sur-
faces of the substrate. The depressions are on the order of 1 mil,
corresponding to the thickness of the masking layer. The forma-
tion of the depressions in the surfaces of the substrate leaves
the endæ of the respective conductors protruding from the depressed
surfaces of the substrate. As previously mentioned these depressions
form part of the air gap between the stacked layers in the multi-
layer interconnection system. The formation of the depressions
leave flanges or spacers S0 and 51 in the unselected areas for
masking on the ends of the substrate. These spacers are used in
part to ioin respective layers to one another and to maintain an
air gap between the respective layersO The metallized sheet is
then fired at an appropirate temperature, depending on its composi-
tion, to transform the green sheet into hard densified ceramic.
Next, as illustrated in Fig. 4E, thin conductive layers 52
and 53 are applied to the front and back surfaces, respectively, of
the substrate. The conductive layers, for example, may comprise
copper.
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1 Photoresist is then applied to the respect~ve surfaces of the substrate
2 and is selectively e~posed, with the conductive layer being stripped
3 from certain areas around the conductors as illustrated at 54 and the
4 conductive layer being left in contact with certain conductors as
illustrated at 55. This is done in a selective manner for either
6 connecting or insulating the conductive layers from respective con-
7 ductors.
8 Then, as illustrated in FIG. 4F, a fusible material such as a
9 solder alloy 56 is applied to the surface of each conductor and to the
surface of each flange. ~ thin film 57 of Au or Ag is then applied on
11 top of the solder alloy to minimi~e surface oxide formatio~. on the
12 conductors and spacers. The types of solder alloys that may be used
13 are described shortly.
14 The resultant reference plane layer is illustrated in a top
view in FIG. 5 whereln an insulating substrate 58 has a plurality of
16 conductors 59 formed therein which protrude a predeter~ined amount
17 from the depressed surface of the substrate, and which are formed in
18 a predecermined pattern, such that they may be aligned with and connec-
19 ted to conductors on a signal plane layer.
FIGS. 6A-6D illustrate an exemplary process for forming signal
21 plane layers according to the present invention. An insulating substrate
22 60 has masking layers, on the order of 1 mil thick, 61 and 62 pressed
23 into selected areas for masking on the front and back surfaces thereof
24 in accordance with the technique described in relation to FIG. 3. Again,
the insulating substrate and masking layers may comprise green ceramic
26 and polyethylene terephthalate, respectively. As illustrated in FIG. 6B,
27 a plurality of through holes 63-66 are formed through the substrate
using E-beam or
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1 mechanical drilling. Signal line patterns 67, 68 and 69 are milled
2 ' in the masking layers on the front and back surfaces of the substrate.
3 Layer joining pad patterns 70, 71 and 72 are also formed on the front
4 and back surfaces of the substrate utilizing the same technique.
As illustrated in FIG. 6C, a conductive material, for example
6 copper paste, is inserted in the through holes 64 and 65 for forming
7 conductor 73 and 74, respectively; in X line pattern 67 and Y line
8 patterns 68 and 69 for forming X line 75, and Y lines 76 and 77,
9 respectively; as well as in layer joining pad patterns 70, 71 and 72
for forming layer.joining pads 78, 79, 80, respectively. Through
11 holes 63 and 66 are left empty to serve as index holes for aligning
12 a signal plane layer with a reference plane layer when the respective
13 layers are stacked to form a multilevel interconnect system.
14 As shown in FIG. 6D, the masking layer is stripped from
each surface of the su~strate utilizing known techniques for forming
16 depressions 81 and 82, on the order of 1 mil thick, corresponding to
17 the thickness of the masking layers, and for forming flanges 83 and
18 84 in the unselected areas for maski~g. The metallized sheet is fired
19 at an appropriate temperature, depending on its composition, to transform
the green sheet into a hard densified ceramic sheet. Then, a fusible
21 material such as a solder alloy 85 is deposited on the surface of each
22 of the flanges, conductors and layer joining pads, with a thin film 86
23 of Au or Ag being applied over the solder alloy to minimize the forma-
24 tion of surface oxide.
Refer now to FIG. 7 which is a top view of a signal plane
26 layer 87 which has a plurality of conductors 88 extending therethrough,
27 which are formed in a predetermined pattern, such that they may be
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1 aligned with and selectively connected to~conductors on a reference
2 plane layer. A plurality of X lines 89, 90 and 91 on the top
3 surface are shown selectively connected to the conductors 88. Shown
4 in phantom, are Y line conductors 92 and 93 on the bottom surface
with line 92 being connected between lines 89 and 91 and with line
6 93 being connected to line 90. The X lines and the Y lines are
7 mutually orthogonal.
8 FIG. 8 illustrates an exemplary process for joining or
9 fusing the respective signal plane layers and reference plane layers
to one another. A base plate 94 has alignment pins 95 and 96 extend-
11 ing from the top surface thereof. A plurality of signal plane layers
12 97, 98 and 99 are alternated with reference plane layers 100 and 101,
13 with the index holes of the respective layers being inserted over the
14 alignment pins. ~ cover plate 103 is then placed over the stacked
layers, with the weight of the cover plates pressing the layers
16 together. The resultant assembly is heated in a reducing atmosphere
17 to reflow the solder alloy, thus joining the layers, as illustrated, at
18 the flanges 104, 105, 106 and 107 as well as fusing aligned conductors
19 and layer forming pads in the respective layers. During heating, the
solder alloys reflow and the pressure from the cover plates c~uses the
21 flanges and selected connectors to be fused together. The air gap
22 between the respective signal plane layers and reference plane layers
23 is determined by the height of the respective flanges, which, as
24 previously stated is determined by the thickness of the respective
flanges which in turn, is determined by the thickness of the respective
26 masking layers. Tables 1 and 2 below, illustrate self-fluxing alloys
27 and gold base alloys, respectively, which may be used as solder alloys
28 in the ~oinlng and fusing process set forth above.
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1 SELF-FLUXING ALLOYS
----- _ _
2 ' BRAZING T~lP. (C) ALLOY COMPOSITION (WT %)
3 880 AG 72 Cu 27.5Li 0.5 ___
4 850 AG 50 Cu 14-14.4 Zn 17 Cd 15 Li 0.;-1.0
800 AG 71 Cu 28 P 1
6730 - 750 Cu 86.5-90.5 Zn 1-3 Sn 2.5-3.5
7 650 Cu 82 Ni 13 . __
TABLE l
8 GOLD BASE ALLOYS
_
9 BRAZING TE~. (C~ ALLOY COMPOSITION (WT ,~)
. _ _ _.~
850 ¦ Au 75 Ag 9 Cu 6 Cd 10
11 830 ¦ Au 75 Cu 15 Cd 8.2 Zn 1.8 .
12 810 ¦ Au-75 Ag 7.5 Cu 7.5 Cd 7Zn 3
13 790 ¦ Au 75 Ag 9 Cu 6 Zn 10 ~ :
14 770 ¦ Au 75 Ag 2.8 Cu 11.2 Cd 9 Zn 2 :
750 1 Au 33.3 Ag 35 Cu 21.7 Cd 10
l _
TABLE 2
16 The above-described process sets forth an exemplary method of
17 fabricating a large scale integrated circuit multilayer interconnect
18 system in which the signal propagation delay is substantially reduced
19 by using air as the dielectri^ between alternated reference plane la~,~ers
and signal plane layers.
~MA/;mh
06/21/76
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