Note: Descriptions are shown in the official language in which they were submitted.
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1 BACKGRO~ND OF THE INVENTION
. . _
1. Field of the Invention
. .
The present invention relates to the ~ield of electronic
~atch circuits, and more particularly integrated watch circuits
having a plurality of operational modes.
2. Description of the Prior Art
In the coventional integrated circuit watch counters,
which also ~unction as frequency divid~rs, are used for both -
counting and storing the time ~or display. Proper carries and
1~ adjustments in regard to seconds, minutes, hours, days, months,
and years is made by means o~ gated couplings among the various
counters. For an integrated circuit watch having a single display-
such as hours, minutes, seconds, and date, this type of circuit
can be economically employed. If a stop watch or chronograph
-- operational mode is added to such a watch, or if an additional
watch display is dasired, the states of each counter must be
selectively gated to the display device by means of an appropriately
hard-wired logic circuit. As the number of operational modes
increases r the comple~ity and the number of logic gates necessary
to selectively display the states of each counter increases non-
linearly. Moreover, whenever, market demands ~or various operation-
al modes changes, the logic circuit must be redesigned. This
increases the cost and time necessary to obtain production
quantities of new watch circuits capable of satisfying new and
diverse consumer demands.
What is needed is a low cost, low power integrated
watch circuit capable o~ operating in a plurality of watch or
chronograph modes and capable of being easily modified to operate
in a plurality of selected modes.
3 BRIEF SU~D!5ARY OF THE INVENTION
The present invention is a time keeping circuit in an
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1 integrat~d circuit watch. The watch has a control means for
selectively generating an address and control signal, has a
master oscillator coupled to the control means, and has an output
means for generating an output signal. The timekeeping circuit
comprises an address decoder means ~Eor the coding of at least
part of the address and control signal. The address decoder means
is coupled to the control means. A random access memory, referred
to as RAM, is coupled to the addressed decoder means. The R~M
is responsive to the address and control signal by providing a
selected binary word from the RAM. A programmable logic array,
re~erred to as PLA, is coupled to the address decoder means.
Finally, memory control means selectively couples the selected
binary word from the RAM to the PLA and to the output means.
The memory control means is ~oupled to the RAM, PLA, and output
means. The PLA generates an output binary word in response to
the address and control signal and in response to the selected
binary word. The memory control means is also for selectively
coupling the output binary word to the RAM and to the output
means from the PLA.
~ The method of operation of the present invention
provides a means for keeping time in an integrated circuit. The
methoa comprises the steps o~ decoding a first address-and control
signal by the address decoder means coupled to the control means.
The address decoder means selectively accesses at least one cell
within the RAM to which it is coupled. The selected binary word
stored in the RAM is coupled to a memory control means in response
to the output from the address decoder means and the control
means. The selectled ~inary word is then selectively coupled from
the memory control means to the PLA, to the RAM or to the output
means.
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1 When the memory means couples the selec~ed binary word
to the PLA, the method may further comprise the s~eps of generat-
ing an output binary word from the PLA. The output binary word
assumes a predetermined reset value if the selected binary word
equals a selected predetermined limit value fixed within the
PLA. However, the outpu-t binary word is equal to the selected
~inary word plus one, if the selected binary word is less than
the selected predetermined limit value fixed within the PL~.
Finally, a second address and control signal is generated if the
output binary word generated by the PLA is the predetermined reset
value.
BRIEF DESCRIPTION OF THE DRAWINGS
FIGURE 1 is a simplified block schematic of one embodi-
ment of the presen~ invention illustrating the system ar&hitecture.
FIGURE 2 is a flow chart illustrating an operational
seguence of one embodiment having two watch display modes, four
chronograph modes and a timeset mode.
FIGURE 3 is a schematic of a typical nand gate and nor
~ate in the main PLA.
FIGURE 4 is a schematic of a typical nand gate in the
segment display decoder, and a nor gate in the segment display
ROM.
FIGURES 5a and 5b are a timing diagram illustrating a
timeset cycle, a display only cycle and a watch increment cycle.
FIGURE 6 (located on page with Fig. 9) is a schematic
of the T and 0 generator ana the first five stages of the prescale
divider.
FIGURE 7 is a schematic of the remaining porti~n of the
prescale divider.
FIGURE 8 is a schematic of the D03, D04, T2, T3, and
T4 master-slave latches and ti~ing request circuits.
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1 FIGURE 9 ~located on page with Fig. 6) is a schematic
of a control circuit for chronograph sequencing.
FIGURES 10a and 10b are a simpli~ied schematic of the
upper and lower portions respectively of the RAM, the RAM mult-
iplexers, out bus and storage means~
FIGURE 11 is a simplified schematic of the Main PLA,
flag flip-flops and~PLA output bus.
FIGUR~ 12 (located on page with Fig. 15) is a schematic
of the calendar correction circuit.
1~ FIGURE 13 is a simplified schematic of ~he display ROM,
nand decoder and output multiplexer.
FIGURE 14 (located on page with Fig. 26) is a simplified
schematic of the digit scan counter, decoder, and segment decoder.
FIGURE 15 (located on page with Fig. 12) is a schematic
of the watch sequence counter and chronograph sequence counter.
FIGURE 16 is a schematic of the master control circuitry
associated with switched Sl and S2, i.e., the watch state counter.
FIGURE 17 is a schematic of the master control circuitry
associated with switch S3, i.e., the chronograph state counter.
FIGURE 18 is a simplified schematic of the time-set PLA
and associated circuitry.
FIGURE 19 (located on p~ge with Fig. 30) is a logic
equivalent schematic ~or the chronograph PLA.
FIGURE 20 (located on page with Figs. 21, 22 and 25)
illustrates the inputs and outputs for the logic circuit for alpha,
numeric A and numeric B.
FIGURE 21 (located on page with Figs. 20, 22 and 25)
illustrates the inputs and outputs for the logic circuit of chron
A, Chron B, and watch I/O.
FIGURE 22 (located on page with Figs. 20, 21, and 25)
.
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l illustrates the inputs and outputs for the logic circuit for the
colon drive.
FIGURE 23 is a schematic for the debounce generator,
debounce circuits and CYCLEC generator.
FIGURE 24 is a schematic for the master reset generator
and the fast test generators.
FIGURE 25 (located on page with Figs. 20, 21 and 22)
illustrates the inputs and outputs to the voltage converter.
- FIGURE 26 (located on page with Fig. 14) is a
schematic for the initialize reset generator.
FIGURE 27 is a schematic for the segment driver latches.
FIGURE 28 is a schematic for the nand decoder, nor ROM
and multiplexer for the segment drivers.
FIGURE 29 is a schematic of a typical segment driver,
a typical D.C. latch and il~ustrates the inputs and outputs to
the segment drivers.
FIGURE 30 (located on page with Fig. l9) is a schematic
of the segment voltage generator.
DETAILED DESCRIPTION OF THE PRE~ERRED EMBODIMENTS
The present invention is a digital watch circuit
fa~ricated on one or more integrated circuit silicon chips. The
logic circuit employs complex logic techniques in order to in-
crease flexi~ility and reduce chip si2e over the prior art approach
for a ~atch having the same number of operational modes. Time
storage and time increment functions are separated to allow a
random access memory (hereinafter referred to as RAM) to be used
for time storage and a programmable logic array (hereinafter
referred to as PLA) to control time counting. A static RAM is
used for storing tlle states of the time digits. For the purposes
30 of illustration only~ the present RAM is organized into 16 words ~ ~ -
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1 of four bits each for the watch storage. Sixteen four bit words
may be used for chronograph A count and storage/ and eight four
bit words are used for chronograph B storage. The PLA employs a
nand-nor logic configuration utilizing dynamic techniques to
permit single device arrays. As will be discussed in greater
detail below, in the present embodiment, the PLA has sixteen inputs,
ten outputs and forty-eight minterms.
SYSTEM ARCHITECTU~E
The overall operation and general organization of the
present invention is illustrated by the block diagram of Figure 1.
The time standard of the clock circuit is a master oscillator 40
having a frequency of 32,768 H~. Oscillator 40 is a crystal
controlled os~illator well known to the art and may have an
accuracy of 2ppm. Oscillator 40 is on the same chip as the re-
maining portion of the circuit with the possible exception of the
crystal and certain external passive devices. Any time standard
well ~nown to the art may be employed.
Oscillator 40 couples its output into a prescale divider
circuit 42. Prescale divider circuit 42 divides the time standard
~ of 32.768 kHz down to 1 Hz, 10 Hz and several other intermediate
frequencies. These frequencies provide the fundamental clocking
signal for timekeeping and a plurality of internal clocking signals
for internal control and sequencing. The frequencies will be
descri~ed in greater detail in connection with the remaining ~-
circuitry. Again, any prescale divider circuitry wèll known to
the art may be employed, and it is to be understood that the
present invention is not limited by the particular embodiment of
prescale divider circuit 42 illustratPd.
Prescale! divider 42 provides a series of frequencies
required by timing generator and mastex control circuit ~4
(sometimes referred to as timing and control circuit 443. Timing
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1 generator and master control circuit 44 is a central element of
the clock circuit used to coordinate the operation of the various
circuit elements. Timing and control circuit 44 has one or more
mechanical switches, Sl - S3, as user inputs and has one or more
internal inputs as feedbacks from other circuit elements. The .-
particular operational function, whether display, timeset, counting
or storage, is timed and controlled by timing and control circuit
4~. The details of timing generator and master control circuit
44 will be described in relation to Figures 6, 8, and 16 - 26O
1g Timing and control circuit 44 is coupled to a RAM address
generator 46. In one embodiment of the present invention RAM
address generator 46 includes a display sequence, programmble
read only memory (ROM) 54. Display seguence ROM 54 generates the
binary addresses of variouswords retained within the storage RAM.
The RAM addresses will be read from ROM 54 according to instruct-
ions received from timing and control circuit 4~ through a decoder
48. Various RAM words, which are to be displayed according to a
preselected display format, are read from ROM 54 by means of a
. digit scan circuit 52. Digit scan circuit 52 generates at least
- ~V one control signal in response to timing signals received from
- timing and control circuit 44. The output of digit scan circuit
52 is coupled to ROM 54 through decoder 48 and is also coupled to
display drivers 56. Thus, display of the output digits is :
synchronized with the generation of RAM addresses.
In othex embodimen~s of the present invention, RAM
address generator 46 may also include one or more sequencing
circuits For example, in Figure 1 RAM address generator 46
includes a watch sequence circuit 58, a chronograph sequence ~:
circuit 60, and a time delay circuit 62. Watch sequence circuit
58, chronograph sequence circuit 60 and time delay circuit 62 are
,
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1 each coupled to and controlled by timing and control circuit 44.
Each circuit appropriately generates an additional address or
addresses which are required for selected operational modes of
the ~atch. The operation and detail of each of these circuits
will be described in reference to Figures 13 - 15. In the preferred
embodiment, RAM address generator 46 includes multiple sequencing
circuits.¦ In order to conserve silicon chip space, the output of
each sequencing circuit of RAM address generator 4~ is read onto
a single address bus through a corresponding plurality of mult-
iplexing circuits, i.e. display sequencing ROM 54 is read onto
address ~us 64 by multiplexer 50, watch sequence counter 58 by
multiplexer 66, chronograph sequence counter 60 by multiplexer
68 and time delay counter 62 by multiplexer 7~.
The incrementing and storage functions of the present
invention are performed by RAM 72 and PLA 74. Address bus 64 is
coupled to an address decoder 76. Address decoder 76 is couplea
both to PLA 74 and RAM 72. Table 1, below, maps the location of
each word within RAM 72 in correspondence to Figures 10a and 10b.
In the embodiment illustrated, RAM 72 has sixteen locations for
~ four ~it words which are associated with the watch storage and
count. RAM 72 also has eight locations for four bit words
associated with the count of chronographs A and B. Similarly,
RAM 72 has eight locations for two four bit words associated with
the storage of chronographs A and B. In the present embodiment only
chronograph A count and chronograph B store portions are used.
Additional storage locations, organization, and word sizes may be
`employed b~ the present invention without departing from its
splrit or scope.
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1 TABLE 1
LOCATION CHRONOGRAPH CHRONOGRAPH
WATCH COUNT STORE
.
o 10 1/10 seconds 1/10 seconds
1 seconds units seconds units seconds units
2 seconds tens seconds tens second tens
3 minutes units minutes units minutes units
1~ 4 minutes tens minutes tens minutes tens
5 hours units .
6 hours tens -
7 AM/PM
8 DOM UNITS C
9 DOM TENS F
10 MONTH UNITS L
11 MONTH TENS P
: .
12
13
~ 14 :
15 time delay ;~
RAM 72, as illustratad in Figures 10a and 10b, has the capacity ~: .
for a full watch count, cou~nting from seconds to year and a .:
chronograph count, counting and storing for, example, from one- .
hundredth of a second to 99 hours. In the present e~bodiment the .
watch storage is preceded with one divide-by-ten prescale. This
location of the watch storage could be labeled, 1/10 seconds ~
tenths,as for chronographs A and B, and is provided only so that
prescale divider circuit 42 is required to generate only a single
10 Hz signal to dr.ive both the watch and chronographs. If desired
the first RAM location for the chronographs and watch could have
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1 been chosen as 100 Hz, if such a frequency were provided by
prescale divider circuit 42. The word labeled, "time delay"
is provided so that fixed delays can be generated. In the present
embodiment a single time delay of ten seconds is provided,
although the present invention could provide multiple delays of
nearly ar~itrary length.
The general operation of the present invention may now
be understood. One or more predetermined control signals will be
generated~by timing and control circuit 44, which may depend in
part upon the switch inputs, Sl - S3. In response to the timing
and control signals from timing and control circuit 4~, RAM address
generator 46 will produce the appropriate R~ address.
Consider, for example, the normal time incrementing
operation of the watch. According to a preselected control
signal, initiated by oscillator 40 and coded by t~ming and control
circuit ~4, the RAM address of location, "O", of the watch storage
will ~e accessed. The contents of location "O" of the watch
storage is coupled by multiplexer 78 onto a common data bus 80.
The contents will ~e stored in a storage means 82. At the
~ appropriate time, the contents of storage means 82 is read into
PLA 74 and compared to a preselacted limit value. The appropriate
limit value is selected in PLA 74 in response to PLA inputs from
by address decoder 76 and timing and control circuit 44. If the
contents of the word read from storage means 82 is less than the
-corresponding selected limit value the data word will ~e incremented
by one and ~ed back by a feedback data bus 84 at the appropriate
time into location "O" of the watch storage. In the case of the
location "O" of th,e watch storage, the predetermined limit value
will ~e 9. When the contents reach 9, the PLA will generate an
increment flag, INIC, which is fed back into timing and control
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1 circuits 44 be feed~ack line 86. The contents of location "O"
of the watch storage is reset to zero and the contents of
location "1" of watch storage, incremented by one and stored in
R~M 72 at location "1"1 In this manner, a cumulative count is
maintained for seconas, minutes, hours, AM or PM, the da~ of the
week, months, and year. The calendar correction provided by
circuit means 68 is for generating additional PLA inputs for the
varying number of days in each month.
According to which switch inputs, Sl - S3, are selected
1~ timing and control circuit 44 will generate various other control
signals which will selectively activate display sequence ROM 54,
chronograph sequence counter 60 and various timese~ting circuitry.
During the display mode, data from RAM 72 and PLA 74 will be
seiectively coupled to decoder 90. Again, according to the
switch inputs and control signals generated by timing and control
circuit 44, one of the plurality of segment fonts may be chosen
from a segment font ROM 92 which will sequentially activate
selected indicia members associated with display driver 56 which
is ~lso controlled by digit scan 52. In the present embodiment
2~ only two of three possible fonts are used~ although the capability
of generating more fonts than three is within the scope of the
present invention.
It may now be appreciated that the control and
cooperation of the various elements of the present embodiment is
organized a~out the timing scheme generated by timing and control
circuit 44. The function to be performed within each timing
interval will be described below.
THE MAIN RAM AND PLA
Various timing schemes may be chosen according to the
functions which the clock is to perform. Any logic value systemJ
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1~7~32
1 positive, negative, or inverted, well known to the art, may he used
in the present invention. In the illustrated embodiment it will
~e assumed that logic values are true when high or one, and false
when low or zero. However, each timing scheme must be ~ased upon
the operation and the specific functions to be performed ~y R~M 72
and PLA 74. The primary function of RAM 72 and PLA 74 is time
storage and time incrementation. In the present embodiment, a
static RAM, and a nand-nor dynamic PLA is used to control time
counting to various ~ases. RAM 72 uses an eight transistor cell
for each bit as illustrated and described in relation to Figures
lOa and 10~. In the present em~odiment, 160 such cells are organized
into 24 words, each having a four bit length. Timing and control
circuit includes a ~ generator and a T generator. The ~ generator,
as described in more detail in relation to Figure 6, generates at
least four distinguishable ~ clock intervals, i.e., ~l - 04. Clock
signals D~3 and D~4 are generally equivalent clock pulses ~3 and
~4, except that D03 and D~4 are inhi~ited during a disPlay-only -~
mode while ~3 and ~4 remain active. Each 0 interval is 30 micro-
seconds long. Thus, the ~ generator has a complete cycle of 120
microseconds. A complete cycle of ~ pu~ses is provided each time
an incremented data is stored in RAM 72 or a display of the data
is required. At all other times the 0 generator is inhi~ited by
appropriate control signals within timing and control circuit 44. -
The first ~ clock signal, ~1, is used to precharge all
dynamic logic nodes within the watch circuit. Thus, as illustrated
in the timing diagram of Figure 5, clock ~l is high at all times
other than during clock signals ~2 - ~4.
A typical PLA nand and nor logic array is illustrated
in Figure 3. The PLA nand is comprised of a series circuit of
~.
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1~74:~32
1 P channel or enhancement MOS devices.
In the PLA nand illustrated as an example, twelve
series P-type devices are employed. The number may be increased
or decreased according to the minterm desired as the output of
the PLA nand~ Each PLA nand will have a series P-type device
96 controlled by a clock signal, which is usually D~3. Thus,
the PLA nand is active whenever clock signal, D03, is low or
false. In the example, four additional series P-type devices
98 - 104 are controlled by the RAM address word. Similarly, an
additional four P-type devices, 106 - 112, are controlled by the
RAM data word stored at storage means 82. Additional P-type
devices, denoted collectively by the reference numberal 114, may
be coupled in s~ries in the PLA nand and controlled by various
control signals according to the minterm output desired. An
N-type precharge device 94 is coupled between the output of the
PLA nand and ground. Precharge device 94 is controlled by pre-
charge clock signal, 01. Similarly, the PLA nor is a standard
nor gate, well known to the art, comprised of parallel N-channel
gates, and are collectively designated by the reference numeral
116. Each of the N-type devices 116 couples the output of the
PLA nor to ground according to the output minterms coupled to
their respective gates. Similarly, a precharged P-type device
118 couples the output of-the PLA nor to the power supply and is
controlled by the precharge clock signal, 01.
In order to avoid possible charge sharing problems in
the PLA nand array, each input of the PLA nand, with the exception
of the RAM addresses AO.- A3 and their complements, are forced
low during clock interval 01. With the exception of P-type
devices 9~ - 104, this turns on all the P-type devices in the
nand array and distributes the precharge or low potential
13 !.
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1 throughout the entire array. During clock signal, 01, RAM
addresses A0-A3 and their complements are changing and reach
a valid state at or before the end of clock interval, 01.
Typically, there is no charge sharing problem created by the
RAM address inputs since they remain stable and are stored until
the following pulse of clock, 01.
As will be shown in greater detail below, RAM 72 is
accessed during clock pulse 02 when decoder 76 is enabled.
Referring now to Figure 10a, it may be seen that one of the six-
1~ teen RAM access lines is pulled high by decoder 76 at pulse clock~2 and the data in the RA~I is read through multiplexer 78 onto
R~M data bus 80. As illustrated in Figures 5a and Sb which are
drawn to the same time scale RAM address bus 64 goes valid ~efore
clock pulse, 02, remains valid through clock pulse, 03 and ~,
and begins to go invalid during clock pulse, 01. At the same
time as RAM decoder 76 is accessing RAM 72, the PLA nand inputs
AO - A3, are set in a valid state.
Each memory cell in the RAM is a CMOS latch co~mprised
of a first an* second inverter having a gated feedback loop.
2~ As shown in Figure 10a the cell is gated to one column to the
array of RAM 72 by a CMOS transmission gate coupled to the cor-
responding row of RAM 72. The store bit in each memory cell
will then be read out whenever the RAM access line at the
cGrresponding location goes high, i.e., during 02. Therefore,
it is possible that 3 RAM words may be simultaneously presented
to multiplexer 78 (WATCH, CHRONOGRAPH COUNTER, CH~ONOGRAPH STORAGE).
Multiplexer 78 is illustrated in Figure 10b by three separately
contxolled multiplexers, each consisting of four CMOS trans-
mission gates. The appropriate RAM word is selectively coupled
to the four line RAM data bus 80 by selective application of amultiplexer control signal, watch I/O, chron A or chron B. The
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1~7~132
1 selected RA~I data word read onto data bus 80 is coupled through
inverters 120 to CMOS transmission gates 122 where the data
word is stored during clock pulse, 02, by means of dynamic
storage of transmission gates 122.
The RAM data word i5 denoted collectively by the
varia~les MO - M3 at the PLA side of transmission gates 122.
as shown in Figure 11. The transmission gates, having been
precharged by P-type devices 124 lFigure lO~), during clock pulse,
~1, are then coupled through inverters 126 (Figure 11) to a series
of nor-gates 128. Nor gate 128 will serve to inhibit RAM data
word, MO - M3, whenever clock signal, ~1, is high, and will
invert and couple the RAM data word into PLA 94 whenever clock
signal, 01 is low. Storage means 82 may be conceptualized as
being comprised of inverters 120, transmiss.ion gate 122, pre-
- charged devices 124, inverters 126, and nor gates 128. Other
`configurations for storage means 82, well known to the art, may
~e employed without altering the scope of the present invention.
During clock pulse, 02, all the remaining PLA nand
inputs also ~ecome valid and remain valid until the ~e~inning of
~ the next ~1 clock pulse. Thus, during clock pulse 02, as
illustrated in (Figures 5a and 5b), the RAM address PLA inputs,
AO - A3 and their complements, the PLA inputs "28", 'i30/31",
"31", "12", and "24" become valid. Thus, the RAM data word,
MO - M3, is coupled to the PLA nand array during clock 02.
: The full clock period, D03, is allowed for comple~e :
access through the PLA. This clock period allows the P-type
nand gate to pull high if all of the inputs are low. The
corresponding no:r gates will pull low if they have any input
connected to a h.igh going nand gate. As shown in Figure 5b,
during clock pulse, ~3, and 04, PLA flags Kl - K3 and their
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1 complements become valid. Kl - K3 and their complements are each
generated from the output of the PLA nor array by means of in-
verters 130 and 132 and divide by two flip-flops 134 (Figure 11).
The output of flip-flops 134 are reinserted into the PLA nand
array through P-type transmission gates clocked by clock signal
~2. Thus, as illustrated in Figure 5b, PLA inputs are valid
during clock signals, 03 and ~4.
During clock signals D04 the PLA output data, D0 - D3
~Figure 10b), may be written back into RAM 72 at the same po-
sition that was accessed for read out. The PLA output data isfirst gated through N-type transmission gates 138. N-type
transmission gates 138 are controlled by the output from nor
gate 140. Nor gate 140 has as its input, a STORE signal and
D~4 clock ~hich are generated by timing the control circuit 44.
Once gated through transmission gates 138, the PLA data outputs
are transmitted along data feedback bus 84 which was precharged ;
during clock signal, ~1 by P-type precharging devices 142 (Figure
10b). The PLA output data then serves as an input to CMOS
inverters 144 which have a valid output during, D04. The
appropriate multiplexers still remain valid and the PLA output
data is written into the original cell in RAM 72 which is un-
latched during D04.
It is also possible, for example, during chronograph
operation that the PLA input data, M0 - M3 may be read onto
feedback data bus 84 through N-t~pe transmission gates 146
~Figure 111. Transmission gates 146 are controlled by the out-
put from nor gate 148. Nor gate 148 has the output of nor gate
140 and clock pu:Lse, D~4j as inputs. Therefore, nor gate has a
; low output, and ~ates 146 are off, at all times except when D~4
is low and STORE is high.
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1~74~3~ .
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.. _ _ ._ . . I
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c~ ;~; . - -- -. . .
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- :.. .. . . . . ... . ; . .: , .. : . .. , - . -:.. :. .. . . : . :... : . . .. .:
.. , .. . . . .. .. . . . ~ .... . .. . .. . . .
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1~7~3;~
1 TABLE 3
12 HOUR MODE ~ ~
SECU SECT ~lINU MINT HRU HCT AMjPM MNU MNT
. __ _ _ _ _
A A A A A B A V B A
B B B B B N XX X AA B
C C C C C O S V D A
D D D D D E A E
E E E E E F F .
F F K F L G G
G G A H A I H
I I J J J
J J . J A A
A A A B&WW B
W BB
. B B .
'`
23 DAY 30 DAY 31 DAY
.
DTU DTT DTU DTT DTU DTT
_ .. . _
FF A FF A FF A
C B C B C B
D LL D SS D TT
E A E UU E UU
F F A F A :
G . G G
H H H .
HH HH _ HH _ :: ; :
. .. _ ~ - -- : ,
~ -17-~-
- "
:
'7~32
1 TABLE 3 CONTINUED
28 DAY 30 DAY 31 DAY
' t ~ O'll` +~ o~r = ¦
~ A ~ A
:
~ -17..9~
: . - - - . ` .
- . ~ ` .
1~74~3Z
TABLE 3 CONTINUE~D
2 4 HOUR MODE
::
-17- ~h-
1~7~
The remaining PLA outputs are used to drive the flags
Kl - K3 and their complements and, in the case of a carry, to
generate the carry signal, INC, which is used in timing and
control circuit ~4.
Tables 2 and 3 ~ay be read in conjunction to specify
the configuration and arrangment of the PLA nand-nor array. For
example, consider the watch function. As counts are stored in -
location "O" corresponding to the word, 10, the minterms
A - J are generated in the cycle and sequence listed in Table 3.
T~e nand gate of the PLA nand array, which outputs the minterm A,
will have as its series gating devices correspvnding to P~type
devices 96 - 114 of Figure 3 coupled to the RAM data word, MO -
M3, and RAM address 0000, so that the devices are conductive
and minterm A is generated whenever the RAM data word is 0000
as shown in Table 2. Another series of similar P-type devices
having a RAM address corresponding to the RAM location for AM/PM,
i.e., 0101, will form a precharged nand gate similar to that
illustrated in Figure 3. This nand gate, not shown, acts as an
inhibit gate which will have a true output during ~2. The out-
~ put of the inhibit gate is coupled to an additional series P-
~ype device which is included in each of those minterm nand
gates controlled by an inhibit term shown in Ta~le 2. During
01 the inhihit and minterm nand gate will go false ~y virtue of
device ~4. During ~2, if the inhi~it term is addressed, the
in~i~it gate goes true, turning its corresponding P-type device
in the minterm nand gate off, leaving the minterm false. During
D~3 the nodal capacitance of the inhibit gate keeps its output
true so that the nand output remains false even if the corre-
sponding nand gate were addressed by AO - A3 or MO - M3 or both.
Multiple inhibit gates can be or-ed ~y coupling their outputs
to a single P-type device in the nand gate.
' ~
-18-
' ~ - . ? `
3L~7~3Z
1 Finally, the PLA nand may have a P-type device which
is gated on by an internal control signal, e.g., resets seconds,
RSC or the signal intialize sequence, MR, which serve to inhibit
the nand gates during selected internal timing sequences as
discussed below.
Consider for example the nand associated with minterm
A which has an outputcoupled to a gate of a PLA nor gate having
the PLA output DO. Minterm A is associated with the first
n~ber in any counting sequence, namely RAM data word OOOO.
None of the PLA nor gates having the PLA outputs, D3 - Dl, will
have minterm A controlling any of their parallel N-type gating
devices 116. Therefore, as previously discussed in connection
with Figure 3, the output from the PLA nor gate corresponding
to DO will be zero while the outputs ~rom the PLA nor gates
corresponding to ~3 - Dl will remain true. The desired number,
D3 - DO, is 0001 which is the next incremented binary number in
the counting sequence.
The output of the PLA will be fed back through feed-
hack data bus 84 and inverted by CMOS inverters 144 (Figure lOb~.
The ~ord, D3 - DO, will ba read onto RAM data bus 80 and presented
to multiplexers 78 to be rewritten into the appropriate RAM cells
during D04. On the next group of 0 cycles, the RAM data word
0001 will then be read out of the same cell, as long as the same
cell is addressed, and the PLA nand, having the R~M data word
M3 - MO, corresponding to 0001 will ~e selected in combination
will the various internal 1ags and inhibit terms to produce a
PLA output corresponding to minterm B~ The appropriate PLA nor
gates will be act:ivated to produce the binary num~er 0010 at data
bus 80 which will be stored in the addressed cell. The sequence
is repeated for each address location in RAM 72 through the
'
.
--19--
. ,~ , . . .
~7~3Z
1 minterms as illustrated in Ta~le 3. When the minterm J is
generated ~y the appropriate PLA nand-nor gates, a carry flag
INC, will be generated and the RAM data word at bus 80 will be
reset at 0000 as shown in Table 2. Referring to Table 3, the
same sequence can be observed for a second unit, SECU, and
minutes units, MINU.
The counting sequence for seconds ten, SECT, is
identical to that of the seconds units, SECU, through minterm
E. After minterm E is generated, the word 0101 will have ~een
written into the RAM cell corresponding to the RAM address
seconds tens. When the ~inary word, 0101, is again presented
to the PLA nand, the RAM address corresponding to seconds tens
will also be coupled into the PLA array through decoder 76.
Thus, the PLA nand corresponding to minterm F will be inhihited
~y the presence of the RAM address seconds tens. The PLA nand-
nor which will be activated ~y the ~AM address seconds tens,
will cause the output minterm K to be generated as shown in
Table 2. The output of minterm K is accompanied by the
generation of the carry flag, INC, and resetting the ~AM word,
D0 - D3 to 0000 as shown in Table 2. Similarly, the minutes
units and tens, hours units and tens, and whether in the 12 or
24 hour mode, months units and tens, 28 day, 30 day, or 31 day,
shown in tables 3 - ~ may similarly ~e analyzed.
K FLIP FLOPS AND CALENDAR CORRECTION CIRCUIT
The flags Kl - X3 are used to record the condition of
various count states within PLA 74. The output of flip-flop
134 (Figure 11) will ~e set to one whenever months tens is zero
and will be reset to zero when months tens is one. Thus, K3
controls the months units. When months tens = 0, K3 = 1 so
that month units go from 2 to 3, ~ut when months tens = 1, K3 = 0
-20-
.
~i74~L3Z
so that months units will go from 2 to 1 as months tens are
reset, i.e., the months will go from 0~ to 03 when K3 = 1 and
from 12 to 01 when K3 = O.
Similarly, the Kl flip-f:Lop 134 will control the hours
count, If the watch is optiOned to run on a 12 hour base, Kl
flip-flop will be set, Kl = 1, when hours tens goes to one and
reset, Kl = O, as hours tens is reset to zero. Thus, when Kl =
O hours units goes from 2 to 3, but when Kl = 1, hours units will
go from 2 to 1 as hours tens is reset. A watch optioned to
~ count on a 24 hour base will cycle Kl in analogous manner.
¦The R2 flag is used to control data counts. The K2
~lip-flop is comprised of a nor latch 131 and a nand latch 133
(Figure 11). As date tens is incremented from 1 to 2 (minterm
CC~ latches 131 will be set lK2 = 1). The K2 latch is set on
the date 24. Any date between 22 and 27 could have been selected
to appropriately flag a 28, 30, or 31 day month and to permit
months to be timeset to February while the date was held constant.
The date 24 is chosen only as a matter of convenience to minimize
the number of input bits in the PLA minterm. Latch 133 will not
2~ be set since its reset and set terminals are normally held true
b~ the output of minterm DD. However, when date units go from
4 to 5, the output from minterm DD will go false and latch 133
will be set thereby resetting latch 131. If the watch is in a
28 day month, flag K2 will ~e reset when date units go from 8
to 1 and the date tens forced from 2 to 1. Flag X2 will be
analogously reset for 30 and 31 day months, so that when date
units go to one, date tens will go from 3 to 0.
Calendar correction circuit 135 generates the PL~
inputs 28, 30, and 31 accord~ng to the appropriate number of
days in a month as shown in Figure 12, the inputs to circuit 135
-21-
.: - :
.' ,
- . . -: ~ . :
L3'~
1 are the PLA inputs M0 - M3 and the PLA outputs MNTHU and MNTHT.
During clock D04, MNTHU and MNTHT, which are true whenever the
months units or months tens respectively are incremented, turn
on transmission gates 137 and turn off transmission gates 139.
The contents of the RAM words DOMU (MO - M3) or DOMT (MO) are
written into storage cells 141. Cells 141 store the data when
DO4 goes false. Thus, storage cel:Ls 141 keep a running record
o~ the number of the month which is current.
The stored values of MO - M3 for DOMU and MO for DOMT
are coupled to a logic circuit which includes nand gate 143.
The inputs to nand gate 143 are MO, Ml, M2, and M3 for DOMU and
MO for DOMT. Since the months are coded beginning at 0 for
January to 11 for December, nand gate 143 will be true at all
times except when DOMU = 0001 and DOMT = O~ or during February.
Therefore, the output of nand gate 143 is the PLA input 28 and
its inverse is 30/31.
The remaining logic circuitry is a complex CMOS
inverter which will go false when M3, M2, Ml, M0-are in any of
the states OXXO, XllX, lXXl for DOMU, or XXXl for DOMU and 1 for
~ MO, DOMT, where X is a "don't care state". The inverter is true
~or all other states so that the output is 31. Clearly, acti-
vation of 30jil without 31 indicates a 30 day month.
PRESCALE DIVIDER CIRCUIT
Prescale divider circuit 42 and a portion of timing
and control circuit 44 is illustrated in Figures 6 - 7. Prescale
di~ider circuit 42 generates a plurality of driving signals for
the watch. Oscillator 40 generates the timing standard, 32768
Hz ~hich drives prescale divider circuit 42. Four synchronous
D type flip-flops, shown in Figure 6, form the basis for a
synchronous counter which drives the ~ and T generators described
below.
- -22-
~.
-
~i~74~L3Z
1 The master clock frequency 32.768 KHz sLmultaneously
clocks the first two flip-flops 178 and 180. The Q output of
flip-flop 178 is coupled to the D input of flip-flop 180. The
Q of flip-flop 180 is fed back and coupled to the D input of
flip-flop 178. Assuming that the initial state of the flip-
flops can be represented ~y the binary number 00, flip-flops
178 and 180 cycle through the colllecti~e states 00, 10, 11, 01,
and then 00 again with each pulse of the 32 KHz clock. The
master clock pulse has gone through four complete cycles during
the same time in which the outputs of flip-flops 178 and 180
have gone through one complete cycle. Therefore, the frequency
at the outputs of flip-flop 178 and 180 is 8192 Hz.
Nand gate 182 has three inputs. The inputs to nand
gate 182 are: the Q output of flip-flop 180; the Q output of
flip-flop 178; and the master clock pulse. The output of nand
gate 182 will always ~e true except when the Q output of flip-
flop 180, the Q output of flip-flop 178 and the master clock
pulse are simultaneously true. This coincidence occurs only once -~
during four cycles of the master clock because the output of flip-
~ flop 178 is shifted in time by one clock cycle, i~e., 3~ micro-
seconds from the output of flip-flop 180. Thus, the output of
nand gate 182 will have a frequency equal to 8192 Hz and a pulse
width equaled to the pulse of the master clock, i.e.,
approximately 15 microseconds.
D type flip-flops 184 and 186 are coupled with each
o~her in the same manner as are flip-flops 178 and 180. There-
fore, the outputs of flip-flops 186 are each one fourth of the
corresponding clock fre~uency applied to these flip-flops, or
2048 Hz. Flip-flops 178 - 186 are synchronized so that transient
false outputs may be eliminated from their outputs, which outputs
.. . : . . :. ..
. . . ...
~L~74~3Z
1 are coupled to the ~ and T generator described below.
Flip-flop 186 is followed by three asynchronous flip-
flops 188 - 192 (Figures 6 and 7). Flip-flops 188 - 192 act as
a three bit counter and will divide the frequency from 2048 Hz
down to 256 Hz by binary steps. Thus, the output of flip-flop
188, which is coupled to CMOS gate 194 and which is used as a
cali~rating output, is 102~ Hz whic:h, as will be shown, is also
used as a driving signal for the debounce circuitry of Figure 23.
The output of flip-flop 190 is 512 Hz and the output of flip-
~O flop 192 is 256 Hz (Figure 7). As will be described below the
256 Hz output is used in the clock as an internal fast test
signal for the integrated circuit chip.
A 10 Hz signal is used to initiate the time advancesfor the watch and stop watch which are resolved to within 0.1
seconds. The 10 Hz signal is derived from the 256 Hz signal
~y deleting every sixteenth pulse to produce a 240 Hz signal.
The 240 Hz signal is divided again ~y three binary orders of
magnitude to a 30 Hz signal which is finally divided by divide-
` ~y-t~ree counter to produce the desired 10 Hz timekeeping signal.
; 20 A 256 Hz signal and its complement is taken from
flip-flop 192 and provided as the clock inputs to the first of
four asynchronous flip-flops 196 - 202. Thus, the output of
flip-flop 196 is 128 Hzj the output of flip-flop 198 is 64 Hz;
: the output of flip-flop 200 is 32 Hz; and the output of flip-
flop 202 is 16 H~. The output of each of the flip-flops, 196-
202, is provided as an input to the gate 204. And gate 204 also
has as one of its inputs the output of nor gate 206. Nor gate
; 206 has as its inputs, the Q output of flip-flop 178 and the Q
output of flip-flop 180 ~Figure 6~. Thus, the output of nor
30 gate 206 i5 alway~s zero except when the Q outputs of flip-flops .
,
7 ~ 3Z
178 and 180 are simultaneously false. Thus, nor gate 206 will
have an output frequency of 8192 Hz and a pulse width defined
by master clock 40, i.e., approximately 30 microseconds. There-
fore, and gate 204 will generate groups of 64 pulses, each
having a 30 microsecond width, with a 16 Hz group repetition rate.
Nor gate 208 also has as its inputs the input from flip-flops
196 - 202 and the 8192 Hz from nor gate 206 thr~ugh inverter 210.
Nor gate 282 will therefore also generate groups 64 pulse, each
~ith a 30 microsecond width with a 16 Hz group repetition rate,
1~ but displaced in time from the output of and gate 204.
- The output of and gate 204 is coupled to the reset
terminal of an R~ nor latch 212 The output of nor gate 208
is coupled to the set terminal of latch 212. The outputs of
nor gate 208 and gate 204 are shifted in time such that there is
never a coincidence between the two. The output of latcn 212 is a
negative 16 Hz signal with a pulse width of approximately 8
milliseconds (lf2 oiE a period of the 256 Hz signal).
The output of latch 212 is coupled, together with the
output o~ flip-flop 192 to the inputs of nand gate 214. On
~ every sixteenth cycle, the output of latch 212 will simulta-
neously be high with the output of fIip-flop 192. Thus, the ~-
output of nand gate 214 will follow the output of flip-flop 192
on every pulse except one each sixteenth pulse, whic~ will be
deleted. Therefore, the input clock signal to asynchronous
flip-1Op 216 wi]Ll be a signal with a frequency of 240 Hz.
The 240 Hz signal will then be divided by one binary order of
magnitude each by flip-flops 218 and 2200 Thus, the output
frequency from iElip-flop 220 will be a 30 Hz signal. ~;
Flip-~Elops 226 and 228 are D type flip-flops which
form the basis oiE a divide-by-three counter. Flip-flops 226
and 228 are each clocked by the 30 Hz input signal from flip-
-25-
\
~74132
1 flop 22~. The Q output of flip-flop 226 is coupled to the
D input of flip-flop 228. The Q output of flip~flop 228 is
fed back through nor ~ate 230 to the D inpu-t of flip-flop 226.
The other input of nor gate 230 is derived from the Q output of
~lip-flop 226. Therefore, the states of flip-flops 226 and 228
may ~e characterized by the binary num~ers 00, 01, 10, and then
again 00 on each clock pulse. Thus, the output of flip-flop 228
is a 10 Hz signal.
The Q output of flip-flop 228 is coupled to the clock
1~ terminals of flip-flops 232 - 236. Flip-flops 232 - 236 are
D ~ype flip-flops which form the basis of a divide-by-five
counter to produce a 2 Hz output signal which is used as an
option for timeset frequency and as frequency of diyit flashing
in the timeset mode. Flip-flops 232 - 236 are combined in
su~stantially the same manner with respect to their D and Q
terminals as the D type flip-flop counters previously described.
`The Q output of flip-flop 236 and Q output of flip-flop 23~ are
cou~led to the inputs of a nor gate 238. The output of nor gate
23~ is coupled to the D input of flip-flop 232. Therefore,
2n flip-flops 232 - 236 are sequenced through a five count pattern
and the output of flip-flop 236 is one fifth the clock frequency,
i.e., 2Hz. The output of flip-flop 236 is in turn coupled to
the clock inputs asynchronous flip-~lop 240 which divides the
2 Hz frequency to a 1 Hz frequency. The 1 Hz signal is used for ;
driving the colon in normal displays and is the frequency counted
by the delay logic when generating a ten second delay, and as an
option for timeset frequency and as frequency of digit flashing
in timeset mode. -
The ou~put of flip-flop 192 is also coupled to three
series asynchronous flip-flops 242- 246. The output of flip-flop
-26-
- .
.
.
- 1~7~
1 246 is thus a 32 Hz signal which is coupled to the input o~ nor
gate 248. Nor gate ~48 has as its other input an internal con-
trol signal, LTINV, which is the lamp test initiate voltage.
Whenever the signal, LTINV, is low, the 32 Hz signal is gated to
~he liquid crystal display (LCD) circui~yas will be described.
Otherwise, the 32 Hz signal to the display is inhibited. It is
necessary to strobe the LCD with a :low frequency voltage in order
to maintain stability and longevity of initial threshold values
of the display.
~) T AND 0 GENERATORS
The lO Hz signal from the Q output of flip-flop 228 i9
coupled to control circuitry for the T and 0 generators as shown
in Figure 6. Consider the generation of each signal, Tl - T4.
The timing signal Tl is the output of nor gate 250. Nor gate
250 has as its inputs the Q output of flip-flop 184, the Q output
of flip-flop 186 and internal control signal select display,
DISP, which can be used to inhibit the output from nor gate 250
but is not used in the present em~odiment. The frequency of
clock signal Tl has a frequency of 2048 Hz and, ~herefore, has a
pulse width of approximately l/2 millisecond. Clock interval Tl
is principally used to multiplex data from RAM 72 to segment
decoder 9O in order to keep the display data current.
The generation of clock signal T2 - T4, D03 and D04
invol~es four master-slave latch circuits. Each master-slave j -
generates an inhibit signal to each one of the T2 - T4 generators,
e.g., namely, WRST for clock T2, CRST for clock T3. The operation
of t~e master-slave control circuits will be described below
with respect to Figure 8. Nor gates 250 - 258 generate the Tl -
T4 clocks and initiate D03 and D04. Each nor gate is coupled to
the outputs of fliE~-flops 184 and 186 and to an inhi~it signal.
-27-
.... .. . . . . . . . ................ . . .
,, : . . . .. . -
741;~;~
1 For the purposes of description only assume that each inhibit
signal is false so that the nor gates are controlled only by
flip-flops 184 and 186. As previously described, the counting
states of flip-flops 184 and 186 can ~e characterized as 00, 10,
11, 01, and then 00 again.
Nor gate 252 has its inputs coupled to the Q output
of flip-flop 184 and the Q output of flip-flop 186~ Thus,
T2 is driven at a frequency of 2048 Hz. However, T2 is true only
when the Q output of flip-flop 184 is true and the Q output of
lO the flip-flop 186 is false, i.e., at 10. Therefore, clock
signal T2 is generated in the pulse of the 8192 Hz clock
immediately following the generation of timing signal Tl (i.e.,
at 00~ b
Similarly, nor gate 254 and 256 generate timing signals
T3 and T4 respectively. The inputs to nor gate 254 are tne Q
output of flip-flop 184 and the Q output of flip-flop 186. Thus,
clock signal T3 is only generated when the Q outputs of flip-
flops 184 and 186 are simultaneously high, which is the clock
pulse of the 8192 Hz clock following the generation of the timing
~ signal T2 ti.e., 11).
Nor gate 256 has its inputs coupled to the Q output of
flip-flop 184 and the Q output of flip-flop 186. Thus, nor gate
256 only has an output when the Q output of flip-flop 184 is
false and the Q output of flip-flop 186 is true ~i.e., 01).
Thus, signal T4 is generated during the clock pulse of the 8192
Hz clock immediately following the generation of clock pulse T3
and immediately proceeding the generation of clock pulse Tl.
Nor gate 258 is similarly coupled to the Q output of
flip-flop 186 and 184, and to the internal control signal reset
30 seconds, RSC. Normally, RSC is false so that nor gate 258 will
-28-
~7~
1 have a false output during T2 - T4 or RSC. As shown ~elow nor
gate 258 is used in the generation of D~3, D~4.
The ~ generator is similarly driven by flip-flops 178
and 180. The clock pulses 02, ~3, 04, and D03 are generated by
nor gates 259, 260, 262, and 264 respectively. Nand gate 266
generates D~4. Consider the clock pulse 02 for example. Nor
gate 259 has an input coupled to the Q output o~ flip-flop 178
and an input coupled to the Q output of flip-flop 180. A third
input o~ nor gate 258 is coupled to nor gate 268 which has each
of the clocks Tl - T4 as its inputs. Therefore, each of the 0
clocks will ~e inhibited whenever all of the T clocks are inhi~ited.
All of the ~ clocks-will ~e active when any T clock is active.
In the same manner as previously descri~ed in regard to the T
generator, the various inputs to the nor gates of the 0 generator
are shared among the possible com~inations of the Q and Q outputs
of flip-~lops 178 and 180 such that three consecutive 30 micro
seconds pulse are generated in the order, ~2, 03, and 04.
Nor gate 270 has one input coupled to nor gate 268, one `
input coupled to the Q output of flip-flop 178 and one input
coupled to the Q output of flip-flop 180. The output of nor
gate 270 is substantially similar to the nor gates 25~ - 262 in
its operation and generates a 30 microsecond pulse which forms
the first of a series of four identical pulses. The output of
~` nor gate 270 is coupled to the input o~ nor gate 272, which also
has as one of its inputs the outputs of nor gate 268. Thus, the
output of nor gate 272 will be true whenever the T generator is
inhibite~. The ~1 clock may thus remain a precharging clock
which is activated during the quiescent phase of the circuit
operation. -~
Nor gate 274 has the same inputs as nor gate 262.
-2~-
. .
. . ` ' ~ , ' ' ~ ' ' -- , :
~74~3'~
1 However, the output of nor gate 274 is coupled to nor gate 276
which serves the same function as nor gate 272 in the 01 clock.
The output of nor gate 276 is the address bus precharge signal,
ADDP which is true during T04. As shown below, address bus 64
will have a precharge whenever ADDP = O (Figure 13). The output
of nor gate 258 serves as an additional inhibit input to nor gate
264. The other inputs to nor gate 264 are identical with nor
gate 260 which generates the clock signal ~3. Therefore, D03
is an identical clock signal to 03 except, as will be shown, D03
will ~e inhibited during a display only sequence. Nand gate
266 generates the output, D04 and has inputs coupled to Q output
of flip-flop 178, ~he Q output flip-flop 180, the output of nor
gate 258 and the inverted output of nor gate 268. Therefore, D04
will always be false except during any T04 when it goes true,
unless inhibited by nor gate 258. As will be shown, D04 is
also inhibited during a display only sequence.
RAM ADDRESS GENERATOR
Each of the four T clocks, Tl T4, is accompanied by
the four ~ cloc~s, 01 - ~4, nested within each T clock. As
~ will be shown the T and D0 clocks can be selectively inhibited.
However, when active the clocks are used to drive the RAM address
generator. The use of the 0 clocks has previously been discussed
in relation to RAM 72 and Figures lOa, lOb and 11. RAM address
generator 46 has five primary purposes: (1) accessing the watch or
chronograph for display; ~2) accesing the watch for time set
displays; (3) accessing the watch for time increments; (4) access-
ing the chronograph for time increments, and (5) accessing
availa~le spare RAM words for time delays. These five functions
are achieved in foùr time intervals defined by the T generator
of timing in control circuit 44. Normally, the T generator is
-30-
~L~74~3'~
1 inhibited, as is the ~ generator, and pulses are only generated
when a specific action is required by timing and control circuit
44.
IlDuring the first T clock, Tl, RAM address generator 46
generates addresses used for accessing the watch or chronograph
for normal display, or accessing the watch for timeset displays.
The RAM addresses for each of the ~ords to be displayed is stored
in a read only memory 278 ~hereinafter ROM) as illustrated in
Figure 13. In the presently preferred e~bodiment ROM 278 has the
~ capacity to permit eight normal and eight timeset displays of
ei~ht digits each. In the actual display sequences described
herein, only six digits are displayed. ~s was the case for PLA
74, ROM 278 is a nor type array of N-type, dynamic circuits
combined with a nand array of P-type dynamic circuits which
comprises decoders 280 and 282, which in turn comprise decoder
48 of Figure 1. Figure 4 illustrates a typical decoder nand and
RO~f nor. The decoder nand is a series of P type devices including:
a precharge device 284; and timeset device 286, which will ~e the
internal control signal WTCH or WTCH indicating whether the
circuit is in watch or chronograph mode; and at least three inputs
from ~iming and control circuit 44 which are collectively denoted
by the reference character 28B. The output of the decoder nand
is also coupled to-device 290 which is an n-type gate coupled to
ground and controlled by clock Tl. Similarly, the ROM nor has a
precharged P-typa device 292 coupled to the address output and
controlled by clock Tl. The ROM nor is a typical nor gate decoder
having a plurality of n-type devices coupled in parallel ~etween ~ -
the output and ground, collectively aenoted by the reference
character 294. Each of the gates o~ n-type devices 294 are
coupled to preselected decoder nands according to a selected coding
-31-
4~3'~
E~
o
X ..
~ .
0~ ~ X ~
o o o o o X X ,, ,, ,, ,, ,, ,, ~ ,,
~: ,~ X X o o o
~ oooooXX oooooooo
o~ ooooo,,~ oooooooo
. ~ ~: ooooo~
~ ~ ,, ~ ,, ,, ~ o o C~ o o o o o o o
_ ~ o o o o o ~ ,, o o o o o o o o
o~ ~ o o ,, ,, ,, ~ ,,
. ~3 ~ ~: ~ o o o o o o o o
~ ~ 1 C o~ N O O O O O O O O O O O O O O O
,~c ooooo-1~ OOOOOOOO
~ ~0 O -~ X O ~ -I X X X X X X X X' : ".
C ~ ~ ~-I O X ~1 ~ X :~C X X ~ X X
C!~ ~ O O X ~ O O O X X ~C X ~: X ~ X
~ O ~I X ~I ~I ~I X X ~: X ~: X ~ X ~
1~ ~ ~I ~ ~I ~ . '
_l ~ o o ,1 o o o o o ~ _1 o o o o o
~ ~ oo~_looo oooooooo .. '
~: o ~1 0 -1 0 ~ . 1 ~ 1 o o o o
_
'~ U O O o o ~
o ~ o ,1 ~ ~ o m o ,~ ~ o o ,1 ~ o .
o o ~ o o ~ ~ ~ o o ~1 ~ o o
~ .
~ 1 o o o o o o o o
'
31a-
~L~74~3;~ ~
X ,.
,_ o o o o
,, ~ ~ ,,
V P~
P. V
~:
Z Z Z Z Z ~ ~ V C) ~ V
H H H H H ~ Z ~
. .. .. .. .. .. Z Z Z Z ~; Z ~; Z
~ ~ 1~ ~ ~ H H H H H H H H
~ w m
¦
~ ~ 0~ X X ~ X o ~C X X X ~ X ~ X X X '. ':
H X X ~--I X O X ~ X ~ X X ~ ~C
(` ......
V N ~ X X --I ~C O X ~ ~C X ~ ~ X ~C X ~
l¢ ~ X X X O ~C X X ~ X ~ X X X X . - . .
_ , . _
~0 O O O O O X X ,:. ,,
, ~1 ~ 1 X ' XO O O O O O O O
~D ~ .
I X ~ 1 ':
¢ O O O O O X X O ~ .'
) o o o o ~
,~ O ,1 ,~ ,1 o m o ~ ,1 0 0 ~ ~ O
O o ~ 1 V ~I ~ ~ .,
:~ .
. ~ ~ O O : ".
.. : -. -31b-
. . ,' '.' ,.'.
3 ~74:~32
1 scheme illustrated in Ta~le 9.
Address data ~us 64, decoders 280, and 282, and ROM
278 are precharged at all times other than during Tl~l - T1~3.
Address data bus 64 is precharged ~y a series of P-type precharging
devices 296 which are controlled by address precharge signal
ADDP. Device 290 maintains the decoder nand in a low precharged
state, while precharge P-type device 292 maintains the ROM nor
in a high precharged state during all times other than Tl. As
a result, all nodes in ROM 278, decoders 280, 282, and address
~ bus ~4 are clamped when not ~eing accessed. As will be shown
below, input signals to nand decoders 280 and 282 are generated
prior to clock interval Tl by timing and control circuit 44. The
inputs to nand decoder 280 are active during chronograph operation
and include: the internal signal, watch, WTCH; chronograph control
lines, CA, CB, ~D; watch control lines, WA, AB, WC; and the
twelve or twenty-four hour option, 12/24.
Referring again to Figures 5a and 5b, at the ~eginning
o~ clock signal Tl the address bus, ROM and decoder precharge is
removed and ROM 278 is accessed. Nand decoders 280 and 282 each
have eight outputs coupled to ROM 278 which is a 16 ~y 32 nor
gate array. Thus, when ROM 278 is accessed, a 32 bit word is
presented to the inputs of multiplexer 50. The 32 bit word is
grouped into four groups of eight. Each of the eight lines is
coupled through an n-type transmission gate to a single output
ter~inal corresponding to that group of eight. Thus, each group
of eight has eight control lines corresponding to the eight control
gates. The eight control lines are coupled to a corresponding
transmission gate in each of the four groups of eight outputs
from ROM 278. Control lines 298 are coupled ~o a P-type nand
decoder 300 (Figure 14~. Wand decoder 300 is driven ~y six lines ;~
:
-32-
.. .. .. . . ~ . ..
.
i7~3;Z
from digit scan 52 ~hose operation will be described in greater
detail ~elow.
As each of the control lines 298 is activated, a new
address will be gated through multiplexer 50 onto address bus 64,
A0 - A4. Thus, during one access of ROM 278 any one of eight
addresses may be selected by digit scan 52, thereby addressing any
of the eight digits during successive Tl periods. The order of
the display digit is identified by digit select circuit 302
which generates digit select signals, DGl - ~G8 (Figure 14). The
1~ digit select signals are coupled from digit scan 52 to display
drivers 56 as illustrated in Figure 1.
Digits scan counter 52 is a three bit asynchronous ~ .
counter comprised of three bistable elements generally denoted
hy the reference character 304. Each of the two outputs of
bista~le elements 304 also provide an internal control signal,
digits scan counter output, DS0 - DS2. Each of bistable elements
304 is reset by the internal control signal, master reset MRST.
IDigit select circuit 302 is coupled to the outputs of
decoder 300 through a P-type transmission gates, collectively
denoted by the reference character 306. Transmission gates 306
are driven by nand gate 308 which in turn has the clock inputs,
~2 and Tl. Thus, transmission gates 306 are non-conductive
during all times, except clock interval T102. The output of
each o transmission gate 306 is grounded through a corresponding
plurality of n-type gates collectively denoted by reference
character 310. Gat.es 310 are driven by clock pulse Tl so that
each input of digit select circuit 302 is fixed to ground at Tl.
Therefore, digit select circuit 302 is disenabled at all.times
other than clock pulse Tl. Each input line in digit select circuit
302 is coupled to a series combination of a nand gate and inverter,
.. . . . . . . . . ... .. .. .
- - . . . ' . . , . ~
~C~74~3Z
1 collectively denoted by the reference character 312. Each nand
gate has one input coupled to the corresponding output from
transmission gates 310 and one input coupled to nor gate 314.
Nor gate 314 has Tl and 04 as its inputs. Therefore, the output
of nor gate 314 is false at all times, except during the clock
interval, T104, at which time the nor gate output goes txue.
Thus, nand-inverter com~inations 312 serve as transmission gates
which read the dynamically stored output from transmission gates
30~, stored during clock interval T102, and coupled to digit
select ~U5, DGl - DG8 during clock inter~ral T1~4.
As will be shown, during a display cycle, the R~S data
is read and the normal increment operation is suppressed. The
RAM data word is coupled by means of decoder 90 and segment FONT
ROM ~2 to display drivers 56, described in greater detail in
connection with Figures 27 - 30. Since incrementation must
normally be suppressed during display periods, timeset for the
watch is also achieved during clock period Tl. During timeset,
the ~M addresses are generated ~y ROM 278 as previously descri~ed.
However, the information which is-displayed is the RAM data which
will be timeset. The timeset rate may arbitrarily ~e selected as
1 or 2 H2 as controlled and generated by timing and control
ci~cuit 44.
~ Clock period T2 permits generation of RAM addresses for
accessing the watch for time increments, the normal operational
phase of the watch. Clock period T3 permits the generation of
addresses for accessing the chronograph for time increments.
The operation in each case is essentially the same. Watch sequence
counter 58 generates the RAM address of the data to be incremented -
~
(Figure 1). Similarly, a chronograph sequence counter 60 gener-
ates the RAM address of chronograph data to be incremented.
-34-
~7~3Z ~
1 Initially both counters are reset to the address of the lowest
order location in the watch or chronograph portion o~ RAM 72.
In the presently preferred embodiment, the counters are set to
the divide~by-ten location of the watch, and to the l/lOth
second location of the chronograph. As will be descri~ed below,
when prescale divider 42 generates a 10 Hz pulse, clock T2 or T3
is appropriately generated as controlled by timing and control
circuit 4~ and the lowest order RAM word incremented by one. As
previously discussed, a carry signal, INC, may be generated
according to the code contained within PLA 7~. When the carry
signal, INC, is generated, watch or chronograph sequence counters
58 and 60 are also incremented to address the neYt higher order
RAM location, i.e., seconds units in the watch or chronograph
portion of RAM 72.
The next T2 or T3 will then allow the second units in
the RAM to be addressed and incremented as previously described.
The incrementation of the seconds units would continue as long as
a carry signal, INC, is generated. However, if no carry signal,
INC, is generated, eac~ counter 58 or 60, is reset ~y activation
of watch sequence counter reset, WRST, or chronograph sequence
counter reset, CRST, to the lowest order location, i~e., divide-
by-ten or l/lOth seconds in the watch and chronograph respectively.
At the next 10 Hz pulse generated ~y prescale divider 42, the
word of the lower order location within RAM 72 is incremented as
previously described. The process is repeated for each of the
words in the RAM with the carry signal, INC, stepping the address
generator of watch sequence counter 58 from lowest order location
throug~ seconds, minutes, hours, ~M and PM, day of the week, and
month. Similarly, chronograph sequence counter 60 steps through
the corresponding seconds, and minutes locations of the chronograph~
-35- ` `
~.
.
~ .
~ .
~74~32
1 Watch sequence counter 58 may be comprised of four
bistable elements, collectively denoted by reference character
322, coupled to form an asynchronous four bit counter (Figure 15)o
The Q output of each counter is gated to one of the address lines
of address bus 64 through an n-type transmission gate collectively
denoted by the reference character 316~ Transmission gates 316
are controlled by nor gate 318. Nor gate 318 has its inputs
coupled to T2 and 04. Thus, addresses are clocked out of watch
sequence counter 58 during clock period T201 - T2~3. Similarly,
the true outputs of each bistable element is coupled to nand gate
32~ which generates the internal timing signal, watch sequence
counter limit, WCH.
Chronograph sequence counter 60 is similarly comprised
o~ ~hree bistable elements, collectively denoted by reference
character 324 and driven by clock pulse T3. The output of
bistable elementS324 are gated through n-type transmisslon gates
collectivel~ denoted by the reference character 326. Transmission
gates 326 are contxolled by nor gate 328. Nor gate 328 has as -
its input, T3 and ~4 so that the output of chronograph se~uence
coun~er 60 is coupled to address bus 64 only during the clock
pulses T3~1 - T3~3. Chronograph sequence counter 60 has a nand
gate 330 coupled to the output o~ the lowest and nighest order
bistable elements 324. The output o~ nand gate 330 is an internal
timing signal, chronograph sequence counter limit, SCH. The
signal, SCH, will be true at all times except when the lowest
and highest order o~ bistable elements 324 both have true outputs.
As soon as bistable elements 324 reach the binary number 101, flag
signal SCH will go false. In the present preferred embodiment
flag signal WCH, and flag signal SCH, signify the end of the watch
and chronograph slequence.
-36-
.
- ,
13'~
During the clock interval T4, RAM address generator 46
accesses available spare RAM words for timed delays. Variable
masks are used to permit spare RAM word addresses to be set as
time delay locations (see Table l). Use of time delay words will
be described in greater detail in relation to Figure 2. Power
supply Vdd is selectively coupled to address bus 64 through a
series of P-type transmission gates, collectively denoted by
re~erence character 332. Transmission gates 332 are in turn
controlled ~y the output from inverted nor gate 334 which has as
its inputs, clock signal T4 and ~4. Thus, Vdd is coupled to
address bus 64 only during T4~1 - T403. During this time the
RP~I address, 1111, is generated.
MASTER-SLA~E LATCHES AND TIMING REQUEST CIRCUITS~
Clearly, the T and ~ generators cannot be allowed to be
free running, but must be activated in response to internal
control signals at a timed rate. For example, a request for
activation of the T2 generator every O.l second is the basis of ~ -
timekeeping in the watch.
The master-slave latch circuit 336(Figure 8~ is comprised -
2~ of a master RS nor latc~ 342 having gated inputs from and gates
344 and 346. Similarly, slave latch 348 is a RS nor latch having
gated inputs from and gates 350 and 352. The internal control
signal, ~atch sequence counter reset, WRST, is generated by the
Q output of slave latch 348. In the normal condition, WRST is
true there~y holding watch sequence counter 58 in the reset state
and i~hi~iting the generation of clock signal T2 ~y virtue of
being coupled to nor gate 252 (Figure 6).
The lO Hz; signal is gated through a CMOS transmission
gate 364 which is normally conductive. The initiation o an
internal control signal, ~ast test watch, FTW, will turn CMOS
~37-
~74~3~
1 transmission gate 364 off, and CMOS transmission gate 366 on,
thereby substituting the 128 Hz signal for the 10 Hz signal to
permit fast testing of the watch.
Normally, the 10 Hz signal is coupled to the rest
terminal of a RS nor latch 368. The set terminal of RS latch
368 is coupled to timing signal T2. Therefore, the~,normal output
of latch 368 is false. The output of latch 368 is coupled to
the input of or gate 370. Additional inputs to or gate 370 are
coupled to the 8192 Hz clock, 03', synchronized to clock 03, and
the 10 Hz clock. Normally, the output of or gate 370 is a 10 Hz
signal superimposed over the 8192 Hz clock, 03'. The output of
or gate 370 is coupled to nand gate 372 which also has one of its
inputs coupled to an internal control signal, initialized sequence
MR. MR is normally true and as will be shown is used as an
inhi~it signal for the T2 requests. MR is used to reset the
entire counting sequence to 12 midnight, January 1. The outpu-t of
nand gate 372 will be groups of 8192 Hz signals with a group
- repetition rate of 10 Hz.
The 10 Hz signal will be synchroni~ed by means of or
~ gate 370 to the 81g2 Hz clock, 03'. When the 10 Hz signal under-
goes a negative transition, the T2 request signal, T2R, will
become true at a time determined by the 8192 Hz clock, 03'. Each
of the reset inputs to latch 342 are normally false. Nor gate 354
has two true inputs, except during T2~3, and, therefore, a ~alse
output. Thus, regardless of the state o~ carry signal, INC, and
gate 344 will have a false output. The other reset input to
latch 336 will also normally be false since the master reset
signal, MRST, is normally false. Similarly, the output of and
gate 346 will remain false. The set inputs to master latch 342
will be false and the latch will normally have false output, Qm.
-38-
- .: . - . -. : . :
~7~3'~ ~
1 The slave latch 348 will synchronously couple the output of latch
342 at the time determined by clock 01i. Clock ~1' is generated
by nor gate 356 (Figure 6).
When T2 request signal, T2R, goes true, latch 342
changes state and is set. Qm goes true. At the clock signal,
~1' and gate 350 will have a true OlltpUt and and gate 352 will
have a false output. Thus, latch 348 will be set at Qs = 1.
This will, therefore, initiate a T2 clock pulse since the inhibit
signal, WRST, which was true, now goes false. T2 is thus enabled
within 1/2 millisecond.
T2 is fed back to latch 368 and will set the latch. As
previously discussed, T2 will also initiate an increment in RAM
72. The output of or gate 370 will remain true, thereby fixing
T2 request, T2R, in the false state (lO Hz signal is still true).
How~ver, master latch 342 will remain in the set position, Q - 1,
even though T2R is false.
During the interval, T203, nor gate 354 will generate
a true output. During the time intPrval, T203, PLA output carry
signal, INC, is valid. If the carry signal, INC, is true, then
~ a carry was produced by the incremented ~AM word. I~ INC, is true,
then no carry was producea. If no carry was produced both inputs
to and gate 344 will go high during T2~3. Similarly, the output
of and gate 326 will go low during T2~3. Master latch 342 will
then ~e reset with Qm = O. On the next positive going ~1' pulse
slave latch 348 will be reset to QS = O. Thus, the inhibit signal,
watch reset, WRST, will be generated and ~he T2 generator inhibited
until the next T2 re~uest signal, T2R. However, slave latch 348
is not reset until the following, ~1' pulse after master latch
342 is set. This delay is accomplished by means of and gates 350
30 and 352. The delay insures that t~e pulse T2~4 is generated as
normal during this T2 period.
.
: . -. .
~7~
1 If, however, the carry signal INC was false during the
interval T203, the output of and gate 344 will be false while the
output of and gate 346 will he true. Thus, master latch 342 will
remain set at Qm = 1. Similarly, slave latch 348 will also remain
set at the next ~1' pulse Qs = 1. As a result, the T2 generator
will remain enabled. T2 will be fed back and again will disenable
the output of nand gate 372, setting T2R = O. The watch sequence
counter reset, WRST, remains reset at zero and allows watch
sequence counter 58 ~o increment the ~A~I address causing the new
~AM word to be incremented by PLA 74. Slave latch 348 remains
set and T2 remains enabled as long as PLA 74 continues to generate
carry signals, INC. If the increment of the new RAM word does
not create a new carry, watch seguence counter 58 and master-
slave latch 336 are reset at the next T2 request for singal T2R.
A similar master-slave combination is used for
chronograph control and the T3 generator, which employs inhi~it
signal chronograph sequence counter, reset, CRST. A 10 Hz latch !~
358, or gate 360 and nand gate 362 are also combined with master-
slave latch 364 to control the timing of the T3 generator. The
~ gated inputs to master-slave latch 364 are also cvupled to
internal carry signal, INC, and to nor gate 366 which has a true
output during T303. The 10 Hz and 256 Hz signals are selectively
coupled to latch 358 through a CMOS transmission gate 374 which
is controlled by the internal control signal, fast test chronograph, -
FTC.
Similarly, master-slave latch 376 inhi~its the operation-
of nor gate 256, the T4 generator. The reset inputs to the master
latch 378 do not include, INC, since the time interval T4 is
employed only for accessing delay words unassociated with carries.
The set terminal of t~e master latch 378 is driven by the output
-40-
.
:
- -, , -: ~:. . . -:
- -- : - . , . . . -
. . - . ~ . . .
1~7~3Z
1 of nor gate 380 which in turn is driven ~y the latch 382. The
1 Hz signal drives latch 382 through nor gate 384. T~e reset
terminal of the master latch 378 is coupled to nor gate 386
which has T4 and ~3 as its inputs.
Three signals are generated in timing and control
circuit 44 to control the operation of the chronograph. These
signals are the internal control signals: stop chronograph,
STOPC; store chronograph sequence, STOREC; and reset chronograph,
RESETC. As shown in Figure 8, the signal STOPC is coupled to nor
gate 360 and latch 358. When STOPC is true, latch 358 is set
and the T3 re~uests are inhi~ited and master latch 342 held rese~.
This will disena~le the T3 generator.
In order to store data during chronograph operation,
fiva RAM words must be transferred from the RAM counter portion
of ~he chronograph to the appropriate RAM store portion of the
chronograph. This is achieved by application of the signal,
STOREC, as follows. Signals STOREC and CYCLEC are simultaneously
generated by activation of switch Sl as described in detail below.
CYCLEC is the internal control signal generated ~y positive
~ transitions of switch signals SWl or SW3 corresponding to
activation of s~itches Sl or S3 respectively. CYCLEC is a 1/2
~illiscond negative pulse ~hich is used to mask erroneous tran-
sistions which may occur during the generation of STOREC. The
external control signal, store chronograph, STCR, is normally
true. The signal STCR is generated ~y RS nand latch 388 (Figure 9)
and is coupled to nand gate 362 ~Figure 8). When STCR goes false
it will cause continuous requests for clock T3 to ~e made
independently of t~e 10 Hz signal~
The si~nal, STCR, will go false provided c~ronograph
sequence counter reset, CRST is true (Figure 9). If nand gate
-41- `
. . . - - . . . . . . . . ..
, ..... : , . . . . . . . . ..
,. . ~ . . :
32
1 390 has each o~ its inputs true, latch 388 will be reset since
the output of nand gate 390 will go false since SCH is normally
true. Nand gate 390 has STOREC, CYCLEC, latch 392, and CRST as
its inputs. That is, STCR goes false if the chronograph sequence
counter is reset (CRST = 1) or not in a carry sequence, and if to
STOREC is true. Should CRST go false, then STCR goes false as
soon as the carry sequence is finished and CRST returns to true,
~hile SCH goes false.
Normally, SCH, MRST, and CYCLEC are true. When CYCLEC
goes false, latch 392 will be set and remain set even when CYCLEC
goes true again. The output o latch 392 is then normally true.
However, when SC~ goes false, indicating the end of a chronograph
counting sequence, latch 392 will ~e reset and nand gate 390 will
~e inhibited. Latch 388 will then ~e set. Nand gate 390 ~ill
remain inhibited until CYCLEC goes false when SCH is true, there~y
setting latch 392 again. Even-through CRST or STOREC remain true,
latch 388 will thus remain set until CYCLEC again goes false.
When T3 clocks are being continuously generated and
STCR is true, STOREC and STCR are true and are coupled to nor
gate 3~4 which generates the internal control signal, STORE.
~TORE is applied to the PLA and RAM to cause RAM data to ~e written
back into the RAM through transmission gates 146 (Figure 11)
directly from the PLA input without passing through the PLA. As
discussed below, STORE also selectively generates internal control
signals chron A or chron B. During the clock interval T3~1 -
T303, the counter portion of the RAM chronograph is accessed for
readout~ During t:he interval T3~4 the store portion of the RA~
chronograph is accessed and data is written in. The chronograph
sequence counter continues transferring data from the counter
portion of the c~onograph RAM to the store portion until the
,j, .,.:"::
-42- ~
3'~
1 internal control signal chronograph sequence counter limit, SCH
goes true. The output of nand gate 330(Figure 15), the signal
SCH, will go false when chronograph sequence counter 60 reaches
the address 101 to indicate the end of a store sequence.
The internal control signal, reset chronograph, RESETC,
STOREC and T3 are used to generate the internal control signal,
write zero, WZ, by means of nor gate 396 and nand gate 397
cFigure 9). Signal WZ is coupled to the chronograph counter
portion of R~M 72 through a n-type transmission gate 398 ~Figure lOa
). Therefore, during the interval T304 the chronograph counter
portion of RAM 72 may be reset to zero.
Internal control signals, watch I/0, which selects the
watch data from the RAM storage, and a chron A and chron B which
select the counter and storage from the RAM, are generated according
to the following logic equations and are implemented by logic-
circuit 400 of Figure 21 which is fabricated by means well known
to the art.
~TCH I/0 ~ ~WTCH) Tl + T2 ~ T4
CHRON A = (WTCH) (Tl) ~CC) ~ T3 (STORE) + T3 (STORE) ~4
CHRON B = tWTCH) (Tl) (CC) + T3 (STORE~ 04
Inspection of the equations illustrates when various portions of
the RAM are read out onto data bus 80.
Timing and control cir~uit 44 provides three additional
signals which control the timing generation and timesetting of
the watch. These signals are: timeset digit, TSDG; display reset,
DFRST; and cycle watch, CYCW.
The signals, TSDG, is used to identify the digit of the
display which is to be timeset. A timeset PLA, described in
detail below, generates TSDG which is then coupled to nor gate 402
(Figure 81 in order to enable request for timing signals, D03 and
D~4.
'
-43-
~74~3'~ .
1 Signal DFRST is used to iaentify the digit being time-
set as well as any digits that must respond to carries generated
~y any digit. DFRST iS coupled to nand gate 404 to reset
master-slave latch 406 (Figure 8)~ Signal CYCW is generated
when switch Sl is closed during timeset. Signal CYCW, will reset
latch 408 and permits D~3 requests to be made every one hal~
or one second. The various T and ~I clocks are not free running
~ut have been shown to be selectively activated by internal
control signals STOPC, STOREC, DFRST, TSDG, RSC, and CYCW. These
and other internal control signals previously discussed are
generated ~y the master control circuitry of Figures 16 - 26.
MASTER CONTROL
The function of the master control is to provide control
pulse for the operational blocks previously described. The
primary data inputpulses into control circuit 44 are the three
switches signals SWl, SW2, and SW3 corresponding to switches Sl -
S3 respectively. The details of control circuit 44 will ~e
determined in part by the switching functions chosen by the
designer. Therefore, the logic design may vary slightly according
~ to the application. The switching functions described are only
one em~odiment of a multiplicity of embodiments which are con~
templated for the present invention and are illustrated only to
show the details of a presently preferred embodiment of the
invention.
Figure 2 is a flow chart which illustrates the control
logic of the present embodiment. Each of the switches are spring
loaded push switches which are normally open. The watch may
have two watch display modes and four stop watch display modes.
Normally the watch is in watch display mode 1 which may ~e hours/
minute~ date. When switch 1 is pushed or activated watch display
~ "
44
: ;~
,. : ' : . . : , . :
1~4~32
1 mode 2, which may be hours/minutes~seconds will be displayed.
When switch 1 is again pushed, the watch reverts to watch display
mode 1. As shown in Figure 2, when switch S2 is pushed the watch
will ~e put in the timeset mode in which each of the stored words
in the watch may be arbitrarily fixed.
During timeset sequencing after switch S2 has ~een
activated, the hours digit will flash at a 1 Hz ra~e indicating
that the hours digit is the digit to be timeset. When switch
Sl is again pushed, the hours digit will stop flashing and the
hours digit will be incremented at a 2 Hz rate. When switch Sl
is released the incrementation will cease and the digit will
continue flashing until S2 is again pushed cycling to the next
digit to ~e set. During timeset the watch count is unaffected.
However, whenever the minutes unit digit is cycled, the seconds
diyit will automatically be set to zero. Thererore, the Sl
closure for minutes units and seconds is the same. After the
date of the month digit has ~een cycled, acti~ation of switch S2
will again return the watch to the last used watch displa~ mode
and the watch will continue counting. During any cycle of the
timeset mode switch S3 may be activated to return watch to the
watch displa~ mode. The watch also has an automatic return
feature whereby 10 seconds after the hours timeset digit is
entered or 10 seconds after correction, whichever is later, the
watch will automatically return to the watch display mode.
Activation of switch S3 from the watch display mode 1 -
or 2 will put the watch in the first chronograph mode or the
standard stop watch. Serial activation of switch S3 will step
the watch to each of the other chronograph modes and finally
return it to watch display mode 1 or 2. If the watch is in the ;
standard stop watch mode, activation of switch Sl begins the stop
-45-
, ~ ~ . . , " .. -
~7~3'~
1 ~atch count. Another activation of switch Sl will stop khe count
and display the elapsed time. During each of the chronograph
modes the minutes and seconds are displayed during counting. An
alphabetical symbol will also be displayed, C, F, L, or P to
indicate which stopwatch mo~e is being used. An alphabetical
symbol, A or P, may also be displayed during normal watch displays
i~ the 12/24 mask is chosen. At the end of the chronograph
sequence, the identifier will be removed and tenths of seconds
displayed. A third activation of switch Sl will return the
chronograph to the beginning of the standard stopwatch sequence
and display a zero count together with the chronograph mode
identifier. The same affect may be achieved by activating switch
S3. Switch S3 may be activated at any time during the standard
chronograph mode, except at the first Sl closure, and will return
the chronograph to the initial point of the sequence.
The second chronograph mode is a flyback stopwatch.
The first activation of switch Sl starts the count. The second
activation of switch Sl stops the count, stores the elapsed count, -
displays the elapsed count, and then it resets the count to zero
~ and begins to count again. Additional activations of switch Sl
repeat the sequence, each time writing the new elapsed count
- into storage over the prior stored count. Activation of switch
S3 at any time resets the count to zero, freezes the count, and
displays zero with the appropriate identifier thereby returning
the sequence to the intial state.
The third chronograph mode is a relay or lap-accumulate
stopwatch. The first activation switch Sl begins the count. The
next activation of switch Sl stores and displays the count while
internal counting continues. Each subsequent activation of
switch Sl repeats the above steps not including the initial
-46-
.. . ..
' . ' - '' " '' ' ." "' .' ~'',- ' " ', ' , '
1~7~3;~
1 activation. Again, activation of switch S3 at any time freezes
the count, sets the count to zero and displays zero with the
appropriate identifier.
Finally, the fourth chronograph mode is an event pause
or pause-accumulate stopwatch. The first activation of switch
Sl begins the count. The next activation of switch Sl stops,
stores, and displays the count. The next activation of switch Sl
begins the count from the indicated time at which it was stopped.
Su~se~uent activations of switch Sl repeat the steps not including
initial activation. Again, activation of switch S3 at anytime
stops the count, resets the count to zero and displays zero with
the appropriate identifier.
The logic circuitry of control circuit 44 may now ~e
understood in light of the various display modes ]ust descri~ed.
During the watch display signal, S~l, must initiate normal
display and during the timeset mode generate a continuous
incrementation cycle. Signal, SWl, is coupled to nor gate 416
whichalso has as its inputs the internal control signals timeset-,
TS, clock ~4, and l*rcH (Figure 16). Normally, the output of nor
gate 416 is false since at least SWl is true. When the Q output
of flip-flop 418 is false, the watch display is set in watch
display mode 2 where the display is hours, minutes, and seconds.
When the Q output of flip-flop 418 is true, the watch display is
set in display mode 1 where the display is hours, minutes, and
date. Flip-flop 418 may only to toggled when the internal control
signals I~TCH, and TS are true. The output of ~lip-flop 418 is
coupled through logic circuit 434 whose opera~ion is descri~ed
below.
Consider the timeset mode. Activation of switch S2 ~;
and signal SW2 as shown in Figuré 16 will cause the watch to go
.-~
-47-
.
~: ~ ' ' ' ' ' :
. . .
~i7~3Z
fro~. the normal display mode to the hours timeset mode. Signal
SW2 is one of the inputs to nor gate 420 which also has as its
input the internal control signal WTCH. Therefore, nor gate 420
will have a true output only when switch S2 is pushed, when the
internal control signal, WTCH, is true. The output of nor gate
420 is a six state Johnson counter ~ased upon the operation of
D type flip-flops 422, 424, and 426. The sixth state of the
three flop-flop counter is providecl by RS nand latch 428.
The Q output of flip-flop 422 is coupled to the D
input of flip-flop 424, while the Q output of flip-flop 424 is
coupled to the D input of flip-flop 426. The Q output of flip-
flop 426 is coupled to the input of nand gate 430 and each of
flip-flops 422 - 426 are synchronously clocked by the inverted
output of nor gate 420. Latch 428 also has as one of its reset
inputs coupled to the clock signal of flip-flops 422 - 426.
Another reset input of latch 428 is coupled to the Q output of
flip-flop 424. The output of latch 428 is normally true thereby
inverting the Q output of flip-flop 426 an~ coupling it to the D
input of flip-flop 422.
The Q outputs of the Johnson counter generate internal
control signals, ~atch control lines, WA, WB, and WC. Signal ~`
WB is also modified during the clock, TS, by the Q output of
~lip-flop 418 as described ~elow. Signal, WA, is the inverted
signal from the Q output of flip-flop 422. Signal, WB, is normally
the inverted Q output from flip-flop 424 after being cycled
through a logic gàte described below. The signal, WC, is the
inverted output of flip-flop 426. ~ohnson counter 422 - 426
cycles through the states as shown in Table 6. Signals WA - WC `
provide a coded sequence which ultimately will result in six
different states during the timeset mode as shown in Figure 2.
.
~ -48-
~74~3Z
1 TABL _5
CONTROL CODES & DATA LOCATIONS (FIG. 14)
.
h7A WB NC TIMESET LOOP CONTROL CODE
~ ..
O O O HR: MIN SEC
1 O O * HR: MIN A/P
. 1 1 O HR: MIN
1 1 1 HR: MIN SEC
10Q 1 1 MN DT ~:
O O 1 - MN DT
O 1 O HR: MIN DT
_ . -
* In 24 Hour Mode This Display Is Changed To HR:MIN
' .
.
: CA CB CC WATCH~STOP W7ATCH MODE CONTROL CODE
_ _ . I .,-:-,
: O O O ~ATCH
201 O Q STANDARD
1 1 O FLY BACK
: O 1 1 LAP ACCUM. -
: O O 1 PAUSE
. . _ ._ ._ _
_ .
~ CD CC CHRONOGRAPH OPERATION CODES
, , ....
O O RESET (DISPLAY SHOW5 C, F, L, or P)
1 COUNT (Dl:SPLAY SHOWS C, F, L, or P)
O 1 - STOP/STORE/PAUSE
301 1 RESET/STORE/COUNT
o 1 RESETjSToRE~PAuSE
.
-48a~
.
.
~74~3Z
1 T~e three bit code WA - WC is used ~oth by the timeset control
PLA 432 and the display sequence ROM 278.
Signal WB is derived from logic circuit 43~. Logic
cirCuit 434 has as its inputs the output of nor gate 436, tl~e Q
output of flip-flop 424 and the Q output of flip-flop 418. No3-
gate 436 is coupled to the Q outputs of flip-flops 4~4 - 426.
Normally, during the timeset sequence, the output of flip-flop
4il3 and nor gate 436 will ~e zero. Logic circuit 434 is in the
forI~ cf an "H" and is comprised of rwo series P~t~pe devices in
parallel with two identical P-type devices. The series pairs of
P-type devices are in series with two pairs of N-type devices.
Each pair of N-type devices forms a two parallel legs analogous
to the P-type devices. The output of the nor gate 436, TS, is
coupled to the gates of one P-type device and one N-type device.
In the same legs, flip-flop 418 has its Q output coupled to one -
N-type device and flip-flop 424 has its Q output coupled to one
P-type device. Similarly, the inverted signal from nor gate 436
is coupled to a P-type and N-type device in the remaining legs.
One P-type device has its gate coupled to the O output of flip-
flop 418 while the remaining N-type device has its gate coupled
to t~e Q output of flip-flop 424. Therefore, when in the normal
counting sequence TS and the Q output of 418 is false, logic
circuit 434 will act as a CMOS inverter coupled to the
Q output of flip-flop 424 in the same manner as the circuit
couplings to WA and WC. However, when the time state counter
reaches the initial counting se~uence 000, the output of the nor
gate 436 will ~e true. Logic circuit 434 will now operate as a
CMOS inverter with respect to the Q output of flip-flop 418.
If the output of flip-flop 418 is false, as assumed, WB will be true
ànd the output of the timeset counter state will appear as 010.
. .
,~
~L~7g~32
1 However, if the output of ~lip-flop 418 is true, then TS is true,
and the WA - ~C would appear to assume the timeset counter state
000.
Seconds are reset and held during the timeset mode by
means of latch 428. I~ switch Sl is closed, i.e.~ SWl true, the
input from SWl to nand gate 438 would be true. Nand gate 438
also has as its inputs, the Q output of flip-flop 426 and the Q
output of flip-flop 422. When the timeset state counter reaches,
the state 111, and switch Sl is closed, nand gate 438 will have a
false output. During the next activation of switch S2, the clock
pulse of the timeset state counter, latch 428 will be set and the
Q output of flip-flop 426 will ~e fed back through nand gate 430, -
uninverted,to the D input of flip-flop 422. The result is that
the timeset state counter will be again set in the counting state
111. The timeset state counter will remain in this counting
state regardless of how ~any times S2 is activated, until SWl
goes false there~y allowing latch 428 to be reset by SW2.
Logic circuit 440 has its inputs drawn from WTCH, W~,
WB, and WC. The output of logic circuit 440 is used to decode
WA - WC and generate a date signal which is given by the following
logic equation.
,
DATE = WTCH (~A~ (WB + WC ) .
'.
The signal, DATE, iS used to determine whether or not the date
; identifier should be on.
Finally, it should ~e noted that the signal, SW3, is
coupled to nand gate 442, which also has as its inputs the master
reset signal, MRSIi, and the output of nand gate 444. Nand gate
442 has its output coupled to the reset terminal of the timeset
: ' '. .
50- ~
..
; ~ ' ", ' .
1~74~L3;~
1 state counter. Thus, the timeset state counter will be reset
whenever switch S3 is activated and SW3 goes false. The watch
control signal WA - WC will be reset in the initial sequence and
control will return to the watch displa~ mode as determined by
flip-flop 418.
Consider now the automatic: return feature of the
present embodiment. When the watch is set at hours timeset and
switch Sl is not closed, a time delay of ten seconds is reqwired
to return the ~atch to normal operat:ion should the period elapse
without a Sl closure. Hours timeset (the timeset state 100)
is detected by nand gate 446 ~hich generates the internal control
signal, delay request, DLYRQ. As shown in Figure 8, DL~RQ is
coupled to latch 382 and nor gate 380 so that it normally inhibits
the generation of T4 request, T4R. However, when DLYRQ goes false -
in hours timeset, T4 pulse are generated with a 1 Hz group
periodi~i~y.
As previously discussed, during T4, the RAM is accessed
at the address 1111 by means of nor gate 334 {Figure lS). Logic
circuit 400 will also generate the internal control signal,
WTC~ I~0, during clock interval T4 (Figure 21~. The RAM word will
then ~e processed according to the state of an internal control
delay reset, DLYRST. The signal DLYRST is generated by nor gate
; 448 in Figure 17. Nor gate ~48 has a signal SWl as one input,
and the Q output of flip-flop 450 as the other input. Flip-flop
450 in ~urn is clocked by clock signal T4. The D input of flip-
flop 450 is coupled to the power supply Vdd. Thus, its output Q
is set at zero during all clock pulses. As long as switch Sl
remains open, SWl will be zero and the output of nor gate 448 will
be true. The signal, DLYRST, is one of the external PLA input
terms which form part of the PLA nand gates. Thus, by means of
the internal PLA code shown in Table 2, if DLYRST is true, then
. ,
-51-
. . ' '
. . . . . . .
~7 ~ 3'~
1 tne contents of RP~I word 1111 are incremented and rewritten in
the address 1111. If DLYRST is false, the delay word is rewritten
into the RAM without incrementation.
The output of nor gate 448 will be false for the Eirst
T4 pulse of any delay request, DLYRQ, since Q of flip-flop 450
is true until the first T4 pulse In addition, DLYRST will be
false if the switch Sl is closed. In hours timeset, as long as
switch Sl remains open, the delay word will be incremented during
each T4 pulse until the contents of the delay word reach 0000.
~hen the delay word 0000 appears on the data bus 80 nor gates
452~ Figure lOb, will generate a true output, internal control
signaL, ZERO, ~hich will be coupled to nand gate 444 (Figure 16).
During the interval T4~2, nand gate 444 will trigger nand gate
442 which in turn will reset the time state counter. Nand gate
446 will then set DLYRQ true, thereby inhibiting the generation
- of any further T4 pulses.
Consider now the operation of the various chronograph
modes in relation to s~itches Sl - S3. Similar to the timeset
state counter, the chronograph state counter shown in Figure 17
~ is a five state Johnson counter based upon D type flip-flops
454, 456, and 458. This counter controls the mode selection of
the four modes of the chronograph. Signal SW3, corresponding to
switch S3, is coupled to nor gate 460. Nor gate 460 in addition
has an input from RS latch 462 and clock signal ~4. The inverted
output from nor gate 460 serves as the clock pulse for each of
the flip-flops 454 - 458. The Q output of flip-flop 454 is
coupled to the D input of flip-flop 456, and likewise in regard -
to flip-flop 456 with respect to flip-flop 458. The Q output of
flip-flops 456 and 458 are coupled to nor gate 464. The output
o nor gate 464 is coupled to the D input of flip-flop 454. The
ive state counting sequence of the counter is shown in Ta~le 6
~74~3i~
1 for the chronograph control signals CA, C~, ~nd CC. As before
the Q output of flip-flop 456 generates CA; the Q output of flip-
flop 458 generates CB; and CC is generated from the Q output of
flip-flop 454 through the logic circuit described in detail
below.
The internal control signal WTCH is generated by nor
gate 466 which has an output coupled to each of the Q outputs of
flip-flops 454 - 458. Thus, WTCH ;s generated from the state
000 of the counter and represents normal watch operation.
Chronograph control signal CC is coupled to ihe Q output
of flip-flop 470 and chronograph control signal CD is coupled to
the Q output of-flip-flop 468. Signals CA - CC are used as inputs
to nand decoder 280 (Figure 13) in conjunction with ROM 278 for
generating preselected address formats. Signals CA - CD are used
in the chronograph PLA to generate internal control signals STOREC,
STOPC, and RESETC as shown in Figure 19. Signal CC is also used
as one of the control signals to select a desired display font,
alpha, or numeric A as illustrated in Figure 20. Finally, CC or
equivalently DEC, from the Q output of flip-flop 470 is used to
drive the decimal point in the chronograph display.
The clock input to flip-flop 468 is provided ~y the
output of nor gate 472. Nor gate 472 has as its inputs SWl and
WTCH. ThereforeJ nor gate 472 will have a true output only during
a chrono~raph sequence when switch Sl is closed. The Q output of
~lip-~lop 468 drives the clock input of flip-flop 470. The D
input of flip-flop 470 is coupled to the power supply Vdd.
Therefore, on the first clock pulse from flip-flop 468, the Q
output of flip-flop 470 will go true and remain true until flip-
flop 470 is reset.
Flip-flop 47Q goes true as soon as there is a Sl
.,
;,
-53-
.
- . . ~ : . . :: ,
1~74~3;~:
1 closure during a chronograph sequence. The preset zero at
flip-flop 468 will be set true thereby clocking the Q output of
flip-flop 470 true. Since the Q output of flip-flops 468 and
470 are provided as inputs to nor gate 474, the output of nor
gate 474 will change from true to false on a Sl closure during
a chronograph mode.
/The output of nor gate 474 is one of the inputs to nand
gate 476. Nand gate 476 has as additional inputs, SW3 and TS.
Normally, during a chronograph sequence, TS, and SW3 will both
be true. The output of nand gate 476 is coupled to the set
terminal of RS nand latch 462~ Normally, the output of nor gate
474 will be true and nand gate 476 false during a chronograph
sequence. Therefore, latch 464 is reset before an Sl closure.
When latch 462 is in a reset state, its Q output, coupled to nor
gate 460, will permit switch S3 closures to sequence the
chronograph state counter.
However, during a chronograph sequence and a Sl closure,
the output of nor gate 474 will go false, the output of nand gate
476 will go true, and latch 462 will be set. The output of latch
2~ 462, coupled to nor gate 460, will disenable the effect of any -
switch S3 closures during a chronograph sequence after the fir~st
Sl-closure. Similarly, the effect of a switch S3 closure during
a timèset cycle is disenabled since signal TS is one of the inputs
to nand gate 476. When TS is zero, the output of nand gate 476
will always be true. Thus, latch 476 will be set and the
chronograph state counter will be decoupled from switch S3. After
the chronograph sequence is completed and flip-flops 468 and 470
reset, ~ ~ill reset latch 462.
During a chronograph sequence SW3 is normally true 50
that nor gate 4?2 w:ill merely invert SWl. The clock pulse to
'' ' ' '- ': ` '' . :
. .
~74~3Z
1 TABLE 6 (FIG. 15)
TIMESET & LEADING ZERO SUPPRESSION
. .
P. L. A.
AND OR
DISPLAY DIGIT _ ---
C ~DE SC~ N SEC. .
NP WB l~C DS2 DSl DS0 TS DFRST TSDG RST. BLANX CO~MENTS
. _ _ ~
1 0 0 0 1 1 1 1 1 HDRG4nitS
1 0 0 1 0 0 1 1 HR Tens DG5
1 0 0 1 0 1 1 1 AM/PM DG6 .
1 1 0 0 1 0 1 1 1 MIN Tens DG3
1 1 1 0 0 1 1 1 1 MIN Units
- DG2 .
1 1 1 1 1 0~ 1 1 - 10 DG7
1 1 1 0 0 0 1 . 1 SEC Units
. . DGl
1 1 1 0 0 1 1 1 . SEC Tens DG2
0 1 1 0 0 1 1 1 1 MN Units DG2
~O 0 1 1 0 1 0 1 1 . MN Tens DG3
; O 0 1 1 1 1 1 1 1 . DT Units DG8
O O 1 0 0 0 1 1 DT Tens DGl
1 0 1 DG6
O 1 1 0 1 1 1- MN Tens DG4 : :
0 ~ 1 0 1 1 1 MN Tens DG4 . .
0 1 1 0 0 1 1 DT Tens DG2
o a 1 o o 1 1 DT Tens DG2 ~:~
a 1 0 0 0 1 ~ 1 DT Tens DG2 .:
___ ,, .. ~ ~
~ : `
,' . ~.'
~ -54a- ~ -
.
:- - . -- ~ - .. . . . . ..
. .
~7~32
1 TABLE 7
STOPWATCH CONTROL P. L. A.
. CONTROL . . _
CODES . COMMENTS
CA CB CC CD STORE~ STOPC RECETC
O O 1 1 1 RESET (C,F,L or P nodes)
0 0 1 X 1 STORE in C Mode
10 1 0 1 X 1 . 1 STORE/RESET in F Mode
1 1 1 X 1 STORE in L Mode
0 1 1 0 _ STORE/PAUSE in P Mode
- X = Don't Care States -:
: 20
'` '~ '
: ' "
.: ' , ' '
'
74~32
1 flip-flop 468 is again inverted and is SWl. Therefore, the clock
of flip-flop 468 goes negative on an Sl closure. Flip-flop 468
and ~70 are clocked on negative edges so that they are sequenced
through the states 00, 10, 01, 10, 01 ... as shown in Ta~le 6,
th~reby providing the four distin~uishable states necessary for
control during chronograph sequencing.
Flip-flops ~68 and 470 are reset by means of nand gates
478 and 480. Nand gate 478 has its inputs coupled to the Q output
o~ flip-~lop 468, the Q output of flip-flop 470, the Q output o
flip-flop 454, and the Q output of flip-flop 456. Thus, nand
gate 478 will always have a true output except when signals CC
and CD are true, and the chronograph state counter is in the state
100. This chronograph state will be the second state generated
on the second closure of switch Sl. On the third activation of
switch Sl, CD will go true thereby generating a false output from
nand gate 478 and triggering nand gate 480 to reset flip-flops
468 and 470. Alternatively, if switch S3 is closed nand gate 480
~ill also be triggered and flip-flops 4~8 and 470 reset.
Timing and control circuit 44 also contains two small
PLA's. Timeset PLA 432 is substantially similar to the main PLA
72 and has its minter~s illustrated in Table 10. The function of
the timeset PLA 432 is to identify the digit to be timeset, identify
the timeset digits that must respond to carries in order to prevent
unwantea rollovers, identify the digits which have leading zero
suppression, and to synchronize the second reset. As sho~n in
; Figure 18, the inputs to timeset PLA 432 are the digits scan
courts DS0 - DS2 and the watch control signals WA - WC. PLA 432
is accessed during interval Tl and generates: timeset digit TSDG;
; delay flag reset, DFRST; a blanking signal, BLANK; and rest seconds,
RSC, as determined by various ~ clocks.
.
-55-
..
. . .
.
.
- , , . ~.
~:97~132
1 For example, internal control signals TSDG and RSC are
valid during the entire Tl interval. The signal DFRST is stored
in memory latch 482 during all time intervals, except T103 when
nor gate 484 open circuits the CMOS transmission gates in the
input and feedback loops of memory latch 482. Thus, DFRST is
valid from the end of one T103 interval to the beginning of the
next T103 interval.
Signal BLANK will be valid from one T02 rise until 02
falls. Signal BLANK is generated by nor gate 48 and thus will
be true only when the pulse 02 and the output of nor gate 488
are both false. The output of nor gate 488 will be ~alse as long
as at least one of its inputs, AND gates 490 and 492, are true/
AND gate 492 will be true whenever the BLANK signal is generated
by PLA 432 and signal ZERO is true, which occurs whenever all
zeros appear on data bus 80. The output of and gate 492 is used
for leading zeros suppression as decoded by PLA 432 (Figure 18).
And gate 490 will be true if signal DFRST is true and CYCW is
true. In addition, AND gate 490 is driven by a 1 or 2 Hz signal,
as optioned, so that a flashing BLANK signal may be generated
during timeset. Signal CYCW is generated by nand gate 494
~Figure 16). Nand gate 494 has as its inputs signals SWl and TS.
Thus, CYCW will have a true output at all times, except during a
switch Sl closure and timesetO Thus, when DFRST is true and
switch Sl is closed, a flashing BLANK signal will be generated
in order to identify the digit being timeset. The digit will
cease flashing during a switch Sl closure and will flash at all
. .
other times during DFRST. TSDG is one of the inputs to NOR gate
402 in Figure 8, cmd is normally true thereby inhibiting D03 and
D04 requests from the master-slave 406. During a timeset mode,
TSDG, goes true thereby identifying the digit to be timeset by
.
~56-
'~:
~74~3Z
1 selectively enabling transmission of clock pulse through nor gate
402. When TSDG goes true, DFRST goes true, will be stored in
storage cell 482 at T1~3. Normally, DFRST is true. During
timeset when TSDG goes true, at T1~3 DFRST will go false. The
output of nand 404 (Figure 83, which is normally faLse, goes
true, thereby holding master-slave 406 reset. Thus, master-slave
4Q6 t~ unction as if no carry ever occurs regardless of the
actual state o~ INC.
The internal control signals STOPC, RESETC, and STOREC
are generated by PLA 496. PLA 496 is illustrated in Figure 19
in terms of symbolic logic since only five minterms are raquired.
P~A 496 may either be constructed similarly to PLA 432 or may assume
the circuit configuration illustrated in Figure 19. The operation
of PLA 4~ may be readily deduced from Ta~le 7. As illustrated
in Figure 8, STOPC iS used ~o inhibit la!~ch 358 there~y stopping
the chronograph sequence by inhibiting T3 request, T3R. STOREC,
as previously described, is used to generate internal control
signal STCR to inhibit T3 request, T3R (Figure 9)~ RESETC is ~.
used in Figure 9 as one input to NOR gate 396 which generates
~ signal WZ which will write ZER06 into the chxonograph counter and
RAl~.
Although the present invention has capacity for at
least three display fonts in the present embodiment only two
fonts are used, namely alpha and numeric A. The characters zero
through nine, and the letters A, C, F, L, and P, stored in RAM
72, as shown in Table 1, are displayed. Logic circuit 498 as
illustrated in Figure 20 generates, by means well known to the
art, signals alpha and numeric A during clock pulse ~3 according
to t~e following ]Logic equations:
Alpha = DGl(DLYRQ + WTCH~CC)) 03
Numeric A = DGl(DLYRQ ~ WTCH(CC)) ~3.
" '~ - - '
~7~32
1 ~y inspection of the logic equation or logic circuit 498, well
known to the art, it may be seem that alphanumeric displays are
generated only for digit DGl during clock pulse ~3 either in
hours timeset (DLYRQ = 1) or during the chronograph counting
mode (CC = 1 and WTCH = l)(Figure 20~.
The alphanumeric identifiers, A, C, F, L, P, are storec
within RAM 52 at uniqut?ly assigned addresses. W~ - WC and CA -
CD are coded such that A and P, for watches incorporating the
AM/P~ option, is displayed only during hours times~:t, and C, F, L~
or P is displayed only during a selected chronograph sequence.
The alphanumeric symbols are permanently stored in the RAM by
modifying a standard memory cell to read only, i.e., by omitting
the first CMOS inverter, and the associated CMOS transmission
gate and by coupling the input of the second CMOS inverter either
to Vdd or Vss as determined ~y the selected cod~.
Logic circuit 500 is a circuit for the generation of
internal control signal L which is directly coupled to the
segment driver for the colon. In the present embodiment as
illustrated in Figure 22 logic circuit 500 is fabricated by means
well known to the art and has a 1 and 2 Hz input and 3 mask options.
Three options will give a pulsed L signal with a 25%, 50%, or
7~% duty cycle. The logic equation for signal L is as follows:
~ = ~A + WTCH + TS ~(lHz)~2Hz~ ~ lHz + ~lHz + 2Hz~
Only one of the or-ed terms within the ~rackets is selected by
appropriate masking and each term represents 25%, 50% and 75%
duty cycles from left to right respectively.
As previously discussed, during a timeset mode, when
minutes units are c:ycled then seconds tens and seconds units are
reset to zero. Int:ernal control signal, reset seconds, RSC
provides this funct:ion and is generated by NOR gate 502 (Figure 18).
-58-
, :,. ~. .
..... . . . . : ..
.. . - ., . .: .. . . ~ . . . , -, - :
. , .: .
- . .~ : .
~74~L3Z
1 NOR gate 502 has one input to PLA 432 and one input to the Q
terminal of latch 428 o~ the timeset state counter Figure 16.
AS previously described, latch 428 will trigger NOR gate 502 to
reset the second units and tens when minutes units are being time-
set. However, when switch S2 is again closed to restart the
watch, the flashing of the colon is resynchronized with the
new seconds count. This is accomplished by means of RS NAND
latch 504 in conjunction with NAND gate 506. The set terminal
of latch 504 is coupled to the Q output of latch 428.
1~ As previously described on an S2 closure, after minutes
units, the Q output of latch 428 is set true (Figure 16). Latch
504 i5 normally in the reset condition. The reset terminal of
latsh 504 is coupled to clock 02. Therefore, during the clock
interval 02 the reset terminal of latch 504 will be false and the
set terminal of latch 504 will go true. The Q output of latch
504 then switches from false to true. The inputs of NAND gate
506 are the Q output of latch 504 and the Q output of latch 428.
Both inputs are now simultaneously true generating a false output
for LRST. When LRST goes low, the output of ~A~D gate 508
illustrated in Figure 7 will reset the 1 and 2 Hz timing generators,
flip-flops 232-240. This will have the effect of resynchronizing
the colon flashing~ timeset cycling, and timeset flashing with
the seconds count.
DEBOUNCE AND ASSOCIATED CIRCUITS
Figure 23 illustrates the generation of switching
signals SWl - SW3 from the switch closures of switches Sl ~ S3
through a debouncle circuit 510. Each switch is coupled directly
to debounce circuit 510 which requires that the input change be
valid for at least 31 milliseconds before such change is
3a acknowledged as valid. Debounce circuit 510 is driven ~y a
'
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. ' - '. ' ' , ~ . . .'. ,. . : ' . , ';
~7~L3Z
1 generator which produces 1/2 millisecond wide pulse every 30
milliseconds alternately from NOR gates 512 and 514~ The 30
millisecond generator is driven by the 32 Hz segment voltage, COM,
described below, and by the 1024 Hz voltage from the prescale
divider.
The signal, COM, provides the clock voltage for flip-
flop 516. The Q and Q outputs of flip-flop 516 are 16 Hz signals
coupled to the inputs of NOR gates 518 and 520 respectively.
When COM is false the output of nand gate 522 must ~e true. The
output of nand gate 522 is coupled to the set terminal of RS nand
latch 524. Therefore, the Q output of latch 524 will be true and
the output of nand gate 526 will ~e true. Normally the output of
nor gate 528 is true so that the outputs of nand gates 512 and 514
will both be false when COM is false. COM and the 1 KHz signal
are synchronized. Therefore, when COM is true, the first pulse
of the 1 ~Hz signal will be inverted and will be false at the
inputs of nand ga~e 522. The output of nand gate 522 will remain
true. Therefore, during the first 1 KHz pulse, the set and reset
terminals of nand latch 524 will simultaneously be true, making
the inputs to nand gate 526 simultaneously true. A false output
from nand gate 526 will then set the output of either nand gate ~ -
512 or 514 true as determined by flip-flop 516. Half a millisecond
later, when the lKHz signal begins to go true, latch 524 will be
:.
reset and stay reset thereby setting the outputs of nand gates -
512 and 514 false.
The output of nand gate 512 is coupled to the input of
and gate 529. The other input of nand gate 529 is coupled to a
CMOS gate input protection circuit 530, well Known to the art,
which protects and gate 529 from accumulation of any static charges.
; 30 The ouput of protection circuit 530 is true on a Sl closure.
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~ .
- . - . . - - ~ . :. : . . . - . , . .. .: , . :
.: , . . . I . . . - : . .: ., . . .. . . : ,.
.: . : - .: : . . . ~:. . :
~C~74~32
1 Normally, pull-down device 532 holds the Sl input of and gate 529
low, but is overridden on an Sl closure. Therefore, normally
the inputs of and gate 529 are ~oth false while and gate 534 has
a false and true input. If Sl closes, and the output of nand gate
512 goes true, the output o~ and gate 529 will go true. This
will set ~he Q output of RS nor latc~l 536 true.
Protection circuit 530, the Q terminal of latch 536,
and the output of nand gate 514 are inputs to and gate 538. Latch
536 will ~e reset on the next pulse from nand gate 512 if switch
Sl is open. If switch Sl remains closed until and gate 514 goes
true and if latch 536 remains set, and gate 538 will have a true
output, and and gate 540 will ~e false. The output of and gate
538 is coupled to the reset terminal of RS nor latch 542. The
signal SWl will then be set false indicating that switch Sl has
remained closed for at least 30 milliseconds. La~ch 542 will be
set on the next pulse from nand gate 514.
An identical de~ounce circuit is associated with switches
S2 and S3 so that any transient signals not valid for at least
33 milliseconds are ignored~
The signals SWl and SW3 are coupled to the inputs of
nand gate 544 to generate internal control signal CYCLEC. CYCLEC ~ ~ -
is a hal~ millisecond negative pulse which occurs for each negative
transition of either SWl or SW3 when the clock is in the chrono-
:
graph mode. CYCLEC is used as one of the input signals to generate ~-
signal STCR as illustrated in Figure 9. I~henever signals SWl or
SW3 have a positive transition indicating a switch Sl, or switch
S3 closure during a chronograph cycle (WTCH = 0) a 1/2 millisecond
negative pulse will ~e generated. -
Normall~, SWl and SW3 are true so that the output of
nand gate 544 is fa]se. The output of nand gate 514 is also
-- .
-61- ~
, -
~1~74~3'2
1 normally false so that nand gate 541 has a true output. Thus,
nand latch 543 is reset and the output of nand gate 545 is
normally true. As either SWl or SW3 go false, the output o~
nand gate 544 will go true and nand 514 will go true. The in-
puts to nand gate 541 will both invert leaving the output true.
Latch 543 will remain in the reset state ~ut all the inputs io
nand gate 545 are now true so that CYCLEC goes false. Thirty
milliseconds later, nand gate 541 will again go false. The in-
puts to nand gate 541 are now both true, setting the output of
nand gate 541 false. Latch 543 will ~e set and CYCLEC will re-
turn true since latch 543 will remain set until SWl and SW3 are
~oth again true.
As shown in Figure 24, whenever RESET is true, pro-
tection circuit 546 will have a high output which is inverted
and coupled to nand gate 549 there~v setting the master reset
signal, MRST, true. MRST is used to reset all D-type flip-flops,
counters, latches, and memories. Every counter within the pre-
scale divider circuit is reset from the frequency 512 ~z and
lower. Thus, during master reset, master oscillator ~0 will
~ drive the first five flip-flops in the prescale divider and will
generate the 1 KHz clock. The 1 KHz clock is used to drive D-
type flip-flop 547. Flip-flop 546 is biased so that when the
battery is inserted into the watch the Q output will always ~e
set ~alse. Thus, MRST will always ~e set true when the chip is
first connected to the power supply. The 1024Hz clock is used to
set the Q output of flip-flop 547 true after a maximum of three
1 KHz clock edges.
F~;ST TEST CIRCUITRY
If RESET is true, nor gates 548, 55a, and 552 will each
have a false input, and nor gates 554 and 556 will have a true ~ ;
input. The terminal fast test one, FTl, coupled to nor gates 548
and 550 through protection circuit 558, will control the internal ` -
, " ,.
-62- ~
- .
~C~74~3Z
control signals, LTON and LTOF, which will turn the entire dis-
play off or on as described below.
The fast test terminal, FT2, coupled through protection
circuit 560 to nor gate 552 will generate the internal control
circuit, LTINV, ~lich will disenable the 32 Hz clock there~y
causing a DC signal to be set in the segment display. Thus,-the
segment display may ~e cycled through all the DC states possible
~y appropriate inputs at FTl and FT2.
When RESET returns from true to false, the output of
nand gata 459, MRST, will ~e fixed true. The output of nand gate
562 in Figure 26, is initialize sequence, MR. When M~ goes true,
a series of sixteen T2 pulses are gen~rated causing the RAM to
access each state of the watch sequence counter. At the 16th
pulse, as illustrated in Figure 15, WCH goes to zero activating
latch 564 so that the output of nand 562 goes true and therefore
inhibits the T2R reguest ~Figure 8). The initialize seguence, MR,
is also one of the PLA inputs as illustrated in Figures 2 and 11.
MR deactivates all normal PLA minterms J and activates the power-
up initialize minterms. As shown in Figure 11, MR will also reset
~ flags Kl - X3 and as shown in Figure 25 will initialize the scart
up of voltage converter 566 which is disclosed in U.S. Patent -
- 3l975,671 Stoll which issued August 17, 1976.
When RESET is low, FTl and FT2 will generate internal
control signals FTW and FTC from nor gates 554 and 556 ~Figure 24).
As previously described, these signals will speed up the T-gener-
ation of latches 358 and 368 to 10 Hz (Figure 8). Finally, when
either FTl or FT2 are true the output of nor gate 528
will disenable the outputs of nand gates 512 and 514 (Figure 23)
so that the debounce circuits remain inoperative. Therefore,
signals SWl - SW3 will respond without delay to any changes in
-~3-
~74~3Z
1 the switch inputs and will allow accelerated testing.
SEGMENT DISP:I:.AY CTRCUITS
- Tne entire watch circuit, excluding output, has now
been descri~ed and the desired information is provided at data
bus 80. The remaining circuitry will decode and display the
information at the selected digit positions.
The digit scan outputs, DGl - DG8, and the RAM data
outputs coupled through decoder 90 and segment font 92 are combined
and displayed in decimal output ~y display drivers 56 ~Figure 1).
During clock 02, RAM data, D0 - D3, iS presented to the inputs of
four CMOS latches collectively denoted in Figure 27 by reference
character 568. Each CMOS latch 568 is comprised of a nor gate
570 coupled to an inverter 572 which has a feed~ack loop to nor
gate 570 through a CMOS transmission gate 574. RAM data inputs
D0 - D3 are also gated into the CMOS latch 568 through a CMOS
transmission gate 576. CMOS transmission gates 574 and 576 are
driven by a nor gate-inverter com~ination 578. Nor gate-inverter
combination 578 is in turn controlled ~y clock signal ~2 and Tl.
Thus, CMOS latches 568 are in the latched mode at all times
except during the clock interval Tl ~2. CMOS latches 568 serve
to ~uffer and isolate the entire display circuitry for the
remainder of the integrated circuit chip and to allow selected
dig~ts and multiplexing rates to be applied to the segment drivers
should the chip ~e adapted to a LED output. In the present
embodiment, a LCD output is descri~ed, although the present
invention may be used with ~ither LCD or LED outputs.
Decoder 90 and segment FON~ ROM 9 2 in Figure 28 form a
nand P-type decoder array in combination with an N-type nor ROM
array in the same manner as PLA 74 and display sequence ROM 54
and decoder 48. Decoder 90 and ROM 92 translate from the BCD code ;
used throughout the chip to a 7 or 9 segment decimal display font.
, .~. ~ ,. . . - . .
-64-
':
.. ..
~:~741l 3~
1 Decoder 90 and ROM 92 are accessed during clock
intervals Tl 03 and Tl 04. In the presently preferred em~odiment
decoder 90 and ROM 92 are programmed and coded as shown in Table
8. Two seven segment and one nine segment display font may he
generated, namely numeric A, numeric B, and alpha although the
present embodiment uses alpha and numeric ~ only.
~ -type transmission gates 580 form a multiplexer which
appropriately selects one of the fonts and couples the selected
display signals, SA - SJ onto the segment bus. Zeros are written
onto each of the lines of t~e segment ~us during the time interval
Tl ~1, and Tl 03 - Tl 04 by means of a disenabling signal coupled
to P-type pull-up devices, collectively denoted by the reference
numeral 582, which devices are combined with inverters, collectively
denoted by the reference numeral 584. Pull-up devices 582 are
driven by nor gate 586 which has Tl and 02 as it inputs.
After the font format has been selected by appropriately
activating selected transmission gates 580, the digits of the
display are strobed by the`digit scan by means of serial activation
of digit select signals, DGl - DG6. The segment driver for segment
4G is illustrated in datail as an example in Figure 29. In the
segment driver corresponding to indicia member 4G, the correspond- -
ing inputs are the digit select signal, DG4 and the segment
select signal SG. Both signals are inputs to nand gate 588. If
bo~ input signals are true, nand gate 588 will have a false
output, otherwise the output is true. Digit select signal DG4
and the output of nand gate 588 are the inputs to nand gate 590.
W~en digit DG4 is strobed but segment SG is selected, nand gate
590 ~ill have a z~sro and one input, and will, therefore, have a
true output.
Nand gates 588 and 590 drive a level shifter circuit
coupled between Vdd and Vtt (Vtt > Vss~ so that an appropriately
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'
~i7~3Z
1 high voltage may be applied between the segments and common plane.
The output of nand gate 588 is also coupled to the gate of P-
type device 592 while the output of nand gate 590 is coupled to
the gate of P~type device 594. If the gate o~ device 594 is
true, it will be nonconductive. However, i~ the gate of 592 is
false, it will be conductive thereby causing node 596 to go true.
Node 596 is coupled to the gates of latching devices 600 and 602.
The binary one at node 596 will hold latching device 600 off
while latching device 602 ~ecomes conductive thereby pulling node
598 to a binary zero. Node 598 is coupled to the gates of latching
devices 604 and 606. A binary zero at node 598 causes latching
:,
device 604 to be nonconductive and latching device 606 to be
conductive thereby reinforcing the binary one at node 596. It
may be appreicated that once latching devices 602 and 606 are
conductive, the inputs to P-type devices 592 and 594 are immaterial
and the circuit is latched into the state defined ~y NAND gates
588 and 590.
In the example illustrated, a binary one at node 596 and -
a binary zero at node 598 causes transmission devices 608 and 610
~ to become conductive. Thus, segment 4G becomes coupled to
potential on the common line, COM. Thus, the data is retained
within the segment driver until the next strobe pulse.
Had digit select signal, DG4, been false, the output
of nand gate 588 would have been true and the output of nand
gate 590 false. Device 592 would have become nonconductive.
Device 594, however, would also have become conductive pulling
, .. ..... .
node 598 to a binary one. The binary one on node 598 would have
caused latching device 604 to become conductive pulling node
596 to a binary zero. Latching device 600 would have become
conductive, latching the level shifter circuit in the opposite
state so that transmission devices 612 and 614 would become
-66-
~L~7~
1 conductive ~-hile transmission devices 60~ and 610 have become
non~onductive. In such a case segment 4G becomes coupled to the
common line, COM. There being no phase difference between the
activated segment and the common plane, segment ~G would remain
unilluminated in a LCD output.
The same result occurs if digit select signal DG4 is
high while segment signal SG is low. In the case w~en both digi-t
select signal DG4 and segment signal SG are low, the output of
nand gate 588 is high. The output of nand gate 590 is also high.
~ In such case, whatever information was previously stored in the
latch circuit remains stored there and the output does not
c~ange. Therefore, the display for each segment remains constant
until the next digit select pulse, DG4, at which time the state
- of the latch is changed to reflect the state of the segment data
bus SG.
The colon, segment L, the decimal point, DEC, and the
date identifier, DATE, are DC signals generated ~y the master
timin~ and control circuit 44, as previously described, and are
presented to a latch circuit 610, which is similar to that of the
segment drivers. Level shifter 616 drives a CMOS transmission
pair 618 similar to devices 608 - 614.
The segment drive, COM, and its complement are generated
from t~e 32 Hz clock derived fro~ and control circuit 44. Driving
the li~uid crystal display at 32 Hz increases itsstability and
longevity. The 32 Hz signal and its complement serve as-the power
supply for phase select circuits 620 a~d 622 which are clocked by
the internal control signals lamp test on, LTON, and lamp test
off, LTOF respectively (Figure 30). The output of phase select
circuits 620 and 622 are coupled to the input of level shifter
30 circuits 624 and 626 respectively. The output of phase select 620
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. ,:
- .... . ,. . .. : . , ~ - . : , ,.,:, . ~ . - - . -
~74~32
l will be the 32 Hz signal when internal control signal LTON is
high, otherwise it will be 32Hz. Level sh:ifter circuit 62~ and
626 are bistable CMOS flip-flops which serve to transform the
voltage levels from those compatible for integrated circuit chip
to that necessary to drive the LCD output.
The output of each level shifter circuit 624 and 626
is coupled to a CMOS inverter 628 and 630 respectively. The
output from CMOS inverter 630 is 180 degrees out of phase from
the output from CMOS inverter 628 provided LTOF and LTON are both
1~ in the same state. By causing internal control circuit LTON to
change state, the output of inverter 628 may be shifted 180
degrees such that COM is changed to its complement and all LCD
segments are displayed regardless of the data stored in the latch
of the segment driver. Similarly, eac~ segment may be turned
of~, regardless of data input by selectively activating internal
control signal LTOF.
Finally, to turn all digits off and to provide control
o~ leading zero suppression, individual digit blanking, and flash-
ingf internal control signal, BLANK, may be generated by timing
~ control circuit 44. As shown in Figure 27, internal control
signal, BLANK, is an input to each nor gate 570. When the internal
control signal, BLANK, goes true, the output of each nor gate
570 must go low. Thus, the output of latches 568 each go true
representing the number llll. There is no valid numeral correspond-
ing to the binary num~er 1111 ~15~ in BCD coding so this number
is decoded by decoder 90 and ROM 92 ~y placing each of the LCD
se~ment signals, SA - SJ in a low state. Thus, the LCD output is
~lank.
The present invention has ~een described in relation
to a specific em~odiment. It is intended that other em~odiments
-68-
"' ,'",
- .: .. . .:,: . . . .
: : . - - .: - - - . - . ~, ~ . : .
.. . . . . . ..
.. ,: , . . .. . : :
~ ~37~3Z
1 may be provided by changing the various PLA, decoder, and ROM
codes or RAM organization. Such embodiments may include an a]arm
clock having multiple and variable alarm settings. For example,
the alarm setting could include:
TABLE 8
ALARM - SETTINGS
_
single month, date, hour, minute
double ~month, date~, (month~ date) 2
double (month, date), (hour, minute~
double Uhour~minute), ~hour,minute) 2
dou~le (month, date, hour, minute)
~month, date~ 2
dou~le (month, date, hour, minute)
~hour, minutel --
Other embodiments could include a double watch capa~le of
simultaneously keeping two independent time records, e.g.~
corresponding to separate time zones. Still further em~odiments
could include a chronograph / counter. For example, the present
em~odiment could be modified to include two stopwatch modes and
an incrementor and decrementor to ~e used for counting. The
watch could also be modified to include three stopwatch modes to
record elapsed times ~or three consecutive events, such as, win,
place, and show, and a counter. Other alterations and modifica-
tions in circuitry may also be made ~y those having ordinary skill
in the art without departing from the spirit and scope of the
present invention
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- : . - . : - . . .
- : :- .
