Note: Descriptions are shown in the official language in which they were submitted.
~L~'7~6
This invention relates to information storage devices.
Background of the invention
There is a wide variety of electrical devices in which
information storage is an essential feature. Memory and
logic devices often rely on magnetic mechanisms in which the
information is represented by the polarity of magnetic
domains stored in a sheet, hollow core or wire.
In the usual form of the video camera an optical image
is stored in the form of electrostatic charge on a monolithic
storage layer. The localized charge density of the electro-
static pattern is then "read" with a scanning electron beam.
Information storage is also implicit in delay lines.
These devices are typically acoustic or electromechanical with
the information stored dynamically in a traveling elastic
wave.
Electrical storage devices commonly comprise arrays of
devices connected in logic patterns in which binary information
is stored and processed by sequential switching of the
devices.
2~ Statement of the Invention
In accordance with an aspect of the invention there is
provided a semiconductive device comprising a semiconductive
charge storage layer having a major surface, an insulating
layer overlying said major surface, an electrode assembly ;
on the insulating layer including a plurality o~ electrodes
for forming a succession of storage sites for the storage of
charge carriers in the charge storage layer and for transfer-
ring stored charge carriers between successive sites în a
predetermined direction, the device characterized in that ~
30 each electrode over-lies a region of the charge storage layer ~-
which is essentially of a single conductivity type. ~
,1 - 1 - .
~ .
.
. : .
~7~ 6
The present invention involves an information storage
mechanism that is unique and versatile. It offers many of the
advantages of the several forms of storage devices mentioned
above.
Applicant has recognized that electric charge can be
stored in a spatially defined potential minimum within a
semiconductor; that the storage site within the semiconductor
can be selected; and, most importantly, that the storage
site can be changed within the semiconductor in at least
.... .. ..
two dimensions. Thus electric charge, representing ;
information, can be generated, translated and retrieved.
In a static sense, the sites are used for storage
according to the invention are well known. They are
depletion layers or
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.... , . . . ;. . . .. ~ . . . .
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locali~ed electric fie]ds that are capable of trapping and
storing MinoriLy charge carriers. For tl-e purpose of the des-
cription of this invention, these storage sites will be termed
"potential wells." It is important to recogni~e that this device
relies on minority carriers exclusively to represent the informa- -
tion throughout the generation-transfer-detection operations.
A potential well can be generated at a desired location
in the semiconductor by locally biasing the semiconductor. '~his
can be facilitated in a representative embodiment by forming an
electric field pattern over the semicondllctor surface. The pat-
tern may be monolithic for certain forms of devices (to be de-
scribed below) or may assume a specific geometry to perform a
desired function, e.g., a logic function. In a preferred embodi-
ment of the invention the devices comprise an MIS array and the
depletion region is formed via the wel:L-known field effect.
The potential wells can be cllarged initially by several
methods. These will be treated in detail below along with de- -
tection or readout schemes. The translating function is achieved ;
by moving the potential wells along the desired translation path.
This has the effect of moving the charge accumulated in each well.
Since mobile charge influenced by more than one potential well ~ ;
wlll accumolate in the deep~es~ po~ential well, operation of some ; ;
charge coupled device embodiments will focus on the deepest of ;~
.
more than one overlapping potential well. -~
Detailed Description of the Invention ;
. .
The following detailed description sets forth various
embodiments of the invention, all of which share the basic in-
formation storage feature described above. In the drawing:
FIGS. lA to lD are schematic diagrams ~llustratlng
the charge translating mechanism according to one embodiment;
FIG. 2 is a front sectional view, partly schematic, of
7~
a shift reglster em~odying the information storage feature;
FIG. 3 ls a pulse program for the shift register of
FIG. 2; .
FIG. 4 is a front sectional view partly schematic il-
lustrating a preferred method of charge translation;
FIGS 5A, 5B and 5C are largely schematic representations
of means for detecting the presence or absence of charge in the
terminal translating stage;
FIGS. 6A and 6B are schematic representations of pre-
ferred techniques for enhancing charge translation,
FIG. 7 is a plan view of a multichannel shift register,an extension of the device of FIG. 2;
FIG. 8 is a plan view of a preferred conductor arrange-
ment designed to avoid crossovers in the three-conductor storage .
control circuit;
~ IG. 9 is a perspective view of a portion of a charge
translating device illustrating a preferred electrical contact :
arrangement;
FIG. 10 is a front sectional view of a charge trans- -
lating device showlng an alternative electrical contact arrange-
ment; :~
FIG. 11 is a front section, largely schematic, of an -
image détection device employing features of the invention; :.:
FIG. 12 is a front sectional view of an alternative
means for transferring charge that does not require wire con- ~ .
nection: to ~ach transfer stAge and ~
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, . . .
.
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FIG. 13 is a front sectional view illustrating a
structure alternative to that of FIG. 12.
Detailed Description
FIGS. lA to lD illustrate the charge transfer
process according to one embodiment. The transfer mechanism
of all embodiments herein is similar in concept. In FIG. lA
the semiconductor substrate 10 is covered with a thin
insulating film 11 and two metal electrodes 12 and 13 which
form part of an array. In FIG. lA, electrode 12 is biased
while electrode 13 is not. A depletion region or potential
well 14 forms under electrode 12. In FIG. lB, minority
charges 15, created through, e.g., hole-electron pair
generation from photon absorption, are shown migrating to
the depletion region 14 and stored there. When electrode 13
is biased simultaneously with electrode 12, the depletion
region extends continuously below both electrodes as shown
in FIG. lC. The charge redistributes across the enlarged
layer. As the bias on electrode 12 is removed, as shown
in FIG. lD, the portion of the depletion region under
; 20 electrode 12 collapses shifting all the charge to the
potential well 14' that is now associated with electrode 13.
In a like manner the charge entity represented in FIG. lD
can be shifted stepwise to any location in the semiconductor.
It will be recognized that the substrate 10 of FIGS. lA to ~ -
lD can be p-typed and the charges reversed in sign. -;
The utilization of this translating mechanism is
illustrated, according to one embodiment of the invention,
in connection with the shift register of FIG. 2. Th~$
device is chosen for illustxation because it is a funda-
30 mental structure from which many forms of logic andImemory ~-
devices can be derived. The structure is similar to that
of FIGS. lA to lD. A semiconductor substrate 20 is covered
4 --
, . , ., - . , ,, . ~ , .
~'7~
with dielectric layer 21 on which is foxmed a sequence of
electrodes 22 to 24, in triplets designated a and b through
n (as beina parl of a series terminating with 24n). Conductors
designated 22', 23', and 24' join each third electrode. In
this embodiment the input or generating stage shown at 25 is
an MIS device driven to avalanche condition. The charge
generated at 25 migrates as shown to the potential well 27a.
This figure illustrates the transmission of a sequential -
pulse train.
The shift register can be operated in a recirculat-
ing mode either for increasing the storage duration, or for
regeneratingthe signal to overcome noise or charge losses,
by simply connecting the output signal back to the input
stage through an appropriate regeneration circuit 33.
It should be appreciated that an important device
application is implicit in the operation of the device of
FIG. 2. That application is information or signal delay.
Many~forms of delay lines can make use of structures similar to
that of FIG. 2. By sequentially biasing conductors 23', 24',
and 22', the charge will shift into pocket 27b. In a like
manner the charge is translated into pocket 27n and then
into the depletion region 28 accompanying the p-n junction
29 of the output stage. A pulse output is then detected
across load 30 as shown. A bias source 31 is connected to
electrode 32 to bias the junction.
The output stage shown here utilizes a p-n junction
to extract charge collected from the terminal stage 24n. A
directly analogous detector which is equally effective is a
Schottky barrier device. An appropriate Schottky device is
described in The Bell System Technical
_ 5 _
~ . , ' -
Journal, ~ol. XLIV, No. 7, Sept. 1965 at pp. 1525-1528. For
purposes of definition, the aforementioned charge detecting de-
vices can be characterized by the term "barrier laycr."
An e~emplary pulse program for the shlft register of
FI~. 2 is shown in FIG. 3. (The ordinate is not to scale.) This
diagram illustrates transmission of the binary code 1101. While
it is no~ evident from this abbreviated representation, it is
clear from FIG. 2 that each element 22a through 22n is simultan-
eously pulsed via conductor 22', likewise for conductors 23' and
24~. The pulses on each element are timed such that the time
perio~ between the initiation of sequential pulses, Vt, is less
than three times the pulse width, t . This ensures that the ;~
pulse on each sequential stage overlaps both the former and the
subsequent stage. Otherwise one potential well may collapse be-
fore the next one is accessible to the charge.
Referring back to FIG. lC, it will be appreciated that
the charge transfer time for that portion of charge situated
under electrode 12 will be equal to the fall time of the pulse
in FIG. 3. Experimental evidence indlcates that the transfer -~
time under the conditions outlined is quite fast. However, if
the pulse program of FIG. 3 is comparably fast, it may be advan-
tageous to use a pulse shape that gives a longer fall time. A
convenlent pulse form serving this function ls a sine wave.
A preferred modification of the charge translating
mechanism makes use of a continuous uniform bias on all conductors
so as to maintain at lea5t a shallow depletion layer over the ~ -~
entire surface of the dev~ice. This bias should be at least equal
to the threshold voltage for producing inverslon under steady ~
state conditions. ;
...
-- 6 --
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In this way the troublesome surface states, which are
inevitably present at semiconduc-tor-insulator interfaces
(and which cause adverse surface recombination), can be
maintained relatively free of majority carriers. That is, by
isolating the bulk of the majority carriers from the interface
via a space-charge layer, the carriers in the surface states,
having once.recombined with minority carriers, cannot then be
replenished. This technique, which simply requires a prebias
on every metal contact, insures a ].ong lifetime for the
minority carriers constituting the signal. In a device
having many stages this expedient may be essential
The modification just described is illustrated in
FIG. 4. The device corresponds to a mlddle portion of the
shift register of FIG. 3. The semiconductor base .layer 40,
which again is n-type, the insulating layer 41, and metal
contacts 42a, 43a, 44a, 42b, 43b, and 44b and the associated
conductors 42', 43', and 44' correspond to similar elements
in FIG. 3. The essential distinction is the presence of a
continuous hias voltage V' on all conductors to form a uniform
depletion region 45 over the entire device. Potential wells 46
are formed under contacts 42a,and 42b as the result of the
pulse voltage Vp superimposed on the bias voltage V'.
Input Stage
The shift register of FIG. 2 is.described as
having an avalanche device for creating charge at the input
location 25. There are several alternative methods for
creating minority charge carriers. For example, if the
input stage comprises a p-n junction, minority charge
carriers can be injected into the bulk region of the . :
semiconductor by forward bias pulses corresponding to the
.
- 7 - .~:
desired input signal. ~lternatively carriers can be in~ected by
MIS surface avalanching as described in Journal of Applied Physics,
Vol. 9, No. 12, p. 444. ~ hybrid structure employing a metal-
oxide surface contact on a p-n junction is effective for the same
purpose. Another alternative is to generate hole~electron pairs
by photon absorption or absorption of other ionizing radiation.
This is treated fully in application of M.G. Bodmer-M.H. Crowell-
E.I. Gordon-F.J. Morris, Serial No. 040,135 filed January 14, 1969,
and which issued as Canadian patent 882,314 on September 28, 1971.
The minority charge carriers will diffuse to a nearby depletion
region which in the case of the shift register of FIG. 2 is the
first stage 27a. A means for achieving this is shown in phantom
at 33 in FIG. 2. The element 33 is a light source - in this case,
a schematic representation of an electroluminescent diode. This
mechanism for minority carrier generation is quite useful in
imaging devices. These will be described in more detail below.
~ ~ .
The outpùt stage can also assume a variety of forms.
FIGS. 5A to 5C illustrate a few alternative embodiments. These
figures show the termlnal section of the device of FIG. 2 in-
cludlng the last transfer stage 24n. ~ach of these devices are
charge detection devices constructed according to known prin-
ciples. In FIG. 5A the detector is an MIS device and is there~
fore especially convenient, from a processing standpoint, where ~;
an MIS array comprises the transfer stages. With the semiconduc- ~;~
tor depleted, the capacitance associated with detector electrode
50 will indicate the presence or absence of externally introduced
charge in the depleted region 51. The capacity acrose the MIS -
detector is measured by a ~ ;
~ ..:,: :' ' '
-- 8 --
~.
,
L6
standard capacitive bridge as shown and the value indicated~
at detector 52. The bias source 53 is arranged via switch
54 to intermittently bias that portion of the semiconductor
below electrode 50 first to establish the depletion region
for attracting the charge to be detected and then to collapse
the depleted region to recombine the charge which may have
accumulated.
In the detection stage of FIG. 5B an alterna-ting
current source 55 is connected to two adjacent field plates
56 and 57, the latter again comprising MIS devices with
semiconductor 20 and insulating layer 21. A bias source 58
maintains a depletion region 59 beneath both electrodes 56
and 57. If charge is present in the terminal transfer stage
24n it is transferred to the potential well accompanying
plate 56 on its negative half cycle and then toward the well
of electrode 57 on the latter's negative half cycle. This
transfer of charge back and forth beneath electrodes 56 and 57
changes the a.c. impedance of the circuit from its value with-
out charge in the depletion layer. The presence or absence
of charge is thus detectable across impedance 60 by potent-
iometer 61. The switch 62 functions to erase the charge in
the manner of switch 54 of FIG. 5A. The speed of the erase
function can be enhanced by providing a switching network to
reverse the d.c. bias rather than merely removing the bias.
The detection stage of FIG. 5C relies on a direct
voltage measurement to detect interface charge QI accumulated -
,.
between semiconductor 20 and insulator 21~ The electrode
63 is biased negatively via source 64 connected in series
with a blocking capacitance which is shown in the figure
as a capacitor, 65, but may alternatively be a diode.
A change in the charge level ~I is reflected by a change
g _
.
7~
in the equivalent capacitance of the MIS device. This
affects the capacitive division between that element and
the capacitor 65 resulting in a change in VD. The voltage
VD can be measured in various ways, e.g., at the gate of a
field-effect transistor. Shown in FIG. 5C is a field-effect
device integrated with the semiconductor base 20 of the
storage device. A p-region 20A is shown representing
isolation according to known integrated circuit techniques.
The voltage VD being measured is connected to the gate
electrode 66. The insulating layer for the gate is shown as
an extension of insulating layer 21. Source and drain
regions 67 and 68 are diffused through windows formed in
this layer. Source and drain electrodes 69 and 70 are
connected through load 71 to bias source 72. Detector 73
indicates the conduction state of the FET which reveals the
presence or absence of charge ~I in the following manner.
A positive pulse delivered by power source 64
recombines any residual charge QI and primes the device for
detection. A negative pulse places negative charge on plate
63 and depletes the region under that electrode for collect-
ing holes delivered(or not delivered) from terminal stage 24n.
The gate 66 is biased at the same potentlal leaving the FET -~
in an "ON" condition indicated at 73. If charge ~I enters
the region below plate 63, the negative potential on the
plate will be reduced. The corresponding reduction in
potential at the gate electrode 66 will place the FET in an
"OFF" conditlon. If there is no charge QI the FET remains
"ON".
The device of FIG. 5C is shown partly integrated ~
30 the FET device can be used separately or the device can be ~;
further integrated, e.g., the elements 65, 71 and the electrical
- 10- ",
.. . : , ... .
~37~46
connections can be integrated.
Charge Translation Enhancement
The charge translating mechanism described in
connection with FIG. 1 relies in part on thermal diffusion to
transport carriers from potential well 14 to potential well
14'. While this transport mechanism is adequate, the response
time of devices using this mechanism can be significantly
reduced by using an electric field to drive the charge to
the new location. In many cases the use of the drive
field will improve the collection efficiency also. One means
of achieving this is to shape the potential well so that a
field gradient exists between adjacent wells. This scheme, -
which for the purpose of this description will be termed
"field enhancement," is shown in two illustrative embodiments
in FIGS. 6A and 6B.
- FIG. 6A shows two conductors 72 and 73 situated
on insulating layer 74 which in turn covers semiconductor
substrate 75. With the conductors 72 and 73 biased, their
respective depletion layers appear to have shapes indicated
by dashed lines 76 and 77. These lines, which represent
the boundaries of the depleted reyion of the semiconductor
also are a ~unction of the potential at the semiconductor-
insulabor interface~ Thus it is convenient in this discussion
to consider these boundary lines as potential profiles along
the surface of the semiconductor where the charge is stored.
As a conse~uence of making the size of the electrode
comparable to, or less than, the thickness of the insulator,
the field approaches the situation where it appears to
emanate as if from a point rather than a plate (as in FIG. 1)
and produces a continuous potentlal gradient along the
surface. This field ~radient is aptly described as a
-- 11 -- .
4a~6
- potential well and tends to confine the charge at its center.
When these wells are made to overlap (a condition implicit
from the previous discussion, e.g., the pulse program of
FIG. 3) the composite field profile is described by the
dotted line 78 of FIG. 6A. Now it is intuitively obvious
that the charges will transport from the region directly
under electrode 72 toward electrode 73. After the depletion
field represented by line 76 collapses, the charges will be
swept to the surface region of highest potential in the well
represented by line 77, or directly under electrode 73.
Field enhancement can be made more effective by
using a shaped pulse as described by FIG. 6B. For example, ~ -
if a saw-tooth pulse is applied to electrodes 72 and 73,
then at a time tl during the period of pulsé overlap (the
charge translating period), electrode 72 will be biased at a
lower ~oltage than electrode 73. This is indicated schematic-
ally by the arrows adjacent the respective pulse forms. The
separate field profiles at t1 are described by dashed lines
79 and 80 with the composite profile appearing as dotted
line 89. The field gradient in the direction of desired
charge translation extends instantaneously all the way to
.
the region immediately below electrode 73.
The schemes just described are but two of many
possibilities for produc1ng a field gradient or drive field
for the charge (or absence of charge) accumulated at the
initial storage location. All those arrangements which
produce field enhancement of charge translation are intended
to be within the scope of this embodiment of the invention.
Other Device Structures
.. . . _ _ ,
The one dimension shift register shown 1n FIG. 2
can advantageously be incorporated in a multichannel register
- 12 -
.
-
~(~7~6
as shown in FIG. 7. It is evident that the linear array
of FIG. 2 requires at least _ crossovers (the figure shows
3n-3 crossovers but a straightforward modification reduces
this number to _). Crossovers are used more economically
in the arrangement of FIG. 7 wherein the same number of
crossovers may provide a large number of channels. FIG. 7
shows four channels but this number can be extended without
àdding additional crossover connections. The conductor
arrangement of conductors 81',`82', and 83' is the same as
that in FIG. 2 with conductor 81' connected to contacts 81a
through 81n in sheet 86 and likewise with conductors 82', 83'
and electrodes 82a to 82n and 83a to 83n. Input stages
84 and output stages 85 have been discussed previously.
Another embodiment which is advantageous from the ; ;~
point of view of minimizing crossovers is illustrated by
the electrode configuration of FIG. 8. Shown there is a
portion of a device which may, for example, be a plan view
of a device similar to that of FIG. 4 and in which the
conductors are so arranged as to avoid the nece~sity of cross~
over connections. Using numbers preceded by "1" to indicate
elements corresponding with those of FIG. 4, the three
conductors 142', 143l and 144' are deposited directly upon a
raised portion of the insulating layer 140 and interconnect
electrodes 142a, 142b, 143a, 143b, and 144a, 144b, respect-
ively. The path followed by the charge as it is stepped
through this section is indicated by the dashed line 145~ In
this connection it should be appreciated that the charge is
being translated under conductor wires and thus forms a
convenient "crossunder" arrangement.
Other arrangements similar in concept to that of
FIG. 8 will occur to those skillPd in the art. These can
be described broadly as electrode configurations having a
- 13 -
~7~446
plurality of electrodes in which every third electrode is
connected to one o~ three conductors and is adjacent to two
electrodes, each of which is connected to a separate conductor
of the remaining two, with all of the conductors and
electrodes deposited on a single substrate surface. The
disposition of the conductors along the surface of the device
can be an important consideration. In a large array it is
impractical to bond each lead to its associated electrode.
Consequently the charge transfer circuit would
10 ordinarily be'printed directly on the'insulator co~ering the ~'
substrate. However, the effectiveness of the device often
relies on careful control o the field profile at the semi-
conductor insulator interface. If the conductors are in , , -
direct contact with the insuLator, the field from each lead
will perturb the desired field profile. To overcome ~his a
dual thickness oxide can be formed over the semiconductor.
Such an arrangement is shown in perspective in FIG. 9. The
semiconductor substrate 110 is first coated with a thin ~ ',
insulating layer 111. Next a thick layer of another
insu1atin~ material is 'formed on layer 111 and etched to form
a grid 112 with open1ngs for the metal field plates 113. The '
field plates can be deposited along with interconnections 114
using a single photolithographic step. Some~overlap is shown
. . .
in the figure to insure complete covering of the site. The
conductor paths 114 to the electrodes 113 are isolated from
the substrate by the thick insulator 112. The dual thickness -'~''
insulating layer is conveniently made by selecting two different
insulating materials, such as SiO2 and Si3N4 that have
.... . ..... .. .
different etching characteristics. Thus when the second
layer is etched to form windows for the electrodes an etch
can be selected which does not attack the first insulating
layer. An' alternate procedure known in the art
,:
-. , : : : ,. : : ..
for formin~ a dual tllickness layer is to deposit a continuous
first layer, etch the windows, and deposit another uniform layer.
~ n especially convenient fabricating techniq-le is il-
lustrated in FIG. 10. This is a front sectional view of a portion
of a planar processed device. The semiconductor substrate 120 is
again covered with a suitable thin insulating layer 121. ~ con-
tinuous metal layer is deposited on layer 121 and etched to form
discrete metal electrodes 122-124. A continuo~s insulating layer
125 is then deposited over the electrodes 122-124. Windows 127
are etched in layer 125 to the underlying metal. A ribbon or
beam lead conductor 128 is then deposited so as to contact elect-
rodes 122~124. The procedure has a distinct advantage in that
it is devoid of any critical photoresist alignment steps.
The capability of producing minority charge carriers in
the semiconductor by photon absorption, as mentioned previously,
and as treated fully in application of T.M. Buck-M.H. Crowell-
.I. Gordon, Serial No. 006,834, filed December 5, 1967, whichissued as Canadian Patent 874,014 on June 22, 1971, introduces
another category of devices which make use of tbe information
storage and charge translation mechanism. One form of this de-
vice is a video camera9 an embodiment of which is illustrated
schematically in FIG. 11. The essential characteristic of this
class of device is parallel read-in of information. Light in
the form of the optical image being recorded is incident on the
side of the semiconductor 130 opposite to the storage control
elements. The latter again comprise metal-insulator-semiconductor
devices as in FIG. 2. It bears repeating tha~ these elemen~s can
be constructed according to any suitable embodiment described
hereln and may comprise other types of
_, .
- 15 -
.
~g~74~6
depletion layer devices such as transistor-type structures.
The array shown contains three bit locations comprising
three electrodes designated 132a to 134a, 132b to 134b, and
132c to 134c connected to conductors 132', 133', and 134' in
a manner similar to the arrangement of FIG. 2. Except for
the parallel read-in feature, -the charge translation and
readout operation can follow the teachings described above.
The linear array shown in FIG. 11 may represent one raster i
line in a video system. The charge is stored at locations
132a-132c during the optical integration period. It is
read out serially by translating the charge to the readout
section (refer to FIG. 2). By sequentially reading each
raster line, the video frame is constructed. ~
It is evident at this point that the essential ~ - -
objective of the charge translation scheme is to create a
traveling potential well along the surface of the semicon-
ductor. The use of electrical connections for this purpose
has been described above. However other means of producing
a traveling potential we;ll offer distinct advantages. For
example, the field accompanying an acoustic wave traveling
in a piezoelectric medium is an attractive alternative. An
embodiment based upon this principle is shown in FIG. 12.
This figure shows a portion of the shift register of FIG. 2
with semiconductor 159, insulator 160, and a series of metal
contacts 161 corresponding essentially to similar elements
in FIG. 2. A piezoelectric layer 162 is deposited over the
metal contacts. This layer may be composed oE a suitable
piezoelectric material such as zinc oxide or cadmium sulfide,
and may be evaporated or sputtered onto the device. A
piezoelectric transducer (not shown) or other suitable means
creates an ultrasonic wave which propagates through the layer
162 parallel to the surface of the device. The electric
- 16 -
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... - . : : . . . .
.. . . .. . . . .. . . ..
~7~
field accompanying the elastic deformation in the piezo-
electric layer sequentially biases the electrodes 161 and
creates potential wells 163 that travel along the surface of
semiconductor 159. This is the same result that is achièved
stepwise in FIG. 2.
By extending the traveling field approach of FI~.
12 the discrete electrodes can be eliminated. For example,
FIG. 13 shows a device very simple in structure. The semi-
conductor 170 is coated directly with a piezoelectric layer
171. In this device the field that propagated in association
with the elastic wave in medium 171 ~initiated by an approp-
riate ultrasonic generator not shown) is used to form
traveling potential wells 172. A metal electrode 173 may be
used to create a uniform depletion layer over the entire charge
translating surface for the purpose described in connection
with ~IG. 4.
While the several embodiments described above are
set forth in terms of structure, a brief discussion of
material considerations is warranted. A very distinct
advantage of the novel device concept herein disclosed is
that materials suitable for each of the devices described
are available and well understood. For example, these
devices can be fabricated of silicon and silicon dioxide
according to well-established technology. Combinations of
insulators such as SiO2 - Si3N4, SiO2-A1203, etc. are
especially use~ul in certain circumstances as the insulating
layer. Known electrode materials are gold, aluminum and doped- -
silicon. A useful structure for the device of FIG. 2 could
employ lOohm/cm. n-type silicon as the base layer 20 and
1,000 A to 2,000 A of thermally grown SiO2 as the layer 21. -
The oxide which has given the best results so far is a dry
O , .
oxide 1,200 A thick grown in oxygen at 1,100C
17
. '
~L~7'~9L9L~
,
for one hour and annealed in a nitrogen atmosphere ~or one hour
at 400 C. The flatband potential for this oxide is typica]ly
-5 V. and the surface state density is of the order of 10
states/cm . Electrodes 22-24 may be gold in any typical thlckness,
e.g., 0.1 to a few microns. An appropriate charge generator is
a p-region, having a boron concentration of 1019 atoms/cm , driven
at a few volts. The detector may be a similar p-n junction. The
creation and detection of minority carriers in semi-conductors
can be accomplished by well-known techniques.
The dimensions of the transfer array can vary widely.
The spacing between electrodes depends upon the extent of the ~ -
space charge region permitted. For example if the semiconductor
is 10 ohm/cm. silicon and a voltage of 10 volts is used, the de-
pletion region will extend approximately 5~. This would suggest
an electrode spacing of the order of a few microns for the neces-
6ary overlap. The creation and detection of minority charge
carriers in silicon are easily accomplished using known techniques.
It should be understood, however9 that the devices described here-
` in are in no way limited to silicon and its associated technology
although that is relied on by way of example.
In assessing the contribution made to the art by the
foregoing device descriptions it may be useful to point out that
devices made in accordance with the novel principles set forth
will normally include a multiplicity of discrete storage sites.
Recognizing that each storage site has three electrodes in a de-
vice with three phase drive, or two electrodes in a device with
;~ two phase drive, and that a useful device would presumably have
at least two bits, then the minimum number of electrodes that
would be disposed between the input stage and the detectlon s~age
would be four. As a practical matter this number would be sig-
nificantly greater, for example 288 in a 96 bit device actually
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developed. Ilowever, these considerations are useful in pointing
out the qualitative difference between this device configuration
and gated MIS devices previously known. Even in efficiently in-
tegrated MIS arrays the signal is conventionally injected and
removed from the semiconductor at each control element. The
storage and transfer of electrical information carriers wholly
within the storage medium is a basically new approach to informa-
tion handling.
Another approach to this form of information handling
is described in U.S. Patent No. 3,621,283, issued November 16,
1971. The devices described in connection with that approach
are constructed so as to gate the free charge between adjacent
diffused regions in a semiconductor. The 8ate overlies one of
the diffused regions more than the other in order to impart di-
rectionali~y to the charge transfer. As a consequence, the
semiconductor area below each gate electrode includes regions of
both conductivity types.
~ y contrast, the charge coupled devices described here
are characterized in that the semiconductor areas below the
transfer electrodes are of a single conductivity type.
Various additional modifications and deviations will
occur to those skilled in the art. ~11 such varlations which
basically rely on the teachings through which the disclosure has
advanced the art are properly considered within the scope of this
invention. ; ;
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