Note: Descriptions are shown in the official language in which they were submitted.
16 BACK(',I:~OUND O~ T~IE I~IVENTION:
17 Fielcl oE the Inven-tioll: This invention relates to
:L3 data proccssincJ sysLems and more particularly to
19 appara-tus which test for malfunc.ions in the ~pera-ticn
of multiprocessing data processing systems.
21 Description of the ~rior Ar~: In one prior art
22 a~proach to system diagnostics, the maintenar.ce engineer
23 performs diagnostics on the svstem by manually setting
24 a series of toggle switches on the face of the s~yster
console. These switches set up a series of test
26 functions to be performed by the svstem while in the
27 maintcnance mode with the results of the tests appearing
2S in a liyht array on the console or printed out on the
29 system !?rinter. ~-
In a second ap~?roach a set of maintenance circuits
31 is providcd in each of the processors. '~he maintenance
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1 circuits are connected to sense and control noints in
2 the processor that are accessed during diagnostics.
3 Only one of the processors can be active during -the
4 diagnostics and the active processor is the only one
responsive to and capable of executing the maintenance
6 instructions. The maintenance functions are limited to
7 reading of sense noint words or writing of control
8 point words.
9 In the prior art each processor contained a copy
of the maintenance circuits and was capable of running
11 diagnostics only on iteslf. If the processor, through
12 hardware failure, was incapable of running its own
13 diagnostics under program control, the maintenance
14 engineer had to manually step the nrocessor through the
diagnostic routine using the console switches and
16 buttons and had to interpret the system state bv
17 reading lights on the svstem console. This nrocedure
18 is wasteful of the customer's time as well as making
19 the system more expensive by reauiring that the main-
tenance circuits be duPlicated in each of the pro-
21 cessors. ~hile the program controlled diagnosis was
22 faster than manual switch diagnosis, it lacked the
23 resolution of manual switch diagnosis because it was
2a limited to the execution of whole instructions.
OBJECTS OF THE INVENTION:
26 It is an object of this invention to enable the
27 main-tenance engineer to run program controlled diagnostics
28 on any E)rocessor in a modular processing system using
29 one of the other processors.
It is a further object of this invention to run
31 diagnostics on a plurality of nrocessors using a
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1 single se-t of maintenance circuits.
2 It is another object of this invention to imnrove
3 serviceability of the processing system.
4 SU~-lARY OF THE I21VENTIO21:
These and other objects of the invention are
6 accomplished by providing a maintenance console con-
7 taining a single block of maintenance logic which
8 serves all the processors in the system. This block
g of logic interfaces with each of processors in the
system and is capable of controlling any one of the
11 processors to run diagnostics on any other processor.
12 The maintenance engineer enters a diagnose instruction
13 into the normal instruction stream of the system
14 through the rna:intenance console. I~hen one of the
lS processors encounters the operation code for the
16 diagnose instruction it temnorarily halts processina
17 and fetches the operand for the diagnose from memorv.
18 The diagnose logic in the maintenance console and the
19 instruction field lines held by the fetching processor
are decoded. The diagnose instruction can be used to
21 perform maintenance console actions including store,
22 display, and logout, to eontrol error checking by
23 injecting errors into the system or disabling error
24 checks, to control a cycle counter during the execution
of instructions, and to inhibit overlap, disable the
26 interval timer and specify the type of rnain storage
27 checking.
28 Serviceability is improved by reducing cliacnosis
29 time through providing the ability to interpret mean-
ingfully the system error state. The two major
31 obstacles that limit the internretation are
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1 1) only a minor fraction of the circui-t elements in the
2 system are accessible to direct program control and
3 interrogation, called the addressing resolution pro-
4 blem, and 2) the time interval at which the system
status can be determined by the program is usually a
6 complete instruction execution time although the svstem
7 passes through many intermediate states. This is
8 called the timing resolution problem. For exam~le, a
9 typical READ instruction consists of generation of one
instruction address, execution of various decodes,
11 generation of an operand address, and the fetch of an
12 operand. Each event is triggered in synchronism with
13 a clock pulse and is limited to certain hardware which
14 can be observed by a logout. ~hile addressing reso-
lution is dictated by the logout and display points
16 chosen~ the diagnose improves time resolution through
17 controlling logout to an exact cycle within an in-
18 struction execution by controlling a cycle counter to
19 capture the status at a desired time at the end of a
clock cycle. In this way, the nresent invention combines
21 the speed of programmed diagnostics with the resolution
22 of manual diagnostics while using only a single set
23 of control logic.
24 BRIEF DESCRIPTION OF THE DRA~JI~IGS:
Figure 1 is a functional block diagram of a modular
26 data processing system including a maintenance console.
27 Figure 2 shows the format of the diagnose instruction.
28 Figure 3 shows the operand format for each diagnose
29 code type.
Figure 4 shows the forma-t of the control bits for
31 the diagnose instruction.
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1 Figure 5 is a functional block diagram of the data
2 flow of the diagnose instruction.
3 Figure 6 is a functional block diagram of the task
- selection logic of the diagnose instruction.
Figure 7 is a functional block diayram of the
6 console task control logic of Figure 5.
7 DESCRIPTIO~I OF THE PREFERRED EMBODIMENT:
Introduction:
9 In the preferred embodiment, the diagnose instruction
~ is used in a modular data pxocessing system of the type
11 shown generally in Figure 1. The modular data process-
12 ing system (M~S) comprises a plurality of autonomouslv
13 operating modules, quads 1-2, which are connected to a
14 common main storage 12 and a common maintenance console
1. Each quad contains two logically independent
16 instruction units 2-3 and 4-5 which share execution
17 units 6-7 and control units 8-9. Instruction execution
18 is performed in successive overlapped or "pipelined"
19 stages. For example, instruction n in I~unit 2 may be
operated on in parallel with instruction n+l in I-unit
21 4. The quad storage control 8 controls the accessing
22 of main storage 12 by I-units 2-3 and quad storage
23 control 9 controls the accessing of main storage 12 by
24 I-units 4-5. nuad storage control also controls input
and output of the system through channels 10 and 11.
26 Referring now to Eigure 5, it can be seen that
27 each I-unit includes a G-register 50 and an E-register
28 56. The function of the E-register 56 is to set up
29 instructions for execution. ~lhen an instruction
requiring an operand is gated into the E-register 56 by
31 the quad storage control 8, the operand is fetched from
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1 main storage 12, or from a small block of high s~eed
2 storage contained in the cruad storage control 8, and
3 gated into the G-register 50. The diagnose instruction
is stored in memory and fetched in the same manner as
other instructions.
6 Description of the Diagnose Instruction:
_
7 The format of the diagnose instruction is shown in
8 Figure 2. It ineludes an operation code field, a
g control code field, and two address code fielcls. When
the dia~nose instruction oneration code is decoded in
11 the É-register 56 of an I-unit, the I-unit initiates a
12 pipeline drain and causes the ~uad storage control to
13 fetc,h the diagnose o~erand from the address in r?e~ory
14 12 s~ecified by the Bl and Dl fields. The ei~ht control
bits frorn the E-register corres~oncling to the I-2
16 field of the diagnose instruction are then transmitted
17 to ~-register decode 57 in the maintenance console
18 over bus ~1 to be decoded to determine the ty~e of
19 diagnose o~eration to be ~erformed.
Figure 4 shows the forr,~at of the control bits for
21 tne diagnose instruction contained in the I-2 field
22 of the instruction and decoded by decode 57. Binary
23 bits S-9 are the class code which is decodec7, to define
24 four types of diagnose o~erations. Cocle 00 in bits S-9
is decoded as a diacJnose Mo-o~eration type of instruction.
26 ~7hen this type instruction is clecoded by decode 57, the
27 diagnose operand is loadec, into the maintenance console
28 staging register (MCSR) 52 from the I-unit G-register 50
29 over the maintenance console data bus in (~ICD~I) 51.
The console will then send a diaynose release signal
31 to the I-unit and normal instruction Processing will
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1 resume. This code is decoded as just described only
2 if bit 12 of the I-2 field is a zero. If bit 12 is a
3 one, the special function discussed later will take
4 place.
If the class code for the instruction type is
6 code 01, the console loads the diagnose operand from the
7 I-unit G-register 50 into the MSCR 52 and then stores the
8 contents of the MCSR 52 into the Console Local Store
9 ~CLS) 60 B-address over bus 65. This causes the ~aintenance
Console Address Register (MCAP~)/Cyclic ~rogram Counter
11 (CPC) double word to be changed, Figure 3. When the
12 store into the CLS 60 has been com~leted the diagnose
13 release signal is issued to the I-unit. The new address
14 contained in the Maintenance Console Address Register
(MCAR) selection of the CLS 60 will be used in conjunction
16 with a switch function initiated when the subseauent
17 diagnose instruction of code 11 is issued. The CPC
18 count will be used when the cycle count function is
19 initiated by a subsequent diagnose instruction of code
11.
21 Upon decoding a code of 10, the console loads the
22 diagnose operand from the I-unit into the ~lCSR 52 and
23 then stores the contents of the ~CSR 52 into GLS 60 at
24 the A-address. This causes the Maintenance Console
Data Register (MCDR) to be changed, Figure 3O When the
26 store into the CLS has been completed the diagnose
27 release signal is issued to the I~unit. The new data
28 contained in the ~CDR will be used in conjunction with
29 a store function initiated by a subseauent diagnose
instruction of code 11. As can be seen, codes 01 and
31 10 set up preliminary data to be used by the executive
32 code 11.
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1 The functions performed by code 11 take place in
2 two consecutive operations af-ter the diagnose operands
3 have been loaded into the MCSR 52. The first o~eration
4 works in conjunction with I-2 field status control word
steering bits 10-11, Figure 4, and status control word
6 mark bits 14-15 and sets new status control bits into
7 the maintenance mode register Q, A, B, or C of Figure
8 6.
9 The status control word mark bits 14-15 select one
of -the first three eight bit bytes (0-2) of the ~CSR
11 52. The mark bits 14-15 are decoded by decode 57 over
12 bus 61 to select the rlCSR byte to be stored into the
13 maintenance mode register by the code 11 diagnose
14 instruction. Bit~ 14-15 of 00, 01, and 10 will select
byte 0, byte 1, and byte 2, respectively. Byte 3 which
16 would be selected by mark bits of 11 has been reserved.
17 The status control word steering bits 10-11 -
18 designate the maintenance mode register to be loaded by
19 the byte selected by bits 14-15. The steering bits 10-
11 are decoded b~ decode 57 to designate one of the
21 four sets of maintenance mode registexs, Q, A, B, and
22 C to be stored into the code 11 diagnose. Steering
23 bits 10-11 of 00, 01, 10, and 11 select the ~O
24 maintenance mode register, the Bo register, or the
CO register for the E-unit.
26 The second operation of the code 11 diagnose works
27 in conjunction with maintenance console staging register
28 bytes 5-7 and performs a maintenance switch function.
29 Maintenance Console Staging Register byte 5 designates
the sink to be stored into for a store function or the
31 source of data for a display function, byte 6 designates ~-
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1 the switch function to be performed and byte 7 selects
2 the unit for which the switch function is to be performed.
3 Bits 12-13 of the diagnose I-2 field are special
a functions. The use of these control bits is an engineering
choice~ In the preferred embodiment bit 12 is used to
6 control the diagnose message display. Under diagnose
7 control, a message may be displayed on a CRT in the
8 Maintenance Console when bit 12 of the I-2 -field is a
9 1. The messages to be displayed are set up in the high
speed storage of the quad storage control 8 or in main
11 storage 12. The starting address of the message area
12 is loaded into the maintenance console address register
13 as part of a code 01 diagnose instruction as stated
14 previously. A subsequent diagnose instruction having
I-2 field bit 12 on will cause the maintenance console
16 1 to fetch the contents of the message area into the
17 Console Local Store 60 and display it on the CRT. The
18 CRT is not shown but is of the type well known to those
19 skilled in the art having the capability to display a
predefined block of data of a fixed size. The message
21 image will remain on the display until a subseauent
22 diagnose instruction uses the console local store 60 or
23 the manual switch input to OR gate 102 is rotated to a
24 position other than message display position. As can
be seen, the diagnose instruction uses the same inter-
26 face as the console manual switches~ The diagnose
27 release signal is issued to the I-unit after the
28 message data has been stored into the console local
29 store 60.
When I 2 field bit 13 is active, .~lCSR 52 data
31 stored into the console local store 60 over bus 65 for
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1 diagnose instructions of code 01 and 10 will be stored
2 with even parity on all bytes. This allows data with
3 "bad" parity to be injected into the odd parity system.
4 As has already been described, it is the function
of the diagnose operand fields of code 01 and code 10
6 to provide preliminary data to be used by the onerands
7 of a code 11 instruction. The functions of the operand
8 fields of code 11 diagnose will now be described in
9 conjunction with Figure 3. Byte 0 of the code 11
diagnose is the quad byte field. All the operand bytes
11 comprise eight bits. The maintenance mode register of
12 each unit in the system, i.e., the I-units, ~-unit and
13 quad storage control, is capable of operating under
14 control of the auad mode byte.
The first two bits of the auad mode byte are the
16 check control bits which control the action taken upon
17 the occurrence of a system error. These bits are
18 encoded to cause the following actions to be taken unon
19 the detection of a system error:
Logout on check-upon the detection of a
21 machine check errors logout is performed on the
22 system display or other output device;
23 s
24 Disable checks-upon detection of machine errors,
the errors are ignored and program execution
26 continues:
27
28 Stop on check-u~on detection of a machine error
29 the system goes into a stopped state;
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l Error correcting code count mode-this mode allows
2 corrected single failures to be counted and the
3 count of the correction to be recorded rather than
~ interrupting the system on each occu~rence of an
error.
6 The third bit of the quad mode byte field is the
7 Cyclic Program Counter bit. This bit, when active,
8 allows the unit to operate in the CPC r~ode under
g control of the CPC Stop byte and the CPC Reset byte
which were stored in the B-address of the CLS 60 by the
~l previous code Ol instruction.
12 The fourth bit of ~uad byte field defines a
13 different operation depending on whether the unit under
14 test is a quad storage control, I-unit, or E-unit. For
the QSC 8, the bit, when active controls all parity
16 generation stations in the ~SC 8 to generate even
17 parity rather than the normal odd parity. This mode is
18 used for diagnostic checkout of the error correcting
l9 code hardware.
For the I-units, the fourth bit de~ines a channel
21 diagnostic mode. 17hen active, this bit causes the
22 fifth through eighth bits of the Ao or Bo maintenance
23 mode registers to be decoded as a four-bit code used to
24 activate a Channel Diagnostic select line 29 to an
attached channel. When inactive, it causes the fifth
26 through eighth bits to be decoded as a four-bit code
27 used to address the I-unit checking stations in order
28 to disable or invert checking functions. This bit has
29 no effect on the E-unit ~'~'R CO.
~7hen the fourth bit is inactive in the I-unit ~rlR,
31 the fiEth through eighth bits are decoded as a four-bit
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1 code check station address. Check stations in the ~IPS
2 are used to detect errors, directly isolate errors,
3 determine data for effecting reconfiguration and
4 recovery and trigger logouts to get error environment
data to subseauent analysis. The four-bit check station
6 address is used to force erroneous check code bits at
7 each of the I-unit's check stations. These bits also
8 serve as the check station address for the E unit ~R,
CO-
Byte 1 of the code 11 diagnose is the I-unit byte-
11 A field. The maintenance mode register of each I-unit
12 in the system is capable of operating under control of
13 the I-unit byte-A field. Its functions are overlap
14 control, interval timer control, repeat instruction
multiple, and repeat instruction single.
16 The overlap control disables instruction overlap
17 and reauires that the execution of each instruction be
18 successfully completed before the next instruction
19 execution begins. This retains the operand of the
instruction under execution in the operand register
21 making it available for logou-t if an error occurs.
22 - The internal timer control disables updating of
23 interval timer. Repeat instruction multiple causes the
24 group of instructions currently in the selected I-
stream instruction buffer to be executed seauentially
26 and continuously, while repeat instruction single
27 causes the selected I-stream to execute one instruction
28 continuously. Repeat instruction multiple and repeat
29 instruction single cannot be active at the same time.
Byte 2 of the code 11 diagnose is the I-unit byte-
31 B field. This byte, like the I-unit byte-~ field, is
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1 eapable of eontrolling each I-unit maintenance mode
2 register. The purpose of the I-unit byte-B field is to
3 eontrol cheek point-retry, channel diagnostics, instruc-
4 tion step rate, fetch bypass, and cache replacement.
Checkpoint-retry disables instruction retry at
6 error eheckpoints. Channel diagnostic modifies channel
7 operations under diagnostic control. For example, data
8 parity can be reversed, byte counter parity can ~e
g reversed, or storage can be suppressed. Instruction
step rate eauses the I-unit to execute one instruction
11 per START. Fetch bypass eauses all I-unit fetch data
12 to come directly from main storage rather than the high
13 speed cache storage located in the quad storage control
14 and cache replacement causes the algorithm which
replaces the data in the high speed storage to be under
16 eontrol of the diagnose.
17 The S/D select field of the eode 11 diagnose
18 instruetion is the store/display se:Lect field byte.
19 This field designates the sink address for a store
function or the source address for a display function.
21 The elements in the system which are capable of being
22 stored into and read from are encoded in this binary
23 byte.
24 The next field of the code 11 diagnose is the
switch function field byte. This field designates the
26 switch functions to be performed and is used in conjunction
27 with the unit select field byte which follows. The
28 following switch functions may be executed under the
29 control of the switch func-tion field byte:
START-instruction processing is started in the I-
31 unit specified by the unit select field at the location
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l specified by tl~ contents of the instruction counter.
2 LOCK-prevents any diagnose request from the
3 alternate I-unit from being accepted by the console.
4 The alternate I-unit will remain stopped until the
U~JLOCK function is initiated by the decoding I-unit.
6 Also the manual controls from the console may not set
7 any maintenance mode register or initiate any function
8 involving the console local store.
9 UL~LOC~-resets the LOCR CO~lDITION.
CHECK RESET-this function resets the error triggers
ll of the selected units.
12 RESTART-this function, in accordance ~ith the unit
13 select field, causes the current program status word to
14 be stored, loads the new programs status word, starts
15 instruction fetching at the new location specified by
16 'che new program status ~ord, and executes instructions
17 as speclfied by the rate control.
18 UPDATE CACHE-causes contents of the hiyh speed
19 memory in the quad storage control to be stored into
20 main storage,
21 CLEAR CACHE-causes the UPDATE function to be
22 performed and also causes the cache directories to be
23 cycled and set to zero with good parity.
24 U~IT RESET-this function resets the units speci-ied
25 by the unit select field.
26 S~OP-stops instruction processing in the I-strean
27specified by the unit select field and places the I-
28stream in the stopped state.
29 LOGOUT causes a logout of the selected unit and
30associated I-unit. When the logout is completed,
31instruction processing resumes.
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l ADVANCE MCAR ADDRESS-causes the contents of the
2 ~lCAR to be incremented by 32 bytes if the store/ display
-3 select field is all zeros. Otherwise, the MCAR contents
4 will be incremented by eight bytes.
STORE-the contents of the MCDR replaces the
6 contents of the facility specified by the ~lC~R and the
7 store/display select field.
8 DISPLAY-the contents of the facility specified bv
9 the ~ICAR and the store/display select field replaces
the contents of the r1CDR.
ll START CPC-this function starts the decrementing of
12 the cyclic program counter on the first clock cycle
13 after the decoding I-unit is notified to start.
14 The last field of the code ll diagnose is the unit
l~ select field byte. The 8 bits of this field desicnate
16 a particular unit, or units, i.e., quad storage
~7 control, ~-unit, decoding I-unit, alternate I-unit, I-
18 stream, Cache, to be acted upon by the function specified
l9 in the switch function field and the store/display
20 select field.
21 DESCRIPTION OF THE DIAGNOSE HARD~1ARE:
22 Referring to Figures l and 5, the diagnose a~paratus
~3 includes a maintenance console staging register 52,
24 decode 53, decode 57, console task control logic 5~,
25 console local store 60, and OR gate 58 located in the
26 maintenance console l. ~c.ditionally, as seen in Figure
27 6, the diagnose apparatus further includes a set of
28 maintenance mode registers Q, A, ~, and C, which control
29 each unit in the system. The execution register 56
of each I-unit is connected to instruction decode 57 in
31 the maintenance console by bus 61. Decode 57 decodes
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1 the I-2 field, Figure 2, of the diagnose instruction.
2 The output of decode 57 is carried by bus 62 into the
3 console task control logic 54. The I-2 field of the
4 diagnose instruction defines which of the three types
S of diagnose instructions shown in Figure 3 is being
6 executed. The operands for the diagnose instruction
7 located in G-register 50 of the decoding I-unit are
8 transferred over maintenance console data bus in 51 to
9 the maintenance console storage register 52. If the
class code field, Figure 4, of the I-2 field, Figure 2,
11 of the diagnose instruction is decoded by decode 57 as
12 01 or 10 all eight bytes of the operand stored in
13 maintenance console staging register 52 are transferred
14 over bus 65 to console local store 60. The contents of
the console local store 60 provides addresses for the
16 subsequent code 11 diagnose instruction as previously
17 defined under the description of the diagnose instruction.
18 Figures 6 and 7 show in detail the apparatus for
19 executing a class code 11 diagnose. The MCSR 52 is
shown in Fi~ures 6 and 7 broken down into bytes
21 according to the code 11 break down of Figure 3.
2~ Decode 57 decodes the I-2 field of the diagnose to
23 determine that a class 11 diagnose is being executed.
24 The SCW mark bits select MCSR 71, 72, or 80, i.e., byte
o, 1, or 2 of code 11, to be transferred to the appropriate
26 MMR. The mark bit output of decode 57 over bus 62
27 selects gate 73, 74, or 81 to pass the selected byte
28 through OR Dot 77 into AR register 78. The decode of
29 the mark bits is also fed into mode reyister set
control 82 over bus 87. The E-register decode 57
31 activa-tes gate 85 to transfer the contents of MCSR S4
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~ through OR gate 86, ~ode register set control 82 and
2 set/reset powering 83 into the selected ~IR. This is
3 the unit.select field which partially defines which of
4 the MMR's will be selected.by the diagnose instruction.
The decode of the SCW sterring bits feeds into mode
6 register set control 82 over bus 8g. The steering
7 bits select whi.ch of the ~IR's, Q through C will
8 receive the byte selected by the mark bits and cause
9 set/reset powering 83 to enable the selected ~IR. Upon
enabling the selected ~IP~ the byte ~asses from ~R
11 register 78 over bus 89 into the selected r~R. The
12 function performed by the selected byte was heretofor
13 described under the description of the diagnose
14 instruction.
The E-register decode 57 controls gate 111 over
16 bus 62 to gate MCSR 110 through OR gate 112 into main
17 storage decode 116 over bus 113 and into de~ode-inter-
18 face 115 over bus 114. Main storage decode 116 decodes
19 the byte to determine if the sink to be stored into for
a store function or the source of data for a display
21 function is main storage 12. Decode 115 decodes the
22 byte to determine the I-unit sink/source for a store/
23 display function. E-register decode 57 also activates
24 gate 101 over bus 62 to transfer the contents of MCSR
100 through OR gate 102 to switch function decode 103.
26 Switch function decode 103 decodes the contents of MCSR
27 byte 6 to set a number of task latches 104 indicating
28 which switch functions, as previously defined, are to
29 be performecl on the element selected by MCSR byte 7.
If the operation is a display, display SeCT 108 is
31 activated by the output of task latch 104 over bus
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1 106. Display seq 108 activates CLS read/write timing
. .
2 - control 118 over bus 126, maintenance console data bus
3 in/maintenance console staging register control 119
4 over bus 127, main storage display seq 109 over bus
128, the maintenance address assembly register/maintenance
6 console address bus out control 117 over bus 125 and
7 the decode/interface 115 over bus 124. The main storage
8 display seq 109 under control of quad storage control
9 120 causes the message contents of the main storage
area defined by the address in the console local store
11 60 to be transferred from main storage 12 into the
12 MCSR 52. Maintenance console data bus in/maintenance
13 console staging register control causes the contents of
14 G-register 50 to be store~ into maintenance console
staging register 50 over bus 51. The contents of the
16 maintenance console staging register 50 are then
17 transferred to console local store 60 over bus 65 under
18 control of the console local store timing control 113.
19 If the operation is a store, store seq 107 is
activated by the output of task laches 104 over bus
21 105. Store seq 107 activates the maintenance address
22 assembly register/maintenance console address bus out
23 control 117 over bus 121, the console local store .
24 read/write timing control 118 over bus 122 and
decode/interface 115 over bus 123. The maintenance
26 address assembly register/maintenance console address
27 bus out control 117 controls address gating to the
28 decoding I-unit. The contents of the console local
29 store 60 is gated over MCDBO by console local store
read/write timing control 118 to the decoding I-unit.
31 Store seq 107 controls the quad storage control to
WA9-75-002 - 18 -
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1 store the data from the decoding I-unit into main
2 storage at the address defined by the maintenance
3 address assembly register/maintenance console address
4 bus out contr~l 117.
OPERATION: .
6 From a normal instruction fetch, when the I-unit
7 encounters the diagnose operation code, all remaining
8 instructions in the instruction stream are removed and
9 the operand for the diagnose instruction is fetched
from the address in main memory defined by the Bl+D1
11 fields of the instruction into G-register 50. The
12 operands of the diagnose instruction are then gated
13 from the G-register 50 into the maintenance console
14 staging register 52 over bus 51. After the fetch, the
decoding I-unit, e.g., I-unit 2, enters a stopped
16 state and no more instructions are placed in -the
17 instruction stream.
18 The eight lines corresponding to the I-2 field of
19 the instruction are decoded by decode 57 into maintenance
console 1 to determine the type of diagnose operation
21 to be performed. There are two basic types of diagnose
22 operations, one for setting up preliminary data and a
23 second for activating console functions. If the
24 diagnose instruction is of the first type, all eight
bytes of the operand stored in the maintenance console
26 staging register 52 are transferred over bus 65 to
27 console local store 60. The contents of the console
28 local store 60 provide addresses for the subsequent
29 diagnose instruction of the second type. A diagnose
release signal is then issued by the maintenance console
31 1 to the decoding I-unit and normal instruction processing
WA9-75-002 - 19 -
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resumes.
Subsequently a diagnose instruc-tion of the second
type will be encountered. Again the operand will be
fetched into G-register 50, then gated into MCSR 52
over bus 51 and -the I-unit stopped. Decode 57 decodes
the I_2 field of the diagnose and determines which of
the first -three bytes of the operand is to be transferred
to the maintenance mode registers Q through C designated
by the I-2 field. The selected byte is gated through
OR Dot 77 into AR regis-ter 78. The decode 57 also
provides two inputs into mode register set con-trol 82
over busses 87 and 88.
The E_register decode 57 also activates ga-te 85
to gate the con-tents of byte 7 of the maintenance
console staging register 52 -through OR gate 86, mode
register set control 82 and set/reset powering 83 into
the selected maintenance mode register. This is the
unit select field which partially defines which of the
maintenance mode registers wi11 be selected by ~he
diagnose instruction. These inputs select which of the
maintenance mode registers, Q through C will receive
the selected byte and control set/reset powering 83
to enable the selected maintenance mode register.
Upon enabling the selected maintenance mode register
the byte passes from the AR register 78 over bus 89
into the selected maintenance mode register.~
The E-register decode 57 next controls gate 111
over bus 62 to gate byte 5 of the maintenance console
staging register 52 through OR gate 112 into main
storage decode 116 over bus 113 and into decode=
interface 115 over bus 114. Main storage decode 116
20_
75362
decodes the byte to de-termine if the sink to be s-tored
into for a store function o~ the source of data for a
display function is main memory ]2. Decode 115 decodes
the byte to de-termine the I_unit sink~source for a store/
display function. E_register decode 57 also activates
gate 101 over bus 62 to transfer byte 6 of the main~
tenance console staging register 52 through OR gate
102 to switch function decode 103. Switch function
decode 103 decodes -the contents of byte 6 of the
maintenance console staging register 52 to set task
latches 104 indicating which switch functions are to
be performed on the element selected by byte 7 of the
maintenance console staging register 52. These
switch functions include start, lock, unlock, check
reset, restart, update cache,clear cache, unit reset,
stop, logout, advance maintenance console address
register address, store, display, and start cyclic
program counter. The functional description of each
of these switch func-tions was previously disclosed in
the "Description of the Diagnose Instruct~lon" section
of the disclosure.
Upon completion of the selected task, the console
1 issues a diagnose release to the decoding I-unit and
normal instruction processing resumes.
While the invention has been particularly shown
and described with reference to a preferred embodiment
thereof, it will be understood by those skilled in the
art -that various changes in form and details may be
made therein without departing from the spirit and
scope of the invention.
