Note: Descriptions are shown in the official language in which they were submitted.
3~75~
Srnith-~,trclin 19-6
1 Baclcgrol~nd of` the Invention
2 Thls lnventlon rela~es to in~ormat:lon storage
3 devices; and, more particularly, to the class of such
devices, known as "charge coupled devlces" (CCD's), in which
mobile electrlc charge representing information is coupled
6 to artiflclally lnduced potential wells in suitable storage
7 media and is stored and translated therein by application of
8 electric rields.
9 Previously disclosed forms of such apparatus,
e.g., the three-phase embodiments disclosed in Canadian
11 patent application Serial No. og7,711, filed November 9,
12 1970, on behalf of W. S. Boyle and G. E. Smith, and the
13 two-phase embodiments disclosed in Canadian patent
14 application Serial No. og7,712, filed November 9, 1970, on
behalf of D. Kahng and E. H. Nicollian, are operable but
16 suffer certain disadvantageous characteristics which it is
17 an object of this invention to alleviate.
18 For example, the three-phase embodiments disclosed
19 in the aforementioned application are not amenable to
20 serpentine data patterns without an unduly complicated
21 interconnection pattern. Fabricating the interconnections
22 is not an appreciable problem per se, but they do require
23 space; and the result is an often unacceptably large area
24 per bit of information.
The two-phase embodiments disclosed in the other
26 application referenced above are readily amenable to
27 serpentine data patterns but are difficult to fabricate in
28 the form disclosed therein. Also, the built-in asymmetry
29 in those devices forecloses the possibility of electronically
reversing the direction of data transfer.
- 1 -
~ -: . . . . . . . .
~L~758~
Summar~ of the rnvention
_
In accordance wi,th one aspect of the invention there
is provided in charge couplecl apparatus of the type including:
a storage medium in which mobile charge can be coupled to
potential wells for storage an~ manipulation; a first
insulating coating disposed over and contiguous with at
least a portion of one surface of the medium; and charge
transfer means including an electrode assembly disposed over
the surface of the first coating, the improvement being that:
the electrode assembly comprises a plurality of pairs of
electrodes disposed successively laterally over and
defining a path along said surface and that each of said
pairs includes a first electrode; a second insulating
coating disposed over substantially all of the first
electrode of each pair; and a second electrode disposed
between and spaced from and partially overlying the first
electrode of said pair and the first electrode of the next
adjacent pair, and that the electrodes of the electrode
assembly are disposed in relation to each other and in
relation to the storage medium such that dynamic storage and
sequential transfer of mobile charge carriers coupled to
induced potential wells in the storage medium along and
underneath the electrode assembly is enabled in response to
application of voltages of sufficient magnitude to the
electrodes.
In accordance with another aspect of the invention
there is provided in a charge-coupled circuit, in combination-
a substrate; a first plurality of side-by-side conductors
capacitively coupled to said substrate; a second plurality
of side-by-side conductors, each spaced from and overlapping
a pair of the first conductors and also capacitively coupled
~ 2 -
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~"' ` . '
- 1CI1758il
to said substrate; Eirst and second conductive lines extend~
iny at right angles to the second plurality of conductors,
one connected to alternate ones of these conductors and the
other connected to the remaining ones of said conductors;
a third conductive line adjacent and parallel to the first
connected to alternate ones of said first conductors; and
a fourth conductive line adjacent and parallel to the
second connected to the remaining ones of said first
conductors.
It is an object of our invention to obviate these
and other disadvantageous characteristics of prior charge
coupled devices, and, more generally, to provide more
flexible and more easily fabricated CCD's.
To these and other ends, a CC~ structure in
accordance with our invention employs two levels of electrode
metallization with the electrodes disposed in pairs
successively laterally over and defining a path above the
surface of a first insulating coating which, in turn,
overlies a suitable storage medium. ~he first electrode of
each pair is disposed over and contiguous with the first
insulating coating and is completely covered by a second
insulating coating which may, but need not, extend over the
spaces between the first electrodes of the pairs. ~he second
electrode of each pair is disposed primarily between but
also partially overlying the first electrode of its pair
and the first electrode of the next pair.
Inasmuch as the thickness of the second insulating
coating determines the width of the space between adjacent
electrodes, fabrication of very closely spaced electrodes
thereby is facilitated. This is an especially advantageous
aspect of our invention because very closely spaced
~ 2a -
.~ . .
~ .
- -
~0758~1
o
electrodes, e.g., about 1000 A separation, are important
if optimum performance is to be obtained in a charge coupled
device.
This overlapping oE electrodes is an important
feature of our invention because the result is a CCD
structure in which all portions of the information channel
are covered by one or more of -the electrodes. In this
manner the channel effectively is sealed from contamination
which otherwise could pene-trate the insulating coating(s)
and deleteriously affect device.
- 2b -
, ' '
~107S~
The above-describecl structure in accordance with
our invention can be operated in a four-phase mode using
four electrodes (two pairs) per bit by applying sinusoidal
or other periodic voltages differimg by one-fourth cycle,
e,g., by 90 degrees, smultaneously to the electrodes in
such manner that the same phase is applied to every fourth
electrode. This mode yields greatest operational flexibility
and highest speed operation because greatest advantage can
be taken of field-enhanced charge transfer.
Because of the repetitive symmetries involved, the
four-phase clock voltages advant~geously are applied to the
electrodes through two pairs of conduction paths disposed
one pair on either side of the CCD information channel.
Each pair of conduction paths includes a first conductor at
the same level of metallization as the first electrode of
each pair of electrodes and a second conductor overlying the
first conductor and physically and electrically separated
therefrom by portions of the second insulating coating. In
each bit, i.e., each four electrode group, the first
electrodes of the two pairs of electrodes are connected to ;~
different ones of the first conductors of the pairs of
conduction paths; and the second electrodes of the t~s pairs
of electrodes are connected to different ones of the
second conductors of the pair of conduction paths~ In
this manner, every fourth electrode is connected to a
common conduction path; and each electrode within each group
of four electrodes is connected to a different one of the
four conduction paths. ;~
The aforementioned structure, connected as
described, also can be operated with a t~o-phase clock
simply by providing a DC offset voltage to the conduction
paths so as to create a corresponding DC offset voltage
- 3 -
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. .; ,
107~i8~
bet~een the first and second electro~es of each pair. The
magnitude of this offset voltage is ad~usted to provide the
requisite asymmetry to the potential wells to ensure
unidirectionality of charge transfer. The clock voltages,
; phase 1 and phase 2, alternately are applied to the
conduction paths so that each pair of electrodes is driven
by the same phase at the same time, e.g., within each group
of four electrodes phase 1 is applied to both electrodes of
one pair and phase 2 is applied to both electrodes of the
other pair at the same time. In this two-phase mode, the
direction of charge transfer can be changed simply by
reversing the polarity of the DC offset voltage.
In another embodiment of this invention, the
second electrode of each pair overlies the preceding first
electrode more than the succeeding first electrode so that
the parasitic capacitance between it and the preceding first
electrode is greater than that between it and the
succeeding first electrode. No direct electrical
connections need be made to any of the first electrodes.
A pair of conduction paths are disposed one on either side
of the CCD channel. Every other one of the second electrodes
is connected to a common one of the conductlon paths.
In operation, two-phase clock voltages applied to
the second electrodes through the conduction paths also
cause voltages of lesser magnitude to be induced on the
first electrodes because of the capacitive coupling there-
between. The induced voltage is of lesser magnitude than
the driving voltage because of capacitive voltage division
between the aforementioned parasitic capacitance and the
capacitance of the first electrode with respect to the
surface of the sto-age medium. Because the induced voltage
is less than the driving voltage, the requisite asymmetry
- 4 _
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3~7~}~
automatically is caused in the potential wells under each
pair of electrodes so as to cause the direction of charge
transfer to be from the first electrodes toward -the second
electrodes.
In an especially advantageous form of this invention
a pair of metallization patterns exhibiting stagyered
symmetry are disposed over a plurality of parallel CCD
channels to provide especially compact appara-tus capable of
sustaining serpentine data flow.
srief Description of the Drawing
.
The aforementioned and other objects, character-
istics, and advantages, and the invention in general will be
better understood from the following more detailed descrip-
tion taken in conjunction with the accompanying drawings in
which:
FIG. 1 iS a cross-sectional v~ew taken along the
channel of a typical charge coupled device structure in
~ accordance with this invention;
;~ FIG. 2 is a plan view of an advantageous CCD
embodiment of which FIG. 1 iS substantially a cross-section;
FIG. 3 is a cross-sectional view similar to FIG. 1
but aaditionally showing capacitive and resistive coupling
- between each pair of electrodes; ~:
FIG. 4 is a plan view of another CCD embodiment in
accordance with this inven-tion adapted to operate as shown
in FIG. 3;
` FIGS. 5 and 6 depict first and second level
; metallization patterns which are, in turn, shown superposed
in FIG. 7 to provide an advantageous serpentine data pattern
in accordance with this invention.
It will be appreciated that for simplicity and
clarity of explanation the figures have not necessarily been
drawn to scale.
-- 5 --
:~ , . : :
~ ~ Smith-~train 19-6
1 Detalled Descriptlorl
2 With more speclfLc re~erence now to the drawing,
3 ~IG. 1 shows a cross-sectlonal view taken along the channel
4 Or a CCD structure in accordance with a ~irst embodiment of
this invention. As shown, the structure includes a bulk
6 portion 11 which is shown, for purposes of illustration
7 only, as N-type semiconduc-tor. In view o~ the disclosure
8 in the Canadian patent application Serlal No. 10l~,589, f-lled
9 February 5, 1971, on behal~ o~ D. Kahng and assigned to the
assignee hereof, it will be appreciated that bulk portion 11
11 may be selected from among any of a wide variety o~ suitable
12 storage media, such as, ~or example, semiconductors, semi-
13 insulators, and insulators.
14 A first insulating layer 12 overlies the storage
medium 11. Layer 12 advantageously is a dual-thickness
16 layer which is relatively thin, e.g., 1000 A~ over the CCD
17 channel where the instant cross-section is taken, and is
18 relatively thick outside the channel area so that voltages
19 applied to conduction paths and other overlay contacts
outside the channel area do not substantially perturb the
21 sur~ace potential o~ the storage medium outside the intended
22 channel. Overlying layer 12 are a plurality o~ spaced
23 electrodes designated with the re~erence numeral 13,
24 ~ollowed by an alphabetic subscript a, b, c, d, etc. Over-
lying each electrode 13 is a second insulating coating 14
26 which may be ~ormed in situ by oxidizing electrodes 13 or
27 which may be deposited, as desired
28 Disposed primarily between but partially over-
29 lapping electrodes 13 are a second plurality o~ electrodes 15
similarly designated, and which constitute a second level of
31 metallization.
.
-- 6 --
'., ' " ` ' '
:
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:~17S81~
In the followlng discuss10n~ the electrocles of
the above-described structure often will be considered Ln
pairs, each pair lncluding one electrode, e.g., 13a of the
first level of metallization, and the ne~t adjacent electrode,
e.g., 15a of the second level of metallization. This
terminology is convenient because of the symmetries involved.
It will be appreciated that the foregoing structure
can be fabricated in a variety of ways. For example, the
so-called "silicon gate" technology, such as disclosed in
U. S. Patent No. 3,475,234, issued October 28, 1969~ to
R.E. Kerwin et al~ can be used. In this case, the first
level of '~etallization" (electrodes 13) is formed by
depositing a layer of silicon; defining the silicon into
electrode geometries by a photolithographic process; oxidizing
the remaining silicon electrodes; depositing a layer of a
suitable metal such as platinum, palladium, gold, or
aluminum, and photolithographically defining this second
layer of metallization into the geometric patterns desired
for electrodes 15.
Alternatively, a so-called ~'film-forming~ metal,
such as the oxidizable metals tungsten7 zirconium, aluminum,
hafnium~ molybdenum~ or nickel, may be substituted for
silicon for the first layer of metallization. Still another `
alternative which may be employed is to use any suitably -~
conductive material instead of silicon for the first level
of metallization and then to deposit, as by sputtering, an
insulating coating thereover rather than to form the
insulating coating by chemical conversion.
It will be appreciated that the overlapping of
electrodes illustrated in FIG. 1 is an important feature of
our invention because the result is a CCD structure in which
all portions of the information channel are covered by one
.. . .
:, -
1~)75~1
or more of the electrodes. In this manner the channel
effectively is sealed from contamination which otherwise
could penetrate the insulating coatings and deleteriously
affect the device.
The above-described structure can be operated in a
four-phase mode using four electrodes (two pairs) per bit
by applying sinusoidal or periodic voltages differing by
one-fourth cycle successively to every fourth electrode.
This is depicted schematically in FIG. 1 where every fourth
electrode is shown connected to a common one of four
conduction paths 16-19. ~pplication of four-phase clock
voltages ~ 4 to these conduction paehs in a similar manner
as taught in the aforementioned Boyle-Smith application for
three-phase applications results in a traveling potential
minimum within the storage medium 11 to which mobile charges
can be coupled for storing and transferring iDformation.
Clearly the four-phase mode yields great operational
flexibility and high speed operation because the direction
of charge transfer can be reversed merely by changing the
applied clock potentials and because greatest advantage can
be taken of field-enhanced charge transfer.
Because of the repetitive sy~metries involved, the
four-phase clock voltages advantageously are applied through
two pairs of conduction paths disposed one pair on either
side of the CCD channel. This is illustrated by the plan
view shown in FIG~ 2. The cross-sectional view shown in
FIG~ 1 is substantially that which would be seen in a
cross-section taken on line 1~ in FIGo 2.
- In FIG~ 2, the information channel is between
parallel broken lines 21 and 22 where a relatively thin
insulating layer, e.g.~ 1000 ~ of silicon oxide~ overlies
and is contiguous with the surface of a storage medium 11.
- 8 -
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~7S8~
Outside the channel, a thicker insulating layer 12,
e.g., 10,000 A of silicon oxide or silicon nitride, overlies
and is contiguous with the rest of the surface of the
storage medium, these outlying portions being thicker to
prevent voltages applied to the conduction paths from
substantially per~urbing the surface potential of the
storage medium outside the channe].
Over this dual thickness insulating coating, two
conduction paths 13' and 13", constituting a first level of
metallization, are disposed one on either side of the
channel. Conduction paths 13' and 13" include interdi8itated
rectangular portions 13a, 13b, 13c, 13d, and 13e which extend
over the channel and serve as field plate electrodes.
Electrodes 13a, 13c, and 13e are a part of conduction
path 13"; and electrodes 13b and 13d are a part of conduction
path 13'.
A second insulating coating is disposed over at
least the electrodes of the first level of metallization;
and two other conduction paths 15' and 15"~ constituting a
~O second level of metallization, are disposed one on either
side of the channel over conduction paths 13' and 13",
respectively. Conduction paths 15' and 15" also inclùde
interdigitated rectangular portions, 15a-15c, which extend
over the channel and serve as field plate electrodesJ
Electrodes 15a, 15c, and 15e are a part of conduction
path 15~; and electrodes 15b and 15d are a part of
conduction path 15".
In four-phase operation, phase one (~1) is applied
to conduction path 13"; phase two (~2) is applied to
conduction path 15'; phase three (~3) is applied to
conduction path 13'; and phase four (~4) is applied to
conduction path 15".
~.~)75~
An important feature of the conduction path
arrangement shown in FIG. 2 is that the conduction path ~15")
for phase four overlies the conduction path (13") for phase
one; and the conduction path (lS') for phase two overlles
the conduction path (13') for phase three, Whether conduction
path 15" o~erlies 13" or vice versa is not important. What
is important is the parasitic capacitive coupling resulting
from the illustrated juxtapos~tion. In structures where
silicon or any other material exhibiting substantial
resistance is used for the first level of metallization,
; eDg., conduction paths 13' and 13", the serles resistance
may be 100 n/D or higher. Because of this resistance and
the distributed capacitive coupling to the storage medium,
such conduction paths act as transmission lines and thus can
substantially retard the phase of signals thereon. However,
because ~4 is 90 degrees ahead of ~1 and because ~2 is
90 degrees ahead of ~3, ~4 will ~end to advance the phase
of ~1 if their conduction paths are capacitively coupled;
; and ~2 will tend to advance the pase of ~3 if their
conduction paths are capacitively coupled. This phase-
adva~cing effect can be used to compensate for the phase-
retarding effect of resistive conduction paths. This is
; done in the apparatus of FIG. 2.
To avoid the complications inherent in generating,
synchronizing, and transmitting four~phase clock pulses~
~-~ the aforementioned structures depicted in FIGS. 1 and 2
` also can be operated with a two-phase clock simply by
providing, in addition to the two-phase cloc1c signals, a
DC offset ~oltage to the conduction paths so as to create
a corresponding DC offset voltage between the first and
second electrodes of each pair. In this case, the clock
voltages~ phase one and phase two, alternately are applied
'
:
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~0~5~
to pairs of the ~olJr conduction paths so tha~ each of said
pairs of electrodes is driven by the same clock phase at
the same time. The function of the DC offset voltage is to
provide the requisite asymmetry to tbe potentlal wells to
ensure unidirectionality of charge transfer~
More specifically, now, with reference to FIG. 1,
for two-phase operationy a DC voltage ~ould be applied
between conduction paths 16 and 17 and between conduction
patbs 18 and 19 so as to make electrodes 15 all positive
(or all negative) with respect to electrodes 13. Clock
phase one then would be applied to conduction paths 16
and 17 simultaneously; and clock phase two would be applied
to conduction paths 18 and 19 simultaneously. At the next
clock cycle, phase one would be applied to conduction
paths 18 and 19 simultaneously; and phase two would be
applied to 16 and 17 simultaneously. And so on, with
information advancing two electrodes to the left (or right,
depending on the polarity of the DC offset voltage) at each
reversal of the clock.
Inasmuch as the direction of charge transfer is
dependent on the polarity of the DC offset voltage, the
direction can be reversed electronically simply by reversing
the polarity of that voltager And, of course, it will be
appreciated that the DC offset voltage need not be applied
between lines 16 and 17 and between lines 18 and 19, but
may as well be applied between lines 17 and 18 and between
16 and 19, in which case the clock phases would be applied
; simultaneously to the newly-paired lines9 i.e., to 17 and 18
and to 16 and 19.
In the above-described embodiments3 four conduction
paths per channel are used. If either this plurality of
conduction paths, or the four-phase clock, or the two-phase
10~5~1~
clock plus DC offset are considered a problem in any
particular application, similar operating results can be
obtained in accordance with this invention with a two-phase
clock and two conduction paths per channel merely by providing
capacitive and resistive coupling between the first and
second electrodes of each pair.
This is illustrated schematically in FIG. 3 where
elements 31a-31d represent capacitors, and elements 32a-32d
represent resistors in parallel pairs with the capacitors
coupling electrodes 13 to 15. Every other one of
electrodes lS is shown coupled to a common one of a pair
of conduction paths 33 and 34 to which two-phase clock
pulse ~1 and ~2 are applied.
In operation, two-phase clock voltages applied to
electrodes 15 cause voltages of lesser magnitude to be induced
on electrodes 13 because of the capacitive coupling. This
induced voltage is of lesser magnitude than the clock
voltages because of capacitive voltage division be~ween the
capacitors 31 and the capacitance of electrodes 13 with
respect to the surface of storage medium ll. Because the
voltage induced on electrodes 13 is of lesser magnitude
than the voltages applied to electrodes 15, the surface
potential under electrodes 13 is less negative than the
surface potential induced under electrodes 15 for any given
negative clock voltage.
Resistors 32 are included not for coupling voltage
pulses from electrodes 15 to electrodes 13 but rather for
~lbleeding" charge from electrodes 13 to prevent charge from
accumulating thereon. Consequently the resistance of
resistors 32 should be much greater than the impedance of
capacitors 31 and much less than the resistance of the
insulator between electrodes 13 and the surface of storage
- 12 -
" ~ ',' ` ~ , ,
~L~75~ mlth-Straln 19-6
1 m~dlum 11 to prevent spuriou~ dlachar~e, For r*~i~tors 32,
2 re~lst~nc~ between 105 nnd 10 1 ohm~J typlcally about
3 106 _ 10~ Ohtll9, normally are appropr1at~. I'c wlll be
4 Rppreciated, however, that although the exact re~istance
~alue 19 n~t critical the f'unctlon whlch th~ae resi~tors
6 ~erve i8 important to prevent undue char~e accumul~tlon on
7 electrodea 13 .
8 0~ course~ it will b~! apprec~ated that the~e bleeder
9 re8i8tor8 need not be u~ed in ~ituatlon~ ~here spurlous
10 dlschar~e and other erfect~ o~ charg~ accumula'tion ar~ not
11 a problem. It w~ll al~o be appreclated that one need not
12 use a separate bleeder resi~tor betw~en each pair of
13 electrod~s,. Rather a plur~lity o~ electrode~ 13 may b~
14 c~nnected to a common conductlon path and a ~ln~l~ bleeder
resistor can be connected between tha~ con~uction path and
16 ~hQ conduct~on path to whlch a correspondlng plurality Or
17 electrode~ 15 arc connected. More ~peGi~ically~ with
18 re~erence ~o FIG. 3, ~lnce electrod~ 15a and 15c are-
19 connect~d to a commo~ conductlon path 33, ~lectrodes 13a
and 13c can be connected to ~n~ther conductlon path (not
21 shown3 and th~n a bleeder re~istor oan be connected betwe~n
22 conductlon ~a~h 33 and the path to which ele~trodee 13a
23 and 13c are connect~dO
24 In Fla. 39 bro~en line 35 repr~sent~ schematlcally
25 the ~urf'ace potent:~al ~d~pth o~ th~ potentlal well~ )
25 adJacent th~ ~ur~ac~ o~ ~torage medlum 11. Where, a~ ~ere,
~7 the operatlr~g medium 1~ ~emlconductivep brok~n llne 35 al~o
28 may be considered a~ representing ~chematically khe
29 boundarl~s Or depletion l;'~gi.0118 corre~ndin6 to the sur~ac~
30 po'cential. It ~hould b2 ob~erved that becau~e of' 'che
31 capacltlve coupllng betslreen electrode~ each o~ the comblned
32 potentlal well~ under e~eh palr Or electrode8 1~ a2ymmetrlcal
~7~
in such a manner as to cat~se the preferred direceion of
positive charge transfcr to be from the first electrode,
e.g., 13a, of each pair toward the second electrode, lSa, of
that pair.
With reference now to Flt. 4 there is shown a plan
view of a portion of apparatus adapted to operate in the
manner described with reference to FIG. 3. In FIG~ 4, the
information channel is between broken lines 41 and 42 where,
as in FIG. 2, an insulating layer is disposed over the
channel and is thinner than is the rest of the insulating
layer theresurrounding.
Over this dual-thickness insulating coating are
disposed a plurality of localized electrodes 43a-43f
(indicated by broken line rectangles correspondingly labelled),
these electrodes constituting a first level of metallization.
A second insulating coating is disposed over at
least the electrodes of the first level of metallization;
and a pair of conduction paths, 44' and 44" are disposed one
on either side of the channel. Conduction paths 44~ and 44"
include interdigitated rectangular portions 44a-44e which
extend over the channel and serve as field plate electrodes.
As can be seen, electrodes 44a, 44c, and 44e are a part of
conduction path 44', while electrodes 44b and 44d are a part
of conduction path 44'1.
In operation two-phase clock voltages alternately
are applied (with respect to the storage medium) to conduction
paths 44' and 44". One of electrodes 43 (of the first level
of metallization) serves as the first electrode of each pair
of electrodes; and one of electrodes 44 serves as the second
electrode of each pair of electrodes.
- 14 _
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~0'7Sl~
To provide the capacitlve coupllng between the
electrodes of each pair~ each electrode 44 overlies the
preceding electrode 43 more than it overlies the succeeding
electrode 43. More speci~ically, electrode 44b overlies 43b
more than it (electrode 44b) overlies 43c; elec~rode 44c
overlies 43c more than 43d; etc. It wlll be appreciated
that the amount of capacitive coupling between any given
electrode 44 and any given electrode 43 is propor~ional to
the area by which the one overlies the other.
In more detail now, consider electrodes 43a~ 44a,
44b, and 43c. It is advantageous that electrode 44a
overlaps 43a more than 43b, i.e., greater capacitive
coupling to 43a than to 43b, so that a voltage of greater
magnitude is induced on 43a than is induced on 43b. This
tends to enhance the asymmetry in the potential wells so
that unidirectionality of charge transfer also is enhanced.
This asymmetry ln the potential wells also is enhanced by
the fact that the two electrodes 44 overlying any given
electrode 43 are connected to opposite clock phases. That
is, electrodes 44a and 44b both overlie electrode 43b;
electrode 44a is part of conduction path 44' which is driven
by one pbase; and electrode 44b is part of conduction
path 44t which is driven by the opposite phase. Because of
this fact, the "net overlap"9 i.e., the amount by which the
area of 44b's overlap exceeds the area of 44a's overlap,
is important. The general rule of thumb is that as net
overlap increases the difference between the surface
potential under electrodes 43b and 44b decreases. By way
of example~ al net overlap area equal to about 20% of the
total area of electrode 43 will be suitable in structures
where the insulating layer between electrodes 43 and 44 is
about 1000 A of silicon oxide and where the two-phase clock
voltages are pulses of -6 volts and -30 volts, respectively.
....... . . .
''' .
~07~
At least aboue 4 kT, i.e., about 0.1 volt, dlfference
in surface potentlal, i.e., potential well asy~metry,
between ad~acent potential wells is required to provlde
desired directionality of charge l:rans~er. In practice,
however, we have found that for optimum operation this
asymmetry advantageously is made about equal to one-half the
difference between the peak-to~peak variations in surface
potential between ad~acent electrodes or electrode palrs.
I~us, where applied clock voltages are -6 volts and -16 volts,
a potential well asymmetry of about 5 volts ~one-half the
difference~ is effective.
If serpentine data patterns are desired, the
apparatus of FIG~ 4 advantageously is modified in accordance
with this invention to that shown in FIGS~ 5-7.
FIGS~ 5 and 6 depict, respectively, first level
and second level metallization patterns which are combined
with an insulating coating therebetween, as in the foregoing
embodiments, and disposed over a dual-thickness insulating
coating on a storage medium to achieve the apparatus
depicted in FIG~ 7. More specifically3 geometric
patterns 51a-51d in FIGo 5 are the electrode configura~ions
used for the first level of metallization in FIG~ 7; and
geometric patterns 53a-53d are the electrode configurations
used for the second level of metallization in FIGo 7. In
FIG~ 7 the electrode patterns are labeled correspondingly
with the patterns of FIGS~ 5 and 6.
Two information channels are depicted in FIG~ 7
a first one lying between parallel broken lines 61 and 62
and a second one lying between parallel broken lines 63
and 64. It should be noted that in contradistinctlon to
the foregoing embodiments, the electrode and conduction path
metallizations, i.e., patterns 51ar51d and 53a-53d, are
- 16 _
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1075811 Sml th- St ra 1 n 19- 6
1 di~po~ed tran~verse to tlle channel~ in ~IG. 7~ wherea~ ln
2 FIaS. 2 ~nd 4 th~ conduction path m~talllzation~ ~re
3 dis?~sed lonl;~,itudinally with respect to th~ channels.
4 In FIG~ 7 the 8tipled portion~ Or ~he ~econd level
5 Or metalllzatlon, i~e,, of patterns 53a-53d, are thoa~
6 portt ons o~ those pa'ctern~ whlch overlie so~ne portlon of' the
7 rlrst level Or m~talll2ation. ~t i9J of' cour0e, tn~e
8 ~tlpled overlap portions whi~h provlde the capacltive
9 couplln~ de~lred for operation Or the type de3crlbed wlth
reference to FI~S. 3 and 4.
11 In more det~il now~ note ~hat wlth re~pect to th~
12 fir~t channel (between lines 61 and 62 ~J ele~tro~e 53~
13 oYerlap~ electrode 51a ln ~tlpled dumbbell-~haped portlon 70a
14 more than lt (53a) overlaps electrode ~lb (~tlpl~d hexagonal-
shaped port~on 71a3. Slmilarly, the ~tipled dumbbell-shaped
lÇ portio~ 70b by which electrode 53b overlap~ electrode Slb
17 1~ larger than the ~tlpled hexa~onal~shaped portlon 71b by
18 whlch electrode 53b overla~ ~lec~rod~ 51c. And, ln all
19 ca~es, over the ~lr~t channel (b~twee~ line~ 61 and 62
20 each electrode of the ~econd level o~ metalllzation ov~rlap~
21 to the le~t more than lt overlap~ to the ri~ht. Accordin~ly,
22 the net capacltive couplln$ 18 to the le~t; and ~03 ln
23 accordance wlth the rore~olng teaching~ with respect to
24 FI~S. 3 and 4, t~ directlon Or char~e tran~er i9 to t~e
rlght ln the rir~t channel in FIOo 7.
26 But~, wlth re~pect to the ~econd channel ~between
27 llnes 63 and 64)~ th~ stlpled dumbbell-sha~ed overlap
28 portion 81a by wh~ch el~ctrode 53a o~rl~ eleçtrode 51a
29 1~ larg~r than the stlpled hexaeona~-~haped portlon 80a by
whlch ~lectrode 53a overlap~ the prevlous electrode (not
31 labeled) o~ the ~ir~t level o~ metalllzatlon. ~lmil~rlyJ ~he
32 ~lpled dumbbell-æh~ped portion ~lb b~ whlch electrode ~3b
10758~L~ Smlth-',tiraln 19-
~1 overlaps clect;rode 5Lb is larger ~han thc stlpled hexagorlal-
2 shaped portion ~Ob by which electrode 53b overlaps
3 electrode 51a. And, in all cases, over the s~cond channel
4 (between lines 63 and 64) each electrode of the second level
of metallization overlaps to the right more than it overlaps
6 to the left. Accordingly, the net capacltive coupling is to
7 the rlght; and so the direct:ion of charge transfer is to the
8 left in the second channel.
9 In light of the foregoing, it will be understood
that application of two-phase clock voltages to electrodes 53
11 through clock lines 65 and 66, shown connected thereto,
12 causes information to advance to the right in the first
13 channel and to the left in the second channel. This is a
14 basic feature required for serpentine data flow.
Of course, the channels must be coupled together
16 at the ends so that information at the end of one channel
17 is coupled into the beginning of the next channel. Means
18 for such coupling are indicated schematically in FIG. 7 by
19 the box 90, labeled "Regeneration Meansl', with electrodes 91
and 92 extending toward the first and second channels,
21 respectively. Inasmuch as charge coupled apparatus in
22 accordance with this invention, like all CCD apparatus
23 heretofore, is subject to some charge loss upon each charge
24 transfer, regenerating the signal while çoupling to the next
channel will be advantageous in most digital applications.
26 A variety of suitable regenerators are known, some of which
27 are described in Canadian patent application Serial
28 No. 121,794, filed August 31, 1971, in behalf of G. E. Smith
29 and M. F. Tompsett, and in Canadian patent application
Serial No. 121,990, filed September 2, 1971, in behalf of
31 R. H. Krambeck and R. J. Strain, both applications being
32 assigned to the assignee hereof.
- 18 -
s~
And finally, Eor completeness, it will be understood
that the staggerdly symmetric metallization patterns of
FIGS. 5-7 are not limited to use over two channels but may
be extending ln the depicted staggerdly symmetrlc fashion
over a vast plurality of channels in which information can
be made to transfer in opposite directions in successive
channels. Also, of course, apparatus such as shown in FIG. 4
and in FIG. 7 can be operaeed in a fotlr-phase mode if desired
by applying four-phase voltages to every electrode of both
levels of metallization if such operation is deemed
advantageous in a particular situation.
~lthough our invention has been described in part
by making detailed reference to certain specific embodiments,
such detail is intended to be and will be understood to be
instructive rather than restrictive. It will be appreciated
by those in the art that many variations may be made in the
structure and modes of operation without departing from the
spirit and scope of our invention as disclosed in the
teachings contained herein~
- 19 _
.
