Note: Descriptions are shown in the official language in which they were submitted.
2 f~ _. I n troduc ti on
27 L~'nis invention relates to a keyl)oar~ operate~l by one
lectronic control circllits. T;~e single-
28 ~ar~, an(; lts e
2~ llan~led oper~-~tior. can in a single ~ovc,~ent ?r~ss one or more
D-i?09-14-() 30
.
1, ~
.
,
.
'7
1 keys to comprise a chord which is sensed by the control
circ~lit~ tllat generate one ox more characters in an
~ output si~nal sequence.
4 1.1 Bac~ground Of The Invention
~r}le conventional two-handed typewriter keyboard has
6 been in use for decades and is well known. The conventional
7 keyboard is not chord operated, that is, only a single key
8 may be pressed at a single time to generate a single output
g character.
The stenotype, which is well known but in lesser use
11 is arranged for both hands to form chords. The stenotype
12 is not a typewriter but rather it is a machine for taking
13 shorthand mechanically.
14 The major disadvantage of the stenotype is that its
output transcription is actually produced at a slower
16 rate than the conventional single-key-at-a-time
17 typewriter because its output format is not in a
18 desired form and therefore must be retyped using the
19 conventional typewriter to transcribe its output. Hence,
the double typing to obtain the final typed product
21 results in a slower overall rate than the rate of the
22 conventional typewriter.
23 The advantage of the stenotype is that it permits
24 the typist to record 200 words per minute on the average
and in exceptional cases up to 300 words per minute using
26 a shorthand type of phonetic chord operation. On the
27 stenotype keyboard, a single finger can press either one
28 or two keys at once and up to all fingers of both hands
29 can be used to simultaneously actuate the keys on the
D-PO9-74-030 -2-
l~S~
1 keyboard which are sensed in left-to-right order for
outputting onto paper.
The present invention performs the function of a type-
writer keyboard and to do this it uses the technique of
forming chords that is used in the stenotype.
Prior art in this area is found in the following:
1. Proceedings AFIPS 1968, Fall Joint Computer Confer-
ence, Pages 395 - 410, "A Research Center for
Augmenting Human Intellect", by D.C. Engelbart
and W.K. English.
2. U.S.A. Patent No. 3,833,765 to Hilborn et al,
filed January 30, 1973 and issued Sept. 3, 1974.
The Engelbart et al paper describes an arrangement having
a five key keyboard, in which the keyboard is operated by one
hand to control CRT cursor functions selected by the other
hand. The five keys of the keyboard are actuated simultan-
eously in 31 combinations to select one character of an
alphabet/case, which is selected by pressing one or more of
these buttons with the other hand.
The Hilborn et al patent discloses a one-handed keyboard
which generates a single character by two sequential key
depressions. Sequential key depressions are not used by
the subject invention for generating a single character. The
subject invention introduces the novel principle of finger
positions in chords, in which a single finger can depress
plural keys to generate a single character with a single
finger depression and multiple characters can be generated
by a single hand depression using multiple fingers to
generate one character per finger in the chord.
PO9-74-030 -3-
1~8S~8!7'
1 _.O ~ectiv~s
2 Tlle keyboard provided by this invention can be
3 designed to be a light weight portable device that can
4 be operated with one hand. The keyboard provides the
full character set conventionally available on commercially
6 available typewriters. The keyboard described herein is
7 shown in a form intended to represent the English alphabet.
8 However, the keyhoard can be used to represent any alphabet
9 used by any language. Also, the invention permits the
user to add special characters and combinations of
11 characters. A properly trained average operator should
12 be able to type with one hand using this keyboard at a
13 rate equal to or better than 60 words per minute, thus
14 equaling the typing speed of a good typist using a
conventional typewriter keyboard. An above average
16 typist should be able to type at a faster rate
17 on this one-handed keyboard than on the conventional
18 two-handed keyboard. The keyboard produces as an output,
19 a series of characters encoded as electric signals that
are suitable for input to a light emitting display,
21 printer, data transmission device, computer, or other
22 such keyboard operated device.
23 2.1 Summary Of The Invention
24 The invention permits one hand to type ~nglish
alphabet characters (or characters in the alphahet of
26 any other language) in a complete unambiguous form.
27 It is not a stenotype for recording sounds which require
28 subsequent typing transcription.
D-PO9-74-030n -4-
1~5~
1 The invention provides a nov~1 ~eyl~oard arr~ngement
2 with novel electronic circuitry Eor nniquely interpreting
3 each chord depression of keys conlprisillcJ plural fin~er
4 positions to genera-te simultaneously on~ or more
characters. ~ach finger position ac-tuates up to four
6 keys for generating each character.
7 The invention provides a one-handed keyboard which
8 is structured with a finger key section and a thumb key
g section. The keys in the thumb key section operate
as follows:
11 1. No thumb key pressed.
12 2. Any one of the thumb keys pressed.
13 3. Any two adjacent thumb keys pressed.
14 The finger key section is operated by the four
fingers of the same hand used to operate the thumb
16 section. Each finger can operate a single finger
17 position involving:
18 1. Pressing no keys.
19 2. Pressing one key.
3. Pressing two adjacent keys.
21 4. Pressing four adjacent keys.
22 While a single chord operation is performable by a
23 single finger to output one character, a complex chord
24 operation is also performable by up to four fingers
simultaneously pressing the keyboard to generate up to
26 four characters.
27 There are 1023 finger-position chords that can be
28 produced with ten keys, but anatomical limitations
29 exclude 48 which are not keyable. This leaves 975
D-PO9-74-030 -5-
~J8~8 ~
1 pl~yahle finger-position chords. When eight thumb-
2 posi-tion chords are available, the total number of
3 playable keyboard chords is 7800. The amount of infor-
4 mation conveyed by a single chord may be calculated to
be log2 7800=12.94 bits. If the typist keys three chords
6 per second, as is done in stenotyping, then the rate at
7 which information is entered becomes
8 3 log2 7800 = 38.8 bits/sec
g This may be compared with the corresponding theoretical
rate of a conventional two~handed keyboard as follows.
11 The rate of 75 words (4 characters and a space) per
12 minute is 6.25 characters per second. There are 48 keys
13 so the theoretical rate is
14 6.25 log2 48 = 34.9 bits/sec
It should be noted that these calculations are only
16 approximate because they ignore several factors including
17 the fact that different characters have different
18 probabilities, some characters are harder to type than
19 others, some have sequences of characters harder than
others, the upper/lower case coding is ignored, and
21 some chords are harder to form than others. However,
22 this analysis provides a qualitatively correct explanation
23 of why the chord keyboard works so well and provides
24 useful quantitive approximations. The stroke of the keys
is changed, as described below, so the typist should be
26 able to exceed the stenotype rate of three strokes per
27 second, thus perhaps exceeding nor:nal keyboard perfor-
28 mance to an even greater degree.
D-PO9-74-030 -6-
iV~487
1 ~he next question is how to implement this invention.
2 There are many ways. A word could be assigned to each
3 chord, but this would be hard to learn. A particularly
4 interesting assignment of meanin~s is shown in
FIGURES 3-2, 3-3 and 3-4 which show the assignment of
6 characters to finger positions used by the detailed
7 embodiment in this specification. This assignment of
8 characters to finger positions (not to be confused with
9 the conventional assignment of characters to keys) makes
it possible to exploit the potentialities of this
11 keyboard without requiring an unreasonable amount of
12 learning on the part of the typist. It is designed for
13 typing English based on the frequencies of common two-
14 letter and three-letter sequences in English.
The finger-position concept can be explained using
'6 FIGURE 3-2. Suppose the typlst presses only the N key;
17 he then outputs the letter N. But if the finger
18 simultaneously presses the N key and the F key, he outputs
19 the letter S shown between the two keys, and he does not
output either letter N or F. Furthermore, if the typist
21 presses the four adjacent keys F, N, M and R with one
22 finger, he outputs the letter V shown centered in this
23 quad-group of keys, and none of the letters F, N, M, R
24 is outputted.
This keyboard, unlike prior chord keyboards, such
26 as the stenotypewriter, allows the novice to do "hunt
27 and poke'i typing with one finger operating on the finger
28 positions.
D-POg-74-030 -7-
i~854~t;~
l The typist who is ~illing to learn touch-typing
2 can take advantage oF a(lditional resources of the
3 keyboard in orc~er to type faster. There are several
4 levels of learning to speed up typing; and when the
typist advances to a new level, he will rise -to a new
6 and faster typing speed.
7 By pressing a chord of several finger positions
8 at once, it ls possible to output several letters with
9 a single hand movement. For example, t~le trigraph "the"
can be entered with one chord, and the digraph "tr" can
11 be entered with one chord. These are outputted as
12 sequences of lower-case letters in the letter alphabet
13 of FIGURE 3-2 by simply pressing simultaneously the
14 finger positions marked with these characters without
pressing any thumb positions.
16 The thumb keys shown in FIGURE 3-5 control the
17 selection of alphabets/cases, and related chord control
18 operations. Four thumb keys can support up to eight
19 alphabets/cases and chord control operations. The
alphabet/cases selection determine in which alphabet
21 and in which case a pressed finger position is to be
22 outputted. Examples of chord-control thumb positions
23 include (1) selecting the output sequence of letters in the
24 chord, i.e. normal or reverse, (2) prefixing a space when
outputting a chord, and (3) capitalizing the first outputted
26 character of a chord. The thumb position controls make
27 it possible to increase substantially the number of
28 characters that can be outputted by pressing a single
29 chord.
D-P09-74-030 -8-
1~35~1~'7
The chord control thumb positions are availa~le
2 to a typist who has reached the second level of learning
3 to touch-type. The first level consists in learning to
4 touch-type on the individual finger positions. This
second level should take very little additional learning
6 time, and it represents the basic skill of a typist using
7 this keyboard.
8 The contribution of chords to typing speed can be
g illustrated by the following example which shows a
sample of text with slashes used to delimit the text
11 entered with each chord. In this example we show the
12 maximum number of characters per chord that could be typed
13 by a skilled typist.
14 /A/ li/ne/ bu/f/fe/r/ co/nt/ain/s/ al/l/ tho/se/
cha/ra/c/te/rs/ re/ad/ by/ the/ sy/st/em/ si/nc/e/
16 the/ la/st/ end/ of/ li/ne/ wa/s/ de/te/c/te/d/./
17 In this example, the typist enters 2.28 characters per
18 chord stroke. If the typist makes three strokes per second,
19 this means a typing speed of 6.8 characters per second or
82 words per minute with a single hand. The other hand
21 is free to do other things, such as turn pages, or even
22 type on a second one-handed keyboard. Thus, it is
23 conceivable that a person could operate two of these
24 keyboards at once, one for each hand. It is possible that
two one-hand 14-key keyboards would overload a typist so
26 he could not quite double his speed by doubling the
27 number of keyboards.
D--PO9--74~030 ~9~
8';Y
1 A careful s-tudy oE the example above ~ill reveal
2 the need for more complica-ted ru]es for interpreting
3 complex cllord-;. A consistent rule was followed in
4 delimiting the sample text, and the r~le will be evident
to someone who studies the examp:Le in detail but will
6 probably be meaningless to someone who does not. The
7 rule is to proceed in the direction indicated analyzing
8 the text, finger position by finger position, to
9 associate them to form chords.
It is clear that there are a lot of chords that
11 can be formed by a typist that would not occur in
12 typing normal English text~ The assignment of a
13 frequently used special word to uncommon chords will
14 allow faster typing at the cost of having to learn them.
For example, the uncommon digraphs "qs" and "pz" are
16 chords that could be assigned the special words "United"
17 and "States", respectively. Also, double letter digraphs
18 like "tt" are very common and could be assigned, like a
19 single character, to respective unused single finger
positions in some alphabet/case.
21 A typist who types a lot of letters might like a
22 single chord, such as "qz" that would write "Sincerely
23 yours,". The invention permits ad hoc special words
24 to be assigned by the typist to a given chord. For
example, in most passages of text, certain words are
26 very common and should be given ad hoc assignments. For
27 typing this specification, the typist might want to
28 assign "keyboard" to a single chord. A chord keyboard
D-PO9-74-030 -10-
37
1 as provided by this invention provides an ample
2 availability of chords for such uses.
3 2.2 Description Of The Drawin~s
4 The foregoing and other objects, features and
advantages o~ the invention wil] be more apparent from
6 the following more particular description of the
7 preferred embodiment of the invention illustrated in
8 the accompanying drawings of which:
g FIGURE 3-1 is a top view of a keyboard embodiment
of this invention.
11 FIGURES 3-2, 3-3 and 3-4 represent three of the
12 alphabets available from the 10 finger keys in the
13 keyboard embodiment of FIGURE 3-1.
14 FIGURE 3-5 illustrates the thumb key section of
the keyboard.
16 FIGURE 3-6 illustrates the window groupings of
17 finger keys used by the electronic circuits for finger
18 position decoding.
19 FIGURES 4-1, and 4-2 illustrate mechanical views
internal of the keyboard.
21 FIGURE 5.1-1 is a block diagram of the keyboard
22 control circuit sections provided in the detailed embodiment.
23 FIGURE 5.2.-1 shows the circuits found in the timing
24 signal generator section of the embodiment.
FIGURE 5.2-2 illustrates the timing of signals of the
26 timing signal generator of FIGURE 5.2-1.
27 FIGURE 5.3-1 shows circuits found in a keyboard word
23 generator part of the embodiment.
D-~09-74-030 -11-
, ,. '
1i?~5~137
1 FIGURI, 5. 3-2 illustrates the timing of waveforms
2 found in the keyboard word yenerator of FIGURE 5.3-1.
3 FIGURE 5. 3A and 5. 3B show two different keyboard
4 word generators, each being alternative to the generator
in FIGURE 5. 3-1.
6 FIGURE 5.4-1 illustrates a special chord circuits
7 part of the embodiment.
8 FIGURE 5. 5-1 shows a special word generator part
9 of the embodiment.
FIGURE 5. 5-2 illustrates waveform timings found in
11 the special word generator of FIGURE 5. 5-1.
12 FIGURES 5. 6-lA, 5. 6-lB and 5 . 6-lC illustrate a
13 regular chord decoder part of the embodiment.
14 FIGURES 5 . 6-2A and 5.6-2B show exemplary timing
waveforms generated during the first eight phases
16 of operation by the regula- chord decoder of FIGURES
17 5.6-lA, 5 . 6-lB and 5 . 6-lC .
18 FIGURES 5 . 6-3A and 5 . 6-3B show exemplary timing
19 waveforms generated during the last eight phases of
operation by the regular chord decoder in FIGURES 5. 6-lA,
21 5.6-lB and 5.6-lC.
22 FIGURES 5. 7-1 shows an output control circuit part
2 3 of the embodiment.
2 4 3 . 0 Detailed Embodiment
General Arrangement The invention comprises the
26 mechanical arrangement of a preferred form of one-handed
27 keyboard, and the electronic circuits which generate
2 8 the electrical signals upon actuation of the keyboard.
D-PO9-74-030 -12--
5~l~7
1 FIGURE 3-1 is a layout of the keyboard designed for
2 right hand operatlon. The keys and controls on the
3 keyboard are as follows:
4 4 "thumb keys" are provided for entering information
with the thumb of the right hand.
6 10 "finger keys" are provided for entering information
7 with the four fingers of the right hand.
8 A "special chord" pushbutton permits the changing
9 of special chords as discussed in section 3.4 below.
A "special word" pushbutton permits the changing of
11 special words as discussed in section 3.4 below.
12 A "power switch" turns keyboard power on and off.
13 The finger keys and thumb keys are arranged in the
14 manner shown in FIGURE 3-1 so that in operation the fingers
of the right hand can rest approximately in the center of
16 the finger keys with the thumb resting in the middle of the
17 thumb keys. The finger and thumb keys are flat and of a
18 hard material with the thumb keys being about one-half
19 inch below the level of the finger keys.
The four fingers of the right hand operate the ten
21 finger keys. Chords are produced by pressing keys
22 using from one to four fingers simultaneously. Each finger
23 can press one finger position in creating a chord. Hence
24 a chord is formed by pressing from one to four finger
positions simultaneously. Each pressed finger position
26 presses up to four keys, as follows:
27 one key
28 two adjacent keys
29 four adjacent keys
D-PO9-74-030 -13-
lV85~87
1 A total of 27 f~n3er positions are pressable on the
2 10 fin~er keys and are respec-tively identified by the
8 27 he~ad~cimal numbers [1] -through [ lB] shown in FIGURE
4 3-6. These 27 finger positions are also shown in FIGURE
3-2 where they are respectively used to represent the 26
6 let-ters of the English alphabet and one finger position
7 is used for the space character ~
8 An example of a chord is to press simultaneously
g the finger positions for characters T, H and E in
FIGURE 3-2. The effect of this chord is to produce the
11 se~uence of letters "THE".
12 The thumb of the right hand operates any of seven
13 thumb positions on the four thumb keys to select one
14 of four alphabets/cases, a normal or reverse output
order for characters in each chord, whether a space
16 character preceeds the chord, and whether the first
17 non-space character in the chord is capitalized. The
18 seven pressable thumb positions [1] through [7] are
19 shown in FIGURE 3-5, as comprising:
Any one of four thumb keys, i.e. [1],[3],[5] or ~7].
21 Any two adjacent thumb keys, i.e. ~2], [4] or [6].
22 3.1 Left-Hand_Keyboard
23 The left hand keyboard (not shown) is a mirror-
24 image reversal of the finger and thumb key locations on
the keyboard.
26 3.2 Thumb Positions
27 In the described embodiment, the thumb section can
28 select any of four alphabets/cases in accordance with
29 the thumb positions. The alphabets are as follows:
D-PO9-74-030 -14-
5~
1 1. LETTER alphahets: provide lower-case and upper~
2 case English alphabet lltters.
3 2. NU~IBER alphabet: provides the decimal digits, control
4 characters, and some special characters.
3. SPECIAL Cl-~AR~CTER alphabet: provides special
6 characters and punctuation symbols. Note that
7 two keys are not assigned any character in this
8 alphabet.
9 The eight thumb positions available with the four
thumb keys in FIGURE 3-5 are defined in the embodiment as
11 follows:
12 [0] No thumb keys pressed: Transmits the lower case
13 characters in the letter slphabet of FIGURE 3-2
14 in the normal left-to-right sequence of the
characters in the chord being pressed with the
16 finger keys.
17 [1] SPECIAL: Transmits characters in the special
18 character alphabet in FIGURE 3-3 in the normal
19 sequence of characters in the chord currently
being pressed with the finger keys.
21 [2] NUMBER: Transmits characters of the number alpha-
22 bet in FIGURE 3-4 in the normal sequence of
23 characters in the currently pressed chord.
24 [3] UPPER: Transmits characters in the upper-case
of the letter alphabet as shown in FIGURE 3-2
26 in the normal sequence of characters in the
27 currently pressed chord.
D-PO9-74-030 -15-
lV8S~87
1 [4] SP~CE CAP LOW: Transmits a single space
2 character followed by an upper-case
3 character in the letter alphabet of FIGURE 3-2
4 for the leftmost finger position followed by
lower-case characters in the letter alphabet
6 of FIGURE 3-2 for any other characters in the
7 currently pressed chord ir- normal sequence.
8 [5] SPACE: Transmits a single space character
g followed by the lower-case letter alphabet
characters of FIGURE 3-2 in the currently
11 pressed chord in normal sequence.
12 [6] SPACE REVERSE: Transmits a single space character
13 followed by lower-case characters in the letter
14 alphabet of FIGURE 3-2 for the currently pressed
chord, with the characters outputted in reverse
16 sequence. This combination would, for example,
17 permit the transmission of the characters "and"
18 with a single chord stroke of keys D, N and A
19 in FIGURE 3-2 with three fingers.
[7] REVERSE: Transmits lower-case characters in the
21 letter alphabet in FIGURE 3-2 in reverse sequence
22 for the currently pressed chord.
23 3.3 Finger Pos-itions
24 Respective assignments of characters to the 27
finger positions (labeled in FIGURE 3-6 in hexadecimal
26 from [1~ to [lB]) for various alphabets/cases are shown
27 in FIGURES 3-2 through 3-4. FIGURE 3-2 illustrates the
28 assignment of upper case characters o~ the "letter" alphabet,
D-PO9-74-030 -16-
lV~ "7
1 but it also represents the assignment of the lower case
2 characters in the letter alphabets to the same finger
3 positions. FïGUR~` 3-3 shows the finger position
4 assignment of characters for the "special" character
alphabet. FIGU~E 3-4 shows the finger position
6 assignment of the characters for the "number" alphabet.
7 One or more finger positions may be simultaneously
8 pressed on the keyboard to form a single chord, and an
9 output character signal is generated for each pressed
finger position in the chord. The alphabet that is used
11 to translate the pressed finger positions into characters
12 is controlled by which thumb position is being pressed.
13 The first chord begins when any one or more keys
14 are pressed from a null keyboard state, which is defined
as the state existing when no finger key is pressed. The
16 second and following chords need not be pressed from a
17 null state; this is explained later in relation to
18 discussions for FIGURE 5.3-1, 5.3A and 5.3B. The
19 transmitted sequence of characters for a chord can be a
normal sequence or a reversed sequence. The normal
21 sequence represents the characters in the chord from
2~ left-to-right across the finger keyboard in the thumb
23 selected alphabet. The reverse sequences represent the
24 characters in the chord from right-to-left across the
~eyboard.
26 A "window" concept is used for decoding the finger
27 positions in the detailed embodiment. A window is
28 comprised of each group of four adjacent finger keys.
D-P09-74-030 -17-
1~)8S~8,~
] A Window is decoded by examining the electrical signals
2 provided from the window's four keys; a key's electric
3 signal is 0 if -the key is not pressed and is 1 if the
4 key is pressed. FIG~RE 3-6 illustrates the five
"windows" available on the -ten finger keys. The
6 decoding operation begins with the leftmost window 1,
7 as follows:
8 A. First, the two signals for the leftmost upper
9 and lower finger keys in window 1 are elec-
tronically sensed to determine if neither
11 of these two keys is pressed. If neither is
12 pressed (i.e. OOXX), there is no detectable
13 finger position for this window; and the next
14 window is accessed by going to step H below.
If either or both of the leftmost keys in the
16 window is pressed, decoding for this window
17 continues by going to step B.
18 B. Next, if all four keys in the window are pressed
19 (i.e. 1111), the decoded finger position is
indicated in the common corner of the four keys
21 e.g. finger position [5] in window 1 in FIGURE 3-6.
22 That is, it will be finger position [5], [B~, [11]
23 or [17] for the respective windows 1, 2, 3 or 4.
24 Then, step H is entered to access the next window.
But, if all four keys are not pressed, step C is
26 entered.
27 C. If the two leftmost keys in the window are both
28 pressed, but not all four keys are pressed, the
29 decoded finger position is indicated between the
D-PO9-74-030 -18-
1~)85~B7
1 leftmos-t upper and lower keys in the window,
2 e.g. [2] i.n window 1. That is, it will be finger
3 position [2], [~], [~], [14] o~ [lAl for the
4 respective windows 1, 2 r 3, 4 or 5. Then Step H
is entered. If the two leftmost keys are not
6 both pressed, step D is entered.
7 D. If the upper left key is the only pressed key in
8 the window (i.e. 1000), that key represents the
9 decoded finger position, e.g. finger position [1~
in window 1. That is, it will be ~inger position
11 [1], [7], [D], [13] or [19] for the respective
12 window 1, 2, 3, 4 or 5. Then Step H is entered.
13 If no finger position has yet been decoded for the
14 window, step E is next entered.
E. If both upper keys in the window are pressed
16 (i.e. 1010), the decoded finger position is
17 indicated between the upper two keys in the window.
18 That is, it will be finger position [4], [A], [10] or
19 [16] for windows 1, 2, 3 or 4 respecti~ely. Then
Step H is entered. If no decoding has occured so
21 far, step F is entered.
22 F. If only the left lower finger key in the window
23 is pressed, i.e. 0100, that key represents the
24 decoded finger position. That is, the decoded
finger position is [3], [9], [F], [15] or ~lB]
26 for the respective windows 1, 2, 3, 4 or 5. Then
27 Step ~l is entered. If no finger position has
28 been decoded thus far, the only remaining decodable
D-PO9-74-030 -19-
8~7
1 co~l~ is ~101 which therl must represent the
2 decode(l Fin(~er posi-tion, which is ~etweerl the
3 two lower keys in the window. That is, the
g decoded finger position is [6], [C], [12] or [18]
for window 1, 2, 3 or 41 respectively. Step H is
6 therl entexed to access the next window.
7 H. At this point, any finger position that can be
8 identified from the information in this window has
g been identified. Any one bit for either or both
right hand keys of the window that has been used
11 in any detected finger position is changed to a
12 zero. Then, the four signals representing the
13 next window are accessed, and Step A is reentered
14 for decoding that next window, which now becomes
the current window. The process continues from
16 window 1 to window 2 to window 3 to window 4 and
17 ends with the decoding of window 5. In window 5
18 in FIGURE 3-6, two non-existent keys are assumed
19 to be in its rightmost two positions, which always
generate "00" for purposes of decoding, i.e. they
21 are considered not pressed. When a finger position
22 is decoded, the thumb position determines the
23 character it represents by chosing one of the four
24 alphabets/cases in which the decoded finger positions
represent a character. Each time a next window is
26 selected, the process returns to Step I above for
27 operation on the new current window.
28 3.4 Special Word and Special Chord Generation
29 The keyboard provides the facility for storing a
special word and a special chordO Whenever the stored
D-PO9-74-030 -20-
~)8S4~7
I specjal c~lord is ~f~yed, the special ~ord (which is a
2 stored sequence of up to ei~ht characters) is transmitted
~ by the };eyhoard.
4 A "special chord" pushbutton and a "special word"
switch shown in FIGURE 3-1 are used to store the special
6 chord and its corresponding special word. With these two
7 separate switches, either the special word or special
8 chord can be independently changed at any time, even though
9 both the currently stored special chord and special word
combine to control a single keyboard operation.
11 To store a special word for subsequent transmission,
12 the special word switch in FIGURE 3-1 is set to LOAD
13 position. Sequences of characters generated by pressing
14 the keyboard when this switch is set to LOAD position
are not transmitted, but they are sent to a special word
16 buffer which can hold up to eight characters. If more
17 than eight characters are generated, only the last eight
18 are retained in this buffer. Returning this switch to its
19 USE position restores normal operation of the keyboard;
so that at any subsequent time, pressing the keys that
21 make up the special chord will cause the characters
22 stored in the special word buffer to be transmitted as
23 keyboard output.
24 ~o store a special chord for subsequent use, the
"special chord" pushbutton in FIGURE 3-1 is set to its
26 LOAD position. The next chord pressed on the keyboard
27 after this button is pushed (and released) is stored as
28 the special chord. Subsequently, when that chord is
29 pressed on the keyboard, it causes the special word stored
in the special word buffer to be transmitted instead of
31 the normal keyboard output for that chord.
D-PO9-74-030 -21-
1~)85487
1 The special cllord pushbutton should not be pressed
2 while the special word switch is set to LOAD unless the
3 special chord is to he part of the special word.
4 3.5 Typing On The Chord ICey oard
A characteristic of this keyboard is that it
6 supports a wide range of learning skills. There are
7 several levels of learning and~ when the typist advances
8 to a new level, he will rise to a new and faster typing
9 speed.
This keyboard, unlike prior chord keyboards; allows
11 the novice to do "hunt and poke" typing with one finger.
12 The typist who is willing to learn touch-typing can
13 take advantage of additional resources of the keyboard in
14 order to type faster.
A second level of learning is to learn by touch the
16 positions of single characters in the letter alphabet on
17 the keyboard and the position of the upper-case thumb key.
18 The third level of learning is to learn to enter
19 several letters with one chord keystroke plus the use of
all thumb positions. Initially, the typist would learn
21 small chord patterns for specific commonly used
22 character sequences.
23 The final learning level would begin when the typist
24 started to generate chords for multiple character sequences
which had not previously been specifically learned. The
26 skilled typist would copy text at close to the maximum
27 number of available keyboard characters per chord stroke.
28
D-PO9-74-030 -22-
10~54~7
1 4.0 Mechanical Design
2 The principal features of the mechanical design of
3 the keyboard are shown in FIGURES 4-1 and 4-2. FIGURE
4 4-1 shows a top view of the keyboard mechanism, and
FIGURE 4-2 is a side view showing the finger keys
6 and their associated components. The side view also
7 shows the height relation between top surfaces of
8 the thumb keys and the finger keys.
g In FIGURE 4-2, the mechanical assembly is constructed
on a base 1. Each key 8 or 9 is fastened securely to its
11 key arm 3. When the key is pressed down, the key arm 3
12 rotates about its axis 4 pressing against a switch 5
13 creating a short circuit between its terminals, 6a and 6b.
14 Terminal 6a is connected to +5 volts (i.e., a logical 1)
whereas terminal 6b is connected through a resistor to 0
16 volts (a logical 0). Therefore, when any key is not
17 depressed, a logical 0 is provided on terminal 6b, but when
18 the key is depressed, the signal on terminal 6b becomes a
19 logical 1. Terminal 6b and its counterparts for the 13
other keys are wired to the keyboard word generator (see
21 FIG. 5.1-1). The switch must finish bouncing within 5
22 milliseconds after key actuation so as not to make errors,
23 but this requirement is easily met by good commercially
24 available switches.
In FIGURE 4-1, it can be seen that all of the finger
26 keys rotate about one axis, 4, while all of the thumb
27 keys rotate about another axis, 10. The key arms of the
28 front row of finger keys are shaped so as not to conflict
29 with the arms of keys of the back row.
D-PO9-74-030 -23-
~1~8S4~7
1 There is a spring, such as 11 shown in FIGUR~ 4-2,
2 for each key that is compressed when that key is
3 depressed. This contributes to providing the proper
4 mechanical resistance when the key is pressed to provide
the proper force to react against -the user's finger.
6 There are restraints, 12 and 13, that limit the motion
7 of the keys to their required upper positions.
8 In FIGURE 4-1, the group of thumb keys is arranged
9 at an angle 14 with respect to the finger keys. In
FIGURE 4-2, it is shown that the upper limit of the thumb
11 keys is below the upper limit of the finger keys by a
12 distance 15. These two values, 14 and 15, are selected
13 properly to acco~modate the fact that the thumb is attached
14 to the hand in a different position and at a different
angle from the fingers. This arrangement makes it
16 comfortable to form chords with the fingers and the thumb.
17 Each thu~b key structure has a sideview (not shown)
18 which may be similar to the sideview of finger key 7 shown
19 in FIGURE 4-2, except that key surface 9 is supported at
a lower position. In FIGURE 4-2, the upper surfaces of
21 the thumb keys are made lower than the upper surfaces of
22 the finger keys by distance 15, e.g. one-half inch.
23 At various places beneath the keyboard, such as at 16
24 and 17 in FIGURE 4-2, the base has holes molded into it to
accept circuit boards~ such as 18 and 19, which hold sockets
26 like 20 and 21, which hold integrated circuit packages like
27 22 and 23. In FIGURE 4-1 the space 24 between the finger
28 key assembly and the thumb key assembly contains the power
29 supply.
An outer container protects the internal working parts
31 so that the assembled keyboard looks like FIGURE 3-1.
D-PO9-74-030 -24-
1~5~8 7
1 5.0 Keyboard E ectronics
2 5.1 Overview
3 The control circuits take the signals produced by
4 pressing the keyboard ~eys and produce as output a series
of serially encoded pulses representing a string of characters
6 that is the output from the manual keyboard actuations.
7 FIGURE 5.1-1 is a block diagram relating the keyboard
8 and its control circuits.
g Pressing the keyboard keys closes sets of contacts
that provide key signals on 14 wires 102 through 115 which
11 are either 5 volts (logical level 1) or 0 volts tlogical
12 level 0). The signals from the keys are fed in parallel
13 to the Keyboard Word Generator which generates a 16 bit
14 word.
Timing Signal generator 5.2 is described in detail in
16 section 5.2. This circuit provides the clock and other
17 timing pulses required by the rest of the keyboard
18 electronics.
19 Keyboard Word Generator 5.3 is described in detail in
section 5.3. This circuit takes the parallel input from
21 the keyboard keys and generates every 5ms a serial output
22 comprising a 16 bit keyboard word which represents all
23 characters in a chord. This word is sent to Regular Chord
24 Decoder 5.6 and to Special Chord Circuits 5.4. The Keyboard
Word Generator 5.3 will generate a sequence of many keyboard
26 words for each chord pressed on the keyboard, since it
27 generates a word every 5ms. However, only one keyboard word
28 is decoded per pressed chord. To accomplish this, the
29 Keyboard Word Generator generates a Chord Present signal
D-PO9-74-030 -25-
~S~7
1 v~hen any ~e~ is released whlch indicates the last word is
2 valid and is to b~ decoded.
3 T~le Special Chord Circuits 5.~ detect when a prede-
4 termined cl~ord conbination is pressed or not. If the
predetermined chord (i.e. special chord) is pressed, a
6 Special Word of up to 8 characters is outputted by the
7 Special Word Generator 5.5. If no Special Word is detected,
8 circuits 5.4 signal the Regular Chord Decoder 5.6 to decode
9 that keyboard word. The Special Chord is loaded by pressing
a Special Chord Pushbutton and then pressing the
11 described special chord on the Keyboard. The Special
12 ~ord is loaded by pressing the Special Word Switch while
13 inputting the characters comprising the special word
14 (up to 8).
The Output Control 5.7 determines if the keyboard
16 output characters are to be the decoded characters from the
17 Regular Chord Decoder or the special word characters from
18 the Special Word Generator; and then it transmits these
19 characters as the output of the keyboard.
5.1.1 Symbols In The Drawings
21 Standard drawing symbols are used for OR circuits, AND
22 gates, inverters, etc. Commercially-available pluggable
23 circuit modules are represented by boxes containing a number,
24 such as 74123 in parenthesis in FIGURE 5.2-1, which identifies
a commercially available integrated circuit module that is
26 available from Texas Instruments, Inc. as TTL module part
27 number SN74123, or from the Signetics Company as part number
28 N74123, and other companies. The standard circuits are
~-~09-74-030 -26-
lV8~487
1 described in prior commercial publications, such as
2 "The TTL Data Book For Design Engineers" published by
3 Texas Instruments Inc, in 1973, or "Designing with TTL
4 Integrated Circults" published by McGraw-Hill Book Company
in 1971.
6 Thus, logic modules used in the detailed embodiment
7 are commercially available off the shelf items.
8 5.2 Timing Signal Generator
9 The Timing Signal Generator produces the basic timing
signals required by the keyboard system. A reset pulse
11 is generated every 5ms to control the period for sampling
12 the key settings. This frequency is chosen because the
13 human finger reaction on the chords cannot press or
14 release the chords more than once in a 5ms period.
During each 5ms period, a higher frequency of 0.625
16 megahertz generates the pulse sequence which operates
17 the system between 5ms reset pulses. These 0.625
18 megahertz signals consist of 4 continuously running pulses
19 of .4 microsecond duration, called PCOUNT, RPULSE, COMPARE,
and NCOUNT. These pulses are shown in FIGURE 5.2-2.
21 The inverse of the RESET pulse (NRESET) is also generated.
22 FIGURE 5.2-1 is a logic diagram of the circuit for
23 generation of the timing signals. This circuit operates
24 as follows.
A Clock multivibrator generates the continuous square-
26 wave output signal OSC (see FIGURE 5.2-2). The Clock
27 multivibrator consists of two monostable multivibrators
28 wired back to back so that they free run at a frequency
D-PO9-74-030 -27-
lV85487
1 determined by the connected resistor and capacitors shown
2 in FIGURE 5.2-1. The resistor is ad justed to give an
3 oscillator output frequency of 1.25 megahertz.
4 The signal OSC is connected to the Cl~ input of a clock
counter, which divides the oscillator frequency ky two to
6 provide an output OSCHALF (see FIGURE 5.2-2) with a frequency
7 of 0.625 megahertz.
8 Pulse gates receive the Q and Q outputs of the clock
9 counter and combine them with the OSC and OSC signals
from the Clock multivibrator to produce the PCOUi~T, RPULSE,
11 COMPARE and NCOUNT output signals.
12 The RESET pulses are controlled by a sample interval
13 timer in FIGURE 5.2-1 which produces a square-wave output
14 with a frequency of approximately 200 cycles per second.
This module is connected with appropriate external resistor
16 and capacitors (not shown) to produce the 0.2 kilohertz
17 square wave. A negative-going signal (TPULSE) appears at
18 the output of the Sample Interval Timer once every 5
19 milliseconds (5ms). First and Second Synch flip flops are
used to produce a RESET pulse coincident with the first
21 RPULSE that starts after the occurrence of the negative-going
22 TPULSE signal. The negative-going TPULSE signal sets
23 the First Synch flip flop bringing its Q output to 1
24 (signal A on FIGURE 5.2-2). With the J input of the
second synch flip flop now at 1, the leading (negative-going)
26 edge of the next RPULSE will set the Second Synch flip flop
27 and take its not Q output to 0 (Signal _B on FIGURE 5.2-2).
28 The RESET pulse is generated by gating the not Q output
D-PO9-74-030 -28-
- ~ , ....
~L~8548 ~'
1 of this flip flop with RP~I.SE in a NO~ ~at(. The inverted
2 RESET pulse !;~RESET) is used -to reC;et the r;rst ';~nch flip
3 flop. The Second ~ynch flip flop is reset hy ()Ring the
4 out~ut of the Second Synch flip flop with t~le C~ RL
signal in a NOR gate (signal C in YIGUR~ ~.2-2). The
6 Second Synch flip flop is thus reset immediatel~ following
7 the generation of the RESET pulse.
8 5.3 Keyboard Word Generator
g The Keyboard Tllord Generator generates a 16 bit word
once every 5ms (after each reset pulse) frorn tihe keyboard
11 cable output signals. But these keyboard words are not
12 decoded until a signal occurs (called C~IORD PRESENT) which
13 is provided when a chord is completely formed on the
14 keyboard. The CHORD PRESENT signal distinguishes each
valid word from all the generated invalid words. Each
16 valid word is to be decoded by the special chord circuits
17 in FIGURE 5.4-1 and the Regular Chord Decoder in FIGURES
18 5.6-lA, lB and lC.
19 5.3.1 Alternate Finger Techniques
The Keyboard electronics controls how the machine
21 will accept chords formed by the user on the keyboard.
22 Three different chord completion techniques are used
23 by three alternative embodiments of the Keyboard Word
24 Generator shown respectively in FIGURES 5.3-1, 5.3A and 5.3B.
5.3.1.i "One-Released" Finger Technique
26 The first and preferred technique is for the machine
27 to recognize completion of a chord by using the "one-
28 released" finger technique. This technique recognizes
D-PO9-74-030 -29-
S4~7
1 completion of a chord (generating the C~IORD PRESENT signal)
2 whenever a user releases one keyboard key after having
3 pressed one or more keyboard keys. Tlle operation of this
4 technique is illustrated in the diagram below which
shows different events and states on a time scale from
6 left to right.
7 "One-Released" Fingers Technique
8 Chord-Being- ¦ Keys-Being- Chord-Being-
9 formed state ¦ Released state formed state
Any new key 1st Key Released Any New Key
11 Pressed (Chord (CHORD PRESENT Pressed (Chord
12 Started Time) signal generated) Started Time)
13 (Chord Completed
14 Time)
Pressing any key places the keyboard word generator in the
16 Chord-Being-Formed state. During that state, any number of
17 keys may be pressed. The first key released generates the
18 CHORD PRESENT signal, the detected chord being made up of
19 those keys pressed just prior to the release of that key.
The keyboard word generator is then placed in the Keys-Being-
21 Released state. Pressing any new key puts the keyboard word
22 generator back in the Chord-Being-Formed state.
23 For example, a chord may be formed by pressing a number
24 of keys and releasing all keys pressed. Another way in
which a chord may be formed is by holding down a number
26 of keys and pressing and releasing additional keys, with
27 a chord formed each time a key is released after one or
28 more keys have been pressed.
29 Thus, this technique allows the user to leave his
fingers pressing keys which are to be part of the next
31 chord, and thereby minimizes the amount of total finger
32 movement required to operate the keyboard.
D-PO9-74-030 -30-
~0854~7
1 5.3.1.2 "~ Released" Finger Technique
2 The second technique used is the "All-Released" Finger
3 Technique. With this technique, a chord is detected at the
4 point where all pressed keys are released. The operation of
this technique is illustrated in the diagram given below.
6 "All-Released" Finger Technique
7 Chord-Being- Wait State Chord-Being-
7a Formed state (No keys Formed state
8 (Keys being pressed)
8a pressed and
9 released)
1st key Last Key 1st Key
10a Pressed Released (~HORD Pressed
11 PRESENT signal
12 generated)
13 The first key pressed places the keyboard word generator
14 in the Chord-Being-Formed state. While in that state the
fact that any key has been pressed is stored by the keyboard
16 word generator. When all keys are released, a chord is
17 detected and the CHORD PRESENT signal is produced. The
18 chord produced is made up of all keys pressed from the time
19 the first key is pressed until all keys are released. (It
is noted that the conventional two-handed stenograph machine
21 recognizes chord formation when all keys are restored after
22 pressing a chord with both hands and it may be said to use
23 a form of the "All-Released" technique.)
24 5.3.L.3 "0ne-Released, All-Released" Finger Technique
The third technique is the "One-Released, All-Released"
26 finger technique. With this technique, a chord is detected
27 at the point when one key is released after one or more
28 keys have been pressed. However, the formation of a new
29 chord does not begin until all keys have been released.
D-PO9-74-030 -31-
~t~854~7
1 The diagram given be],ow illustrates the operation of this
2 technique.
3 "One-Released, All-Released" Finger Technique
4 Chord-Being ¦ Keys-Being ¦ Chord-Being
Formed State ¦ Re:Leased State ¦ Formed State
6 All Keys 1st Key All Keys
7 Released Released (C~ORD Released
8 PRESENT signal
9 generated)
With no keys pressed, the keyboard word generator is in
11 the Chord-Being-Formed state. During that state, any number
12 of keys may be pressed. The first key released generates
13 the CHORD PRESENT signal and places the Keyboard word
14 generator in the Keys-Being-Released state. The detected
chord is made up of those keys pressed just prior to the
16 release of that key. Once all keys have been released the
17 keyboard word generator is placed back in the Chord Being
18 Formed state~
19 This third technique combines the first two techniques
by using the "One-Released" technique to recognize chord
21 completion and using the "All-Released" technique before
22 permitting the next chord to be started. That is, it
23 inhibits formation of the next chord until after all keys
24 are released. Note that no key is pressed after one finger
is lifted but before all fingers are lifted can be
26 included in any chord.
27 5.3.1.4 Comparison of Finger Techniques
28 The third technique provides faster electronic
29 operation than the second technique by permitting earlier
decoding of a chord than the second technique. However,
31 the first technique permits the fastest operation but
32 may result in a higher error frequency than the second or
33 third technique.
D-PO9-74-030 -32-
1~)854~7
1 Orlly one chord formation technique should be used in
2 constructio~ of a keyboard, because a user trained in one
3 techni~ue will have difficulty in switching to another.
4 In general, and depending to some extent on his finger
s pressing habits, a user who has formed the habits required
6 to use the "All-Released" fingers chord formation technique
7 may get the same keyboard output results when using a
8 keyboard incorporating the "One-Released" technique because
9 lifting one finger is included in the operation of
lifting all fingers. E~owever, the converse is not true.
11 That is, a user who has formed the habits of the "One-
12 Released" finger technique or the "One-Released, All-Released"
13 finger technique may not always get the same keyboard output
14 results when using a keyboard incorporating the "All-Released"
chord formation technique.
16 5 3.2 Overview of "One-Released" Keyboard Word Generator
17 FIGURE 5.3.1 is a diagram of the "One-Released" keyboard
18 word generator. The keyboard cables shown in FIGURE 5.3 1
19 connect to the key switches shown in FIGURE 4-1.
The output of each key switch (as described in Section
21 4.0) is either 0 volts (key is raised) or 5 volts (key
22 pressed). These voltages correspond to logic levels 0
23 (e.g. 0 volts) and 1 (e.g. 5 volts) used by the logic
24 circuits in the keyboard electronics.
There are 14 keys on the keyboard shown in FIGURE 3-1.
26 The key switch associated with each of these keys is
27 connected through a keyboard cable to the keyboard multiplexer
28 shown in FIGURE 5.3.1. Each key switch determines the state
D-PO9-74-030 -33-
1~)8S4~'7
l of a respective one of bit positions 2 through 15 in a
16-bit word referred to as the new keyboard word. sit
positions 0 and l of the new keyboard word are always at 0
state. Thus, if a key is pressed, the corresponding bit
is in the l state in the new keyboard word; and if a key
is not pressed or is released, the corresponding bit position
is in 0 state. Section 5.6.1 describes in more detail the
correspondence between the bit position numbers and the
keyboard key positions.
once every 5ms, one new keyboard word is generated and
compared bit-by-bit with the keyboard word generated 5ms
before (the last keyboard word). This sampling interval
was selected to be sufficiently short, relative to human
finger movement, so that finger movement could not change
the key state more than once (from 0 to l, or l to 0) during
any 5ms sampling period. (It may be possible to operate
a keyboard without loss of data at a longer sampling interval
than 5ms, because maximum human finger reaction is of the
order of 50ms.) The circuit as designed is capable of
operating with a much shorter or longer sampling interval
than 5ms. It is all right if the keys comprising a chord
are not all pressed in the same 5ms interval, since resulting
keyboard words for incomplete chords are ignored by the
electronic system.
The bit-by-bit comparison of the new and last keyboard
words is done by comparison gates 27 and 28 in FIGURE 5.3-l
to determine which keyboard word represents the completed
chord and should be decoded. Whether a chord has completed
or a chord has started, is determined by comparison gates
27 and 28 which control a S~ate flip flop to indicate the
PO9-74-030 _34_
16~8S4~
1 respective one of these two keyboard states. A chord
2 completed signal from gate 27 sets a C~IORD ~RESENT flip
3 flop, which conditions a C~iORD PRESENT gate 29 upon
4 completion of the new keyboard word, indicated by setting
of the COUNT CUTOFF Elip flop. Gate 29 then transmits a
6 CHORD PRESENT signal to indicate the last chord is the
7 valid chord which should be decode~ by the Regular Chord
8 Decoder and the Special Chord Circuits after the final bit
9 of the last keyboard word has been transmitted to those
circuits by the Keyboard Word Shift Register. Thus, the
11 CIIORD PRESENT signal indicates that the keyboard word just
12 transmitted is a valid chord which needs to be decoded.
13 The CHORD PRESENT signal remains active throughout the
14 current 5ms sampllng interval during which the decoding
and resulting character outputting takes place.
16 The comparison and shifting of the keyboard words
17 takes a small fraction of the 5ms sampling interval.
18 The circuits have been designed to shift one bit every 1.6
19 microsecond, thus completing the comparison and shift
operation in approximately 26 microseconds; hence the
21 remainder of the 5ms interval is available for decoding the
22 keyboard word. However, the design of the disclosed
23 circuit could permit considerably faster shifting and
24 comparison than 26 microseconds, if necessary.
5.3.3 Modules Used in The "One-Released" Keyboard Word Generator
26 FIGURE 5.3.1 is a logic diagram of the Keyboard Word
27 Generator. The significant modules shown in FIGURE 5.3-1
28 are as follows. They are listed roughly left to right and
D-PO9-74-030 -35-
~LC385~
1 top to bottom on FIGURE 5.3-1.
2 1. The input gate 21 controls PCOUNT pulses to the
3 Bit Counter.
4 2. The Bit Counter is used to generate the count input
to the Keyboard Multip~exer for it to sample
6 successively the signal levels on each of the ~ourteen
7 keyboard cables E2 through E15 from the key switches.
8 3. The Count Gate 22 determines when a count of hexa-
3 decimal E (all l's) has been reached on the Bit
Counter to terminate a sequence of 15 PCOUNT pulses.
11 4. The Keyboard Multiplexer has 16 parallel inputs and
12 an output W that converts the 16 input levels
13 representing the positions of the 14 keys on the
14 keyboard) to a serial output.
5. The COUNT CUTOFF flip flop is a J-K flip flop with
16 outputs used to control the three gates 24, 26, 29
17 that control the shifting and comparison of data.
18 6. The Shift Gate 24 controls the PCOUNT pulses used to
19 shift the Keyboard Word shift register.
7. The Keyboard Word shift register is a 16-bit shift
21 register used to hold the last keyboard word for
22 the purpose of comparison with the new keyboard
23 word. The keyboard word stored in this register is
24 passed to the regular chord decoder and the special
chord circuits as the KEYBOARD BITS signal.
26 8. The CHORD PRESENT flip flop is a J-K flip flop that is
27 used to indicate when a completed chord has been
28 detected.
D-P09-74-030 -36-
'
~38S4~q
1 9. The Chord gate 26 contro]s the times as which comparisons
2 are made between corresponding bits in the new and
3 last keyboard words~
4 10. The Comparison gates 27 and 28 are used to determine
the Chord-Completed and Chord-Started times.
6 11~ The State flip flop is a J-K flip flop that is used
7 to indicate whether the Chord-Being-Formed State or
8 the Keys-Being-Released state is the current keyboard
g state.
12. The CHORD PRESENT gate 29 produces a signal that is
11 sent to the regular chord detector and special
12 chord circuits to indicate that the keyboard word
13 last transmitted to those circuits represents a
14 completed chord, and that its contained characters
should be detected and outputted.
16 5.3.4 Detailed Operation of Keyboard Word Generator
17 FIGURE 5.3-2 illustrates the timing of significant
18 Keyboard Word Generator signals. Three clocking pulses
19 for driving the system are derived from FIGURE 5.2-1 as
the COMPARE, PCOUNT, and RESET pulses. NRESET pulses
21 are RESET pulses inverted. The COMPARE and PCOUNT pulses
22 are continuous pulses which are offset in time by an
23 interval 2t, as shown in FIGURE 5.3-2. The interval t
24 may be assumed to be .4 microseconds for this discussion
although the circuit will operate with a t considerably
26 longer or shorter than this period. The RESET pulse
27 has a width of t and occurs once each timing interval where
28 the timing interval is as discussed previously. The
D-PO9-74-030 -37-
~8s~8q
1 RES~T pulse is synchronized to occur between a PCOUNT and a
2 COMPARE pulse, as shown in FIGURE 5.3-2. The generation of
3 these pulses is discussed in the section Timing Signal
4 Generator.
In the following discussion, -the various waveforms
6 identified by the circled letters A through L on FIGURE
7 5.3-2, are found on lines referenced with circled letters
8 on FIGURE 5.3.1.
g The RESET pulse resets the Bit Counter so that its
outputs QA, QB, QC, QD are all 0. The COUNT CUTOFF flip
11 flop and the CHORD PRESENT flip flop are also reset at
12 the same time by an NRESET pulse. With the output lines
13 of the sit Counter all at zero, the output of the count
14 gate 22 (waveform B) is also zero, so that a one output
from inverter 23 enables the input gate 21 to pass PCOUNT
16 pulses to the input of the Bit Counter (waveform A). As
17 a result, the Bit Counter steps through 15 counts, one
18 count each time that the trailing edge of a PCOUNT pulse
19 occurs, until gate 21 is blocked by count 15 (all ones)
enabling gate 22 and dropping the output of inverter 23
21 to thereby block any further PCOUNT pulses through gate 21.
22 During the 15 counts of the keyboard word, the Q
23 output of the COUNT CUTOFF flip flop (waveform G) is one,
24 enabling the shift gate 24 and the chord gate 26. This Q
signal is also sent to the Regular Chord Decoder as the
26 COMPARE ENABLE signal. With shift gate 24 enabled, PCOUNT
27 pulses are transmitted to the shift clock input CP of the
28 Keyboard Word shift register (waveform K); it is then
D-PO9-74-030 -38-
~35~7
1 shifted one bit on the leading edge of each PCOUNT pulse.
2 With chord gate 26 enabled, COMPARE pulses are transmitted
3 to the clock input o~ the State flip flop (waveform L)
4 causing that flip flop to sample the Comparison gates
each time that a COMPARE pulse occurs.
6 In more detail, the comparison of the first bit
7 positions in the new and last keyboard words occurs at
8 the COMPARE pulse that follows the RESET pulse. ~t that
9 time, the four outputs from the Bit Counter are all set
to zeroes due to the RESET pulse, and thus inputs A, B,
11 C and D of the Keyboard Multiplex are set to zero.
12 During this first count, the Keyboard Multiplexer connects
13 its E0 input to its W output line (waveform C). The E2
14 through E15 input lines of the Keyboard Multiplexer are
connected to Keyboard cables 2 through 15, respectively,
16 as shown in FIGURE 5.3-1. Inputs E0 and El are not
17 used, and are only padded zero bits in each keyboard word.
18 The 16-bit Keyboard Word shift register at this point
19 contains bit positions 15 through 0 of the last keyboard
word. Bit position 0 is in the rightmost bit position
21 of the register, as shown in FIGURE 5.3-1; and, thus,
22 the Q output of that shift register indicates the state
23 of that bit position. The COMPARE pulse is used to
24 compare bit N of the last keyboard word with bit N of
the new keyboard word, where N is the number of the
26 keyboard word bit position currently in the rightmost bit
27 position of the input shift register. Two types of
28 comparisons are of interest. The Chord-Started condition
D-PO9-74-030 -39-
~54~7'
1 is indicated when the State flip flop is in the Key-seing-
2 Released state and any bit N of the new keyboard word is
3 a 1 and the corresponding bit N in the last keyboard word
4 is a 0. This comparison is achieved through Comparison
gate 28, which is an AND gate receiving the inverted output
6 of the shift register, the output of the multiplexer,
7 and the Keys-Being-Released output of the State flip flop.
8 If all of these inputs are 1, the output of AND gate 28
g will trigger the J input of the State flip flop at
the trailing edge of the COMPARE pulse and the State flip
11 flop will be RESET to the Chord-Being-Formed state.
12 The system is put in the Keys-Being-Released state
13 when the State flip flop is in the Chord-Being-Formed
14 state and any bit N in the new keyboard word is a 0 and
the corresponding bit N in the last keyboard word is a
16 1. Comparison gate 27 detects this situation. The inverted
17 output of the keyboard multiplexer (representing a bit in
18 the new keyboard word) is compared with the output of the
19 N bit of the shift register (representing the corresponding
bit in the last keyboard word). When the
21 output of the inverted multiplexer is 1 (representing a 0
22 bit), the output of the rightmost bit of the shift register
23 is 1, and the State flip flop output is 1 representing the
24 Chord-Being-Formed signal, the output of comparison gate 27
will go to 1 and the State flip flop will be switched to
26 the Keys-Being-Released state on the trailing edge of the
27 COMPARE pulse. In addition, a 1 output from Chord Comparison
28 gate 27 sets the CHORD PRESENT flip flop on the trailing
29 edge of the COMPARE pulse.
~-PO9-74-030 -40-
IIL~38S4~7
1 In more detail, the comparison for all of the bits in
2 the new ancl last keyboard wor~s operates in the
3 following manner. The leading edc~e of the PCOUI~T pulse
4 shifts the Keyboard Word shift register 1 bit to the right.
The output of the shift register is passed to the Regular
6 Chord Decoder and the Special Chord circuits as the XEYBOARD
7 BITS signal. The trailing edge of each passed PCOUNT pulse
8 (waveform A) increments the Bit Counter by 1. As the
9 outputs of the Bit Counter are provided to the inputs of
the Keyboard Multiplexer, the next sequential bit of the
11 new keyboard word (on the 16-input lines to the Multi-
12 plexer) is selected for output. At this point, the output
13 Of the Multiplexer represents bit N of the new keyboard
14 word, and the output of the Keyboard Word shift register
represents bit N of the last keyboard word. The COMPARE
16 pulse which occurs following the PCOUNT pulse changes the
17 state of the State flip flop if either comparison gate 27
18 or 28 has a 1 output for that bit comparison as previously
19 described. Thus, if the State flip flop is in the Chord-
Being-Formed state, if any bit in the new keyboard word is
21 0 where the corresponding bit in the last keyboard word is
22 1, a chord completed signal will be generated by gate 28.
23 Similarly, any bit going from 0 to 1 during the Xeys-Being-
24 Released state will cause the State flip flop to be set to
the Chord-Being-Formed state.
26 The waveforms in FIGURE 5.3-2 illustrate a case where
27 prior to the RESET pulse the State flip flop is in the
28 Chord-Being-Formed state (waveform J). The bit pattern
D-PO9-74-030 -41-
1~85~7
1 in bit positions 0, 1 and 2 of the last keyboard word is
2 001. The bit pattern in bit positions 0, 1, and 2 of new
3 keyboard word is 000. Thus, a Chord Completed signal is
4 generated when bit positions 2 of the two words are compared.
Waveforms C and D on FIGURE 5.3-2 represent the two signals
6 compared. Note that the output of comparison gate 27
7 (waveform E) goes to 1 at bit 2 time and that the trailing
8 edge of the COMPARE waveform resets the State flip flop
g (waveform J) and sets the CHORD PRES~NT flip flop (waveform
H).
11 The comparison cycle continues until the Bit Counter
12 reaches a count of 15 (all output bits are set to 1). At
13 that time, the output of Count gate 22 (waveform B) goes to
14 1, and the output of gate 21 goes to 0, preventing any
further PCOUNT pulses from being transmitted to the Bit
16 Counter. The output from count gate 22 also goes to the J
17 input of the COUNT CUTOFF flip flop.
18 The comparison pulse now makes a comparison of bit
19 position 15 of the new keyboard word with bit position 15
of the last keyboard word. The leading edge of the next
21 PCOUNT pulse shifts the last bit out of the Keyboard Word
22 shift register. The shift register now contains the bits
23 from the new keyboard word (which thereafter becomes the
24 last keyboard word for the next cycle). As the J input to
the COUNT CUTOFF flip flop is now one, the trailing edge
26 of the PCOUNT pulse sets the COUNT CUTOFF flip flop. With
27 the COUNT CUTOFF flip flop set, its Q input to shift gate
28 24 and chord gate 26 is brought to 0 (waveform G). This
D-PO9-74-030 -42-
~185~7
1 corldition prevents further PCOUNT pulses from reaching
2 the shift register and further COMP~RE pulses from
3 reaching the State flip flop or the CHORD PRESENT flip
4 flop. The Q output of the COUNT CUTOFF flip flop goes to
the CHORD PRESENT gate. If the CHORD PRESENT flip flop
6 has been set, an output signal is produced at the output
7 of gate 29 generating a CHORD PRESENT signal that indicates
8 that a completed chord is represented by the last keyboard
9 word sent to the Regular Chord Decoder and the Special
Chord Circuits (waveform I). Note that this signal is not
11 produced until the last bit has been shifted out of the
12 shift register to the Special Chord register in FIGURE
13 5.4-1 and the Finger Bit Register in FIGURE 5.6-1.
14 No further action takes place in the Chord Detector in
FIGURE 5.3-1 until the next RESET pulse occurs. It resets
16 the Bit Counter, the COUNT CUTOFF flip flop, and the CHORD
17 PRESENT flip flop; and then the above described operation
18 repeats.
19 5.3.5 "ALl-~eleased" Keyboard Word Generator
The circuit logic in FIGURE 5.3A uses the "All-Released"
21 fingers technique, which requires all keys on the keyboard
22 to be returned to their zero position (not pressed) for
23 a CHORD PRESENT signal to be generated. See Section 5.3.1.2
24 for a more detailed external description of this technique.
Chord Completion detection in FIGURE 5.3A is as follows:
26 When any key on the keyboard is pressed, it is stored as a
27 one state in its assigned bit position in the Keyboard Word
28 Shift Register, and it remains stored there until all keys
D-PO9-74-030 -43-
10854~7
1 are returned to the zero state which is when the chord is
2 detected. The chord detected is made up of all keys
3 pressed between the time the first key is pressed and the
4 time all keys are returned to the zero state. The
following components in the alternative Keyboard Word
6 Generator in FIGURE 5.3A operate in the same way as
7 described for FIGURE 5.3-1: Input gate 21, the Bit
8 Counter, Count gate 22, the Keyboard Multiplexer,
9 the COUNT CUTOFF flip flop, and Shift gate 24.
After each NRESET pulse (every 5ms), which begins a
11 Multiplexer cycle, the 16 bit position content of the
12 Keyboard Word shift register is both outputted and
13 recirculated to its input through a Bit Accumulation OR
14 gate 31. This gate merges the 1 bit for each newly pressed
key with the same bit in the stored word. That is, this OR
16 circuit provides a 1 bit to the input of the shift register
17 if either an output bit from the Keyboard Multiplexer is 1
18 or the same bit position in the recirculated word is a 1.
19 This accumulation of bits in the shift register takes place
from the time the first key of a chord is pressed on the
21 keyboard until all keys on the keyboard are returned to 0
22 state before a CHORD PRESENT signal is provided to signal
23 that the chord is completed.
24 As with the embodiments in FIGURE 5.3-1 and 5.3B, it
will take as many 5ms periods to form the chord in the
26 shift register as it takes the user to press the keys at
27 any user speed and in any key pressing order.
28 A Zero Detection flip flop senses when all keys are
29 returned to the zero state.
D-PO9-74-030 -44-
i4~7
1 At the beginning of each M~lltiplexer cycle, the Zero
2 ~etection flip flop an~ the Chord Present flip fLop are
3 cleared with an NRF,SET pulse so that each has its Q output
4 set to 0 and its Q output set to 1. ~-lence, the C~ORD
PRESENT signal is then 0.
6 If thereafter any output bit position of the Keyboard
7 Multiplexer becomes 1 (representing a pressed key in a
8 chord), the ~ero Detection flip flop will be set and its
9 Q output becomes 0. The signal from Shift gate 24 clocks
both the Zero Detection flip flop and the Keyboard
11 Word shift register for a single recirculation cycle of
12 the shift register after each NRESET pulse (every 5ms).
13 The first pressed key in a chord also causes the
14 Recirculate Enable flip-flop to be preset by enablement of
ga'ce 34 (at the time that a 1 bit is inputted into the
16 shift register). This preset, brings up the Q output of the
17 Recirculate Enable flip flop to enable the Recirculate
18 Enable gate 32, but the Q output does not affect the Chord
19 Present flip flop at this time because the Clock input
is only actuated by a negative-going signal, which is
21 provided later when the Recirculate Enable flip flop is
22 later cleared by gate 33. With gate 32 enabled, all pulses
23 shifted out of the Keyboard Word shift register are
24 recirculated back to its input through the Bit Accumulation
OR circuit 31.
26 When all keys on the keyboard are returned to a
27 released state, all zeros are provided in the output of
28 the Keyboard Multiplexer. Then the Zero Detection flip
D-PO9-74-030 -45-
~8s4~q
1 flop will not be set due to lack of any 1 bit from the
2 output of the Keyboard Multiplexer during a Multiplexer
3 cycle. Ilence, its Q output will remain at its 1 state
4 after the Multiplexer cycle completes. Thus, when the
Q output of the COUNT CUTOFF Flip flop goes to 1, the
6 output of gate 33 produces a negative-going zero signal
7 to the clear input of the Recirculate Enable flip flop.
8 This signal causes its Q output to switch to zero,
9 producing a negative-going transition at the clock input
of the CHORD PRESENT flip flop. This signal sets its Q
11 output to 1, producing a CHORD PRESENT signal that indicates
12 the last outputted word from the Keyboard Word shift register
13 represents a valid chord which should be decoded.
14 With the Q output of the Recirculate Enable flip
flop set at 0, the Recirculate Enable gate 32 is disabled.
16 Therefore, after the next NRESET pulse, the bits in the
17 Keyboard Word shift register are not recirculated. The
18 output bits of the Keyboard Multiplexer are all 0 at this
19 time so that all input bits to the Keyboard Word shift
register are zeros. The shift register content is thereby
21 reset to all zeros until the next chord is started by
22 pressing at least one key on the keyboard.
23 After being set, the CHORD PRESENT flip flop will
24 remain set only until the next NRESET pulse. It will not
be set again until the next chord is formed since the
26 Recirculate Enable flip flop can not again be preset until
27 the next time a key on the keyboard is pressed, which
28 enables gate 34.
D-PO9-74-030 -46-
54~7
1 5.3.6 "One-Released, A11-Releasecl" Keyboard Wor _ nerator
2 The implementation of the "One-Released, All-Released"
3 finger technique keyboard word generator is shown in
4 FIGURE 5.3B. It generates a CHORI) PRESENT signal indicating
completion of the chord stored in the last outputted
6 keyboard word when the first finger is released in the
7 chord, but the next chord cannot be started on the keyboard
8 until after all keys have been released. See Section 5.3.1.3
g for a more complete discussion of this technique.
In FIGURE 5.3B, the following components operate in the
11 same way as explained for FIGURE 5.3-1: Input gate 21, Count
12 gate 22, the Bit Counter, the Keyboard Multiplexer, the COUNT
13 CUTOFF Flip Flop, Shift Gate 24, Keyboard Word shift register,
14 Chord gate 26, Comparison gate 27, the CHORD PRESENT flip
flop, and CHORD PRESENT gate 29.
16 Thus, the Comparison gate 27 senses the first key to
17 be released and generates a Chord Completed signal which
18 sets the CHORD PRESENT flip flop in the manner previously
19 described for FIGURE 5.3-1. The Chord Completed signal
also sets the State flip flop to the Keys-Being-Released
21 state.
22 The major difference in the operation of the circuit
23 in FIGURE 5.3B over the circuit in 5.3-1 occurs in the
24 way the State flip flop is cleared (reset) which controls
when the next chord can be electronically recognized. That
26 is, gate 27 is blocked by the lack of a Chord-Being-Formed
27 output (i.e. Q being zero) which inhibits the enablement
28 of gate 27 until after gate 41 signals that all keys have
D-PO9-74-030 -47-
~854~t~
1 been released. A negative-going signal level from NAND gate
2 41 is required to the Clear input oE the State flip flop
3 before it can be reset.
4 The clearing of the State flip flop operates as follows:
After each NR~SET pulse, the All Zero flip flop is cleared,
which activates its Q output to an input of NAND gate 41.
7 However, NAND gate 41 does not then provide any output signal
8 because its input from the Count Cutoff flip flop is
9 deactivated while the Keyboard Multiplexer is outputting
its 16 bit position word. If any bit position in the Multi-
11 plexer output word is a 1 bit (indicating a key is pressed)
12 the J input of the All Zeros flip flop is activated. The
13 trailing edge of the output from the Chord gate 26 then
14 sets the flip flop swinging down its Q output and inhibiting
gate 41 and preventing any output from clearing the State
16 flip flop as long as any key is being pressed. When all
17 keys are released, the All Zero flip flop will be set due
18 to the lack of l's from the Multiplexer word, and its Q
19 output will remain up after the Multiplexer word ends. ~hen
the COUNT CUTOFF flip flop output Q is activated following
21 the completion of the multiplexer cycle, the Keys-Released
22 signal from gate 41 is produced to clear the State flip flop
23 and place it in the Chord-Being-Formed state. Gate 27 is
24 now conditioned so that it can generate the next chord
Completed signal when the first key of the next chord is
26 released. Accordingly, in FIGURE 5.3B, the electronic
27 recognition of any pressed chord (which is recognized by
28 generating a CHORD PRESENT SIGNAL) cannot be provided until
29 all fingers are released from the last chord prior to the
pressing of the next chord.
D-PO9-74-030 -48-
S~8~7
1 5.~ Special Chord Circuits
2 The Specia~ C!lord Circuits are sho~ln in FIGUR~ 5.4~1.
3 They receive each ]ceyboard word from t]~e Chord Detec-tor in
4 FIGUR~ 5.3-1 ~nd determine whether the currently pressed
chord is a regular chord or a special chord. I~ the current
6 chord is a regular chord, the Regular Chord Detec-tor is
7 notified by a REGCIIORD signal, that it sl-ould do the
8 decoding. If it is determined to be a special chord, it
9 causes the special word (up to 8 characters stored in the
Special Word Generator in FIGURE 5.4-1) to be outputted
11 as the keyboard characters.
12 In the Special Chord Circuits, this determination is
13 indicated by one of two output signals, REGCHORD (i.e.
14 regular chord) or SPECHORD (i.e. special chord); these
signals are gated only for keyboard words indicated as
16 valid by the CHORD PRESENT signal. The keyboard bits are
17 compared to the special chord bits stored in the Special
18 Chord Register to determine if they represent the special
19 chord. If so, the keyboard is caused to output the
special word stored in the Special Word Register in
21 FIGURE 5.5-1. But, if the keyboard bits are determined
22 not to be the spQcial chord, it is thereby determined to
23 be a regular chord, which is to be decoded by the Regular
24 Chord Decoder in FIGURE 5.6-1.
The Special Chord Circuits in FIGURE 5.~-1 are able
26 to accept and store a new special chord at any time. The
27 special chord is stored in à 16-bit shift register, called
28 the Special Chord Register. A Use/Load flip flop controls
D-PO9-74-030 -49-
~V8~ '7
1 whether the keyboard bits are being compared to a previously
2 stored special chord, or are being inputted as a new
3 special chord. To do this, the tlip-flop opposite outputs
4 Q and Q control gates 201 and 202. Gate 201 recirculates the
bits previously stored in the Special Chord Register, while
6 they are being compared to the keyboard word by Exclusive-OR
7 circuit 203. Gate 202 loads the keyboard bits into the special
8 chord register where they become the new special chord. The
9 Use/Load flip flop is set to Load state by momentarily
pushing down the Special Chord pushbutton. While the push
11 button is pressed down, each successive group of KEYBOARD
12 BITS is stored into the special chord register. After the
13 push button is released, the Chord Detector detects the
14 next chord and provides a Chord Present signal, which
resets the flip-flop to enable gate 201 and disable gate 202.
16 Thereafter the stored chord is used as the special chord
17 until the Special Chord pushbutton is pushed again.
18 If the push button is pressed without pressing any chord,
19 all zeros are loaded, resulting in there not being any
special chord available for use.
21 After a special chord has been loaded and the USE/LOAD
22 flip flop has returned to the USE state, Exclusive-OR circuit
230 203 compares all KEYBOARD BITS to the bits in the Special
24 Chord register. If any bit is different, the keyboard word
does not represent the special chord, and are thereby presumed
26 to represent a regular chord, which produces a signal at the
27 output of Exclusive-OR circuit 203 that sets the Regular
28 Chord flip flop. After the SHIFT pulses for each set of
29 keyboard bits are completed, a CHORD PRESENT signal appears
D-PO9-74-030 -50-
1C~854~7
1 which ena~les the REGCilORD signal to pass the Q output,
2 or enables a SPECI-IORD signal to pass the ~ output of the
3 Regular Chord flip flop.
4 The Regular Chord flip flop s preset by the next
RESET pulse.
6 5.5 Special Word Generator
7 The Special Word Generator is shown in FIGURE 5.5-1.
8 The Special Word switch shown in FIGURE 3-1 determines
9 whether a special word is being LOADED, or whether a
previously loaded special word is being USED.
11 When the Special Word switch is set to USE and the
12 Special Chord circuits provide a SPECHORD signal, an
13 eight byte special word currently stored in a Special Word
14 register is outputted by the keyboard.
When the Special Word switch is set to LOAD, the
16 Special Word register is reset; and as long as the switch
17 is in LOAD position, the Decoded Characters output from
18 the Regular Chord decoder in FIGURE 5.6-1 is inputted
19 into the Special Word register, thus reloading it. When
the switch is moved back to USE position, the last eight
21 characters from the Regular Chord Decoder inputted to the
22 Special Word register remain stored in their inputted
23 sequence as the new special word, which may now be used.
24 5.5.1 Special Word Load Control
The action of the Special Word Generator is controlled
26 by a Preload flip flop and a Load flip flop, which are
27 controlled by the Special Word switch and the RESET pulse
28 provided from FIGURE 5.2-1. When the switch is in the USE
D-PO9-74-030 -51-
1(~854Br~
position, the Preload flip flop and the Load flip flop are
2 both maintained in reset state. When the switch is positioned
3 to LOAD, the next RESET pulse turns on the Preload flip
4 flop to enable ~ate 301. The followin~ received RESET
pulses pass through gate 301 to become LOAD RESET pulses,
6 which continue until the switch is changed back to USE
7 position. The next RESET pulse after the switch is changed
8 back to USE position turns off the Preload flip flop which
9 terminates the LOAD RESET pulses.
The J-K inputs of the Load flip flop are connected
11 to the J-K inputs of the Preload flip flop, and hence they
12 are controlled together. mus, when the switch is set to
13 LOAD, the first LOAD RESET pulse in a group passes through
14 gate 301 and turns on the Load flip flop. The Load flip
flop then provides the LOAD signal from output Q to enable
16 gate 303 when it is on and provides the USE signal from
17 its output Q to disable gates 302 and 304. The Load flip
18 flop is turned off by the first LOAD RESET pulse after
19 the switch is changed to USE position to then enable
gates 302 and 304.
21 When gate 303 is enahled, the decoded characters
22 (resulting from pressing chords while the Special Word
23 switch is in Load position) are loaded into the Special
24 Word register.
A Special Word Counter controls the eight character
26 cycle of the Special Word Register during both USE and
27 LOAD operations. If the switch is set to USE, the special
28 word register, a 64-bit shift register, is set to recirculate
D-PO9-74-030 --52--
~(~854~
through gate304 while the special word counter and gate
2 307 are providing S~IFT pulses.
3 The USE operation is controlled by the Special Chord
4 Circuits when it detects a special chord and provides the
SPECHORD signal to start the action. The Special Word
6 Counter then counts out 64 COMPARE pulses via gate 306 and
7 stops at count 64 which disables gates 306 and 308 via the
8 inverter. It remains at count 64 until it gets reset to
9 zero by the next RESET pulse, from which it can begin another
cycle. These 64 pulses are applied through gate 307 to
11 recirculate the Special Word register which then outputs
12 the SPECIAL WORD CHARACTERS to the Output Control in
13 FIGURE 5.7-1. Gate 308 passes 64 PCOUNT pulses to the
14 Output Control in FIGURE 5. 7-1 as SPECIAL SYNCH OUT signal.
5.6 Overall Description
16 5. 6.1 Overall Description
17 The 16 bit positions in each keyboard word directly
18 correspond to the thumb and finger keys in the chord
19 currently being pressed. The circuits in the Regular Chord
Decoder generate and output the characters represented by
21 the keyboard word. The bit positions in the keyboard word
22 are labeled:
23 (0) (1) (2) (3) (4) (5) (6) (7) (8) (9) (A) (B) (C) (D) (E) (F)
24
Table 1 Word Bit Positions, and Cable Wire Labels
26 Bit positions (0) and (1) are always "0" state, and the
27 fourteen bit positions (2) through (F) correspond to the keys
28 on the keyboard, and are shown in parenthesis on the keys in
D-PO9-74-030 -53-
~V85~7
1 Figures 3-5 and 3-6. A bi-t position state of "1" indicates
2 that the corresponding key is pressed and a "0" stc~te indicates
3 it is not pressed. These bit position labels are also used
4 to label the cables from the respective key switches S in
Figure 4-2 since each can be identified by these labels. As
6 may be seen in Figures 3-5 and 3-6, the key locations on the
7 keyboard are as follows:
8 (6 ) (8) (A) tC) 1E)
9 Fingex Keys
(7)(9)(B)(D)(F)
11 Thumb Keys (2)(3)(4)(5)
12 Table 2 Key Location Arrangement
13 The first stage of decoding the chords is to determine
14 which finger positions have been pressed by examining the
signals for the finger keys (6) through (F). To do this,
16 the finger bit positions (6) through (F) in the keyboard
17 word are examined in five overlapping subgroups representing
18 the respective five windows, Wl through W5, which are shown
19 in Figure 3-6. The data that is observed through a single
window indicates whether the operator pressed any one of
21 the six finger positions observable through that window.
22 Each window is represented by four keys which are
23 respectively represented by four keyword bit positions that
24 are shown in parenthesis on the finger keys. Note that the
non-existent two keys in window 5 are not in the keyboard
26 word but are presumed to have permanent zero states in its
27 3rd and 4th bit positions. The windows are represented in
28 Table 3 as follows:
29 Window Window Bit Positions
. .
Wl (6~,(7~,(8),(9)
31 W2 (8),(9),(A),(B)
D-PO9-74-030 -54-
~98548 ,~
1 W3 (A),~B),(C),(D)
2 ~14 (C),(D),(E),(F),
3 W5 (E),~F),(~),(~)
4 Table 3 ~indow Bit Positions in Keyboard Word
A single finger can press a combination comprising
6 1, 2 or 4 keys in any window, which combination is identified
7 as a single finger position on the keyboard. There are 27
8 single finger positions which correspond directly to the
9 characters in any alphabet/case on the finger keyboard.
The single finger positions are labeled in brackets in
11 Figure 3-6, and they are as follows:
12 [1] [4] [7] [A~ [D] [10] [13] [16] tl9]
13 [2] [5] [8] [B] [R] [113 [14] [17] [lA]
14 [3] [6] [9] [C] [F] [12] [15] [18] [lB]
Table 4 Finger Position Labels
16 Ten of these single finger positions in Table 4 press
17 a single key, and they are positions [1], [3], [7], ~9], [D~,
18 [F], [13], [15], [19] and ~lB]. The other 17 single finger
19 positions press two or four keys.
The decoding process for a valid keyboard word (signalled
21 by a CHORD PRESENT Signal) decodes its window suhgroups
22 beginning with window 1 and ending with window 5. In any
23 window (except window 5), a single finger can press any of
24 nine possible key combinations indicated by the 9 different
finger positions in each such window. IIowever, part of the
26 data for the rightmost three finger positions in each of
27 windows Wl-W4 are found in the next window. For example,
28 window 1 in Figure 3-6 may indicate no finger position or
D-PO9-74-030 -55-
~.V~4~7
1 One of finger positions [l], [2], [3], [4], [5], [6], [7~,
2 [8J, [9] of which the last -three finger positions [7], [B3,
3 [9] are also three finger positions in ne~t window 2.
4 Since some of the data required to iclentify the last three
finger positions not found in this window, the decoding is
6 assigned ~o the next window. This leaves each window with
7 six decodable finger positions except W5 which has three
8 decodable finger positions. This accounts for the total
9 of 27 finger positions on the keyboard, which correspond
to respective characters in each alphabet in Figure 3-2,
ll 3-3, or 3-4.
12 Therefore, a four ~it code represents the four key
13 positions for each finger position in each window. These
14 finger position codes are easily determined by an inspection
of Figure 3-6, and they are tabulated in the following
16 Table 4A:
D-PO9-74-030 -56-
~8s48r7~
1 Table 4A - 4-Bit Window Codes
2 Finger
3 Position Wl W2 W3 W4 W5
4 (6)(7)(8)(9) (8)(9)(A)(B) (A)(B)(C)(D) (C)(D)(E)(F) (E)(F)(O (0)
None 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6 (1) 1 0 0 0
7 (2) 1 1 0 0
8 (3) 0 1 0 0
9 (4) 1 0 1 0
(5)
11 (6) 0 1 0
12 (7) 0 0 1 0 1 0 0 0
13 (8) 0 0 1 1 1 1 0 0
14 (9) 0 0 0 1 0 1 0 0
(A) 1 0 1 0
16 (B)
17 (C) 0 1 0
18 (D) 0 0 1 0 1 0 0 0
19 (E) 0 0 1 1 1 1 0 0
(F) 0 0 0 1 0 1 0 0
21 (10) 1 0 1 0
22 (11) 1 1 1 1
23 (12) 0 1 0
24 (13) 0 0 1 0 1 0 0 0
(14) 0 0 1 1 1 1 0 0
26 (15) 0 0 0 1 0 1 0 0
27 (16) 1 0 1 0
28 (17)
29 (18) 0 1 0
(19) 0 0 1 0 1 0 0 0
31 (lA) 0 0 1 1 1 1 0 0
32 (lB) 0 0 0 1 0 1 0 0
P09740~~ 57
1~85'~t~7
1 Observation of Table 4A will show that: (1) the codes
2 repeat for each window, except window 5 which has only f
3 three codes, (2) the last three codes of each of windows Wl-W4
4 identify three finger positions also coded for the next
window, and (3) the three overlapping codes all have 00 in
6 its first two bit positions, (4) the first six codes for each
7 window after the all zero code do not have 00 in their
8 first two bit positions, and (5) the first six codes are
9 identical for each of the five windows, except that window
5 uses only the first three of these codes. Only the first
11 six codes are assigned for decoding at each window, since
12 the finger positions for the last three will be decoded by
13 the first three codes of the next window.
14 A single chord may be formed with up to four finger
positions, which are simultaneously coded in a keyboard word.
16 The Regular Chord Decoder scans the keyboard word to
17 detect the chord's finger positions. To do this, the
18 decoder systematically detects each window subgroup. The
19 Regular Chord Decoder in the described embodiment begins
by detecting any of the six detectable finger positions in
21 the window 1 subgroup and repeats this detection process at
22 each of the other window subgroups.
23 Up to eight alphabets/cases can be permanently recorded
24 in the Character Memory in which each alphabet/case does
not have over 32 characters. An eight bit address is used
26 to select each character from such Memory. The address
27 includes a 3 bit part which addresses the particular
28 alphabet/case selected by the thumb key depression(s),
D-PO9-74-030 -58-
S4~;7
1 and the re~ainin~ 5 bit part addresses one of the characters
2 selected by the fin~er key depression(s) comprising the
3 chord.
4 The thumb key bit positions (2) throu~h (5) in the
keyboard word are used in generating the three bit part
6 of the address, and keyboard word bits (6) through ~F)
7 are used to ~enerate the 5 bit part of the address.
8 In this manner, the pressed finger positions in a chord
9 get translated into a character in the alphabet selected
by the thumb and finger positionsO The first or last
11 finger position in a chord may be translated into two
12 characters in some alphabets/case. For example, the
13 first character in a chord may be capitalized and preceded
14 by a space in one case, or it may be uncapitalized and
not preceeded by a space in another case.
16 5 6 2 Window Bit Decoder
17 The process of decoding window bits is now discussed
18 in detail. The first four bits 6, 7, 8, 9 of the keyboard
19 word in the Finger Bit register are outputted as window 1
at output terminals QA, QB, QC, QD to the Window Decoder
21 Memory and each next window is outputted by a 2 bit
22 position left shift of the remaining finger bits ln
23 the Finger Bit Register. The current window output QA, QB~
24 QC, QD is the 4 bit window code which the Window Decoder
Memory translates into a 3 bit code Y3, Y4, Y5 which is
26 provided at the Memory output to the Comparator inputs Al,
27 A2,A3. Also, this Memory provides two Reload bit outputs
PO9-74-030 -59-
1~38~4~7
1 Y1, Y2 back to the Finger sit register inputs C, D, to set
2 to zero each 1 blt at QC, QD which was significant in
3 decoding the current window, so that i-t canno-t be used in
4 decoding the next window.
Table 5, which follows, relates the six-teen 4-Bit
6 Window codes Q~, QB, QC, QD to a resulting 3 bit code Y3,
7 Y4, Y5 provided to the Comparator. It also relates the
8 4-Bit Window codes to Reload bits Yl, Y2, which reset to
9 zero each one bi. in QC, QD which is significant to the
current window but must not appear in the next window~
11 The 3 bit code is used to represent the six detectable
12 finger positions at each of windows Wl-W4 and the three
13 detectable positions at W5 discussed in connection with
14 Table 4A. Table 5 shows how the 3 bit codes correspond to
the 4 bit codes. The Window Bit Significance Column groups
16 together the different 4 bit codes which have the same
17 3-bit code. Thus, the 3 bit code eliminates the effect of
18 certain bits in the 4 bit code that are not significant
19 to the detection of the current window.
D-PO9-74-030 -60-
~8S14~7
1 Window
2 Decoder Finger
3 Step Window Code Memory Positions
4 Counter Window Bit In Finger Output to Represented Reload
ount Significance Bit Register Comparator By Code Bit _
6 QA QB QC QD QA QB QC QD Y3 Y4 Y5 W1 W2 W3 W4 W5 Yl Y2
7 0 0 0 0 0 0 0 0 0
8 0 0 1 0 0 0 0 1 0
9 0 0 0 r r O 0 1 1 0 0 0
0 0 0 1 0 0 0 0 1
11 1 0 0 0 0 1 0 01 07 OD 13 19 0 0
12 2 d O O r 1 0 0 1 0 1 0 01 07 OD 13 0
13 l 1 0 0 0 1 1 02 08 OE 14 lA O O
14 3 d d r r 1 l l O O l l 02 08 OE 14 1 0
1 l 0 1 0 1 1 02 08 OE 14 0
16 0 1 0 0 1 0 0 03 09 OF 15 lB O O
17 4 0 d r O 0 1 1 0 l O 0 03 09 OF 15 1 0
18 1 0 l 0 1 0 1 04 OA 10 16 0 0
19 5 d O d r 1 0 1 1 1 0 1 04 OA 10 16 0
6 d d d d 1 1 1 1 1 1 0 05 OB 11 17 0 0
21 0 l O l l l 1 06 OC 12 18 0 0
22 7 0 d r d 0 1 1 1 1 1 1 06 OC 12 18 1 0
"
23 Table 5 - Action of Finger Memory and Comparator
974030 ~ 61
1~8548t7
1 Window Key
2 Window Bit Actuation Finger Positions
3 Significance Combinations Represented
4 QA QB QC QD W1 W2 W3 W4 W5
_
0 0 r r Or Or 00 00 none
6 Or 00 00 Or
7 d O O r dO dO 01 07 OD 13 19
8 00 Or
9 d d r r dO dr dO 02 08 OE 14 lA
dO dO dr
11 0 d r O 00 Or 03 09 OF 14 lB
12 dO dO
13 d O d r dd dd 04 OA 10 16
14 00 Or
d d d d dd 05 OB 11 17
16 dd
17 0 d r d 00 Or 06 OC 12 18
18 dd dd
19 Table 6 - Key Operations and Resulting Window Bit Codings
P0974030 61a
S48'7
1 The "Window Bit Significance" column shown in Tables
2 5 and 6 indicates which bits in the 4-bit code are significant
3 and which are not significant. The "Window ICey Actuation
4 Combination" column in Table 5 shows each of the sixteen
4 key window combinations, in which the key locations
6 relate to the bits in the 4-bit code as QA QC. Thus~
QB QD
7 Table 6 shows the sixteen different combinations that keys
8 can be pressed in any window and also shows the other columns
9 in Table 5 and the corresponding "Finger Positions" and
corresponding "Window Bit Significance" for each bit in the
11 current window. Thus, the 16 pressable combinations for a
12 4 key window are shown in the "Window Key Actuation Combinations"
13 column, in which the relative position for each of the four
14 keys in the window is shown by one of three symbols, 0, d or r
which have the following meaning:
16 0 key not depressed
17 d significant key depression, interpreted as a l bit
18 for decoding the current window
19 r ignored key for decoding the current window by
interpreting it as a 0 bit whether it is pressed
21 or not (the r key is significant in decoding the
22 next window).
23 The significant keys d are used in decoding the current
24 window, but once used, they should not be used again in
decoding the next window. The problem is that significant
26 keys d in bit positions QC, QD could appear as a one bit
27 in positions QA, QB in the next window where they would be
28 decoded again, unless something is done to prevent their
29 appearance in the next QA, QB. The Reload bits prevent
D-PO9-74-030 -6 ~
5~7
l ~he appearance of d blts in ~he next window by forcing them
2 to zero state in QC, QD in the current window.
3 ~lote that the first eleven 4-bit codes in Table 5
4 do not have any d keys in bit positions QC, QD and there-
fore have Reload bits Yl, Y2 which are identical to QC, QD
6 codes; hence their Reload bits do not chan~e their bit
7 pattern for QC, QD. However, the last of the 4-bit five
8 window codes in Table 5 have d keys in QC, QD. Thus,
9 the Reload bits Yl, Y2 for patterns 5, 6, 7 will have the
corresponding bit code QC, QD except that a zero bit is
11 substituted whenever a d bit existed.
12 In more detail, in the window subgroup QA, QB, QC, ~D
13 for windows Wl-W4, the last two bits QC, QD will again
14 appear as the QA, QB bits of the next window subgroup. It
will be noted in Table 5 tha~ in bit positions QC, QD
16 sometimes a bit is significant and sometimes it is not
17 significant. If it is not significant (i.e., r), it is
18 treated as a zero, regardless of its actual state, for
19 decoding the current window, but it is significant in the
decoding of the next window in which it becomes a d. If it
21 is significant (i.e. d), it is a l bit used in decoding the
22 current window; but it should not be used in decoding the
23 next window. To avoid use of a d key in the next window
24 after its use in decoding the current window, each d bit
in QC, QD is set to zero by a Reload bit. Therefore,
26 in detecting the next window, the 1 bits for d keys that
27 were used in the detection of the prior window were deleted,
28 i.e. set to 0, but any 1 bits that were not used (i.e. for
D-PO9-74-030 -63-
lV854~';'
l r keys) remain in the next window. This is accomplished
in FIGURE 5.6-lA by reload bit inputs C, D into the Finger
Bit Register from the window Decoder Memory. The Reload
bits are gated into Finger Bit register bit positions QC,
QD by an equal output from the Comparator, which occurs
when the current window detection is performed. Therefore,
the changing of the bits QC, QD in the Finger Bit Register
cannot affect the decoding of the current window, but only
the decoding of the next window. If no finger position is
detected in a window, no Reload bits are gated into the
Finger Bit Register. The Reload bits do not effect the
current windows bit positions QA, QB because they are only
used by the current window, and they will be shifted out
of the Finger Bit Register in the 2-bit shift that occurs
in positioning the next window for decoding.
5.6.3 The Major Components of The Regular Chord Decoder
-
The Regular Chord Decoder is shown in FIGURES 5.6-lA,
lB and lC.
In FIGURE 5.6-lA, the major components are: -
(a) Finger Bit Register (8 and 4 bit shift registers):
The 8 bit register output QH is serially coupled to the 4
bit register input L. Together they provide a 12 bit shift
register which initially receives and stores the last 12 bits,
i.e. bit 3-15, in the current keyboard word as they are
received from the Chord Detector under the timing of 16
NSHIFT pulses. The first bits, i.e. 0-3 of the keyboard
word are shifted into the Thumb Bit Register in FIGURE
5.6-lC from the output QA of the 4 bit shift register.
Then a preshift by a 2 bit shift left to these three
PO9-74-030 -64-
1 registers leaves thumb bits 2-5 in the Thum}) Bit Registerr
2 and finger bits 6-9 in the Finger Bit Register at its
3 outputs QD-QA to provide the window 1 four ~)its in parallel
4 to the Window Decoder Memory as the current window to be
decoded. Thereafter, each next window is presented for
6 decoding by shifting 2 bits left only the contents of the
7 Finger Bit Register That is, the Thumb Bit register outputs
8 remain static until all windows are decoded from the
g current keyboard word.
Parallel inpu-ts C, D, of the Finger Bit register
11 receive Reload bits Yl, Y2 from the Window Decoder Memory.
12 (The Reload bits reset to 0 each 1 bit which is common
13 with the next window if that bit is used in decoding the
14 current window. Thus, the Reload bits can only affect the
3rd and 4th bit positions in the current window. The
16 Reload bits permit each 1 bit in the finger bit positions
17 6-15 of a keyboard to contribute to the decoding of only
18 one respective character in the chord.)
19 (b) Window Decoder Memory ~8 x 32 Read-Only Memory):
Translates the current four window bits (being received
21 from the finger bit register) into a 3 bit finger position
22 code Y3, Y4, Y5 that defines a finger position related only
23 to the current window being decoded, and generates the 2
24 Reload bits. The 3 bit window code can be code 0 to
indicate no finger position was pressed in the current
26 window, or one of the codes 2 through 7 which indicate
27 the six finger position which can be decoded from the
28 current window. The 3 bit code is outputted to the
D-PO9-74-030 -65-
~3854~S7
1 Comparator. The two bit Reload si~nal Yl, Y2 is connected
2 back to the C, D inputs of the Finger Bit Re~ister to
3 eliminate any bit decoded for the current window from being
4 used in decoding the next window.
(c) Test Counter (4 stage binary counter):
6 It provides the overall clocking which controls the decoding
7 and outputting of the characters represented by each chord.
8 Its 16 output counts define 16 phases of operation for
9 each chord, which operation beings at count 0 and ends when
count 15 is incremented back to count 0. It is initially
11 preset to count 0, in which phase it remains until it
12 is set to count 1 by a REGCHORD signal from the Special
13 Chord Circuit, which starts the operations which handle the
14 current chord (REGCIIORD energizes a gate 301 and 320 in
FIGURE 5.6-lA that sets the counter to 1.) Once set to
16 count 1, the Test Counter synchronously cycles to count
17 15 and back to 0 under actuations from the ~tep Counter.
18 (The synchronous cycling of the Test Counter begins when
19 AND gate 316 is enabled by inverter 300 to pass a sequence
of PCOUNT pulses to the input of the step counter, which
21 then synchronously outputs carry pulses to the input of
22 the Test Counter and they stop when the Test Counter cycles
23 back to count 0, which drops the enabling output of
24 inverter 300.
(d) Step Counter (3 stage binary counter):
26 It provides 8 counts of subclocking within each count
27 (i.e. phase) of the Test Counter to control the electronic
28 operations within each clocking phase. For example, in
D-PO9-74-030 -66-
~08s4~3q
1 phase lr the step counter provides its first 2 pulses to
2 preshift the Finger Bit Register to position window 1,
3 and to position the thumb bits in the Thumb Bit Register.
4 In each next of phases 2-6, it preshifts the Finger Bit
Register to the next window. The remaining six subclock
6 pulses in each of phases 2-6 control the Comparator for
7 decoding the current windows flnger position code to detect
8 which one of the six permissible fin~er position codes it
g happens to be. These six subclock pulses also concurrently
increment the Finger Position Counter to provide a respective
11 six of the 27 finger position addresses for the Finger
12 Position Memory so that it can keep track of which of the
13 five windows the current window happens to be, and store
14 therein the detected code. ~In more detail, this is done
by sending each of step counts 2 through 7 to the Comparator;
16 the coding of counts 2-7 on Step Counter outputs QB, QC, QD
17 is the same as the six possible finger position codes
18 translated on outputs Y3,Y4,Y5 from the Window Decoder
19 Memory, and one of the step counts will be equal to the
current window code unless it is all zeros. ~ence, an
21 equal condition between a particular Test Count and the
22 output of the Window Decoder Memory signals the decoding
23 of the finger position for the current window to provide
24 an EQUALPULSE output. The same set of counts 2 through 7
are also sent to the Finger Position Counter to increment
26 it in a count-up direction during the decoding process.
27 Each sequence of step counts 2-7 increments the finger
28 position counter to address another set of six bit
29 positions in the Finger Position Memory corresponding to
D-PO9-74-030 -67
~8~4B~
1 the current window among the 27 finger positions, and an
2 EQUALPULSE sets to "1" the bit position corresponding
3 to the detected code for the respective window.
4 (e) Comparator :
Provides an EQUALPULSE output whenever its Test Counter input
6 Bl, B2, B3 hecomes equal to its input Al, A2, A3 (finger
7 position code) from the Window Decoder Memory to signal which
8 of the Step Counter subcycles 0 through 7 represents
9 the current finger position code. The EQUALPULSE output
is timed with the selected one of Test Counts 2 through 7.
11 The EQUALPULSE signal is provided to the Finger Position
12 Memory to set to 1 its currently addressed bit position
13 (of 27 bit positions), which represents the current
14 windows finger position to store the result of decoding the
current window.
16 In FIGURE 5.6-lB, the major components are:
17 (f) Position Flip Flop:
18 It is set during phase 7 if a space character is signalled by
19 the Y3 output of the Thumb Memory, and it may be set during
any of phases 8 through 15 in which a 1 bit is signalled by
21 the Y output of the Finger Position Memory. That Memory is
22 output scanned for 1 bits during phases 8 through 15. After
23 being set, the Position flip flop is reset at the beginning
24 of the next phase during the first Step count.
(g) Shift Flip Flop:
26 It is set by the same pulse that resets the Position flip
27 flop, which occurs only if the Position flip flop was set
28 by a space or a finger position being sensed in the Finger
D-PO9-74-030 -68-
~LV85~t8~
1 Position Memor~. Therefore, the Shift flip flop is set
2 only when a character is to be outputted. The setting
3 of the Shift flip flop is timed with the first Step count,
4 and its resetting is done during the eighth Step Count
of the same phase. Ilence, eight step counts occur
6 while it is set an~ they gate eight COMPARE pulses to
7 the Output Buffer to shift out the eight bits of the
8 character.
9 The Shift flip flop is reset by the CLEARS~-IIFT signal
which is a negative PCOUNT pulse that occurs at the very
11 end of step 7. This CLEARSHIFT signal goes to the clock
12 input of the Shift flip flop. Since the Shift flip flop
13 is now cleared, and since its output controls the
14 SHIFT/LOAD input of the shift register, the shift register
loads the next character when it gets the CLEARSHIFT
16 signal.
17 In FIGURE 5.6-lC, the major components are:
18 ~) Thumb Bit Register (4 bit shift register~:
19 It receives the thumb bits 2, 3, 4, 5 in the current keyboard
word from output QA of the Finger Bit Register during the
21 last two of the 16 NSHIFT pulses followed by a 2 bit
22 preshift (as explained for the Finger Bit Register). The
23 Thumb Bit Register statically stores the thumb bits
24 throughout the decode and character output operations for
the current chord.
26 (i) Finger-Position Memory (lX256 RAM):
27 The 2nd through 28th bit positions in the memory respectively
28 correspond to the 27 finger positions on the keyboard.
D-PO9-74-030 -69-
lV8S'~8 7
1 ~t the heginning of the chord detection process in
2 phase 0, its bits are all reset to zero state. ~uring
3 phases 2 through 7, those of bit positions with addresses
4 1 through 27 corresponding to the detected finger positions in
the current chord will be set to the one state to store the
6 results of the finger position detection. During phases
7 8 through 15, the one bit settings control the selection
8 of the output characters in the alphabet/case selected by
g the Thumb Bit Register outputs. In more detail, each
finger position in the current chord is detected by
11 the timing of an EQUALPULSE signal from the Comparator,
12 which is synchronized with the sequential addressing of
13 the Finger Position Memory by the Finger Position Counter,
14 in order to set a 1 bit precisely at each bit position
representing a detected finger position.
16 (j) Thumb Memory (32 x 8 read-only memory):
17 It translates five input bits (of which four bits A, B,
18 C, D are the thumb bits provided from the output of the
19 thumb bit register and bit E is the output of the Case
flip flop), which controls upper case for only the first
21 character of a chord. The Thumb Memory provides outputs
22 Yl, Y2 to select the required alphabet/case in the
23 Character Memory. The Thumb Memory also outputs a FIFO
24 signal which indicates whether the chord characters are
to be outputted in normal or reverse sequence. It further
26 outputs a C~ORDSPACE signal which indicates whether the
27 first character in the chord is to be preceded with a
28 blank character.
D-PO9-74-030 -70-
1i~385~7
1 (k) Fin~er Position Counter (8 position UP/DO~n~ shift
2 reglster :
3 It receives ~COUMT pulses controlled by the Step Counter,
4 which steps it through a count of six for each respective
window being decoded for a total of 27 step counts for each
6 keyboard word, i.e. counts 1-6 for window 1, cotmts 7-12
7 for window 2, counts 13-18 for window 3, counts 19~24 for
8 window 4, and counts 25-27 for window 5. It outputs five
9 bits for addressing in sequence each of 27 finger posltion
bits in the Finger Position Memory. The output sequence
11 of detected characters for the current chord is controlled
12 by the up or down Count direction; it counts up for the
13 from 1 to 27 normal output sequence, or it counts down from
14 27 to 1 for the reverse output sequence. The Thumb Memory
Output signal FIFO selects the direction of output sequence.
16 (1) First Character Flip Flop : This flip flop is
17 reset at the beginning of each phase by an NRESET pulse to
18 provide a Q output of "0" which disables NAND gate 361.
19 The flip flop is set by the first 1 bit scanned in
the Finger Position Memory during its output scan during
21 Phases 8-15. The first 1 bit represents the first
22 character to be outputted for the current chord. When
23 set, it provides a Q output of "1" which conditions NAND
24 gate 361 to set the Case Flip Flop at the beginning of
the next phase.
26 (m) Case Flip Flop: This flip flop, in combination
27 with the First Character flip flop and the bits in Thumb
28 Memory, controls the generation of an upper case character
29 as the first non-space character outputted for a chord;
D-PO9-74-030 -71-
l~ss~s7
1 any following characters in such a chord will be lower
2 case. This operation occurs when a Space Capital Low
3 Thumb position is pressed in a chord. The Case flip flop
4 is set during any of Phases 9-15 after the First Character
flip flop is set during the precedin~ Phase 8-14. Thus, if
6 the First Character flip flop is set, its output Q
7 conditions NAND gate 361 so that the PCOUNT pulse during
8 the first Step Count (i.e. FIRSTSTEP signal) activates
9 AND gate 362 and therefore NAIID gate 361 at the beginning
of the next phase to set the Case flip flop. Then its
11 output Q switches from 0 to 1 at the input E of the Thumb
12 Memory to switch its Y2 output to the A6 input of the
13 character Memory from 1 to 0 which then selects the lower
14 case output for any second and following characters in
the current chord.
16 (n) Character Memory (8 x 256 Read Only Memory~:
17 It is used during the keyboard output operation for the
18 current chord. It translates the decoded finger positions
19 (stored in the Finger Position Memory as one bit) into
the thumb-selected character set. The Character Memory
21 can store up to eight character sets (i.e. alphabets/cases)
22 because its addressing bits A5, A6, A7 can address up to
23 eight different alphabets/cases. However, in the
24 embodiment, four alphabets/cases are stored. The Yl and
Y2 outputs of Thumb Memory become the two address bits
26 A5 and A6 which select one of the four alphabet/cases.
27 Two address bits from the Thumb Memory select the
28 alphabet/case. Five address bits A0 through A4 select
D-PO9-74--030 --72--
~.V~ 7
1 the required character in the selected alphabet/case.
2 When a one bit is read from the position memory, the
3 selected character is read from the Character Memory.
4 (o) Output Buffer (8 bit shift register):
The Output Buffer is used with the Character Memory
6 to sequentially output the characters of the current
7 chord during the clock phases 8-15 after the decoding
8 of all of its finger positions during clock phases 2-7.
9 It receives each character as eight parallel bits from
the output of the Character Memory, and outputs each
11 received character serial by bit as the keyboard output.
12 5.6.3.1 Initial Condition for Certain Major Components
13 In every 5ms operation, the following registers in
14 the Regular Chord Decoder are set to zero by a RESET pulse
from FIGURE 5.2, or by some other means:
16 a) Case flip flop (0 until first character in a chord
17 has been found, then (1) in FIGURE 5.6-lC.
18 b) Finger Position Counter (scale of 32) in FIGURE
19 5.6-lC.
c) Step Counter (scale of 8) in FIGURE 5.6-lA.
21 d) Test Counter (scale of 16) in FIGURE 5.6-lA.
22 e) Position ~emory in FIGURE 5.6-lC.
23 In every sample period (e.g. 5ms), a keyboard word
24 is loaded into the Finger Bit register (in FIGURE 5.6-lA)
and the Thumb Bit register (in FIGURE 5.6-lC). These
26 come from the keyboard word received from the Keyboard Word
27 Generator in FIGURE 5.3-1. However, the received keyboard
28 word is not used until a REGCHORD signal arrives from
D-PO9-74-030 -73-
lV854~7
1 The special chord circuits in FIGURE 5.4-1 to indicate
the received keyboard word representing a regular chord
which was determined to be valid for decoding.
The REGCHORD signal starts a decoding operation when
it causes the Test Counter in FIGURE 5.6-lA to go from
0 to 1. As soon as the Test Counter is non-zero, the Step
Counter starts counting PCOUNT pulses. Carry outputs from
the Step Counter are counted by the Test Counter. When the
Test Counter reaches 0, indicating the completion of a
keyboard word, the decoding operation is complete and the
characters that the chord represents have been outputted
from the keyboard. The Regular Chord Decoder then waits
for the next REGCHORD signal to handle the next chord.
5.6.4 Electronic Phases of Handling Each Chord
The Test Counter controls sixteen test phases. Each
of the phases is represented by a different output count,
which are:
0 WAIT: Wait for a REGCHORD signal to indicate a
valid keyboard word has been generated. The
REGCHORD signal advances the Test Counter to
Phase 1.
1 START: Start a chord decode and output sequence by
advancing the Finger Position Counter to count
1.
PO9-74-030 -74-
~.~B548~
1 2 POSITIQ~im~ST: Decodes Finger Bit Register bi-ts
2 (6), (7), (8), (9) for window 1. There
3 are five POSITIOI~T~ST phases which
4 decode windows 1-5 respectively. One or none
of the six possible ~.ey combinations is
6 detected in each window. If a finger
7 position is decoded, a one bi-t is stored
8 in a corresponding bit position in the Finger
9 Position Memory to record the fact; the
bits in the Finger Position Memory are
11 sequentially assigned to the respective 27
12 finger positions. Thus, each of windows W1-W4
13 has a different group of addressable bits in
14 the Finger Position Memory, and window W5 has
the last three addressable bits. Six counts
16 from the Step Counter advance the Finger
17 Position Counter through each of the six
18 finger position tests in each window. Hence,
19 it advances from 0 to 6 at window 1.
3 POSITIONT~ST: Decodes bits (8), (9), (A),(B) in
21 window 2. The Finger Position Counter advances
22 the bit addresses from 6 to 12 in the Finger
23 Position Memory.
24 4 POSITIONTEST: Decodes bits ~A),(B),(C),(D) in window
3. The Finger Position Counter advances the
26 bit addresses from 12 to 18 in the Finger
27 Position Memory.
28
D-PO9-74-030 -75-
1V~3'54~7
1 5 POSITIONT~.ST: Decodes bits (C),(D),(E),(F) in window
2 4. The Finger Position Counter advances the
3 bit addresse~s from 18 to 2~ ln the Finger
4 Position Memory.
6 POSITIONTEST: Decodes bits (E), (F), (~ ) in window
6 5. Window 5 only has three tests because there
7 are only three combinations of the two keys in
8 window 5. The Finger Position Counter advances
9 the bit addresses from 24 to 27 in the Finger
Position ~lemory.
11 7 SPACE: If the thumb position generates the thu~b bits
12 0110, 0010, or 0011, a space character, i.e. a
13 blank (~), will preceed the first character
14 in the chord. These thumb bits cause the
Position flip flop to be set in FIGURE 516-lB,
16 to control the emission of a space character
17 in Phase 8 prior to the other chord characters.
18 If the Thumb chord is not 0001 or 0011, the
19 n-gram is not reversed. Therefore, in this
phase, the Finger Position Counter is set to
21 zero in preparation for reading out the
22 characters from left to right.
23 8 EMITCHAR: If the Position flip flop is set, then it
24 is reset, and the byte from Character ~lemory is
loaded into the Output Shift Register and shifted
26 out. In the part of the phase that follows reading
27 character memory, count the finger position
28 counter, addressing position Memory after each
29 count, until reading a one from Position ~emory,
D-PO9-74-030 -76-
~8~ 7
1 or, a~ter the sixth count, running out of time
2 in the phase. If a one is found, the finger
3 co~lnter stops ancl the position flip ~lop i.s
4 set. The final step in every EMI~CH~R nhase
is to read character memory wllich puts a
6 byte on its output lines whether or not it
7 is needed.
8 9 to 15 These phases are each an EMITCliAR phase
9 identical to phase 8. This guarantees that
all characters that were found in Phases 1-7
11 will be emitted since the ma~imum number of
12 characters that can be represented by a
13 regular chord is six~ e.g. a space followed
14 by five other characters.
5.6.5 Operation of Phases 2, 3, 4, 5 and 6
16 Phases 2 through 6 perform the window decoding operations
17 described in Section 5.6.2 "Window Bit Detection". In each
18 of Phases 2-6, an eight step count process decodes one of
19 the five windows in a valid keyboard word. During each of
Phases 2-6, the first two Step Counts, 0 and 1, are used to
21 shift the next window into the shift register outputs QA,
22 QB, QC and QD so that it can be decoded during the
23 remaining step counts 2-8 in the phase.
24 In Phase 2, during Step Counts 0 and 1, the Finger
Bit Register is shifted left two bits to eliminate the
26 first two dum~y zero bits in the keyboard word, leaving
27 only the keyboard word bits at bit positions (2), (3), (4),
D-PO9-7~-030 -77-
~6~854~7
1 ~5), (which are the window 1 bits) as the outputs QA, QB,
2 ~C, QD of the Finger Bit Register.
3 The window output is connected to the Window Decoder
4 Memory which translates the four bit code in the window
to a 3-bit code at its outputs Y3, Y4, Y5 which are
6 provided to the Comparator. During the next six
7 Step Counts 2 through 8, respectively, the Comparator
8 decodes the 3-bit code to determine if it represents
9 none or one of the six different finger positions. To
do this, the comparator compares code Y3, Y4, Y5 with the
11 set of Codes found in the 3-bit binary-coded output counts
12 from the Step Counter during step counts 2-8. Step
13 counts 2-6 provide a set of codes equal to the set of
14 six different finger position codes shown in Table 5.
An equal condition between a respective step count and
16 the Y3, Y4, Y5 code detects that the window contains the
17 respective step count. Hence, if step counts 2-8 are
18 considered on a scale of 1-6, respectively, the number
19 of any step count providing an equal condition is the
decoded number for that window.
21 Phase 3 repeats the process described for Phase 2,
22 except that its initial Step Counts 0 and 1 provide
23 the initial two bit left shift which moves window 2 into
24 decoding position. The same process is repeated in
Phases 4, 5 and 6 for the respective windows 3, 4 and 5.
26 The window decoding operation also uses the Finger
27 Position Memory. It contains a separate bit position
28 for each finger position, which are respectively addressed
D-PO9-74-030 -78-
~85'~7
1 by the output of the Finger Position Counter. Iihen any
2 one or more bits are set to 1 in the Finger Position
3 Memory, each 1 indicates that the respective finger
4 position was decoded. For example, if the bits at
addresses 7 and 18 are set to 1, then the 7th and 18th
6 finger positions were decoded.
7 The Finger Position Counter counts through a
8 scale of 32. It is incremented as the Step counter
9 counts through its six decoding counts 2-8. In other
words, the Finger Position Counter is advanced by
11 each Step count that is compared for a finger position,
12 and it is advanced through six counts for each window
13 for a total advance of 30 counts while decoding the five
14 windows in a keyboard word for the 27 finger positions.
The Finger Position Counter outputs five bits as
16 the address provided as inputs A, B, C, D, and E of
17 the Finger Position Memory to address each bit corres-
18 ponding to one of the 27 finger positions. The incre-
19 menting (or decrementing) counts to this counter are
provided through OR circuit 347 as a signal called
21 FINGERCOUNT.
22 Thus, whenever the comparator finds agreement
23 between the Step count and the output of the Window
24 Decoder Memory, it causes two things to happen:
1. It stores a 1 in the currently addressed bit
26 in the Finger Position Memory. This will later cause
27 a character to be read out.
D-PO9-74-030 -79-
~S1~8~
1 2. ~t also causes a pair of Reload bits from Window
2 Decoder Memory to be provided to inpu-ts C, D in the
3 Finger Bit Register.
4 5.6.6 Character Memory
A typical set of contents for Character Memory is
6 shown in Table 7, which illustrates four alphabets/cases
7 in columns 00, 01, 10 and 11.
8 FIN&ER A5, A6
POSITION A0 Al A2 A3 A4 00 01 10 11 Definitions
9 ---- ---- -- -- _ _
DEC HEX
11 0 0 0 0 0 ~ ~ b
12 [1] [1] 0 0 0 0 1 d D ¢
13 [2] [2] 0 0 0 1 0 t t & ATTN ATTENTION
14 [3] [3] 0 0 0 1 1 g G ! *
[4] [4] 0 0 1 0 0 b B @ CR CARRIAGE RETURN
16 [5] [5] 0 0 1 0 1 w W ' BS BACKSPACE
17 [6] [6] 0 0 1 1 0 c C " TAB TAB
18 [7] [7] 0 0 1 1 1 f F ¦ +
19 [8] [8] 0 1 0 0 0 p P NA NOT ASSI~NED
[9] [9] 0 1 0 0 1 m M ~ -
21 [10] [A] 0 1 0 1 0 s S ~ NA
22 [11] [B] 0 1 0 1 1 v V NA NA
23 [12] [C] 0 1 1 0 0 1 L # NA
24 [13~ [D] 0 1 1 0 1 n N
[14] [E] 0 1 1 1 0 h H ( NA
26 [15] [F] 0 1 1 1 1 r R ?
27 [16] [10] 1 0 0 0 0 k K NA NA
28 ~17] [11] 1 0 0 0 1 x X NA NA
29 [18] [12] 1 0 0 1 0 q Q NA NA
[19] [13] 1 0 0 1 1 j J = 7
31 L20] ~14] 1 0 1 0 0 z Z ~ 4
32 [21] [15] 1 0 1 0 1 y Y NA
33 [22] [16] 1 0 1 1 0 u U ~ 8
34 [23] [17] 1 0 1 1 1 ~ ~ > 5
[24] [18] 1 1 0 0 0 i I NA 2
36 [25] [19] 1 1 0 0 1 a A ; 9
37 [26] [lA] 1 1 0 1 0 e E : 6
38 [27] [lB] 1 1 0 1 1 o O , 3
39 1 1 1 0 0
1 1 1 0
41 1 1 1 1 0
42
43 Table 7 - Contents of Character Memory
44 The Character Memory is a read-only memory chip, and by
replacing the chip with another, it is possible to change
46 alphabets/cases.
D-PO9-74-030 -8~-
iV8~8~
1 The Character Memory is adclressed by bits A0, Al, A2,
2 A3, A4, A5, A6 of which A0-A4 are the outputs of the
3 Finger Position Counter, and A5, A6 are outputs of the
4 Thumb Memory. An address AO-A6 selects one character
in the Finger Position Memory in an alphabet/case
6 selected by address bits A5, A6 received from the Thumb
7 Memory.
8 The four codes for address bits A5, A6 are shown
9 in Table 7 as the headings of columns 00, 01, 10 and 11
which contain the names or graphic characters. These
11 graphic characters represent 8-bit bytes in the EBCDIC
12 code in the Memory. The column headed by 00 contains
13 the "lower case" of the English Alphabet. The column
14 headed by code 01 contains the "upper case" of the
English alphabet. The column headed by 10 is the
16 "special" alphabet; and the column headed by code 11
17 is called the "number" alphabet even though it also
18 contains control characters.
19 In each alphabet/case in the read-only memory, the
A0-A4 addresses 00000 and 10111 and 11111 are used to
21 hold the byte that represents a space, i.e. ~. The choice
22 among these addresses for a preceding space is determined
23 by whether the thumb keys call for a preceding space in
24 the chord and whether the characters in the chord are
to be emitted in left-to-right sequence (normal) or from
26 right-to-left sequence (reverse), or whether finger
27 position [23] is typing a space character.
D-PO9-74-030 -81-
1 5.6.7 Thumb Memory
2 The Thumb Memory in FIGURE 5.6-lC uses 32X4 bits of
3 read-only memory space. Its inputs D, C, B, A are the
4 four thumb bits from the thumb keys. Input E is the Q
output of -the Case flip flop. Together, inputs E, D, C,
6 B, A provide a 5-bit address to the Thumb Memory, which
7 then provides the corresponding content shown in Table 8
8 as its output, as follows:
9 THUMB THUMB MEMORY THUMB MEMORY
POSITION ADDRESS CONTENTS THUMB POSITION NAME
11 _ D C B A Yl Y2 Y3 Y4_ _ _ _ _ _ _
12 [0~ 0 0 0 0 0 0 0 0 1 Forward lower case
13 [7] 0 0 0 0 1 0 0 0 0 Reverse lower case
14 [5] 0 0 0 1 0 0 0 1 1 Space forward lower case
[6] 0 0 0 1 1 0 0 1 0 Space reverse lower case
16 [3] 0 0 1 0 0 0 1 0 1 Upper case
17 0 0 1 0 1 0 0 0 1 *
18 [4] 0 0 1 1 0 0 1 1 1 space cap low
19 0 0 1 1 1 0 0 0 1 *
[1] 0 1 0 0 0 1 0 0 1 special character alphabet
21 0 1 0 0 1 0 0 0 1 *
22 0 1 0 1 0 0 0 0 1 *
23 0 1 0 1 1 0 0 0 1 *
24 [2] 0 1 1 0 0 1 1 0 1 number alphabet
0 1 1 0 1 0 0 0 1 *
26 0 1 1 1 0 0 0 0 1 *
27 0 1 1 1 1 0 0 0 1 *
28 [0] 1 0 0 0 0 0 0 0 1 Forward lower case
29 [7] 1 0 0 0 1 0 0 0 0 Reverse lower case
[5] 1 0 0 1 0 0 0 1 1 Space forward lower case
31 [6] 1 0 0 1 1 0 0 1 0 Space reverse lower case
32 [3] 1 0 1 0 0 0 1 0 1 Upper case
33 1 0 1 0 1 0 0 0 1 *
34 [4] 1 0 1 1 0 0 0 1 1 Space cap low
1 0 1 1 1 0 0 0 1 *
36 [1] 1 1 0 0 0 1 0 0 1 Special character alphabet
37 1 1 0 0 1 0 0 0 1 *
38 1 1 0 1 0 0 0 0 1 *
39 1 1 0 1 1 0 0 0 1 *
[2] 1 1 1 0 0 1 1 0 1 Number alphabet
41 1 1 1 0 1 0 0 0 1 *
42 1 1 1 1 0 0 0 0 1 *
43 1 1 1 1 1 0 0 0 1 *
44 Table 8 - Contents of Thumb Memory
D-PO9-74-030 -82-
~8'~
1 Two output bits Yl, Y2 provide address bits A5, A6 to the
Character Memory to select one of four alphabets/cases
stored in the Character Memory. Another output bit Y3
from the Thumb Memory provides a signal called CHORDSPACE
which determines whether the chord is to be preceeded by a
space character. Another output bit Y4 from the Thumb
Memory provides a signal called FORWARD which controls the
output sequence of characters of the chord, i.e. whether
they are to be outputted in normal or reverse sequence.
The E bit in the address is logically significant
only for the single thumb position [4], called "SP. CAP.
LOW", which means "Space, Capital, then Lower Case".
Table 8 shows the thumb bit codes in its address columns
D, C, B, A in two places for thumb position [4], one place
with E being 0 and the other with E being 1. Note that
the Y2 bit in the content for the SP. CAP. LOW thumb
position changes from 1 to 0 when the E bit in the address
changes from 0 to 1. A change in the E bit is insignificant
for all other codes in Table 8, since their content codes
do not change when the E bit changes.
A case control operation is caused by the SP.CAP.LOW
thumb position [4] bit code 0110, which is found in the
D, C, B, A columns of the Thumb Memory Address in Table 8.
Initially, the E bit has a "0" state to provide a total
Thumb Memory Address of 00110, which in Table 8 selects
the Thumb Memory content Yl, Y2, Y3, Y4 of 0111. Later
when E is "1", the content Yl, Y2, Y3, Y4 is 0011. The
P09-74-030 -83-
87
1 difference is in the Y2 bit, which is also the A5 bit
2 in the Character Memory Address. (The Yl bit, which is
3 also the A5 bit in the Character Memory Address, does
4 not change when the ~ bit changes.) ~ow look at Table 7,
in which it will be seen that when the A5, A6 bits are 01,
6 (corresponding to Yl, Y2 when E is "0") the upper case
7 is selected; but when A5, A6 are 00 (corresponding to
8 Yl, Y2 when E is "1"), the lower case is selected.
91 The sequential control for the SP. CAP. LOW operation
uses a First Character flip flop and a case flip flop in
11 FIGURE 5.6-lC, in which both are initially cleared by an
12 NRESET pulse. The latter then provides a Q output "0"
13 as the E bit for the Thumb Memory to cause an upper
14 case character to be outputted by the Character Memory as
the first chord character when the first "1" bit is
16 scanned in the Finger Position Memory. Thus, the first
17 "1" bit scanned for a chord in the Finger Position
18 Memory provides a POSOUT signal which sets the First
19 Character flip flop. Its Q output then conditions NAND
gate 361, which is actuated by AND gate 362 at the
21 beginning of the next phase by a PCOUNT pulse during
22 Step Count 0, which then sets the case flip flop. Hence,
23 the first upper case character is addressed in the
24 Character Memory and outputted into the Output Buffer
during one phase, which is before the Case flip flop
26 sets E to "1" at the beginning of the next phase for
27 selecting lower case characters thereafter in the chord.
D-PO9-74-030 -84-
5i~87
1 The thumb key codes ~, B, C, D that are marked with
2 an asterisk in Table 8 will not occur in the proper
3 operation of the keyboard. If they are pressed, however,
4 they have been given the same meaning as pressing no
thumb keys at all, i.e. Thumb Memory Content 0001. which
6 provides the "forward lower case" output control for
7 the characters in the chord.
8 5 8 Control Signals of Regular Chord Decoder
9 FIGURES 5.6-2A and B show the timing of the control
signals. Not all of the signals are shown in FIGURE 5.6-2A
11 and B, and equations are provided below to include signals
12 that may not be shown.
13 The first four signals corlpARE~ PCOUNT, NCOUI~T, and
14 RESET are received from the Timing Signal Generator in
FIGURE 5.2-1.
16 SHIFT is received from the Keyboard Word Generator
17 in either 5.3-1 or 5.3A or 5.3B.
18 REGCHORD from FIGURE 5.4-1 signals that the current
19 keyboard word is valid and should be decoded by the
Regular Chord Decoder. It is generated by the Special
21 Chord Circuits in FIGURE 5.4-1 and has the same timing
22 as the CHORD PRESENT signal from the Keyboard Word
23 Generator.
24 Before attempting to read the next paragraphs 7 the
reader should have clearly in mind the description of
26 the operation of the Step Counter and Test Counter in
27 FIGURE 5.6-lA which were given previously in Section 5.6.3,
D-PO9-74-030 -85-
~.5~ 8'7
1 and the phases of testing which are described in Section
2 5.6.4. Thus, the Test Counter determines the overall
3 timing phases, and the Step Counter clocks the operations
4 within each phase.
SCB, SCC, and SCD are the three outputs of the Step
6 Counter which is stepped by eight PCOUNT pulses during
7 each of phases 1 through 15.
8 TCA, TCB, TCC and TCD are the four outputs of the
g Test Counter controlling the sixteen phases. While in
Phase 0, the system waits for a REGCHORD signal which
11 steps the Test Counter from Phase 0 to Phase 1 and
12 causes a sequence of PCOUNT pulses to step the Step
13 Counter. Thereafter, carries from the Step Counter at
14 its Count 7 step the Test Counter from Phase 1 to 15
and back to 0. When the Test Counter returns to Phase 0,
16 PCOUNT pulses are then blocked from input to the Step
17 Counter by AND gate 316 so that no carries are thereafter
18 provided to the Test Counter, and it hences stops at
19 PAase 0. That is, the REGTEST signal from inverter 300
inhibits gate 316 from passing PCOUNT pulses to the
21 Step Counter when the 0 count of the Test Counter is
22 detected by AND gate 302. From a practical circuit point
23 of view, the Test Counter increments on negative transitions
24 of outputs from OR circuit 320 which receives each SCD
signal (carry) and the output of AND circuit 301. Test
26 Counter incrementing is defined as:
27 SCDl/(-REGTEST®CHORD&PCOUNT)
28 Note 1: The / symbol is an 5R function, - is a NOT function,
29 and & is an AND function.
D-PO9-74-030 -86-
l~)B5~W7
Note 2: The - is regarded as being more tightly bound
2 to the symbol at it:s right than that symbol is
3 bound to anything else. The following truth
4 table illustrates t:he notation:
A BA & B A / B -A --A& B --(A& B)
6 0 0 0 0 1 0
7 0 1 0
8 1 0 0 1 0 0
9 1 1 1 1 0 0 0
REGTEST frominverter 300 enables gate 316 to
11 pass PCOUNT pulses while a regular chord is being
12 decoded, and it only inhibits the Test Counter when
13 it is 0. The output of inverter 300 and AND circuit
14 302 is defined as:
REGTEST = --(--TCA&--TCB&--TCC&--TCD)
16 To save space, four signals are shown together
17 in FIGURES 5.6-2A and B on one line with REGTEST. They
18 are all defined below.
19 5.6.8.1 Phase 1 Control
.
Phase 1 is initiated by the REGCHORD signal passing
21 through gate 301 and OR circuit 320 to increment the Test
22 Counter to count 1. This is permitted only during Phase 0
23 because gate 301 is onlv conditioned during Phase 0 by the
24 WAIT output of gate 302. Test Count 1 activates the
START signal from AND circuit 303, as follows:
26 START = --TCD&-TCC&--TCB&TCA
27 5.6.8.2 Phases 2-6 Control ::~
28 Phases 2 through 6 are controlled by the POSITIONTEST
29 signal from AND gate 305 and NAND gate 304, defined as
follows:
31 POSITIONTEST = --TCD&--(--TCC&--TCB)
D-PO9-74--030 -87-
i~54~37
1 The PosIlIoNTEsT signal is provided to an inverter 309
2 arld to AND gate 311. The inverter generates a PRESHIFT
3 signal used to preshift the first window into a decodable
4 position in the Finger Bit Register. AND gate 311
generates an ENABLECOMP signal. ENABLECOMP does two
6 things. It is applied through inverter 318 to the
7 Window Decoder Memory input G for controlling its 3-bit
8 code to the Comparator. ENABLECOMP is also applied to
9 the S0 input of the Finger Bit Register to control Reload
bits to the Finger Position Register on the next clock
11 pulse. Thus, ENABLECOMP is 1 while the five windows are
12 being decoded during step counts 2-7 in each of phases
13 2, 3, 4, 5 and 6. OR circuit 310 and AND gate 311 operate
14 as follows:
ENABLECOMP = POSITIONTEST&(SCC/SCD)
16 The keyboard bits are shifted in from the Keyboard
17 Word Generator with NSHIFT pulses, which are provided by
18 AND gate 330, defined as follows:
19 NSHIFT = NCOUNT & -(COMPARE ENABLE)
These signals are all normally positive "1" and the
21 pulses go to "0", because the 74194 shift register
22 circuit controls S0 and S1 can be changed only when the
23 clock is positive.
24 At the beginning of each decoding phase 2 through 6
there are two PRESHIFT pulses during Step counts 0 and 1.
26 These pulses bring the next window in place for decoding.
27 OR circuit 312 defines the PRESHIFT SIGNAL as follows:
28 PRESHIFT = SCC/SCD/NCOUNT/-POSITIONTEST
D-PO9-74-030 -88-
iOB5487
1 The first two of the 16 bits in a word are not
significant, they are dummy bit positions which are always
"0". In Phase 2, the PRESHIFT pulses move the first -two
non-significant bit positions out to leave the first four
significant bits available at QA, ~)B, QC andQD for decoding
the first window.
Notice also that the pair of PRESHIFT pulses from OR
312 in Phase 2 also shifts the Thumb Bit Register by
providing THUMBSHIFT from AND 331 to position the thumb
bits in the Thumb Bit Register for decoding.
The Equal (=) signal output of the Comparator occurs
when the Step Counter output equals the Window Decoder
Memory output during Phases 2-6. The (=) output of the
Window Decoder Memory activates OR circuit 313 to provide
an EQUALPULSE signal provided from AND gate 313 which
indicates as a negative-going pulse that a finger position
has been found. It is defined as:
EQUALPULSE = -EQUAL/NCOUNT
An AND gate 314 generates a REGSHIFT signal which
is shown in FIGURE 5.6.2. It is defined as:
REGSHIFT = NSHIFT & PRESHIFT & EQUALPULSE
The shift pulses of REGSHIFT are applied only to the
74194 part of the Finger Bit Register since it must not
receive EQUALPULSE. Only the NSHIFT pulses are applied
to the Thumb Register.
In FIGURE 5.6-lB, a DIRECTION signal is the output
of OR circuit 341, which is used to control the direction
of counting of the Finger Position Counter. It counts up
PO9-74-030 -89-
~8S~87
1 during Phases 2-7, bu-t it may count up or count down
2 during th~ emit Phases 8-15 as controlled by the ~~4
3 output of the Thumb Bit Register. If the Y4 output
4 is 0, it indicates that the characters are to be read
out in reverse order, i.e. DOWN, o-therwise it must count
6 UP. OR circuit 341 defines the DIRECTION signal as
7 ~ollows:
8 DIRECTION = -TCD/FORWARD
g AND gates 342 and 343 control whether input pulses
to the Finger Position Counter will cause it to eount
11 UP or DOWN. The TESTCOUNT signal from AlID 317 in FIGURE
12 5.6-lA controls the number of pulses to be counted by
13 the Finger Position Counter, which are six pulses during
14 eaeh of Phases 1 through 6. TESTCOUNT is generated by
AND gate 316l OR eireuit 310 and AND eireuit 317, as
i 16 follows:
17 TESTCOUNT = PCOUNT®TEST&(SCC/SCD)&POSITIONTEST
18 The deteetion of a finger position oeeurs when a
19 one is stored in the Finger Position Memory in FIGURE
5.6-lC when EQUALPULSE goes negative. This signal is applied
21 to the WE (Write Enable) input of the 74S200, Finger Position
22 Memory by AND gate 352 in FIGURE 5.6-lB whieh provides
23 the WRITENABLE signal as follows:
24 WRITENABLE = ZEROWRITE&EQUALPULSE
5.6.8.3 Phase 7 Control
26 Phase 7 deeodes any spaee eharacter whieh is to preeeed
27 the eharacters outputted for the ehord, and detects the
28 output sequenee for the ehord characters. This oeeurs
D-PO9-74-030 -90-
~yl5~7
1 for the three thumb positions [4], [5] and [6]. Phase 7
2 is signalled by the SPACETIME output of AND gate 306 in
3 FIGURE 5.6-LA, defined as follows:
4 SPACETIME = -TCD&TCC&TCB&TCA
The thumb positions [4], [5], and [6] cause the Y3 output
6 of the Thumb Memory, called CHORDSPACE, to be 1 and it is
7 provided t~ NAND 361, AND 362 in FIGURE 5.6-lB to set
8 the POSITION flip flop with the following output signal:
9 SETPOS = -(CHORDSPACE&SPACETIME)&POSOUT
The output Q of the Position flip flop provides the POSFLIP
11 output to AND 363.
12 The output character sequence is controlled by the
13 thumb position bits. If the thumb position bits are not
14 0001 or 0011, i.e. not reverse thumb positions [7] or [6],
then the Y4 output of the Thumb Memory is FORWARD, which
16 is 1 to signal the normal output sequence. In this
17 case, the Finger Position Counter must be cleared by
18 the CLEARFINGER output of AND 351 in FIGURE 5.6-lB, as
19 follows:
CLEARFINGER = FIRSTSTEP&SPACETIME&FORWARD&COMPARE
21 When cleared, the Finger Position Counter is set to its
22 0 count output.
23 5.6.8.4 Phases 8-15 Control
24 The chord finger positions which were decoded
and stored in the Finger Position Memory during Phase 2
26 through 7 are translated to characters and outputted from
27 the keyboard during Phases 8 through 15, which occur during
28 the TCD signal from output QD of the Test Counter. If
D-PO9-74-030 -91-
~ !3S4~7
a preceding space character was decoded, the Position
flip flop was set in Phase 7. Then, a compare pulse at
the beginning of the Phase 8 loads the space byte from the
Character Memory into the output Buffer, clears the Position
flip flop, and sets the Shift flip flop. This is done
by the FINDPOS output of AND gate 363 during the Step
count 0 of Phase 8, defined as follows:
FIRSTSTEP = -(SCB/SCC/SCD) = Step Count 0
FINDPOS = COMPARE&FIRSTSTEP&TCD&POSFLIP
The Shift flip flop in FIGURE 5.6-lB controls the
shift/load input of the Output Buffer in FIGURE 5.6-lC.
When the Shift flip flop is set, it outputs the SHIFTFLIP
signal to AND gate 364, which then enables the Regular
Decoder SYNCHOUT signal:
SYNCHOUT = COMPARE&TCD&SHIFTFLIP
The SYNCHOUT signal shifts the Output shift register and
also goes to the Output Control in FIGURE 5.7-1.
The last step count 7 in each Phase 8-15 clears the
Shift flip flop from the output of AND 366, and its invert,
20 called CLEARSHIFT, controls the Output Buffer to the next
byte from the Character Memory. AND gate 366 therefore
provides:
CLEARSHIFT = -(TCD&LASTSTEP&PCOUNT)
The CS signal from NOR circuit 323 in FIGURE 5.6-lA
enables the Character Memory to read a byte during Step
counts 7 and 0. The CS pulse is 4 microseconds, and a Step
count pulse is 2 microseconds long. During the CS pulse,
the Memory settles and the output can be read during
Step Count 0 of the next phase.
PO9-74-030 -92- -
54~7
1The CS signal is provided during Step counts 1-6.
It and its component signals are defined as follows:
LASTSTEP = SCB~SCC6SCD
FIRSTSTEP = -(SCB/SCC/SCD)
CS = -(FIRSTSTEP/LASTSTEP)
During each of Phases 8-15, up to six bit positions
in the Finger Position Memory are scanned. The scan
continues during each of Phases 8-15 as long as the bits
are sensed in zero state. That is during any of Phases
108-15, the scan stops at the first 1 bit sensed. The 1
bit is set to zero at the end of the phase during the
Step count 7 before the scan continues. The scan starts
again for the next phase at the next bit position. The
reset to zero for each 1 bit prepares the Finger Position
Memory for the next chord decoding.
In more detail to perform the scan, the Finger Position
counter is incremented (up) or decremented (down) by up
to six SCAN pulses (synchronized by Step Counts 1-6 and
PCOUNT pulses). But this sequence of up to six pulses is
stopped by the setting of the Position flip flop upon the
sensing of a 1 bit at the currently scanned addressed
location in the Finger Position Memory. At the end of each
Phase 8-15 during Step count 7, the scan is moved to the next
memory bit position, after the last bit position is reset
by the WRITENABLE signal, and the MEMENABLE signal from
AND gate 372.
Thus, a SCAN pulse is provided during each of Step counts
1 through 6 within each Phase 8 through 15
PO9-74-030 -93-
85~7
1 until the Position flip flop is set during the phase or
until the sixth SCAN pulse is provided during step count
6. During each Step count 1-6 of the same phase, a PTEST
pulse reads the currently addressed bit position in the
Finger Position Memory, and if a 1 bit is found therein,
POSOUT sets the Position flip flop, and WRITENABLE during
Step count 7 resets the 1 bit. The PTEST signal is
provided by NAND gates 354, and the SCAN signal is provided
by AND gate 356, defined as follows:
PTEST = -(TCD&CS&COMPARE&-POSFLIP)
SCAN = TCD&CS&PCOUNT&-POSFLIP
The PTEST pulse enables the ME input of the Finger Position
Memory during the Step Counts 1-6 to read the bit before
the ZEROWRITE enables WE to erase the bit during Step
count 7.
5.6.8.5 Finger Position Counter Control
The Finger Position Counter counts in every phase.
Its operations may be summarized as follows:
FINGERCOUNT = START/TESTCOUNT/SPACECOUNT/SCAN/CLEARSHIFT
SPACECOUNT = PCOUNT&SPACETIMER&FIRSTSTEP
It also can be reset during Phase 7 with CLEARFINGER, and
always is reset by a RESET pulse.
CLEARFINGER = SPACETIME&FIRSTSTEP&FORWARD&COMPARE
_.6.8 6 Finger Position Memory
This is a 256Xl bit random access memory which is
used to record, with a 1, the discovery of each finger
PO9-74-030 -94-
10~5~7
1 position decoded during Phases 2-6. It is read and reset
during Phases 8-15 and, whenever it produces a 1, a
character is outputted.
The Memory has Write Enable (WE) and Memory Enable
~ME) inputs which are each enabled by a negative signal,
i.e. down level. Gate 352 (in FIGURE 5.6-lB) and gate
372 (in FIGURE 5.6-lC) act as OR circuits because their
negative output is provided when any input is at its
down level. The controlling signals are defined as follows:
ZEROWRITE = -(TCD~LASTSTEP&COMPARE)
The PTEST and the EQUALPULSE are both negative-going
signals, so they are at their up levels when not providing
pulses.
WRITENABLE = ZEROWRITE/EQUALPULSE
MEMENABLE = WRITENABLE/PTEST
A PTEST pulse that enables the reading of a 1 bit gets
chopped off, as shown in FIGURE 5.6-3. The way this happens
is that when the PTEST enables the Finger Position Memory
to read and produce a 1 at its output Y which provides a
POSOUT signal through inverter 373 to AND 362 for setting
the Position flip flop, which then drops the NOT POSFLIP
signal to turn off the PTEST and SCAN signals from AND
circuits 354 and 356. This happens quickly enough to chop
off part of the PTEST pulse.
After the PTEST pulse is chopped off, the Finger
Position Memory is still sitting at the same address
because the SCAN pulses also have been ended at least
PO9-74-030 -95-
1~8S4~
1 by the Step count 6. A ZEROWRITE signal in Step 7 of
each Phase 8-15 writes a "0" in that bit position in
Position Memory whether that bit position has a "0" or
"1". Since the scan stopped at every "1", they are zll set
to "0" at the end of a scan of -the Memory. In this manner,
every 1 bit in the first 28 positions of the Finger Position
Memory gets detected, used, and changed to 0, and the
memory is made ready for its next chord.
The final thing that has to be done at the end of
each Phase 8-15 is that, after ZEROWRITE and before the
end of Step count 7, the Finger Position counter has to
be incremented by 1 to get ready for the next phase. This
is done with the last NOT CLEARSHIFT pulse from inverter
357, which is gated by the next PCOUNT pulse.
It should be noticed that the search for l's in
Finger Position Memory can go beyond the area where
detected finger positions are stored. This is harmless
as the Finger Position Counter gets reset to its zero
position by a RESET pulse so its output address is
initialized for the next chord regardless of any excess
scanning for the current chord.
5.7 Output Control
The output control is shown in FIGURE 5.7-1. It
accepts characters in serial-by-bit form and gates them
out with SYNCH OUT pulses, one for each bit of data from
either the Regular Chord Decoder or the Special Word circuits.
It also is gated by the REGCHORD AND SPECHORD signals.
If REGCHORD is 1, then SPECHORD is 0 during
PO9-74-030 -96-
1V85~87
1 Phases 1 through 15 (see FIGURE 5.6-2) and the Keyboard
Output characters are the decoded characters from the
Regular Chord Decoder. Otherwise, the Keyboard Output
Characters are the Special Word Characters.
5.8 Alternative Embodiments
The alternatives described in the following sections
occurred to the inventors during the design of the
embodiment and are described here to elucidate further
the scope of the invention.
5.8.1 Parallel vs Serial Logic
Parallel implementation for decoding all 14 keyboard
word bits can be done in parallel. However, fewer components
~esult in serially decoding the windows as is done in the
detailed embodiment with no restriction in speed in view
of human speed limitations.
5.8.2 Number of Finger Keys
A different number of finger keys could be used than
- the 2x5 array of keys. In particular, a 2x6 array of keys
seems very appropriate for European alphabets which have
things like umlauts so that the number of characters is
increased a little bit over the standard Roman alphabet.
Also, three rows of keys may be used instead of two rows.
This should be useful for some kinds of applications. The
choice of the 2x5 array in the present embodiment was
preferred as the simplest arrangement for typing English,
using the conventional alphabets.
5.8.3 Number of Thumb Keys
... . .
It would be easy to put in a fifth thumb key, but
four was preferred on the basis of simplicity. Also,
PO9-74-030 -97-
1~85~8~7
1 two rows of thumb keys may be provided but thumb control
~f quad-groups of keys is more difficult than finger
contro] due to the flat position of the thumb in relation
to the keys. If there were two rows of five thumb keys,
there would be 28 thumb positions instead of the 8 in
the present embodiment. This would provide much greater
power at the expense of increased difficulty of learning.
It will be possible to increase both the number of
finger keys and the number of thumb keys. Suppose there
were three rows of 6 finger keys and two rows of 5 thumb
keys. There would be somewhat fewer than 168,000 chords
that could be keyed with one hand. This is an obvious
application of the invention which could be used if an
appropriate need arose.
5.8.4 Different Use of Finger Positions and Thumb Positions
It is not essential to use the finger positions to
identify members of an alphabet and to use the thumb
postions to select among alphabets/cases. Instead, some
of the finger positions could select alphabets/cases and
some of the thumb positions could select character from
alphabets. There are a variety of alternatives of this
sort. The choice in the detailed embodiment is preferred
because of simplicity in structure and in ease of learning.
Other changes would be to use different alphabets
or to assign the alphabets to finger po~tions differently.
The assignment of letters to finger positions has been
optimized with respect to English and with respect to
PO9-74-030 -98-
~}854~7
1 the samples of English text that were experimentally
2 used. If the assignment were optimized with respect
3 to text of foreign language, the assignment would be
4 different.
5.8.5 Other Switch Mechanisms
6 The structure of each key may support it to go up
7 and down vertically in slides instead of being pivoted
8 on lever arms. Alternatively, the keys need not be
9 mechanically movable at all, but may be marked positions
in which the presence of a finger is sensed capacitively,
11 or the pressure of a finger on that position could
12 actuate some electrical property of the material under
13 neath when pressure is exerted, e.g. strain gauge.
14 5.8.6 Surfaces Of The Keys
lS Flat surfaces are shown and preferred due to
16 simplicity. However, there are many alternatives.
17 For example, a dish-shaped depression or a bump at each
18 finger position might be useful for guiding the finger
19 to the finger position. The angle between the thumb
key group and the finger key group, and their relative
21 heights, may be changed to conform to the different hand
22 structures.
23 5.8.7 Special Chords and Words
24 The embodiment shows a single special chord and a
special word of limited length. An obvious extension would
26 be to have a larger number or perhaps an unlimited
27 number of special chords, and longer or perhaps
28 unlimited maximum length for special words. For many
D-PO9-74-030 -99-
los~4~7
1 applications, this would be extremely attractive and
might become the primary method of slgnalling with a
keyboard.
5.8.8 Independent Meanings for Separate Chords
Instead of using several alphabets and selecting
among them, it would be possible to assign a distinct
meaning to each chord. For example, a chord could be
assigned to each of the several thousand characters
used in writing Chinese, then one could type Chinese
with one character per chord. Another such application
would be to assign a separate English word or word stem
or word ending to separate chords. Then one could get
merely one word per chord which would approximately
double the speed of typing.
While the invention has been particularly shown and
described with reference to the preferred embodiments
thereof, it will be understood by those skilled in the
art that the foregoing and other changes in form and
detail may be made therein without departing from the
spirit and scope of the invention.
What is claimed is:
PO9-74-030 -100-
