Note: Descriptions are shown in the official language in which they were submitted.
10~7ZS5
DISCLOSURE
The present invention pertains to a particular architecture of a
digitally programmable sampled-analog transversal filter whose transfer
function can be altered by digital means. The said filter circuit provides
good accuracy, ease of programming and a wide output dynamic range. In
particular, this architecture of the programmable filter allows considerable
saving of silicon real estate in an integrated circuit implementation.
The progress of semiconductor charge transfer device (CTD) technology
has made possible the implementation of transversal filters in analog form.
The primary advantages of CTD transversal filters are their real time
operation, inherent simplicity and low cost, and therefore, they have
applications in a myriad of signal processing requirements. However, the
major efforts, so far, were confined to implementing fixed coefficient CTD
transversal filters, where the weighting coefficients or the tap weights are
mask programmed, i.e. the tap weights cannot be changed once the filter is
fabricated. A versatile transversal filter should provide the capability
to alter the tap weights at the will of the users. Such a device has
enormous potential in applications that require real time programmability
of the filter tap weight coefficients, e.g. in match filtering, equalisa-
tion, adaptive filtering, echo cancelling in telephone systems, etc.
In a previous art on a variable tap weight programmable transversal
filter, the analog signal samples are held in capacitor storage sites and
the binary tap weights are rotated relative to the analog signal samples.
The multiplications between the tap weights and the analog signal samples
are performed in parallel using N number of multipliers for an N tap filter.
This approach is limited by inaccuracies, primarily because of the non-
uniform characteristics of the multipliers and other identical elements
across the integrated circuit chip. In addition, the relative motion of
the tap weights with respect to the analog signal gives rise to noise
components at the submultiples of the sampling frequency. These noise
components constitute a fixed pattern in the noise spectrum. Hence, they
are referred to as fixed pattern noise (FPN). This FPN limits the dynamic
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range of the filter. Therefore, the approach is not suitable in applica-
tions that require a wide dynamic range.
An object of the invention is the provision of a digitally programmable
analog transversal filter with wide output dynamic range and good accuracy
in the realization of the filter tap weight coefficients.
According to the present invention, a programmable analog transversal
filter comprises of a charge transfer device delay means having a plurality
of stages with a non-destructive readout mechanism at each of said stages; a
multiplying digital to analog conversion means to multiply a digital word
with the output of a charge transfer device delay stage and produce an analog
output; a serial summer network means to sum a finite series of pulse
amplitude modulated signals appearing at different times. In one embodiment
of the invention, a circuit configuration for serial summation of said
signals is provided.
In a further embodiment of the invention, a completely integrated
circuit configuration of a programmable transversal filter is provided. The
integrated circuit comprises of logic circuits to generate necessary clock
voltage waveforms; a differential input digital to analog converter circuit
to multiply an input signal sample with a digital word and to produce an
output that is independent of the applied input bias signal; a parallel-
input-serial-output charge coupled device delay line to perform a progressive
summation of the tap weighted signals.
A circuit configuration of a differential input multiplying digital
to analog converter, and a parallel input charge coupled device delay line
are additional embodiments of the present invention.
By way of example, embodiments of the invention will be described in
greater detail with reference to the drawings, where in:
Figure 1 is a schematic of the programmable transversal filter
illustrating the basic concept behind the approach;
Figure 2a is a detailed circuit configuration of the programmable filter
illustrating important circuit elements including the serial summer network;
Figure 2B is a graphical illustration of typical clock voltage waveforms
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required for the operation of the programmable transversal filter;
Figure 3a is a photograph illustrating the experimental results,
obtained by using the circuit configuration of Figure 2a, on the frequency
and noise spectra of a linear phase low pass filter;
Figure 3b is a photograph illustrating the experimental results,
obtained by using the circuit configuration of Figure 2a, on the frequency
and noise spectra of a linear phase band pass filter;
Figure 4 is an alternate circuit configuration of the programmable
filter which is also suitable for monolithic integrated circuit implementa-
tion;
Figure 5a is a circuit schematic of a differential input multiplying
digital to analog converter which removes the effect of input bias signal
from the output of the said converter,
Figure 5b is a graphic illustration of the relative timing positions
of different clock voltage waveforms required for proper operation of the
MDAC of Figure Sa;
Figure 6a is a schematic of a parallel-input charge coupled device
delay line which is an integral part of the filter configuration shown in
Figure 4i
Figure 6b is a graphic illustration of the relative timing positions
of the important clock voltage waveforms to illustrate the operation of the
circuit shown in Figure 6a in the context of the filter configuration
shown in Figure 4;
Figure 7a is a schematic of an echo canceller illustrating an application
of the programmable transversal filter;
Figure 7b is a schematic of a sliding discrete fourier transformer
illustratlng an application of the programmable transversal filter.
With reference now to the drawings, Figure 1 shows the basic organisa-
tion of the programmable analog transversal filter. The heart of the system
is a tapped analog charge transfer device (CTD) delay line 10 and a multiplying
digital to analog converter (MDAC) 12. During each clock period of the CTD
delay line, the analog signal sample at each tap position 11 is multiplied
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by the corresponding digital word representing a tap weight. For an N tap
filter, N number of multiplications are performed serially during each clock
period. The summation of the tap weighted signal samples is performed
serially in a summer network 14. The output from the summer is sampled
and held by a sample and hold circuit 16 to provide the results of a discrete
time convolution which is given by the following equation for causal signals:
N-l
Yk ~ xnhk_n (1 )
n=O
where, {xn} is the sequence of the input signal samples, {hn} is the tap
weight sequence and {hk n} represents the sequence {h n} which is shifted
by K samples. The output sequence {Yk} is the sum of a finite series
as shown in equation (1), in which hk n is zero for (k n) less than zero.
The operation of the said filter requires quantization of the tap weight
sequence into digital words which are sequentially presented to the input 13
of the MDAC. The MDAC being multiplexed amongst N tap positions, is operated
at N times the speed of the CTD delay line as is the serial summer network.
The possible sources of non-ideal behaviour in the said filter structure
are:
(i) tap weight errors, represented by an error sequence {n}
which primarily arises from the quantization of tap weights in
a limited number of digital bits,
(ii) offset variations, represented by a sequence {fn}~ f the
buffers 17 at the tap positions of the delay line, and
(iii) gain variations of the above mentioned buffer stages. This can
be represented by a sequence {(l~gn)} which denotes departures
from nominal unity gains of the buffer stages.
With the said error sources, the output of the filter, with reference
to equation (1) can be written as:
.~. .
2S5
N-l
Yk = ~ [(1 ~ 9n)Xn + fn~thk n + Ek-n)
n=O
N-1 N-l N-l
n~O Xnhk-n n~O XnEk-n n0 gnxnhk_n
N-l N-l N-l
no 9nXn~k-n n-O n k-n n-O n k-n (2)
where,
(i) the term ~xnhk n is the desired filter output,
(ii) the term ~XnEk n is due to tap weight errors which limits the
achievable stop band attenuation. This term is present in any
filter realization where the tap weights are represented by a
limited number of digital bits,
(iii) the term ~gnxnhk n produces an error output that is transfer
function dependent, and, therefore, will not limit the stop band
attenuation,
(iv) the error contribution due to the term ~Xn9nEk n is negligible,
since both sequences {gn} and {En} comprise of small numbers,
(v) for a set of fixed tap weights, and a sequence of stationary
random tap weight errors, the terms ~fnhk n and ~fnFk n only
add fixed offset to the output.
The important conclusions from the above arguments are that the only
significant source of output error, in the said filter organization, arises
from the tap weight errors which are present in any form of filter organiza-
tion. This source of error is primarily dependent on the number of bits
used to quantize a tap weight. The error contribution can be reduced by
digitizing in more digital bits. Further, fixed offests at the tap positions
do not contribute to the output error signals.
Due to the act of mulitplexing of the MDAC, the overall band width of
the filter is llmited to,
; ,~ ,,~
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Bandwidth /max 2.N
where, Fmax is the maximum operating frequency of the MDAC which is limited
by settling time and N is the number of taps. The said filter organisation
is ideally suited for audio frequency applications, particularly, in telephone
systems.
With reference to Figure 2a, a practical circuit configuration of the
programmable transversal filter is illustrated. The important clock voltage
waveforms and their relative timing positions are illustrated in Figure 2b.
The tapped delay line 10 shown in Figure 2a is a bucket brigade delay line
operated by two phase clocks, ~1 and ~2 shown in Figure 2b. During the clock
period Tc of the delay line, the outputs from all the tap positions are sequentially
switched by means of multiplexing switches 18 onto a sample and hold site
16. The switches are selected serially by a decoding logic circuit which
is operated by a master clock, ~MC' at N times the clocking rate of the
delay line. The bias voltage is eliminated by means of an RC network 20
from the output of the sample and hold circuit to avoid the bias voltage
from reaching the input of the MDAC. Consequently, tap weight dependent
bias voltage at the output of the MDAC is eliminated. For an output from
each tap position, a digital word representing a tap weight is latched by
a latch circuit 22 into the input of the MDAC 12 during the on time TSl of
~sl clock shown in Figure 2b. The output from the MDAC is fed to a summer
network 14 which performs a serial summation of the tap weighted signals.
g n time Tsum1 f ~suml~ which comes on following the settling time
of the MDAC, the capacitor C1 is charged to the output voltage level of the
MDAC. When ~sum2 comes on high, during TSum2~ the output of the summer
network is given by,
vO(m) = _ CC1 vj(m) + vO(m - 1) (4)
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where, vj(m) and vO(m) are, respectively, the input and output voltage at the
mth clocking instant, and vO(m - 1) is the output voltage at the previous
clocking instant,
vO(m - 1) = -C2 vj(m - 1) + vO(m - 2) (5)
Equations (4) and (5) illustrate the serial summing action After summing
N number of samples, the output of the said circuit is sampled by the ~S2
clock pulse and then reset by the ~CLAMP pulse durins TcLAMp.
With reference to Figure 3 (a) and (b) respectively, the experimental
results on frequency and noise spectra of a low pass and a wide-band band
pass filter are illustrated for a 32 tap filter at a sampling rate of 8 KHZ.
The filter coefficients were coded in 8 binary bits using an offset-binary
coding scheme. Thus providing an effective quantization of only 7 bits.
A microprocessor was interfaced to the filter for ease of programming.
The results on frequency responses closely match their theoretical predic-
tions. A stop band attenuation of about 40 dB indicates a high degree of
accuracy of the filter. As expected, the noise spectra indicate h;gh
accuracy and wide dynamic range capability of the filter structure.
With reference to Figure 4, an alternate circuit organisation is
illustrated which is suitable for monolithic integrated circuit implementa-
tion of the programmable analog transversal filter. Specifically, the
multiplying digital to analog converter 24 produces N number of tap weighted
input signal samples during one sampling period. These samples are entered
into separate storage locations of a parallel input charge transfer device
delay line 25 of N number of delay stages. The samples are then shifted
one position down the delay line and the operation is repeated with a new
analog sample of the input signal. A progressive summation takes place as
the tap weighted input signal samples are clocked down the CCD delay line.
The results of a convolution or a correlation is directly available at the
output of the CCD delay line. The circuit arrangement of Figure 4 can be
implemented using standard CCD process technology in a modest silicon area.
The MDAC can be designed to operate in a differential mode such that
the effect of input signal bias is removed from the output. One possible
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circuit organisation of the MDAC and a suitable architecture of the parallel
input CCD delay line will now be presented in the context of an integrated
programmable filter chip.
With reference to Figure 5a, a circuit schematic of a differential input
MDAC is illustrated. The bias voltage VB and the signal voltage Vs
superimposed on VB, are applied to the input of the MDAC. The output of
the MDAC is proportional to the input signal weighted by a digital code and
is independent of the input bias signal. The MDAC makes use of binary-
ratioed capacitors 26, which are selected by a digital bit pattern representing
a tap weight. The operation of the circuit requires sign-magnitude form of
coding for digital representation of a tap weight. The operation of the
circuit of Figure 5a is illustrated with reference to the clock voltage
waveforms of Figure 5b. When ~R clock pulse is turned on, Node C is set to
a reference potential VR, by means of the MOS switch 27. The nodes A and
B are set to VB(n), or VB(n) + Vs(n), and VB(n) + Vs(n), or VB(n), depending
upon whether the tap weight is positive, or negative. For a positive tap
weight, only MOS switch pair 28 is turned on by the ~SW1 clock pulse. For a
negative tap weight, only MOS switch pair 29 is turned on by the ~SW2 clock
pulse. The node Dj corresponding to the ith bit position is set to the
potential of node A by turning on the ~Ii clock pulse which is applied to the
gate of the ith MOS switch of the switch bank 30. The potential of node B
is then applied to node Dj, by turning on the ith switch of the switch bank
31 by means of ~Mi clock pulse, provided the ith bit is a digital "one". The
~Mi clock pulse may be complementary to the ~Ii clock pulse. The voltage at
node C is sampled by the ~SAMP clock pulse as shown in Figure 5b, and is held
for one clock period of the MDAC. The voltage at the output of the sample
and hold amplifier at the end of the mth clock period is given by,
VOuT(m) ~ VR + KVs(2 1w1 + 2 2w2 + ... + 2-Mwm)
where, w; represents the ith bit of a digital word and has value either 1 or
O and K is a constant of proportionality.
10 .
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The output from the MDAC thus sits on a fixed reference potential VR,
irrespective of the tap weights. The binary-ratioed capacitors can be gate
to diffusion, gate to inversion layer, or polysilicon to polysilicon layer
capacitors.
With reference to Figure 6(a), a ecD delay line structure is illustrated
for parallel loading of tap weighted signal samples as required in the
integrated circuit implementation of the programmable filter. The relative
timings of important clock voltage waveforms are shown in Figure 6(b). The
operation of the circuit is as follows: the output from the MDAC is sequentially
loaded into the storage locations under the storage gates 32, as shown in
Figure 6a, by serally applying PG1 to ~GN pulses to gates 34. The charge
packets under the storage gates 32 are held until the transfer gate 36 pulse
~T turns on, i.e. ~T turns off, when the charge packets are transferred to
the respective ~1 storage locations 38 of the serial CCD register 40, and
are added to the charge packets already present in the said locations. Since
the bias charge determined by the reference potential VR, as indicated in
Figure 5(a), is also progressively added, as is the signal charge, the width
of the serial CCD register can be progressively increased from the input to
the output in order to increase the charge handling capability of the device.
The parallel transfer channels should be isolated from each other by channel
stop diffusions 42. All input diffusions 44 are corrected together and can be
held to a fixed potential or can be pulsed for "fill and spill" method of
charge injection. The detection of charge from the output of the serial
register can be done in a conventional manner using a sense and a reset
diffusion, and a reset gate. Although, the discussions here are made with
respect to a two-phase device, the concept is equally applicable to a three-
phase or a four-phase device structure.
With reference to Figure 7a and 7b, two applications of a programmable
analog transversal filters are illustrated. An analog programmable transversal
filter in an integrated circuit form can provide tremendous cost advantage in
many ophisticated signal processing applications. Figure 7a shows a block
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diagram of an echo canceller used in telephone systems. The hybrid transformer
S0 produces an echo which can be cancelled by using a programmable transversal
filter 52 in an arrangement shown in the figure. The error signal which is
the difference between the signals at the output of the transversal filter
and the hybrid transformer is fed to a decision circuit 54 which modifies
the tap weights of the transversal filter in an iterative manner so as to
minimise the mean square error. At the end of the operation, the transversal
filter adapts to the impulse response of the hybrid transformer to produce a
replica which is then subtracted from the original echo.
With reference to Figure 7b, a circuit diagram is illustrated where
programmable transversal filters are used to obtain a sliding discrete fourier
transform of an analog signal. The difference between the sliding and the
actual discrete fourier transform is that in the sliding transform, the input
data is shifted each time a spectral component is calculated. The spectral
power density for the sliding transform is given by,
IFkl = [ ~ Xn+k {cos ( N ) - j sin ( N )}]~ (6)
where Fk is a frequency component for each value of k, and xn is the input
data vector.
For an input sequence that is periodic after N samples, the sliding and
non-sliding discrete fourier transform provide identical results. As shown
in Figure 7(b), the cosine and the sine coefficients are stored digitally in
read only memories 56. Two programmable filters 52 are used to handle real
and imaginary signals. However, if the architecture of Figure 1 is used,
only one tapped delay line and two MDACs for multiplications with the cosine
and the sine coefficients, and two separate serial summer and sample and hold
networks are necessary. During each clock period of the filters, N number
of cosine and N number of sine coefficients for any given K are introduced as
tap weights to the two filters. The outputs from the filters provide Kth
real and Kth imaginary frequency components. The results can be squared in
squaring circuits 58, and summed in a summer 60, to obtain the magnitude
spectrum. In this manner, N number of frequency components are computed in
N number of sampling pulses. In applications requiring low data rates, the
approach is a very strong alternative to the chirp-Z-transform filters. Two
progra~mable transversal filters can be integrated in one chip.
