Note: Descriptions are shown in the official language in which they were submitted.
~ACKGROUND OF T.h:F I~ NTION
This invention relatss ~o elsctron c circuitry for
; control of electrical power 2nd p~rticularly to digital
logic circuitry for controlling the mode of c? r2~ion of a
solid state relay.
In electrical power systsms there ~.-s been increaC-
ing interest in the use of solid state relays for controlledenergization of a load from a power supply. ~or DC circuits,
this usually takes the form of some kind of t.ansistorized
~ switching circuit such as is snown in Ea'~er ~_~ent 3,898,552,
: issued August 5, 1975.
In various ap?lications, different modes of operation
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are requlred from a solld state rel~y. Whlle the same basic
power swltching clrcult may be employed generally in each
of these modes of operation, they each require a dlfferent
sort of control circuit in order to make the power switch
operate in the requlred manner.
The ~unctions desired of a solld state relay are
dlrectly analogous to the functions of electromechanlcal
relays. The required functlons include those re~erred to
as normally open (NO), normally closed (NC), and latched.
In normally open operation, the solid state relay (SSR) ls
to be OFF or to present an open clrcult between the source
and the load unless and until a control signal is applled
to the power switch to close it and complete the circuit
between the source and the load. In the normally open mode,
the power switch will remain closed only so long as such a
control signal is applied to it. In normally closed opera-
tion, the converse is to occur with the switch ON and the
load circuit closed except when a control signal of a certain
type is present that causes and maintains interruption of
the load circuit. In both the normally open and normally
closed modes of operation, a change of state of the relay
occurs only as a result of a change in the applied control
signal. In the third mode o~ operation, the latched mode,
lt is the case that the state of the relay can be changed
by application of a control signal and will remain in the
same changed state when the control signal is removed until
a further control signal is applied to change the state again.
All of the types of operation referred to in the
preceding paragraph reIate t~ relays that may be called
3~ single pole, single-throw (SPST) relays because the operation
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of the relay is to connect or disconnect between a slngle
llne or power pole and a single load. There are, however,
systems that require operation between a plurality of lines
and a single load or a single line and a plurallty of loads
wlth some interrelation of the individual relay functions
such that one is to remain in or out of phase with the other.
For this purpose, it is necessary that the relays be adapted
for associating different control circuits in master-slave
relationship.
Because of the number and variety of functions
desired of an SSR, it has been previously necessary to make
and use dif~erent specific control circuits for different
ones of the required SSR functions with the natural conse-
quence of poor economics as compared with a single circult
that could serve multiple purposes. -
SUMMARY OF THE INVENTION
In accordance with the present invention, a multi-
mode control logic circuit provides the interface between a
low level input control signal and a power switch in a solid ~.
- 20 sbate relay. Any one of a plurality of modes of operation ~ :
is made possible with a single control circuit, including
operation as either a normally open relay, a normally closed
relay, or a latching relay. The same control circuit also makes ~ ~:
possible combinations of such relays for operation in parallel ~:
with a-second relay operating in or out of phase with a first
relay. ..
The control logic circuit includes digital logic
gates and associated components, preferably in a single package
with certain internal interconnections within the package
being fixed but also wi*h a plurality of external terminals
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extending from the package. The external termlnals are
dlstinctly identified and lnclude olle termlnal referred to
as a "mode" terminal which is associated with the lnternal
logic gates in such a manner that the external connection of
the mode terminal to a llne terminal ti.e., on the supply
- side of the power switch) provides a control circult for
normally open relay operation. The mode terminal is, alter-
natively, connectable to a power ground terminal in order to
achleve normally closed operation. The mode terminal may
also be left unconnected, in which casej a latching relay
results.
The differences in operation result because the
mode terminal has a fixed connection internally in the pack-
age to one input of a logic gate which may be an "exclusive
OR" gate whose output is a "1" when any one but not all its
inputs has a "1" on it. The use o~ an "exclusive OR" gate
gives the mode terminal the functions as ~ust described in
the circuit to be specifically described as an example
hereafter. Other logic gates may be used and may be associated
with the rest of the control logic circuitry such that the
mode terminal achieves other modes of operation than those
referred to. The point is that circuits in accordance with
the present invention take advantage of the fact that by
having a logic gate with an externally available terminal
(the mode terminal) one may achieve any of the different
modes of relay operation by tying that terminal to a point
which maintains a "l" on that input to the gate (e.g., by
tying it to the supply or line), or to a point that maintains
a "zero" te.g.~ power ground), or by leaving that terminal
unconnected (not tied to "1" or "zero") but, internally,
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that gate input sees a "1" or a "zero" accordlng to the
state of other internal elements in the control logic clrcuit.
In addition to the mode terminal, circuits in
accordance with this lnvention have separate "master" and
"slave" terminals avallable for interconnecting between the
two relay units to achieve the requlred two pole arrange-
ments. The master terminal is one that bears an output "1"
or "zero" from an internal lo~ic gate. Thls output slgnal
may be the same or different, by choice of design of the
internal circuitry, than the output of the control logic
circuit that goes to the power switch. The master output
terminal, when used, is connected to the slave terminal, or
slave input terminal, of another relay's control logic
circuit. The second control logic circuit therefore has one
of its logic gates with an input tied to an output of the
first so they can be made to operate in or out of phase.
. .
Since the control logic circuits in accordance
with this invention need include only a relatively small
number of individual logic gates and their associated components,
2~ they may be readily miniaturized and included in a single
package along with the rest of the relay components. All
required functions are provided by use of eight external
terminals: line, load, control input, control ground, mode,
master output, slave input and power ground. Control logic
circuits in accordance with this invention therefore provide
much greater flexibility in use than if distinct control
logic circuits were required for each individual mode of
operation.
THE DRAWING
Figure 1 is a general schematic diagram of a solid
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state relay in which the present invention may be incorporated;
Fig. 2 is a schematic diagram of a solid state
relay including an embodiment of the present invention;
Figs. 3 to 6 found on the same sheet as Fig. 1 are
- schematic diagrams of single unit relays in accordance with
this invention;
Fig. 7 is a set of waveforms for understanding the
operation of the relay in the mode of Fig. 6; and
Figs. a to 11 are schematic diagrams of master-
slave combinations of relays in accordance with the present
invention.
PREFERRED EMBODIMENTS
Referring to Figure 1, there is shown a genera-
lized circuit schematic of a solid state relay (SSR) con-
nected between a Direct Voltage Source and a Load. The SSR
principally comprises a Power Switching Circuit that is
directly connected between the Source and Load and has a
control input from a Control Logic Circuit which in turn has
an input from a Control Input Circuit.
The Control Input Circuit is one that is respon-
sive to some system condition to produce a signal which may
influence the operation of the relay. U.S. Patent No.
4,086,503 issued April 25, 197a to Fox et al and assigned
to the present assignee, discloses a suitable Control Input
Circuit. The Control Input Circuit preferably also includes
means providing electrical isolation between the source of in-
put signal and the Control Logic Circuit.
The Control Logic Circuit preferably incluùes at
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its input a threshold sensing circult portion for determining
if the character (~or example, the n~agnltude and polarity)
o~ the signal from the Control Input Circuit is of the type
desired for the operation o~ the Control Logic Circuit. ~he
Control Logic Circuit principally includes logie gates for '
- producing a signal applied to the Power Switching Circuit in
accordance with a predetermined logic design.
The Power Switching Circuit may take various ~orms
in accordance with known practice of which one preferred
form is generally in accordance with Baker~Patent 3,898,552,
issued August 5, 1975.
It is particularly to the Control Logic Circuit
` that the present invention is directed. Although of more
`~ general utility, the invention will be principally described
by an example of a circuit developed for use where high
reliability (e.g., good noise immunity), low power dissipation,
and suitability for miniturization are important, such as in
aerospace applications.
Referring to Figure 2, a circuit schematic is
shown of an example of an SSR including a Control Logic
Circuit in accordance with one embodiment of the present
invention. The input is developed by a control input circuit
10 that may, for example, include an optical lsolator Pl,
but which could instead have a transistor,'op-amp, or a
relay for the purpose.
Optical isolator Pl provides electrical isolation
which is desirable.' The'Control and Control Ground terminals
have no coupllng to the rest of the SSR except through Pl.
The Control terminal ln this example recei~es a signal from
3~ elsewhere,'such''as the'trip eircuit of roferrcd to patent
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3,697,~13 issued October 10~ 1972 to D. A. Fox, but that trip
circuit could also be in the relay p~ckage as part of the con-
trol input circuit; also see the referred to U.S.Patent ~,0~6,503.
When control current begins to flow through the
llght emitting diode Dl of Pl, radiation turns on the photo
transistor Ql of Pl. When the transistor portion of Pl
begins to turn on, its collector voltage will drop to the
threshold of ZlA which is an exclusive OR gate connected as
a non-inverting (or buffer) amplifier.
The output of ZlA goes to "zero" when the control
signal is applied (both inputs "zero") and now begins to
charge capacitor Cl at a rate determined by the current
source capability of ZlA and the size of capacitor Cl. This -
controlled fall time provides the required control noise
immunity for the circuit. Since ZlA acts as a controlled
current source in both the high and low states, symmetrical
nolse immunity is obtained.
; The voltage across Cl is sensed by ZlB, also an
exclusive OR gate connected as a non-inverting amplifier.
ZlB, along with R3 and R4, forms a Schmitt trigger with
positive snap action around the threshold voltage of ZlB.
This provides a clean logic signal for the remainder of the
control circuit. ZlA has a pair of inputs o~ which one is
connected to the regulated B+ supply through resistor Rl and to
the collector of phototransistor Ql. The other input of ZlA
is connected to the power ground. ZlB also has an input
connected to the power ground while its other input is
connected through resistors R2 and R3 to the output of ZlA
and resistor R4 is connected in a circuit branch between
that input and the output of ZlB. Capacitor Cl is connected
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from the B~ line to a point between resistors R2 and R3.
The element~ ZlA, ZlB, Rl, R2, R3, RL~ and Cl, connected a~
shown, may be referred to as the thr~shold sensing portion
12 of a control logic circuit 14 which also includes logic
circuit portion 13 in which are located the principal elements
of the inventlon.
The logic circuit portion 13 includes excluslve OR
logic gates ZlC and ZlD of whlch ZlC may be regarded as the
"main" gate as it ls operatlve in all modes and comblnations.
It has an lnput 16 with a fixed connectlon, through R6, to
the output of ZlB. The same input 16 ls connected to the
4g~ ~esis ~ ~7
slave input terminal of the relay~ The output of ZlC goes
to the power switch as well as to one input of ZlD. ZlD is
an "auxiliary" gate operative only when the illustrated
relay is connected from the output of ZlD (the Master Output
terminal) to another relay as will be described.
The main gate ZlC has a second input 18 that is
permanently connected, through R8, to Z2 at terminal Q. Z2
is a D type flip-flop connected to toggle. The toggling
action occurs when the clock input (C) of Z2 goes positive.
Input 18 of ZlC is also connected through R9 to the external
mode terminal.
Before proceeding with the description of logic
circuit 13, Power Switching Circuit 20 should be introduced
primarily to show how the Line, Load, and Power Ground
terminals come out of the relay. While a specific example
of switch 20 is shown for ¢ompleteness, it is generally in
accordance with the referred to Baker patent and will not be
discussed in detail.
The SSR of ~ig. 2 wi11 now be recognized to lnclude
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the bullding blocks of Flg. 1 and will also be seen to have
elght external termlnals illustrated ln Fig. 3. Here the
SSR ls contalned in a unitary packa~e with the eight ter
minals identified on the package in some manner, such as:
L - Line; LD - Load
MD - Mode; PG - Power Ground
S - Slave Input M - Master Input
CG - Control Ground C - Control
Proceeding now to a description of operation o~
the loglc circuit portion 13:
With no connection to the Slave Input and wlth the
Mode input tied to Line, as shown in Fig. 4, the output of
ZlB goes through R6 to ZlC which, with a "one" on the Mode
input, acts as an in~erter. The output of ZlC, in phase
with the Control Input, then goes to "one" and turns on Q2
and Q3 which control the power stage 20. Thus the SSR acts
as a Normally Open switch in the connection of Fig. 4.
Resistors R8 and R9 are sized such that inputs at the Mode
input dominate over any signals from Z2.
If the Mode input is connected to Power Ground, as
shown in Fig. 5, ZlC becomes non-inverting, and the switch
becomes Normally Closed.
If the Mode terminal is left open, Fig. 6, the
functlon of the circuit is best understood by reference to
the waveforms of Fig. 7. Waveform A shows a possible shape
of the input sign~l to ZlA~ ignoring noise~ and B is the
ZlB output which follows the input to ZlA and i5 applied to
the Z2 clock at terminal C o~ Z2.
With the Mode terminal open, the output of Z2 at
terminal Q (wave C) is now effective. It and the output of
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ZlB are connected to the inputs 16 and 18 Or excluslve OR
gate ZlC whose output is as shown at wave D. The swltch
thus toggles on and o~ only at the falling edge of the ZlA
input signal ~hus providing Latched operation of the relay
(wave E). The initial state of the switch is determined by
the connection of CRl and R5 to the input terminal S of Z2.
Gate ZlD ls connected as an inverter to provide a
Master output signal inverted with respect to the state of
ZlC ("one" when ZlC is orf). The Slave input is designedJ
through R6 and R7, to override normal control input signals
and to directly control the state of ZlC. With the Mode
control connected to the Line input (~igs. 8 and 9), a Slave
switch will'assume the same state as the Master it is connected
to. With the Mode control connected to Power Ground (Figs.
10 and 11), a Slave switch will assume the opposite state as ,
the Master it is connected to. '~
Power for the control logic is derived ~rom the ''~
:
line input through R16 and regulated by CR3. '
The following table summarizes the operation of
the SSR in the various connections aescribed:
Function Connect Mode Terminal To
Single Unit or Master Normally Open Line
Single Unit or Master Normally Closed Power Ground
Single Unit or Master Latching (Not Connected)
Slave Unit Non-Inverting Line
Slave Unit Inverting Power Ground
The following table identifies components~ merely
by way of further example,'suitable'for use in the Control
Logic clrcuit 14 of Fig. 2 and operable'to'mee't the following
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requirements:
Control voltage 16-32 v. DC
Control current less than 50 mA
Control isolation greater than 5000 Mohm
Control Noise Immunity 1-5 m Sec.
Components:
Resistors Rl and R4 1 Megohm
Resistors R2 and R5 20,000 ohms
Resistors R3, R6 and R8 100,000 ohms
10 Resistors R7, R9 and R10 10,000 ohms
- Capacitor Cl 0.1 microf.
Zener diode CRl 3.3 V.
Zener diode CR2 8.2 V.
Exclusive-OR gates Zl MC 14507
D Flip-Flop Z2 MC 14013
The circuit in accordance with this invention is
particularly advantageous because all of the electrical
components of the entire relay can be mounted on a single
substrate in a single package. The general nature of the
20 components assembly and packaging may be in accordance with
U.S. Patent 4,059,849 issued November 22, 1977 and assigned
to the assignee of the present application.
The present invention has been developed with a
particular intention to provide a small lightweight device
that is suitable for aerospace applications or which may be
subjected to severe environmental conditions. The invention
is, of course, not so limited and where space and durability
considerations are not so critical, it may take other forms
while retaining the advantages of providing a single control
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h;'~ loglc circuit~the capability through select~ble interconnecting
external terminals to provide the various functions of the
relay including normally open, normally closed and latched
in single or two pole configurations.
The general principles of this invention are, for
example, applicable to AC, as well as DC, power relays. An
AC version would require merely an AC Power Swltching Circuit
with a DC power supply for the Control Logic Circuit in
accordance with this invention. The AC Power Switching
Circuit may be selected from various known forms with the
Control Logic Circuit supplying gating signals.
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