Note: Descriptions are shown in the official language in which they were submitted.
4 ¦ Backqround of the Invention
..
The present invention relates generally to
6 enhancement-mode or "normally-off" field-effect transistors
7 (FETs) and depletion-mode or "normally-on" FrTs provided
8 on the same semiconductive substrate, and the fa~rication
q ¦ thereof using five basic lithographic, pattern-delineating
¦ steps. The five lithographic masking steps ~elir.eate in
1~ ¦ order:
12 l (1) the field isolation regions;
13 ! (2) the enhancement-mode FET gate electrodes;
14 ¦ (3) the depletion-mode FET gate electrodes;
l~ (4) contact holes or vias to FET source and
16 ll drain regions and to depletion-mode FrT
17 !I gates; and
18 (5) the high electrical-condvctiv:ty retallic-
I .
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1 type interconnection pattern.
2 Using the five basic masking steps, enhancement-mode and
3 depletion-mode EETs can be fabricated and interconnected
4 as desired to provide integrated circuits.
More particularly, the present invention relates
6 to enhancement-mode FETs and depletion-mode FETs on the
7 same semiconductive substrate which are formed from two
8 separately deposited polycrystalline silicon (i.e., poly-
9 silicon) layers.
Depletion-mode FETs are known in the art and
11 are generally used in FET integrated circuits as nonlinear
12 load devices to provide a more favorable current-voltage
13 relationship than is possible with linear load circuits
14 using resistors or enhancement-mode devices. Enhancement-
mode EETs are also known in the art and are used in digital
16 integrated circuits as switches to prevent or allow the
17 flow of electrical currents (i.e., signals).
18 Enhancement-mode and depletion-mode FETs are
19 often fabricated on the same semiconductive substrate or
chip to provide an integrated circuit such as a micro-
21 processor. Fabrication of such integrated circuits re-
22 quires at least five basic lithographic masking steps and
23 generally utilizes one layer of polysilicon to provide the
24 gate electrodes of both the enhancement-mode and depletion-mode FETs. Known fabrication methods generally employ
26 conventional etched contact holes to provide electrical
27 connection between the polysilicon gate electrodes and the
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1 ¦I metallic-ty~e interconnection pattern. The present inven-
2 ji tion can likewise be used to fabricate both enhancement-
3 i~mode and depletion-mode FETs on the same semiconductive
4 1 substrate, whereby only five basic lithographic masking
S j' steps are required. In comparison to known methods, how-
6 !! ever, a nu~ber of particular advantages can be achleved
7 ¦¦ with the present invention which arise from the unique
8 j utilization of two layers of polysilicon.
9 One unique aspect of the present invention is
that, since the enhancement-mode and depletion-mode gate
11 ~ electrodes are formed from different steps, a nonoxidizing
12 ¦! masking layer can be used to define the enhancement-mode
13 ¦ gate electrode. This provides a self-registering or mis-
14 ¦I registration tolerant electrical connection between the
~ I!gate electrode of the enhancement-mode FET and the metallic
16 ¦!interconnection line pattern. This leads to PETs and in-
17 I tegrated circuits of higher relative density than those
18 ¦ attainable with conventional etched contact holes to the
19 lenhancement-mode gate electrodes.
i Another unique aspect of the present invention
21 ¦¦is that, since the enhancement-mode gate electrode is
22 !Ifabricated before the depletion-mode gate electrode and
23 lifrom a different layer of polysilicon, a blanket or mask-
24 I~less doping to form the depletion-mode channel regions may
',be made after forming the enhancement-mode gate electrode
26 I but before forming the depletion-mode gate electrode.
27 ¦~hus, an additional masking step is not required. In the
Il :
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1 I present invention, the doping to form thé source and drain
, regions of the FETs is provided after forming the depletion-
3 ! ~ mode gate electrodes from the second layer of polysilicon.
4 j Since the source and drain doping is of the same type, but
S ~i of much greater concentration than the depletion-mode
6 ~¦ channel doping, the source and drain doping overlays and
? !¦ complements the maskless depletion-mode channel doping in
8 i the source and drain regions.
g ¦ In addition, other more particular advantages
can be achieved when the present invention is employed to
11 fabricate a dynamic random-access memory chip containing
1~ ~an array of one-device memory cells. In the one switching
13 - device per cell or one-device cell, the enhancement-mode
14 FET acts as a switch to allow electronic charges to enter
15- or leave a storage capacitor. The presence or absence of
16 ¦ charge on the storage capacitor represents binary infor-
7 ¦ mation. The enhancement-mode FET with its self-registering
1~ ! gate contact of the present invention provides a high
19 ¦ density switch for the one-device cell. Uniquely, the
! fabrication step used to provide the gate electrode struc-
21 ¦! ture of the depletion-mode FET can be used to provide the
22 1¦ charge storage capacitor. In particular,~the doping which
2~ ll provides the depletion-mode channel doping also provides
24 i the lower electrode, the gate insulator of the depletion-
,i mode FET provides the dielectric insulation layer, and
26 l! the polysilicon gate electrode of the depletion-mode FET
27 !! provides the upper electrode of the charge storage capacitor
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1 ¦I Furthermore, both enhancement-mode and depletion-mode
2 il devices are used in the peripheral circuits of the random-
3 ~ access memory chip.
4 ~~ When the depletion-mode gate structure is used
1I to form the charge storage capacitor, the biasing require-
6 ¦ ments for the memory cell are relieved. In addition, the
7 i depletion-mode FET can serve in its conventional capacity
8 I as a nonlinear load device in the driver circuit peripheral
9 j to the array, and as a current limiter for the upper
lD ¦ electrode of the storage capacitor.
11 ¦ The one-device memory cells to which the present
12 I invention is also directed are of the type referred to as
13 ¦ metal word line/diffused bit line cells as distinguished
14 I from metal bit line/polysilicon word line cells. The pre-
sent invention requires only five basic, lithographic,
16 j pattern-delineating, masking steps to achieve the desired
l? ¦ integrated circuit comprising an array of one-device memory
18 i cells and the associated addressing, decoding, and sensing
19 1~ circuits which are positioned peripherally to the array of
jl cells.
21 ¦~ Summ_ry of the Invention
22 !~ The present invention is directed to certain
23 ! enhancement-mode and depletion-mode FETs and to a method
24 1l for f abricating a semiconductor integrated circuit having
', at least one such enhancement-mode FET and one such deple-
26 !~ tion-mode FET device formed therein. The enhancement-mode
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1 li and depletion-mode ~ETs may be interconnected as desired
2 1, to form an integrated circuit. Each FET has source, drain,
3 I~.and channel regions. Electrical connections are provided
- 4 1; to the source, drain, gate electrode, and substrate regions
li of the FETs for the purpose of applying or obtaining elec-
6 ¦I trical signals.
7 ! The fabrication method requires five basic,
8 lithographic, pattern-delineating steps. Two critical
9 I doping steps in the process provide a low-concentration
¦ doping layer for the depletion-mode channel regions, and
11 a high-concentration doping for the source and drain regions.
12 The method of the present invention requires that two
13 separately deposited layers of polysilicon be used to pro-
14 j vide the enhancement-mode gate electrodes and the depletion-
I mode gate electrodes. The particular sequence of the five
16 ¦ lithographic masking steps and the two doping steps pro-
17 ¦ vided by the present invention along with the use of two
18 ¦ layers of polysilicon provide dénsely packed integrated
19 i circuits containing enhancement-mode and depletion-mode FETs.
il The present invention is particularly advantageous
21 ¦¦ when employed to fabricate charge storage capacitors along
22 1! with the depletion-mode and enhancement-mode FETs such as
23 ¦l a dynamic random-access memory chip comprising an array of
24 , one-device memory cells and associated sensing, addressing,
!! decoding, and clocking circuits located on the same chip
26 I but peripheral to the array of cells. Each cell consists
27 ¦ of an enhancement-mode FET switch and a charge storage
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l ¦~ capacitor. ~he enhancement-mode FET serves to charge or
2 1I discharge the capacitor and the presence or absence of
3 1, charge on the capacitor represents binary information.
4 ¦I Conventionally, the capacitor is fabricated with
I the same materials and steps used to provide the gate
6 electrode of the enhancement-mode FET, however, a unique
approach is utilized according to the present inventio~
where~y the fabrication steps which are employed to provide
9 the gate electrode structure of the depletion-mode FET are
1~ also utilized to provide the charge storage capacitor.
ll The doping for the channel region of the depletion-mode
12 I device also provides the lower electrode of the capacitor.
13 I ~he polysilicon layer used for forming the polysilicon
14 ¦ gate electrode of the depletion-mode FET is also used for
~ forming the upper electrode of the charge storage capacitor.
16 ! Also the material used to provide the gate insulator is
17 ¦ also used to provide the insulator for the charge storage
18 ¦ capacitor.
l9 I The present invention provides certain biasing -
' advantages when charge storage capacitors are present such
2~ 1 as in memory cells. In particular, in other known devices
2? ~ in which the charqe storage capacitor is formed along with
23 1 the enhancement-mode gate electrode structure, an additional
24 ¦ voltage level is required for the upper capacitor electrode
¦¦ to maintain an inversion layer under the electrode at the ~;~
2~ l~ surface of the semiconductive substrate. Generally, the
27 I voltage supplied to the upper capacitor electrode is larger
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i l,l in absolute magnitude than the voltage supplied to the
2 ~ word line, ~nd different in polarity from that supplied
to the semiconductive substrate. When the doping employed
, to provide the channel doping for the depletion-mode FET
5 1l is also used to provide the lower electrode of the charge
6 ! storage capacitor according to the present invention, the
7 ¦ threshold voltage necessary to create a surface inversion
jl layer is lowered, and a lower voltage is required for the
~ upper capacitor electrode. This reduction in the required
¦l voltage for the upper capacitor electrode makes it possi-
11 ~ ble to operate the word line and the upper capacitor
12 1l electrode at the same voltage level. This advantageously
13 1! reduces two different voltage levels to one. In addition,
14 ¦¦ the required magnitude of the bias on the upper electrode
1S j! f the capacitor is reduced. This in turn lowers the
16 li electric field strength across the capacitor dielectric
17 1l and leads to higher reliability circuits.
13 i, The present invention also provides a memory
19 1i cell of very small dimensions and an integrated memory
2~ ¦! circuit of very high packing density.
21 ¦I The enhancement-mode FET, the depletion-mode FET,
22 ! and/or the one-device memory cell of the integrated circuit
23- j~ are surrounded by a relatively thick isolation region
24 commonly referred to as the field oxide region. The field
~~ oxide serves to electrically isolate one FET or memory cell
26 " from other like FETs and/or memory cells which are present
27 " on the same semiconductive substrate. This field oxide
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1 may be formed by thermal oxidation of the semiconductive
2 substrate or by well known vacuum or chemical vapor depo-
3 sition techniques. The field oxide may be formed on the
4 surface of the semiconductive substrate or it may be par-
tially or fully recessed into the semiconductive substrate
6 such as described by Dennard, Rideout, and Walker in U.S.
7 patent 3,899,363 issued August 12, 1975, to the assignee
8 of the present application.
9 The gate electrodes of the enhancement-mode and
the depletion-mode FETs, and the upper electrode of the
11 charge storage capacitor, when present, are of polysilicon.
12 The fabrication of the enhancement-mode gate is performed
13 prior to and in a separate lithographic masking step from
14 the fabrication of the depletion-mode gate.
Two separate layers of polysilicon are used to
16 form the enhancement-mode FET gates and depletion-mode FET
17 gates and upper capacitor electrodes, when present. The
18 polysilicon layer for fabrication of the enhancement-mode
19 gates is deposited separately and prior to the polysilicon
layer employed for fabrication of the depletion-mode gates
21 and upper storage capacitor electrodes. This fabrication
22 sequence makes it possible to preserve an oxidation barrier
23 masking layer above the enhancement-mode gates, to provide
24 a doped lower capacitor electrode beneath the polysilicon
upper capacitor electrodes, to provide a doped channel re- -
26 gion beneath the depletion-mode polysilicon gate electrodes,
27 and to provide a thick insulation oxide over the polysilicon
28 upper capacitor electrodes and over the depletion-mode poly-
29 silicon gate. The oxidation barrier masking layer is used
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1 I to delineate the enhancement-mode gate region and to prc-
2 1! serve the polysilicon gate material of the enhancement-mode
FET during the growth of the oxid~ insulation layer. When the
~ ¦~ oxidation barrier layer is removed, the entire gate region
.~ I is revealed for contacting. A metallic-type interconnection
6 line that passes over any portion of the enhancement-mode
gate electrode will make electrical connection to that gate
. . ~ . thus providing a self-registering or misregistration tolerant
contact to the gate electrode.
In particular, the present invention is concerned
11 with a method for fabricating both enhancement-mode and
12 depletion-mode FETs on the same semiconductive substrate
13 with only five basic lithographic masking pattern-delineatins
14 steps.
The five basic lithographic masking fabrication
16 ¦ steps and sequence required by the present invention are
17 I as follows: . :
. 18 l (1) delineating field isolation regions
19 ¦~ as distinguished from the device regions;
¦¦ ~2) delineating FET enhancement-mode gate
21 ¦¦ . electrodes from a first polysilicon layer;
22 1l . (3) delineating FET depletion-mode gate
23 11 . pattern from a second and subsequently
24 1I deposited polysilicon layer;
2~ ¦~ (4) delineating contact hole pattern to pro-
26 ¦, .vide vias to FET depletion-mode gates,
27 I and to enhancement-mode and depletion- ~-
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1 ¦! mode source and drain regions; and
2 ¦! (5) delineating high-electrical conductivity
"' m~tallic-type interFonnection pattern.
The contact holes or vias referred to in step (4)
I above do not generally appear in an array of enhancement-
6 ¦ mode FETs but rather appear in circuits peripheral to the
7 ¦ array of enhancement-mode FETs.
11 .
¦I The present invention is also directed to inte-
g ,i grated circuits obtained by the above-discussed process.
¦ Another aspect of the present invention is the
11 ¦ fabrication of an array of enhancement-mode FETs and charge
12 storage capacitors, and depletion-mode FETs and enhancement-
13- li mode FETs in circuits peripheral to the array with only
five basic lithographic masking steps. The five litho-
¦¦ graphic masking steps delineate in order:
16 l ~1) the field isolation regions;
17 I (2) the enhancement-mode FET gate electrodes;
lP i (3) the depletion-mode FET gate electrodes
1~ I and the storage capacitor upper electrodes;
¦1 (4) contact holes or vias to FET source and
21 ! drain regions, to depletion-mode FET gates,
22 j~ and to upper storage capacitor electrodes
23 I! and
24 ~, (5) the high-electrical conductivity metallic-
2S ¦~ type interconnection pattern.
?6 i' The contact hole or vias referred to in step (4)
27 11 above do no~ appear in the array but rather appear in
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1 circuits peripheral to the array.
2 Another aspect of the present invention is a
3 random-access memory integrated circuit comprising an
4 array of dynamic one-device memory cells wherein each
cell contains an enhancement-mode FET switch and a charge
6 storage capacitor; and circuits peripheral to the array
7 containing both enhancement-mode FETs and depletion-mode
8 FETs; and wherein the integrated circuit comprises:
9 (A) a semiconductive substrate of a first
conductive type containing active im-
11 purities of a first conductive type;
12 (B) doped polycrystalline silicon FET en-
13 hancement-mode gate electrodes delineated
14 from a first layer of polycrystalline
silicon;
16 (C) doped polycrystalline silicon electrodes
17 delineated from a second layer of poly-
18 crystalline silicon deposited subsequent
19 to said first layer of polycrystalline
silicon, wherein the electrodes delineated
21 from said second layer which are located
22 in the array provide the upper electrodes
23 of the charge storage capacitors, and
24 wherein the electrodes delineated from
said second layer which are located in
26 circuits peripheral to the array provide
27 the FET depletion-mode gate electrodes;
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) low concentration doping of a second
2 1~ and opposite conductive type beneath
3 Ij' the electrodes delineated from the
, second layer, wherein the doping which
¦ . is in the array provides the lower
6 , electrodes of the charge storage
? capacitors, and wherein the doping
which is in the circuits peripheral
S to the array provides the depletion- ~:
mode channel regions;
11 (E) high concentration doping of a second
12 and opposite conductive type wherein
1~ ¦ the high concentration doping which
14 is in the array provides the doped bit
line and the electrical connection be- .
16 tween the FET switches and the lower
17 ¦ electrodes of the charge storage
18 I capacitors; and wherein the high con-
19 I centration doping which is in the cir-
I cuits peripheral to the array provides
21 ~ the source and drain regions for both
22 !! the enhancement mode FETs and depletion
23 ¦¦ mode FETs located in the circuits per-
24 !' ipheral to the array; .
!i (F) a high-electrical conductivity metallic-
26 I type pattern wherein the metallic-type
27 I - pattern which is in the array provides
28 !
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1 ! the word lines to the memory cells,
2 i, and the metallic-type pattern in
~ 1~, the circuits peripheral to the
4 " array serves as an interconnection
1i line pattern;
6 ¦! (G) self-registering electrical connec-
I ~ tion between polycrystalline silicon
8 1~ enhancement-mode gate elec~rodes and
9 1~ the metallic-type high-electrical
¦¦ . conductivity pattern. .-
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1 jl Brief Description of the Dr~winqs
2 ll Figures lA-lJ are cross-sectional views taken
3 ' along the lines indicated in Figure 2 of an FET one-
4 I; device memory cell and an FET depletion-mode device in
¦l various stages of fabrication.
Figures 2A-2E show a top view of the sequence
7 , and relative positioning of the five basic lithographic
8 ¦~ masks employed according to the present invention.
,oc ¦ Figure 3 shows the doping profile of the
¦ channel region of the depletion-mode device as predicted
~1 ¦ by a numerical computer model.
12 ¦ Figure 4 shows a circuit diagram of a word
13 I line driver comprising both enhancement-mode and depletion-
14 ¦ mode FETs.
¦ Figure 5 shows a circuit diagram of a
11 - , .
16 jl depletion-mode FET used as a current limiter for the
17 1, upper storage capacitor electrode of a one-device cell
18 1' memory circuit.
I - ; - .
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19 1, Description of Preferred Embodiments
'~ For convenience, the discussion of the fabrication
21 ! steps is directed to the preferred aspect of preparing an in-
22 1! tegrated circuit array containing FET one-device memory cell
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1 and enhancement-mode and depletion-mode FETs. Accordingly,
2 it is understood that the present invention can be employed
3 to fabricate combinations of enhancement-mode and depletion-
4 mode FETs in general.
Also, for convenience, the discussion of the
6 fabrication steps is directed to the preferred aspects
7 of employing a p-type silicon substrate as the semicon-
8 ductîve substrate and n-type impurities as the diffused -
9 or implanted dopant impurities in the source and drain
regions. This leads to the n-type channel FET technology.
11 Accordingly, it is understood that an n-type substrate
12 and p-type diffused or implanted dopant impurities in the
13 source and drain regions can be employed according to the
14 present invention in the p-type channel FET technology.
It is understood that when the discussion refers
16 to n-type impurities, the process steps are applicable to
17 p-type impurities and vice versa. Also, the present in-
18 vention is applicable to substrates other than silicon
19 which are known in the art. Also, as used herein, the
terms "metallic-type interconnection lines" or "high
21 electrical conductivity interconnection lines" refers to
22 lines or stripes of a metal such as aluminum as well as to
23 non-metallic materials such as highly doped polysilicon of
24 inter-metallic silicides which nevertheless can have elec-
trical conductivities of the magnitude generally possessed
26 by metals. Moreover, the terms "polysilicon" and "polycrystal-
27 line silicon" are used herein interchangeably as in the prior
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1 art. Also, when reference is made to impurities of a
2 "first type" and to impurities of the "second type", it
3 is understood that the "first type" refers to n or p-type
4 impurities and "second type" refers to the opposite con-
ductivity type. That is, if the "first type" is p, then
6 the "second type" is n. If the "first type" is n, then
7 the "second type" is p. As used herein, the terms "gate"
8 and "gate electrode" are interchangeable.
9 Referring to Figure lA, there is shown a frag-
ment of the initial structure of the invention generally
11 shown as 1. A p-type silicon substrate 2 having any
12 desired crystal orientation (e.g., <100>) is prepared by
13 slicing and polishing a p-type silicon boule grown in the
14 presence of a p-type dopant such as boron following con-
ventional crystal growth techniques. Other p-type dopants
16 for silicon include aluminum, gallium, and indium.
17 As discussed hereinabove, the field oxide isola
18 tion can be fabricated by any of several known procedures
19 including thermal oxidation of the simiconductor substrate
or by well known vacuum or chemical vapor deposition tech-
21 niques. Furthermore, the field oxide may be formed above
22 the semiconductive surface or it may be partially or fully
23 recessed into the semiconductive substrate. An example of
24 one such procedure is the fully recessed oxide isolation
technique disclosed in U.S. patent 3,899,363. For the
26 purpose of illustration of the five masking step procedure
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l 1 of the present invention, a fully recesséd field isolation
2 ' oxide will be used.
3 ! ~, ~igure lA shows the recessed field oxide regions
4 3 and their associated implanted p-type channel stopper
, regions 4 fabricated following the technique disclosed in
6 1, U.S. patent 3,899,363. The field oxide isolation regions
7 j' are about 4,000 to lO,000 A thick and are fully recessed
¦I with respect to the silicon surface. The lithographic mask
9 il shown in Figure 2A is used tc delineate the field oxide
¦, regions 3 as distinguished from the enhancement-mode and
ll !I depletion-mode device regions 5 and 6, respectively. This
l~ j; is the first basic lithographic masking step. The mask is
¦l of a transparent material having opaque portions in a pre-
14 li determined pattern. It is noted that the enhancement-mode
lS Ij and depletion-mode devices may be located within the same
16 j device region or may occupy separate device regions.
17 ',l A thin enhancement-mode FET gate insulator layer
l~ ! of silicon dioxide 7 is grown on or deposited onto the
l9 ¦, silicon substrate 2. This gate insulator, which is about
1! 200 to l,000 Angstroms thick, is preferably formed by thermal
21 1 oxidation of the silicon surface at l,000C in the presence
22 il of dry oxygen. It is noted that, when desired, the p-type
23 ¦ doping at the semiconductor surface in regions 5 and 6 can
24 be increased by ion implantation or diffusion of boron.
1 As shown in the art, this additional low-concentration
26 l surface doping is used to increase the gate threshold vol-
2? " tage of the enhancement-mode FET to a desired value and to
~ 19-
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1 prevent source to drain depletion layer punch-through or
2 short-channel effects. The technique of enhanced surface
3 doping is described, for example, by V. L. Rideout et al
4 in "Device Design Considerations for Ion-Implanted n-
Channel MOSFETs", IBM J. Res. Develop., Vol. 19, No. 1,
6 pp. 50-59, Jan. 1975. The additional surface doping may
7 be provided prior to or subsequent to forming gate oxide
8 layer 7 as desired.
g A layer of polycrystalline silicon 8 is then
deposited. The polysilicon layer is approximately 1500
11 to 5000 A thick, and may be formed by chemical-vapor
12 deposition. The polysilicon layer is now doped with an
13 n-type dopant such as arsenic, phosphorus, or antimony by
14 one of several conventional techniques. Preferably, the
polysilicon is doped with phosphorus and preferably uses
16 the techniques of depositing a POC13 layer and heating it
17 to approximately 870C to drive the phosphorus into the
18 polysilicon making it n-type. After this, the residual
19 of the POC13 layer is removed by etching the water in
buffered hydrofluoric acid. A thin surface protection
21 layer of silicon dioxide 9 about 50 to 200 A thick is
22 grown on or deposited onto the polysilicon layer to pre-
23 vent a subsequently deposited oxidation barrier layer 10
24 from reacting with the polysilicon and thereby rendering
it difficult to later remove the oxidation barrier layer.
26 An adherent oxidation barrier layer 10 or a non-
27 oxidizing material such as silicon nitride, aluminum
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1 nitride, boron nitride, aluminum oxide, or silicon carbide
2 is then deposited. Preferably the layer 10 is of silicon
3 nitride and is approximately 500 to 1000 A thick. The
4 layer 10 may be deposited by conventional chemical-vapor
deposition techniques. An additional layer of silicon
6 dioxide 11 is then deposited. The silicon dioxide layer
7 11 is approximately 500 to 1000 A thick and may be formed
8 by chemical-vapor deposition. This layer 11 serves as an
9 etching mask to delineate the layer 10.
The layer 10 serves as an etching mask to
11 delineate the gate pattern into the silicon-dioxide layer
12 9, and as an oxidation barrier layer during subsequent
13 growth of the insulation oxide over other parts of the
14 structure. The oxidation barrier layer material should
not oxidize, or at most only oxidize extremely slowly
16 relative to the oxidation rate of silicon and polysilicon.
17 The oxidation barrier layer material is considered to be
18 a nonoxidizing material under the conditions to which it
19 is subjected in the method of the present invention. The
oxidation barrier layer 10 is preferably a nitride such
21 as silicon nitride and it prevents oxidation of the upper
22 surface of the polysilicon layer 8 thereunder.
23 A gate pattern determining layer such as a layer
24 of resist material 12 of the type employed in known litho-
graphic masking and etching techniques is placed over the
26 surface of the upper oxide layer 11. Any of the well-
27 known photosensitive polymerizable resist materials known
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1 in the art may be used. The resist material is applied
2 such as by spinning on or by spraying. The resultant
3 structure is shown in Figure lB.
4 The layer of photoresist material 12 is dried
and then selectively exposed to ultraviolet radiation
6 using the photolithographic mask shown in Figure 2B. The
7 mask is of a transparent material having opaque portions
8 in a predetermined pattern. The masked wafer is subjected
9 to ultraviolet light which polymerizes the portions of the
resist material underlying the transparent regions of the
11 mask. After removing the mask, the wafer is rinsed in a
12 suitable developing solution which washes away the portions
13 of the resist material which were under the opaque regions
14 of the mask and thus not exposed to the ultraviolet light.
The assembly may then be baked to further polymerize and
16 harden the remaining resist material which conforms to the
17 desired masking pattern, i.e., it covers the regions in
18 which the polysilicon enhancement-mode FET gate regions
19 will subsequently be formed.
Next the structure is treated to remove the por-
21 tions of the silicon dioxide 11 not protected by the resist
22 material 12. The wafer is immersed in a solution of buf- -
23 fered hydrofluoric acid. The etching solution dissolves
24 silicon dioxide but does not attack the resist, oxidation
barrier layer 10 such as silicon nitride, or other materials
26 of the assembly, as illustrated by Figure lC.
27 The photoresist material 12 above the pattern
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1 etched into silicon dioxide layer 11 is then removed by
2 dissolving in a suitable solvent. The remaining silicon
3 dioxide regions 11 conform to a predetermined pattern,
4 and now serve as a mask for etching predetermined patterns
in the oxidation barrier layer 10. Patterns in layer 10
6 then serve as a mask for etching patterns in the thin
7 oxide layer 9, and patterns in layer 9 in turn serve as
8 a mask for etching patterns in the polysilicon layer 8.
9 Patterns in polysilicon layer 8 then serve as a mask for
etching patterns in silicon dioxide layer 7.
11 Patterns in the layer 10, when silicon nitride
12 is employed, can be formed by etching in a phosphoric
13 acid solution at 180C. Patterns in the thin oxide layer
14 9 formed by etching in a solution of buffered hydrofluoric
acid. Patterns in the polysilicon layer 8 are formed by
16 etching in a well-known etchant such as ethylene diamine
17 pyrocatechol at 100C. This completes the second basic
18 lithographic masking step which delineates the polysilicon
19 gate electrode 13 of the enhancement-mode FET as illustrated
in Figure lD.
21 Next those portions of thin silicon dioxide
22 layer 7 not under the n-type polysilicon gate 13 are re-
23 moved by etching in a solution of buffered hydrofluoric
24 acid. The etchant also removes all or most of the remain-
ing regions of oxide layer 11. Any part of layer 11 not
26 removed can be removed at a later step by a short time or
27 'rdip" etch in buffered hydrofluoric acid.
.,
-23-
886176.
! -'' .
1 ¦¦ Althouyh it is generally preferable to remove
2 I the exposed portions of thin layer 7 at this stage of the
3 !j~process, they can be retained and removed subsequently
4 Ij such as after providing the n-type doping for the channel
1¦ regions of the depletion-mode FETs and for the lower doped
6 ¦ silicon electrodes of the storage capacitors, or even re-
7 ¦ tained throughout the entire process, as desired.
8 Next a thin insulating layer 18 is formed. This
9 insulator layer is grown on or deposited onto the assembly.
¦ Layer 18 is approximately 200 to 1000 A thick, is preferably
11 ¦ of silicon dioxide, and is preferably formed by thermal
12 oxidation of the assembly at 1000 C in the presence of
13 dry oxygen. Layer 18 serves as both the dielectric insulation
14 between electrodes of the storage capacitor to be formed
adjacent to the enhancement-mode FET and as the gate insulation
16 of the depletion-mode FET to be foxmed in region 6. The ex-
17 ¦ posed portions of the thin silicon dioxide layer 7 are
1~ I preferably but not necessarily removed prior to forming
19 I the thin insulation layer 18. When layer 7 is completely
¦ retained, the thickness of the gate insulator of the
21 depletion-mode FET will exceed that of the enhancement-
22 j, mode FET.
23 Il An advantage of the present invention is that
24, ! the enhancement-mode FET gate insulator layer 7 and the
1l depletion-mode FET gate and storage capacitor insulator
26 11 layer 18 can be of different thicknesses. For instance,
27 1l it may be desirable to make the s-torage capacitor insulator
!l .
11 -24-
il - .
~88167~;
1 thinner than the enhancement-mode FET gate insulator in
2 order to increase the capacitance of the storage capacitor;
3 whereas, the enhancement-mode FET gate insulator could be
4 thicker to prevent breakdown due to the voltages experienced
by that gate insulator during operation.
6 The thin insulator layer 18 is preferably formed
7 prior to the thermal diffusion or ion implantation of the
8 n-type impurities, and is thin enough that the n-type im-
9 purities pass therethrough. However, if desired, the thin
storage capacitor insulator layer 18 can be formed subsequent
11 to the ion implantation or thermal diffusion of the n-type
12 impurities. The n-type impurities are ion implanted or
13 thermally diffused to dope the exposed regions 14, 15 and
14 16 of the silicon substrate as shown in Figure lE. These
impurities provide the n-type doping for the channel region
16 14 of the depletion-mode FET to be formed in region 6, and
17 the silicon lower electrode 15 of the storage capacitor.
18 Region 16 will later become the drain region (bit line) of
19 the enhancement-mode FET. When low-concentration p-type
dopants are used to enhance the surface doping in regions
21 5 and 6, the n-type impurity concentration in region 6 is
22 large enough to overcome the effect of the p-type impurities
23 and to provide a negative gate threshold voltage for the
24 depletion-mode FET.
The n-type impurities do not enter the channel
26 region 17 of the enhancement-mode FET because of the block-
27 ing action of the gate electrode 13 and of the remaining
-25-
~: , , '.
.
.. . . .
I ~:~88676
1 1 portions of layers 7, 9, and 10. Similarly, the thick
2 ! field oxide 3 prevents n-type impurities from entering
3 1,~.the silicon substrate beneath field isolation region 3.
4 !! For purposes of illustrating the present
invention, ion implantation o n-type impurities has
6 been selected. For'instance, a shallow, lightly doped,
7 n-type region can be formed in the silicon substrate
8 beneath insulation layer 18 by a p31 implant of about 75
9 I KeV energy and about 1012 atoms/cm2 dose when a 500 A
¦ thick silicon dioxide capacitor insulator layer 13 is
11 ¦ formed prior to the ion implantation.
12 The n-type doping profile as predicted by a
13 ¦ numerical computer analysis program is shown in Figure 3 -
14 for a 2 ohm-cm (7.5x1015 cm~3) p-type substrate. The pro-
file prediction program is described by F. F. Morehead in
16 "A General Calculation of the Redistribution of lon Im-
17 planted Profiles in MOS and Other Processing", ECS Fall
18 I Meeting Extended Abstracts, pp. 474-475, Oct. 13-17, lg74.
19 When the ion implantation is performed prior to the forma-
¦ tion of the insulation layer 18, a p31 implant of about 50
21 ¦ KeV energy and about 1012 atoms/cm2 dose is employed.
22 I The magnitude of the n-type doping provided by
23 j the implantation is too small by several orders of magni-
24 1, tude to also provide source and drain regions suitable for
¦I FET operation. In particular, the resistance in the
26 1l regions which subsequently are to be FET drain and source
27 ¦, regions is thus far very high. Also~ shallow lightly-
' - -26- ~
. ~
1~867~i
1 doped regions of the general magnitude formed herein are
2 extremely difficult to be electrically contacted by metallic
3 interconnection lines.
4 A second layer of polysilicon 19 is then deposited
over the entire structure. Polysilicon layer 19 can be
6 either p- or n-type, hut preferably is also n-type. The
7 polysilicon layer is approximately 3500 to 5000 A thick
8 and may be formed by chemical-vapor deposition. The poly-
9 silicon is doped with POC13 as described hereinabove.
After doping, a layer 20 of silicon dioxide 500 to 1000 A
11 thick is grown on or is deposited onto the second poly-
12 silicon layer. Preferably the silicon dioxide is deposited
13 by conventional chemical-vapor deposition techniques. The
14 residual of the POC13 layer need not be removed prior to
forming the silicon dioxide layer 20.
16 It is noted that the depletion-mode channel re-
17 gion 14 and lower capacitor electrode region 15 are formed
18 by ion implantation or diffusion, after delineating the
19 enhancement-mode polysilicon gate electrode 13 but before
delineating the upper storage capacitor electrode and the
21 depletion-mode FET gate in the second layer of polysilicon
22 19. The n-type ion implantation or thermal diffusion must
23 be carried out before the step of depositing the second
24 polysilicon layer 19 in order to form an n-type channel
region 14 beneath the depletion-mode polysilicon gate and
26 an n-type, doped silicon, lower capacitor electrode under
27 the polysilicon capacitor upper electrode.
.
, ~ 8~676
1 li A layex of resist material 21 of the type
2 , described previously for defining the enhancement-mode
3 ~ gate pattern is now used to define the polysilicon de-
4 I, pletion-mode gate and the polysilicon upper capacitor
¦l electrode patterns. The resist material 21 is applied,
~ ¦l exposed with ultraviolet radiation using the lithographic
i ¦! masking pattern shown in Figure 2C and the unexposed re-
8 , gions of the resist are dissolved away. This is the third
9 1 basic lithographic masking step. ~ext, the structure is
lG ! treated to remove the portions of the silicon dioxide 20
11 ! not protected by the resist material 21 as illustrated by
12 ¦ Figure lF.
13 ! The wafer is immersed in a solution of buffered
14 ~ hydrofluoric acid which dissolves the exposed parts of
lS 1l silicon dioxide layer 20 but does not attack resist, oxi-
16 ¦~ dation barrier layer such as silicon nitride, silicon, or
17 1¦ other materials of the assembly. The remaining photoresist
18 li regions 21 and 21' above the etched silicon dioxide pat-
19 ii terns 20 and 20' are then removed by dissolving in a suit-
li able solvent. The remaining portions of silicon dioxide
21 1i 20 and 20' conform to predetermined depletion-mode gate
22 ! and upper storage capacitor electrode patterns 22 and 23
23 I respectively as shown in Figure 2C. The depletion-mode
24 I polysilicon gate and the polysilicon upper capacitor
electrode patterns 22 and 23 respectively are formed by
26 etching in a well-known etchant such as ethylene diamine
27 I pyrocatechol at 100C. The etchant does not attack the
I'
!, ~
1' -28-
, ~
88676
1 1, enhancement-mode polysilicon gate regions 13 which are
2 j covered on the sides with a protective layer of silicon
3 l~" dioxide 18 and on the top with an oxidation barrier layer
, 10 and oxide layer 9 as shown in Figure lG because the
~ etchant does not attack silicon dioxide or silicon nitride.
6 ¦I The defining regions of silicon dioxide 20 and 20' are pre-
7 ¦~ ferably retained over the polysilicon regions 22 and 23
8 ¦l, because they enhance the thickness of the dielectric in-
c ¦¦ sulation over the polysilicon regions as illustrated in
1I Fiqure lG.
11 ¦ The high concentration n-type source and drain
12 ! regions of both the enhancement-mode and depletion-mode
13 ¦I FETs are now formed by well-known ion implantation or
14 ! diffusion techniques. Exposed portions of silicon dioxide
layer 18 may be removed prior to implanting or diffusing
16 ! the souxce and drain regions of the FETs. Preferably the
17 ~¦ layer 18 is retained and the source and drain regions formed
18 ~I by implanting through exposed portions of layer 18. For
19 !i purposes of illustrating the present invention, ion implan-
2G ¦, tation has been selected. For instance, the n-type source
21 jl and drain regions 24 and 25 respectively of the enhancement-
22 ¦~ mode FET, and source and drain regions 26 and 27 respectively
23 1~ of the depletion-mode FET can be formed 2000 A deep by an
24 i As75 implant of about 100 KeV energy and 4X1015 atoms/cm2
! dose. It is noted that this dose and the resultant doping
26 ' concentration are about four thousand times greater than
27 1 that required for the n-type depletion-mode channel region
li .
... i'i ' '
~ 29-
-1088fi76
14 and lower capacitor electrode lS. This additional n-
2 , type implantation or diffusion is performed to provide th~ ,
3 I' high electrical conductivity necessary for the souree and
4 ¦; the drain regions of the FETs. This n-type doping does
not enhance the conductivities of the lower eleetrode 15
I of the eapacitor due to the bloeking aetion of the poly-
7 , silieon upper capacitor eleetrode 23 and its assoeiated
i portion of silicon dioxide 20, nor does it enhance the
9 ~ eonductivity of the depletion-mode channel region 14 due
¦I to the bloeking aetion of the polysilicon depletion-mode
~ FET gate electrode 22 and its associated portion of silieon
12 j dioxide 20'. The doping concentration providing the source
13 I regions 24 and 26 and the drain regions 25 and 27 is be-
14 ! tween about 10 and 100,000 times greater and preferably
1~ I between about 1000 and 10,000 times greater than the doping
16 I eoneentration employed in providing the doping for the de-
17 ! pletion-mode channel and the lower eleetrode of the storage
18 ~ eapaeitor. The n-type doping ions employed ean be the same
19 ! ehemieal species as those used for the depletion ehannel
I and lower electrode of the storage eapaeitor, or can be
2 li different n-type species.
22 Il The boundaries between the n-type source and
23 i drain regions and the channel of the FET are determined
24 ¦, by the polysilicon gate. This is generally referred to
1 in the prior art as the "self-aligned gate technique'~.
26 i With the gate self-aligned with respect to the source and
!
~7 ! drain, the parasitie gate to source and drain overlap
' .,
I -30-
8~76
1 capacitances are advantageously reduced over other FET
2 fabrication techniques. It is noted that the polysilicon
3 upper capacitor electrode 23, when desired, can be spaced
4 arbitrarily close or even overlap onto the polysilicon
gate 13 because regions 23 and 13 are formed in separate
6 lithographic steps.
7 Next, a dielectric insulation layer 28 is formed
8 above the polysilicon plate 23, above the depletion mode
9 gate 22, and above the n-type sources 24 and 26 and drains
25 and 27 as shown in Figure lH. Insulation layer 28 does not
11 form over the enhancement-mode gate 13. Formation of layer 28
12 also increases the thickness of the field oxide 3 in those
13 regions 28' not covered by polysilicon plate 23 or by de-
14 pletion-mode polysilicon gate 22. It is noted that the
insulation layer 28 does not affect to any serious degree
16 the n-type lower capacitor electrode 15 which is situated
17 under the polysilicon capacitor plate, nor the n-type
18 depletion-mode channel region 14 which is situated under
19 the polysilicon depletion-mode gate 22 as shown in Figure
lH. Layer 28 electrically insulates the subsequently
21 formed metallic-type line to the gates from the upper
22 capacitor electrode 23, and from the n-type source and
23 drain regions. Layer 28 also decreases the capacitive
24 coupling between the metallic-type interconnection line
and upper capacitor electrode, source, drain and sub-
26 strate regions. Accordingly, layer 28 should be as
27 thick as possible, but not so thick as to cause degradation
' ': '
-31-
1 1088676
', ,
1 '~ of or discontinuities in the conductive lines to any un-
i desired extent, nor so thick that the polysilicon gate 22
~ and capacitor electrode 23 are consumed during oxidation
4 ' to any undesired extent.
j The dielectric insulation 28 over the upper
6 ¦ capacitor electrode and over the n-type sources 24 and 26
¦ and drains 25 and 27 is formed by growing a silicon dioxide
8 ¦ layer 1500 to 5000 A thick by thermal oxidation at 1000C
9 i in the presence of steam. During this oxidation, about 600
I to 2000 A of the 3500 A thick polysilicon plate is converted
11 ! to silicon dioxide, and about 600 to 2000 A of the silicon
12 ¦¦ substrate over the n-type source and drain regions is also
13 ¦~ converted to silicon dioxide. The n-type sources 24 and 26
¦ and drains 25 and 27 are driven down into the substrate and
¦ laterally around the growing oxide as shown in Figure lH.
16 ! Since the ox;de tends to expel n-type dopants, the n-type
17 I dopant is not consumed to any significant extent during
18 I this oxidation. The top of the enhancement-mode gate 13
19 ¦l is protected from oxidation by an oxidation barrier layer
1, 10, whereas the sides of the gate 13 are subjected to the
21 1! oxidation which desirably provides protective insulation
22 ¦~ up to the nonoxidizing layer 10. During oxidation the
2~ ¦' thickness of the field oxide 3 in those regions 28' not
24 ' covered by polysilicon regions 22 and 23 is advantageously
! increased by about 500 to 1500 A.
26 ', Next, the enhancement-mode polysilicon gate 13
27 l is revealed. First, any part of layer 11 still remaining
I -32-
I .................... , ' .
-` ~(i88676
1 is now removed by a short time or "dip" etch in hydrofluoric
2 acid. Next, the silicon nitride oxidation barrier layer 10
3 over the gate is removed by etching in a phosphoric acid solu-
4 tion at 180C. Then, the thin oxide layer 9 is removed
by dip etching in a buffered hydrofluoric acid solution.
6 In fabricating FET integrated circuits, it is
7 necessary to connect high-electrical conductivity lines
8 to the polysilicon upper capacitor electrode, to the poly-
9 silicon depletion-mode gate, and to n-type silicon source
and drain regions. These connections do not occur in the
11 array of one-device memory cells, but are in the outer
12 lying addressing, decoding and sensing circuits referred
13 to as peripheral circuits.
14 The electrical connections are fabricated by
applying a photoresist layer to the assembly. The resist
16 material is exposed with ultraviolet radiation using the
17 lithographic masking pattern shown in Figure 2D, and the
18 unexposed regions of the resist are dissolved away. This
19 is the fourth basic lithographic masking step. Next, the
structure is treated to remove the portions of the silicon
21 dioxide not protected by the resist material. The wafer
22 is immersed in a solution of buffered hydrofluoric acid
23 to provide contact holes or vias 29, 30, and 31 through
24 the oxide insulation layer 28 to allow electrical connection
to be made to the drain 25 of the enhancement-mode FET, to
26 the polysilicon upper electrode 23 of the storage capacitor,
27 and to the polysilicon gate electrode 22 of the depletion-mode
-33-
- , . ' : . ' .. :
~ - , ' ,:: . ~
.- ~
518676
1 FET as shown in Figure lI. Source region 24 can, of course,
2 be contacted in the above-mentioned manner where desired.
3 Figure 2D also shows representative contact holes 32 and
4 33 to the source 26 and drain 27 regions of the depletion-
mode FET. The remaining photoresist above the etched
6 silicon dioxide is then removed by dissolving in a suitable
7 solvent. Now the n-type drain region 25, the polysilicon
8 plate region 23, and the polysilicon gate 22 of the depletion-
9 mode FET in the contact holes 29, 30, and 31, respectively,
also have been revealed for contacting. It is noted that the
11 sequence of removing nonoxidizing layer 10, and then etching
12 contact holes 29, 30, and 31 may be reversed without seri-
13 ously affecting the final structure. The polysilicon gate
14 of the enhancement-mode FET was previously revealed for
contacting by dissolving the oxidation barrier layer with
16 an etchant.
17 Next, the metallic-type high electrical conduc-
18 tivity interconnection line material 34, preferably a metal,
19 is deposited and the interconnection pattern is delineated.
An example of a highly-conductive material commonly used
21 for interconnections is aluminum which may contain relatively
22 small amounts of impurities introduced to decrease elec-
23 tromigration effects or to prevent or reduce chemical re-
24 actions between the aluminum and the semiconductive material
to be contacted. The high-electrical conductivity material
26 such as aluminum may be deposited by sputtering or, prefer-
27 ably, by evaporation.
-34-
s . ~ .
.
~88~76
1 It is noted that a barrier layer (not shown) may
2 be placed between the aluminum and the silicon or poly-
3 silicon semiconductive material to prevent or reduce chem-
4 ical reaction between the aluminum and the semiconductive
material. The barrier layer may be of a metal such as
6 titanium or chromium, or of an intermetallic silicide such
7 as platinum silicide or palladium silicide.
8 Next, a photoresist layer is applied to the
9 assembly. The resist material is exposed with ultraviolet
radiation using the predetermined mask pattern shown in
11 Figure 2E and the unexposed regions of the resist are
12 dissolved away. This is the fifth basic lithographic
13 masking step. Then the structure is treated to remove
14 the portions of the conductive material not protected by
the resist as illustrated in Figure lJ. When a barrier
16 layer is employed under the conductive material, the pat-
17 tern in the conductive material can serve as an etching
18 mask for delineating the barrier layer.
19 Figure 2E illustrates a top view of the mask pat- -
terns for an FET one-device memory cell and a depletion-mode
21 FET fabricated according to the present invention. The one-
22 device memory cell comprises an enhancement-mode FET switch,
23 and a charge storage capacitor. The depletion-mode FET may
24 be interconnected to the memory cell, or to other enhancement-
mode or depletion-mode devices to form peripheral circuits
26 on the same semiconductive substrate. Also, shown in Figure
27 2E are the mask patterns for representative electrical
28 connections through vias
.
..
, ::
. ~ . .-.
"11 1(~8~3676
1 jl to the drain of the enhancement-mode FET (i.e., the bit
~ 1 line of the memory cell), to the upper electrode or plate
3 ,~ of the storage capacitor, and to source, gate, and drain
4 I regions of a depletion-mode FET fabricated according to
j the present invention. Such representative electrical
6 ¦~ connections occur in the peripheral circuits.
7 ¦1 In other FET processes that use a conventional
etched contact hole for connnection between the metal word
9 ¦l line and the polysilicon gate of the enhancement-mode FET,
, extreme precision in registration between the contact hole
11 lithographic mask and the polysilicon gate lithographic
12 mask is required. Furthermore, since only that portion of
13 ' the enhancement-mode gate revealed by the etched contact
14 hole is available for contacting, precise registration be-
tween the contact hole lithogr'aphic mask and the inter-
16 ~ connection line lithographic mask is also required. In
17 I the "self-registering" enhancement mode gate contact tech-
18 nique employed in the present invention, the entire poly-
19 'I silicon gate electrode of the enhancement-mode FET is
¦i revealed for contacting and the metallic conductive material
21 !¦ need merely to cross over any portion of the enhancement-
22 l, mode polysilicon gate in order to make electrical connections
23 jj to it. Accordingly, this misregistration tolerant aspect
24 ,' considerably reduces the required degree of registration
, precision between the polysilicon enhancement-mode gate
26 ~ lithographic mask and the interconnection line lithographic
27 j mask.
Il . . . ' , .
88676
~,
1 Another advantage of the present invention is
2 that relatively smaller peripheral circuits may be fabri-
3 cated with the self-registered gate contact technique
4 than with conventional etched gate contact hole techniques.
As known in the art, further layers (not shown)
6 may be provided over the metallic-type layer 34 such as
7 sputtered silicon dioxide for the purpose of passivating
8 the integrated circuit. Furthermore, as is known in the
9 art, when desired, other masking steps may be used to pro-
vide vias through the passivation layer in order to make
11 contact to the metallic interconnection layer or to the
12 semiconductive substrate. Also, as known in the art,
13 electrical connection to the semiconductive substrate may
14 be provided by a metallic layer deposited by evaporation
onto the lower or backside surface of semiconductive sub-
16 strate 2.
17 Figure 3 shows the impurity profile under the
18 gate electrode of the depletion-mode device of the present
19 invention as predicted by the aforementioned numerical one-
dimensional computer model of Morehead. The same profile
21 will occur under the upper electrode of the charge storage
22 capacitor in the one-device cell of the present invention.
23 The profile illustrated is that anticipated after all
24 process steps have been completed. Presently, no experi-
mental technique is available that gives an accurate
26 measure of such low concentration profiles.
27 The depletion-mode channel doping of Figure 3
.
. ' : . .
~ 8867~;
1 consists of three parts; the uniform p-type boron substrate
2 doping, the n-type p31 depletion-mode channel doping, and
3 the p-type Bll enhancement-mode channel doping~ The two
4 channel doping concentrations are provided preferably by
ion implantation and are used to shift the gate threshold
6 voltage of the FET to more positive (p-type implant) or
7 more negative (n-type implant) voltage values. If the p-
8 type substrate doping concentration is sufficiently large
9 enough (e.g., about 2.5x1016 cm 3) the threshold voltage of
the enhancement-mode FET will be of the order of ~1 to +2
11 volts and no additional p-type doping in the enhancement-
12 mode channel region will be required. In the example con-
13 sidered here, a substrate doping of 7.5x1015 cm 3 is assumed
14 and both enhancement-mode and depletion-mode channel implants
are utilized. In the method of the present invention, when
16 it is used, the p-type enhancement-mode implant occurs in
17 the channel regions of both the enhancement-mode and
18 depletion-mode FETs. The n-type depletion-mode channel
19 implant occurs only in the channel region of the depletion~
mode FET. The threshold voltage of the depletion-mode FET
21 is of the order of -3 volts. Preferably the channel im-
22 plants are performed after forming the gate insulator which
23 in the example of Figure 3 was 500 A thick.
24 Figure 4 shows the circuit diagram of a depletion-
mode FET (D) and three enhancement-mode FETs (E) inter-
26 connected to form a driver circuit. Such a circuit could
27 be used, for instance, to provide the electrical current to
-38-
88676
1 1! the word line of the one-device cells of tne present invention.
2 I The depletion-mode device serves in this example as a non-
3 ,' linear load device to provide relatively more current per
4 l unit time and a larger voltage range during the on-off
i switching time cycle than a comparable enhancemen.-mode
6 1l load element. The depletion-mode load is also superior to
7 ¦¦ a linear resistive load in terms of both switching speed
8 ll and circuit density. The circuit of Figure 4 can be fab-
9 il ricated using the method of the present invention which
¦! provides both enhancement-mode and depletion-mode FETs.
11 ll Figure 5 shows another application of the pre-
12 l sent invention. In this case the depletion-mode FET (D)
13 is used as a current limiter to supply the DC bias to the
14 upper capacitor electrode which maintains an inversion
lS layer on the silicon substrate beneath the upper capacitor
16 1 e}ectrode of a one-device cell. Without the depletion-
17 mode device~in the event of an oxide flaw or defect, a
18 large current would flow from the upper electrode to the
19 ¦ lower electrode since the upper electrode is held at a
jl potential higher in absolute magnitude than the substrate.
21 ¦¦ The use of the depletion-mode device limits the defect
22 ~li leakage current. These calls are then not accessed or used
23 ~I on the chip, i.e., they remain dormant and do not affect
24 lll the chip operation as iong as their leakage current level
~ is tolerable.
26 1 An important aspect made possible by the present
27 j invention is that the electrode structure of the depletion-
Il _39_ ' ~
~:
676
i l! mode device can also be used to provide an ~lectrode struc-
2 I ture of a charge storaye capacitor in a one-device memory
3 'I~ cell. In addition to the resulting structural advantages
such as providing an upper electrocle over which thick oxide
insulation i5 formed and a self-re~istering gate contact to
j¦ the FET switch in the cell, the use of a low-concentration
7 !I n-type layer as the lower electrode of the charge storage
8 1¦ capacitors offers certain biasing advantages. In particular,in
9 11 other known devices in which the charge storage capacitor
~¦ is formed along with the enhancement-mode gate electrode
structure, an additional voltage level is required for the
12 I upper capacitor electrode to maintain an inversion layer
13 ¦ under the electrode at the surface of the semiconductive
14 substrate. Generally, the voltage supplied to the upper
capacitor electrode is larger in absolute magnitude than
16 ~¦ the voltage supplied to the word line and different in
17 ¦¦ plurality than that supplied to the semiconductive substrate.
18 ¦j When the doping employed to provide the channel doping for
19 ~¦ the depletion-mode FET is also used to provide the lower
2~ i¦ electrode of the charge storage capacitor according to the
21 il present invention, the threshold voltage necessary to
22 1¦ create a surface inversion layer is lowered, and a lower
23 jl~ voltage is required for the upper capacitor electrode.
24 !1 This reduction in the needed voltage for the upper capacitor
il electrode makes it possible to operate the word line and
26 ll the upper capacitor electrode at the same voltage level.
27 ~I This advantageously reduces two different voltage levels
.' jl ' ' ' , .
o
'!j
Il .
.
8~36~76
1 ,I to one. In addition, the required magnitude of the bias
on the upper electrode of the capacitor is reduced. This
3 .' in turn lowers the electric field strength across the
4 ,; capacitor dielectric and leads to higher reliability circuits.
., ,
I! :
, ~ .
!
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, .
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Il
