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Patent 1090425 Summary

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Claims and Abstract availability

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(12) Patent: (11) CA 1090425
(21) Application Number: 1090425
(54) English Title: DIGITAL RADIO RELAY SYSTEMS
(54) French Title: SYSTEME DIGITAL DE RELAIS RADIO
Status: Term Expired - Post Grant
Bibliographic Data
(51) International Patent Classification (IPC):
  • H04B 7/15 (2006.01)
  • H04L 1/22 (2006.01)
(72) Inventors :
  • ADDERLEY, JOHN A. (United Kingdom)
  • BESTER, DENNIS R. (United Kingdom)
(73) Owners :
  • GENERAL ELECTRIC COMPANY LIMITED (THE)
(71) Applicants :
  • GENERAL ELECTRIC COMPANY LIMITED (THE)
(74) Agent: SMART & BIGGAR LP
(74) Associate agent:
(45) Issued: 1980-11-25
(22) Filed Date: 1977-02-04
Availability of licence: N/A
Dedicated to the Public: N/A
(25) Language of filing: English

Patent Cooperation Treaty (PCT): No

(30) Application Priority Data:
Application No. Country/Territory Date
4730/76 (United Kingdom) 1976-02-06

Abstracts

English Abstract


-1-
ABSTRACT
In a digital relay system, a standby channel
is arranged to replace any one Or five operational
channels and the standby channel contains a variable
delay which is automatically controlled prior to change-
over to ensure that there is no slip or break in the
data of the switched channel. Preferably the data is
transmitted in a 'double-rate' binary code in which
binary 'O' is transmitted as '01' or '10' and binary
'1' is transmitted alternately as '00' or '11'.


Claims

Note: Claims are shown in the official language in which they were submitted.


THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A digital signal transmission system comprising
transmitting apparatus at a first station and receiving
apparatus at a second station for providing a plurality of
normal transmission channels and a standby channel between said
first and second stations, means for applying digital information
signals to the transmitting apparatus for transmission over the
normal channels, switching means for selecting digital informa-
tion signals in respect of any one of the normal channels for
transmission over said standby channel, means providing a
predetermined delay in each normal transmission channel, means
providing a variable delay in said standby channel, comparator
means for comparing digital information signals received over
said standby channel and said selected normal channel and for
adjusting said variable delay means until said received
signals are substantially in synchronism, and switching means
reponsive to an output signal from the comparator indicating
that said received signals are in synchronism to effect the
replacement of the selected normal transmission channel by the
standby channel.
2. A digital relay system as claimed in claim 1, wherein
the normal channel which. is to be replaced by the standby
channel is selected manually.
3. A digital relay system as claimed in claim 1, wherein
the channels include radio links.
4. A digital relay system as claimed in claim 1, wherein
the channels comprise land lines.
11

Description

Note: Descriptions are shown in the official language in which they were submitted.


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~his invention relates to digital relay
system~ and to apparatus for such system~. Such digital
relay systems may operate over radio links or over land
lines.
With digital relay system~ having a number of
channels it is often desirable to replace one of thé
channels with another ch~nnel while said one channel
is operating, and in such circumstances the problem
arises that some of the data being transmitted may be
10 lost, or some of the data may be transm~tted twice,
when the cha~geover to the other ch~nnel takes place.
hn object of this invention i~ to provide a
digital relay system which overcomes the above-mentioned
problem.
According to the present invention there i8
provided a digital signal transmission system comprising
transmitting apparatus at a first station and receiving
apparatus at a second station for providing a plurality
of normal transmission channelQ and a standby channel
20 between 3aid first and second stations, means for apply-
in~ digital information signals to the transmitting
apparatus for transmission over the normal channels,
switching means for selecting digital information sig-
nals in respect of any o~e Or the normal channels for
25 transmission oYer said standby channel, means providing
a predetermined delay in each normal transmig~ion
channel, means providing a variable delay in ~aid stand-
by channel, comparator mean~ for comparing digital
information siEnals received over said standby channel
~0 and said selected normal channel and for adjusting said
variable delay means until ~aid received signals are
substantially in synchronism, and switching means re-
spon~i~e to an output signal from the comparator
indicating that said received signals are in synchronism
~5 to effect the replacement of the selected normal
transmission channel by the standby channel.
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Preerably, a variable delay arrangement is
connected in the standby channel and is arranged to
ad~ust the phase of the data signal~ pa~sing along the
standby channel.
The control means may include means for com- ;~
paring the phase of the data signals passing along the
standby channel with the phase of the data signals
passing along the selected channel and providing an
error ~ignal which is used to adjust the phase of the
10 data signals passing alo~g the standby channel.
~he normal channel which is to be replaced ~-
by the standby channel may be selected manually or may
be selected automatically.
~he in~ention will now be described, by way
15 of example, with reference to the accompanying drawings
in which:-
Figure 1 i~ a bloc~ schematic diagram of a digi
tal r~dio relay s~stem in accordance with the invention;
and
~igure 2 i8 a block s¢hematic diagram of a ?
s~itching arrangement sho~n in block ~orm in ~igure 1.
Referring in the first instance to Figure l~the
~igita1 ~dl~ relay system co~prises five normal cha~nels
1 to 5 and a standb~ channel 6 which extend between
25 respective input terminal~ I and correspondIng output
terminals 0 and have their input terminals I connected
to associated fixed contacts of a rotar~ ~witc~ 7.
~he input terminals I of the five normal channels 1 to
5 are arranged to have applied thereto 'double rate''
30 binary signal~ o~ the ~ind described in co-pending
Canadian Patent ~pplication ~o. 211355. Such 'double
rate' binary signals carry the data of a normal binary
signal at twice the digit rate of the normal binary
signal, each digit of the normal binar~ signal ha~ing
~5 one particular binary value being represented in the
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'double rate' binary signal by a pair of digits having
the values '01' ~or '10') and the digits Or the n~rmal
binary signal having the other binary value being
represented by pairs of digits having the values '00'
5 and '11' alternately.
~ he input terminals I of the five normal
channels 1 to 5 are connected to the inputs of five
associated signal processing arrangements 8 each of
which is arranged to derive from the 'double rate'
10 binary signal applied to the input terminals I of the
associated normal channel, a normal binary sisnal and
a clock signal comprising a train of clock pulses.
Each signal processi~g arrangement 8 i~ also arranged
to convert the normal binar~ signal and the clock signal -~
15 into a *orm suitable for modulating an associated radio
channel 9 Or a radio link 10. A movable contact 11 of
the rotary switch 7 is connected to the input of a
standby signal processing arrangement 12 also arranged
to derive from a 'double rate' binary signal a normal
20 binary signal and a clock signal, and to convert theæe
signals into form suitable for modulating a standby
radio chaunel 13 of the radio link 10.
~ he output signals from each of the radio
channels 9 are arranged to be fed tO respective digital
25 processing circuits 14, each arranged to derive from an
output signal a normal binary signal and a clock signal.
Similarly, the output signal from the standby radio
chan~el 13 i8 fed to a standby digital processing
circuit 15 arranged to derive from the output ~ignal a
30 normal binary signal and a clock sisnalD The normal ~
binary signal~ and the clock signal~ from the proce~ing ~;
circuits 14 are fed to respective input leads 16 to 20
of a switching arrangement 21, the corresponding output
leads 22 to 26 of which are fed to respective circuit
35 arran~ements 27 for converting the ~ormal binary signals
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to 'dollble rate r binary signals. The normal binary
signals and the clock signals from the standby process-
ing circuit 15 are also fed to an input lead 28 of the
switching arrangement 21 a correspondiDg output lead 29
5 of which i~ fed to a standby circuit arransement 30 for
converting normal binary signals to 'double rate' binary
signals.
~ he po~ition of the movable contact 11 of the
rotary switch 7 is monitored and controlled by a monitor
10 and control arrangement 31 which i8 connected o~er an
auxiliar~ channel 32 of the radio link 10 to a further
monitor and control arrangement ~3 arranged to monitor
and control the operation of the switching arrangement
21.
Referring now also to Figure 2, the switching :-
arrangement 21 comprises five change-over switching
contacts 34 to 38 each having one fixed contact conn-
ected to one of the input leads 16 to 20 and its movable
contact connected to one of the output leads 22 to 26.
20 The other fixed contacts of the change-over contacts 34
to 38 are connected in common to the output of a variabb .:~
delay arrangement 39 to which an input is fed from
` input lead 28. ~he output of the variable delay arrange-
ment 39 forms one input of an error detector 40`which
25 receives another input by way of the movable contact 41
of a rotary switch 42 having fi~e fixed contacts each
connected to one of the input leads 16 to 20. ~he
output of the error detector 40 i8 fed to the input of .
a control logic circuit 43 ha~ing five output leadc 44
30 to 48 each of which controls the operation of one of the
change-over ¢onta~ts 34 to 38. ~ further output lead
49 controls the operation of the variable delay arrange-
ment 39. ~ ~: ~he apparatus desc~ibed above operates in the
35 following manner to effect replacement of the equipment
which forms a selected one of the normal channel~ 1 to : -
~'; , ' , . ' ' . ' . . ' .. :' ' ~, ' . ~

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5, say for example normal chAnnel 1, by the equipment
which forms the standby channel 6. When the normal
channel 1 which is to be replaced is selected the moni-
tor and control arrangement 33 passes a signal to the
5 control circuit 43 and also passes a signal o~er the
auxiliary channel 32 of the radio link to the monitor
and control arrangement 31. The monitor and control
arrangement 31 monitors the position of the movable
contact 11 and moves it so that it connects the input
10 termQnal I of normal ch~nnel 1 to the standby signalling
proces~ing arrangement 12, while the monitor and control
arrangement 33 monitors the position of the movable
contact 41 and moves it so that it connects the input
lead 16 to the input of the error detector 40. At
15 this time the po~itions of all the movable contacts of
the change-over switching contacts 34 to 38 are as shown
in Figure 2.
~ he error detector 40 therefore receives the
signals passing along normal channel 1 by way Or signal
20 processing arrangement 8, radio channel 9, digital pro-
cessing circuit 14t input lead 16, movable contact 41
and input lead 5~j and Plso receives the signals which
are applied to the input terminal I of normal channel ~:
1 but which pass along standby channel 6 by way of
25 movable contact 11, standby signalling processing
arrangement 12, standby radio link 13, standby digital
processing circuit 15, input lead 28 and the variable
delay arrangement 39 and input lead 51. The error
detector 4~ compares the phase of the signals received
30 over these two routes-and provides an error signal which
is fed to the control circuit 43 by wa~ of lead 52.
q'he control circuit 43 provide~ an output signal on
output lead 49 which ad~usts the delay provided b~ --
variable delay arrangement 39 until the phase Or the
35 data supplied to the error detector 4~:~by way of
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input lead 51 is bit synchronous with the phase of the
data ~upplied to the error detector 40 by way of input
lead 50.
The normal channel 1 and standby channel 6
5 are then synchronous and the signal fed to the control
circuit 43 by way of lead 52 produces an output sig~al
on lead 48 which operates change-over contacts 34. ~he
signals applied to input terminal I of normal channel 1
then pass by way of standby signal proce~sing arrange-
10 ment 12, 9tandby radio channel 13, standby digitAlprocessing circuit 15 to the associated output circuit
arrangement 27. ~hus the equipment forming standby
channel 6 is caused to replace the equipment forming
normal ch~nnel 1 without causing any significant ~lip
15 or break in the data which is being transmitted by the
replaced channel, ~n associated circuit arrangment
53 may be connected between each of the output leads 22
to 26 and 29 and the associated circuit arrangements
27 and 30 to reduce any ~jitter' being transmitted to
20 the output terminal 0.
~he apparatus may also be used to perform
- the reverse procedure, that i~ to say to ef$e¢t re-
placement of the equipment which forms the standby
channel 6 by the equipment which forms the selectea
25 normal channel 1. As before the error detector 40
receives signals passing along normal channel 1 by
way of sig~al proces~ing arrangement 8, radio channel
9, digital processing circuit 14, input lead 16, mov~
abl~ contact 41 and input lead 50, and also receives the
30 signals which are applied to the input terminal I of
normal channel 1 but which pass along standby channel
6 by way of movable contact 11, standby signalling
processing arrangeme~t 12, standby radio link 13,
: standby digital processing circuit 15, input lead 28~.
35 and the variable delay arrangement 39 and input lead 51.
~he error detector 40 compares the phase of the signals -~
. - .
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recei~ed over these two route~ and provides an error
signal which i~ fed to the control circuit 43 by way of
lead 52. The control circuit 43 provides an output
signal on output lead 49 which adjusts the delay pro-
5 vided by variable delay arrangement 39 until the phaseof the data supplied to the error detector 40 by way of
input lead 51 i8 bit synchronous with the phase of the
data supplied to the error detector 40 by way of input
lead 50.
The normal chan~el 1 and stPndby channel 6
are then synchronous and the signal fed to the control
circuit 43 by way of lead 52 produces an output signal
on lead 48 which operates changeover contacts 34 to
restore them to their originPl position. The signal~
15 applied to input terminal I of normal channel 1 then
pass by way of its signal processing arrangement 8~
radio channel 9, digital processi~g circuit 14, circuit
arrangement 53 to the output circuit arrangement 27.
Thus the equipment forming the standby channel 6 i8
20 replaced by the eguipment forming the normal channel 1
withou~ causing any significant slip or brea~ in the
data which i~ being transmitted the circuit arrangement
5~ acting to reduce any '~itter~ being transmitted.
~pically, the 'double rate' binary ~ignals
25 and the normal binary signals and cloc~ pulses are
transmitted at 139.264 megabits per second and the total
spread of the delay through digital sections is arranged
to be not more thAn l 3 digits or 21 nanos~econds. In
order that the variable delay in standby channel 6 is
30 always positive, channels 1 to 5 may be delayed by a
fixed delay o~ 3 digits or 21 nanoseco~ds. Thus the
delay produced by the variable delay arrangement 39
need be no more than from 0 to 6 digits or 0 to 42
nanoseconds in order to cater~for the maximum spread` of
35 delay~ between channels.
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The channel which is to be replaced by the
standby ch~nnel 6 may be selected manually or may be
selected automatically. The channels may include
radio links as described above or may comprise land
5 lines which may be conventional conductors or ma~ com-
prise optic ribres.
The most difficult combination of circumstances
i~ which to test for synchronism is in the high error '~
rate ~greater than 1 in 104), and quiescent data in the
10 traffic i.e. all l's or ~0~8 in the traffic except ~or
the frame alignment signal which is assumed to be'of the
form 1111101000000 occurring approximately every 3000
bits. In this case if the two data ~treams entering
the error detector 40 are not properly aligned then
15 no more than 4 errors (plus noise) can be guaranteed
in approximately 3000 digits. Thus the problem is to ~,
recognise the 1 in 103 error rate due to non-alignment
in the presence of a ~oise error rate greater than 1 in
104. In order to overcome this difficulty use is ~ ~
20 made of the fact that the four errors due to non-align- ~,
ment of the two data streams occur within a spread of
8 digits.
' ~he strategy for determi,ning alignment between
the two data streams entering the error detector is '~
25 thus as follows:
1. If 4 in any 8 digits are in error, i.e. not ~'g~
equivalent, the two data streams are not aligned ~ ~
or are not the same data. - ' '
2. If les~ than 4 in any 8 digits are in error for
~0 a period greater than the time between two frame
alignment signals, then the two data streams are
regarded as being ide~tical and in alignment.
~sing the above criteria the following situations ma~ -
be considered.-
35 1- If the two data stream~ are not aligned and the
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traffic approximate~ to random data, then oYer
a sample of 12 digit~ non-alignment will be de-
tected to a probability of approximately 99%.
2. If the two data strea~ are correctly aligned but
noise is producing a Poisson error rate of 1 in
102 the probability of more than 3 errors occurring
in a sample of 8 is approximatel~ l in 10~. Thus
over the time between the frame alignment signals
probability of a spurious detection of non-align-
ment i~ of the order o~ l in 1 ~ .
. If the two data streams are not aligned and all
traffic is quiescent, except the frame alignment
signal~, the probability of the frame alignment
signal being masked in a line error rate of 1 in
102 i8 approximately l in 25. 2
~hus in a noise error rate of l in 10
non-alignment can be detected in about 12 data bits or
approximately lO0 nanosecond~. If the band width of
the control loop of the variable delay is about 500 EHz
20 the time to change the delay by 1 bit i8 approximately
2 microseconds. ~u~ all 6 delay positions can be
sampled in about 10 micro~econd~. If data i8 all
'zero~' o~ 'one~" except for frame alignment 5ignal8
the time increases to about 100 microseconds with a
25 failure rate (depending on the 1 in 102 line error
rate) of l in 25. In lower noise conditions (l ~n
104 or better) the failure rate of correct alignment -
1B tO lower than l in lO~ or better.
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Representative Drawing

Sorry, the representative drawing for patent document number 1090425 was not found.

Administrative Status

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Event History

Description Date
Inactive: IPC expired 2015-01-01
Inactive: IPC from MCD 2006-03-11
Inactive: IPC from MCD 2006-03-11
Inactive: Expired (old Act Patent) latest possible expiry date 1997-11-25
Grant by Issuance 1980-11-25

Abandonment History

There is no abandonment history.

Owners on Record

Note: Records showing the ownership history in alphabetical order.

Current Owners on Record
GENERAL ELECTRIC COMPANY LIMITED (THE)
Past Owners on Record
DENNIS R. BESTER
JOHN A. ADDERLEY
Past Owners that do not appear in the "Owners on Record" listing will appear in other documentation within the application.
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Document
Description 
Date
(yyyy-mm-dd) 
Number of pages   Size of Image (KB) 
Cover Page 1994-04-13 1 30
Claims 1994-04-13 1 43
Abstract 1994-04-13 1 18
Drawings 1994-04-13 2 64
Descriptions 1994-04-13 9 428