Note: Descriptions are shown in the official language in which they were submitted.
109i~
This invention relates to a circuit for monitoring the
degradation of a digitally transmitted signal and more particularly to
one wh;ch is capable of a direct indication of very low error densities
in the regenerated signal.
Background of the Invention
During transmission, a binary signal suffers degradation
from such factors as intersymbol interference, random noise, tonal
interference and distortion. Consequently, a number of errors will
develop during regeneration as a result of an incorrect decision being
made in the regenerator. Since such errors are normally randomly
distributed throughout the pulse train, it is possible to statistically
determine the number of errors being generated by the transmission system
by periodically transmitting a known digit of a unique sequence and
conducting a parity check at the receiving terminal. To conduct such
parity checks however, requires that the transmitted signal be completely
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demodulated down to baseband in order to extract the known digits, and
then to compare them against a known sequence of the same digits in order
to derive the number of errors introduced by the transmission system.
Alternately, if duobinary or level coded correlative transmission is
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; 20 utilized, a check for violations in the predetermined rules of the
correlated pulse train can be made to determine errors. This is
described in an article entitled: "Faster Digital Communications With
Duobinary Techniques" by Adam Lender, Electronics, March 22, 1963,
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- pp.61-65. Again however, par;ty checking on a bit-by-bit basis of the
signal is required.
A study concerned with monitoring the performance of such
a system is described in an article by Benjamin J. Leon et al entitled:
"A Bit Error Rate Monitor for Digital PSK Links". Here, the monitoring
- method is based on the use of an artificial threshold for the decision
variable and the generation of a measurable "pseudoerror". Another
article dealing with the quality of service in digital transmission systems
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is one by G.S. Fang, entitled: "Alarm Statistics of the Violation Monitor
and Remover", BSTJ, October 1976, pp.ll97-1217.
In a typical digital radio system, employing a large number
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of relays located at relatively short distances compared to the overall
- length of the system, this requirement to completely parity check the
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baseband signal in order to determine the quality of the system along
~; each hop of the network is relatively expensive. Thus, while it may be
economically feasible to provide such a counter at each major terminal of
the network, such counters are not considered viable at each relay along
the transmission path. It is, howeverj still desirable to monitor the
performance of each radio hop in order that trouble on the system can be
readily located. A similar problem also exists in a cable transmission
system of digital information with the exception that the introduction
of errors results solely from deterioration of the equipment and not from
- fading along the transmission path.
Statement of the Invention
It has been discovered that an adaptive degradation of the
~- binary signal prior to regeneration can be utilized in conjunction with a
closed and constant error-rate feedback loop to realize a performance
; 20 monitor which is simple and yet capable of direct indications of very low
error densities.
Thus, in accordance with the present invention there is
provided a performance monitor for a degraded digital signal which
comprises: regenerators for regenerating the degraded digital signal
and the degraded digital signal offset against a d-c voltage. In addition
the monitor includes a comparator for detecting parity errors in the
digital state between the two regenerated digital signals; and a negative
feedback circuit, responsive to the output of the comparator, for varying
the magnitude of the d-c voltage in such a direction as to maintain a
substantially constant error rate between the two regenerated digital
signals. The magnitude of this d-c voltage is then a measure of the
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degradation of the incoming digital signal and hence the error density
introduced by the system. This d-c voltage is proportional to one point
~- on the probability distribution function of the restored linear
(unregenerated) signal.
Brief Description of the Drawings
An example embodiment of the invention will now be described
with reference to the accompanying drawings in which:
Figure 1 is a schematic circuit diagram of a performance
monitor in accordance with the present invention;
Figure 2 is an eye pattern of an idealized binary signal;
Figure 3 is a typical eye pattern of a received binary
signal having intersymbol interferencei and
-~ Figure 4 shows typical curves of loop error rates vs d-c
error voltage for various fade conditions of the incoming signal.
Description of the Preferred Embodiment
Referring to Figure 1, the performance monitor comprises
a pair of regenerators consisting of differential amplifiers Al and A2,
the outputs of which are connected to a parity comparator consisting
of an exclusive -NOR gate Gl. Amplifier Al functions as the primary or
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main regenerator thereby providing the regenerated binary output signal
at its output, while amplifier A2 functions as the secondary or
pseudo-error regenerator. The output of the gate Gl is fed to the input
of a negative feedback loop, generally 10, which controls the magnitude
of a d-c offset voltage fed to regenerator A2. The detailed structure
r of the performance monitor will be readily apparent from the following
description of the function and operation of the various elements therein.
` In this description, the error density or error rate of the regenerated
binary s-ignal refers to the ratio of error bits to the total number of
transmitted bits resulting from decision errors introduced in the
regenerator of the receiver. This ratio which is normally very low,
will increase dramatically during severe fading of the transmitted signal
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or deterioration of the transmitting and/or receiving equipment. It is to
be distinguished from the loop error rate or loop error density which is
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the ratio of the error bits to the total number of transmitted bits at
the output of the regenerator A2. This ratio is set by design parameters
of the feedback loop 10 and remains substantially constant during changes
in the error rate of the regenerated signal. However as explained
hereinafter, the d-c offset or error voltage in the loop will vary during
degradation of the incoming binary signal so as to maintain this loop
error rate constant.
In operation, a non-regenerated binary signal, such as from
the demodulator of a digital radio system, is connected in-phase to both
the "-" inputs of the regenerators Al and A2 which are both clocked in
parallel from a recovered clock source in the demodulator (not shown).
- Regenerator Al has its "+" input connected to ground while regenerator A2
has its "+" input connected to a source of variable d-c offset voltage.
A received binary signal at the input to the monitor, can
be viewed as having an idealized eye pattern as shown in Figure 2. The
concept of the eye pattern is discussed at length in an article entitled:
- "Correlative Level Coding For Binary-Data Transmission" by Adam Lender,
` 20 IEEE Spectrum, February 1966, pp. 104-115. However, due to band
limitations on the transmitted signal and other degradations introduced
by the system, a typical eye pattern of a non-faded signal coupled to
the input of the performance monitor, is as shown in Figure 3. Thus,
it is important to note that partial closure of the eye is observed even
under ideal transmitting conditions due to normal degradation of the signal
introduced by design limitations in the system. Since the signal is
relatively symmetrical, the slicing level of regenerator Al falls midway
between the "O" and "1" levels. On the other hand, due to the offset
voltage coupled to the "+" input of regenerator A2, the slicing level
under normal conditions is offset as shown in Figure 3. As will be
explained in detail hereinafter, this level is set by the negative
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feedback loop 10 to generate a predetermined bit error rate at the input
to the exclusive -NOR gate Gl.
With the slicing level of regenerator A2 set as shown,
parity between the regenerated signals is normally achieved at the
outputs of the two regenerators Al and A2. As a result, the output of
the exclusive -NOR gate Gl is normally held high. This generates a "1"
at the Q output of the D-type flip-flop FF when gated by the clock input.
. Transistor Ql is biased OFF whenever the Q output of the flip-flop isa "1". Consequently during this time, no current flows from the negative
source of voltage through the transistor Ql.
Due to the random distribution of noise on the binary input
signal and the offset voltage applied to regenerator A2, parity violations
or non-coincidence between the two signals will occur a small proportion
of the time. This causes the output of the exclusive NOR gate Gl to go
low which in turn causes the Q output of the flip-flop also to go low
(i.e. more negative than the bias voltage on the base of transistor Ql
which is set by bias resistors Rl and R2). At this point, transistor Ql
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` is turned ON and current flows from the negative source of voltage through
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a resistor R3 and transistor Ql into a capacitor Cl. Capacitor Cl in
conjunction with a resistor R4 forms a preintegration circuit whose
e function is to average the pulses sufficiently from transistor Ql to
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prevent the slew rate of the following differential amplifier A3, being
exceeded.
The output from the preintegrator is then fed to the main
;,~ integrator comprising a resistor R5 and a capacitor C2 in conjunctionwith the differential amplifier A3. The output voltage from the
amplifier A3 is determined by the bias on its "+" input which in turn
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'` is set by the voltage divider comprising resistors R6 and R7 connected
between the positive source of voltage and ground. The output of the
. 30 differential amplifier A3 is coupled through a diode Dl which is usedto prevent reversal of the d-c offset voltage during start-up of the circuit.
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The output of the diode Dl produces the error d-c output which, as will
be explained hereinafter, provides a measure of the system performance.
` The d-c output voltage from the diode Dl is coupled through a voltage
divider comprising resistors R8, R9 and a smoothing capacitor C3 to
the "+" input of the regenerator A2. Due to negative feedback within
the loop 10, the bias voltage at the input to regenerator A2, moves in
- a direction to establish a constant error rate at the input to the
flip-flop FF. This bit error rate is predominately set by the ratio
of the currents through resistors R3 and R4. In a typical application
: 10 the peak current ratio is (3.3x103):1 yielding a loop error rate which
; is the reciprocal thereof, i.e. 3xlO 4. As can be seen from the slicing
levels in Figure 3, only half-wave detection is used. This however is
an accurate reflection of one-half the total number of errors developed
in the regenerator because the received binary signal is symmetrical.
In a typical high capacity digital system, a 45 megabit
signal is transmitted over the radio transmission system. In order to
conserve spectrum bandwidth, the transmit signal is band limited in the
' transmitter. With additional noise and distortion generated in the
balance of the system, the eye pattern of an idealized (i.e. unfaded)
received signal is similar to that shown in Figure 3. This signal is
considered to be substantially error free with a bit error rate in the
regenerated signal of <<lxlO 16. Such bit error rates are extremely
difficult to monitor directly since the errors are so widely spaced in
time. However, during a severe fade of the transmitted radio signal,
the bit error rate can readily climb to >lxlO 4.
Referring again to Figure 3, it can be seen that the
offset voltage applied to the "~" input of regenerator A2 causes its
slicing level to differ from that of regenerator Al. As noise and/or
distortion on the system increases, the signal will suffer greater
perturbations, and the magnitude of the eye opening will be seen to
decrease. Since the negative feedback loop 10 attempts to maintain
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a constant bit error rate at the input to the exclusive ~OR gate G1,
the magnitude of the d-c offset or error voltage will decrease with
increasing noise so that the slicing level of regenerator A2 moves
` towards that of regenerator A1. This decrease in d-c error voltage is
therefore a measure of the magnitude of the eye opening which in turn
can be directly correlated with error densities at the input to the
monitor, although it does not directly detect individual errors.
Typical curves of error density at the output of the
flip-flop FF vs the corresponding output d-c error voltage, are shown
in Figure 4. When the loop error rate is high ~10-2, the d-c error
voltage at the output of the monitor is dominated by peak limited
intersymbol interference distribution (as indicated by the converging
' of the curves towards the top of the graph). On the other hand at low
, loop error rates <10 5 a point far down the noise distribution curve is
being monitored which is dominated by gaussian interference (as indicated
by crowding towards the lower left portion of the graph). In the initial
application, optimum performance of the monitor occurred with loop error
rates between 10 3 and 10 4.
Curve A of Figure 4 illustrates the normalized error voltage
, 2Q when the feedback loop is set for various loop error rates with an
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~ idealized received signal (one in which virtually no decision errors are
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. made in the regenerator Al). Curve G illustrates the normalized error
voltage for various loop error rates of a received signal which has an
error density of about 10 3. Such a signal would be experienced during
a deep fade of the transmitted radio signal. The other curves B - F
illustrate the normalized error voltage for binary signals between the
two extremes shown in curves A and G. This set of curves A - G is typical
: of those which would be obtained for flat gaussian noise interference on
~, the received signal. Tonal or monotonic generated interference willcause the entire set of curves to shift towards the left, while impulse
~ noise will cause only the lower portions of those curves to shift slightly
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to the left.
The intersection of the curves A - G with the horizontal
line H illustrates the normalized d-c error voltage at the output of
the monitor, with a selected loop error rate of 3xlO 4. This error
voltage can be readily translated into error density on the regenerated
binary signal for gaussian interference. Typical error densities which
would be monitored are shown in the following table:
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rate 3x10-4)NORMALIZED D-C ERROR DENSITY
A 0.50 ~10 16
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B 0.40 lxlO 12
C 0.30 lxlO 8
D 0.20 lxlO 6
E 0.12 lxlO 4
F 0.08 3xlO 4
G 0.05 lxlO 3
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It will be evident that this performance monitor measures
the change in eye opening caused by changes in the probability function,
and does not count the errors directly. However, such a check is a
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` relatively accurate indication of the overall performance of the system.
The above table illustrates that there is meaningful
variation in the d-c error voltage at extremely low error rates where
the system normally operates. In addition, the monitor responds
very rapidly to sudden increases in error density because the whole
digital pulse stream is being monitored rather than only a sample
portion as in the parity checkers or error counters of the prior art.
Also the feedback loop is non-linear as to rate of change of d-c
error voltage with respect to time. Thus any sudden increase in the
error density of the incoming pulse stream will cause a large number
of parity violations to develop at the output of the comparator until
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the system restabilizes at the loop error rate. In general therefore
` the perforrnance monitor will indicate the error density much quicker
;~. than an error counter which must average the results over a period :
. of time in order to determine the true error density.
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