Note: Descriptions are shown in the official language in which they were submitted.
16BACKGROUND OF THE INVENTION
17Field of the Invention
18The present invention relates to a circuit for subtracting or
19 obtaining a signal proportional to the difference between two quantities
of charge, and more particularly to a charge quantity differencing
21 circuit including a charge transfer device with a floating gate electrode
22 which provides a time-shared capacitor function.
-
23Description of the Prior Art
. 24Heretofore, the differencing of charge quantities normally
: 25employed circuits including two capacitors wherein the two quantities of
26 charge are stored on sep OE ate capacitors and are converted into two
27 corresponding voltages, one of which is then subtracted from the other.
.. :
' Y0976-081 -1-
.
, . . _ , ,,
,
,,,,, , ,.. =~
,j:~., . , :
` " '' ' ~ :,
' " ' " "
.
, '
. ~ ~
10~94~)9
1 An example of a circuit of this type is described in the publication
"Magnitude Differencing Circuit", by D. L. Critchlow et al, in the
3 IBM Technical Disclosure Bulletin, Vol. 18, No. 9, February 1976 at
4 page 3071.
Two capacitor circuits exhibit the undesirable feature that
6 the two capacitors may have inherently different characteristics which
7 effect the charge stored thereon, and when the two resultant voltages
8 are subtracted the effect of the characteristic differences is included
g in the difference voltage as a distortion and poses a limit on the accuracy
10 - of the circuit.
11 The present invention is distinct from the two-capacitor
12 devices of the prior art in that it is embodied with a single time-shared
13 floating gate capacitor. Since both charge quantities are sequentially
14 placed on the same capacitor there is no tracking error which might
arise if the charge quantities were placed on two separate capacitors.
16 The use of floating gate techniques in charge-coupled devices
17 have been shown in the prior art however, no references are known which -
18 employ a floating gate as a time-shared capacitor for-charge differencing.
19 A typical example of a floating gate in a charge-coupled device environ-
ment is shown in U.S. patent 3,623,132, issued November 23, 1971, to
21 R. D. Green on an application filed December 14, 1970, and assigned to
22 North American Rockwell Corporation. This patent is cited as being of
23 general background interest and does not relate to the-use of a time-
24 shared-capacitor function for charge differencing.
.
SUMMARY OF THE INVENTION
26 An object of the present invention is to provide a charge
27 transfer device employing a single time-shared capacitor for charge
28 differencing.
Y0976-081 -2-
,
.
10~94~9
1 Another object of the present invention is to provide a time-
2 shared capacltor charge differencing circuit~wherein tracking and non-
3 linearity errors are cancelled.
4 A further object of the present invention is to provide
a charge transfer circuit for comparing two charge quantities on a
6 single capacitor nondestructively.
7 The foregoing and other ob;ects, features and advantages
8 of the inventlon will be apparent from the following more particular
9 description of preferred embodiments of the invention, as illustrated
in the accompanying drawings.
11 BRIEF DESCRIPTION OF THE DRAWINGS
12 FIG. 1 is a partial schematic illustration of an embodiment of
13 a charge transfer circuit including a time-shared capacitor for charge
14 differencing.
FIG. 2 is a schematic diagram of an equivalent circuit of the
16 device shown in FIG. 1.
,
17 DESCRIPTION OF PREFERRED EMBODIMENTS
18 -In charge transfer device technology involving charge coupled
19 devices and bucket brigade devices, an often required function is the
determination of the difference between two charge quantities. Since
21 there is no effective way of directly subtracting one charge packet from
22 another, a simple approach is to convert the charge packets to voltages
23 and then subtract. Heretofore, the conventional approach was to introduce
24 the two charge packets to two capacitors and then determine the difference
between the resulting voltages. Since the characteristics of the two
26 capacitors are never identical, an inherent capacitor tracking error and
27 non-linearity error will be present in the difference voltage.
Y0976-081 - }
~ sss;l~s
1 FIG. 1 illustrates an embodiment of an n-channel charge
2 traasfer device wherein a single capacitor function of a floating gate
3 electrode is time-shared by the two charge packets and a difference
4 voltage is produced which avoids the aforementioned errors. Charge
coupled devices are well known in the art as are the techniques for
6 charge retentlon and transfer used in the description of the embodiment
7 of FIG. 1, and need not be described in detail.
8 More particularly, FIG. 1 shows a schematic view of a charge
g coupled device embodiment on the invention including semiconductor
substrate 10. A plate 12 of capacitor 14 i9 disposed over semiconductor
11 substrate 10 and insulated from semiconductor substrate 10 by an insulating
12 layer, for example silicon dioxide or a silicon nitride. Plate 12 is -
13 referred to as a floating gate Connected to it is a total loading capaci-
14 tance CL. Plate 12 is connected to a bias voltage source 13 through
switch 15. With appropriate bias voltage on plate 12, the region sub-
16 jacent plate 12 in the silicon surface becomes what is referred to in
17 the art as a potential well in which mobil minority charge carriers can
18 be stored, entered, or removed by charge transfer techniques. The
19 mobile charge carriers in the potential well plus the immobile charge in
the depletion region of the potential well form the second plate of
21 capacitor 14. The potential well is represented in FIG. 1 as region 16.
Z2 Two charge transfer electrodes 18 and 20 are disposed over
23 semiconductor substrate 10 on either side of plate 12. Transfer electrodes
24 18 and 20 are connected to pulse sources such that quantities of charge
may be transferred into and out of potential well 16 in response to
26 transfer pulses applied to electrodes 18 and 20.
Y0976-081 -4~
-
~(i. 94~9
1 Additional electrodes 22 and 24 are disposed over semiconductor
2 substrate 10 on the opposite sides of transfer electrodes 18 and 20 and
3 are connected to voltage sources to create respectively potential wells
4 26 and 28 which serve to store quantities of charge carriers which may be
transferred into or out of potential well 16.
6 In operation, assume that the difference is to be determined
7 between a charge quantity deslgnated as charge packet Q and a different
8 charge quantity designated as charge packet Qb. Initially, one charge
9 packet, for example Q , is stored in potential well 16, having been
transferret therein at a previous time to. In order to effect the
11 transfer of charge packet Qa i~to potential well 16, switch 15 is temporarl-
12 ly closed to establish the patential well 16 under plate 12. At the
13 completion o the transfer of charge packet Qa into potential well 16
14 plate 12 and output terminal 30 have an initial voltage condition, and
switch 15 is open, allowing plate 12 to float.
16 The second charge packet Qb is initially stored in potential
lJ well 28, having been inserted therein by conventional charge coupled
18 device charge transfer techniques well known to those skilled in the
19 art.
At a time tl a clocking pulse is applied to transfer electrode
21 18 causing charge packet Qa to be transferred from potential well 16 and
22 into potential well 26. After a sufficient time to allow the clocking
23 transients to decay, the transferring of Qa out from under plate 12
24 produces a proportional increase in the floating gate voltage at terminal
30 as follows:
Q C
26 V , a ox
[ t ( COX + C )] (COX + CL) (1)
Y097~-081 -5-
". . .
.
~a~s~s
1 where CL is the previously mentioned loading capacitance,
2 COX is the oxide capacitance of capacitor 14,
3 Cd is the non-linear depletion capacitance of capacitor 14.
4 At a time t2 a second clocking pulse is applied to transfer
electrode 20 and charge packet Qb is transferred into potential well 16,
6 which,after transient decay, produces a proportional decrease in the
7 floating gate voltage as follows:
b C C
[ ( C~x + CL ) ] L (2)
9 Thus, a net change in the floating gate voltage ~V results
that is related to Qa ~ Qb; to the extent that non-linearities are
11 small,
12 ~V a (Qa ~ Qb) (3)
13 Any error in the difference voltage as a result of the non-
14 linearity of Cd can be minimized by using a lightly doped substrate and
i~ particularly minimized when ~V is small. Since the capacitance 14 -
16 between the floating gate and the substrate 10 is time-shared by both Qa
17 and Qb' the tracking error which would exist between two unmatched
18 capacitors is non-existent. In the specific case where it is only
l9 - desired to determine which of the quantities Qa and Qb is larger, any
non-linearities will not effect such a determination.
21 Another import-ant feature of the present invention as embodied
22 in FIG. 1 is that the difference voltage QV is independent of the relative
23 amplitudes of the clocking pulses applied to transfer electrode 18 at t
24 and transfer electrode 20 at t2. The two clocking pulses may have
different amplitudes, which is the usual situation in~practice, but as
~ .
Y0976-081 -6-
~q9g~g
1 long as each pulse returns to its o~iginal level the difference voltage
2 ~V will not be affected. Although the charge transfer functions were
3 described using clock pulses applied to electrodes 18 and 20, alternative
4 techniques known in the art, such as varying the potential on electrodes
22 and 24, may also be used.
6 FIG. 2 is a schematic illustration of the equivalent circuit
7 of the structure of FIG. 1 showing the relative arrangement of the C x'
8 Cd and-CL parameters.
9 The present invention can have wide application as a differencing
circuit in many charge transfer device systems such as analog-to-digital
11 and digital-to-analog converters. Also, if only an indication of the
12 greater of Qa and Qb is desired, as in comparator circults and many
13 analog-to-digital converters, the polarity of ~V can be detected accurate-
14 ly by a non-precision high gain amplifier and latch.
Although the embodiment of FIG. 1 employs an n-channel charge
16 coupled device structure a p-channel device structure may also be employed.
17 Also, one skilled in the art will appreciate that an equivalent bucket
18 brigade device structure can be used rather than a charge coupled device.
19 While the invention has been particularly shown and described
2~ with reference to preferred embodiments thereof, it will be understood
21 by those skilled in the art that the foregoing and other changes in form
22 and details may be made therein without departing from the spirit and
23 scope of the invention.
YO976-081 -7-
