Note: Descriptions are shown in the official language in which they were submitted.
PHN. 871~.
dZ~Z3
The invention relates to a semiconductor
device having a semiconductor body comprising an
integrated circuit having a number of semiconductor
circuit elements in which at least a part of the
surface of the semiconductor body has a first elec-
trically insulating layer, a first metallisation
pattern which is sunk in the first insulating layer
and the surface of which coincides substantially wi~h
that of the first insulating layer, a second insula-
ting layer overlying the first insulating layer andthe first metallisation pattern~ and a second metal-
lisation pattern overlying the first metallisation
pattern and being separated therefrom by insulating
material.
The invention also relates to a method of
manufacturing such semiconductor devices.
It is to be noted that where in this appli-
cation there is referred~to a metallisation pattern,,
said metallisation pattern need not necessarily con-
sist of a metal but ma~ also consist of polycrystal-
; ~ ~ line silicon or similar conductive materials~
Semiconductor devices having several metal-
lisation patterns are used in particular when a num-
ber of circuit eleman~s have to cooperate in an
integrated circuit. In such cases, one metallisation
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~ - 2 -
~ z3 PHN 8718
pattern is often not sufficient for the contacting
and the interconnection of the various circuit ele-
ments.
The use of several metallisation patterns
may solve this problem. In this case, a first metal-
lisation pattern which is connected to the zones of
the semiconductor elements ia contact windows is
situated on an insulating layer covering the semi-
conductor body. On said metallisation pattern is -
situated a second metallisation pattern which is
separated from the first metallisation pattern by a
second insulating layer and is contacted therewith,
where necessary, vla contact windows.
The disadvantage of said solution is that
the ultimate surface shows unevennesses and, in places
where crossing connections occur, the second metalli-
sation pattern can hardly be provided in such manner
that said metallisation in said places is sufficiently
reliable. Said reliability problems may result from
mechanical stresses in the metal or from insufficient
layer thickness of the metallisation in said places.
A semiconductor device of the kind mentioned
in the preamble in which said disadvantages are miti-
; gated is disclosed in British Patent 1,286,737 by ITT
Industries Inc. and published on August 23, 1972~
In said disclosed device a first electrically
insulating layer is situated on the surface of the
semiconductor body, in which
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PHN~8718
20,1.78
Z3
layer a first metallisation pattern is sunk the
surface of which coincides substantially with the
surface of the first insulating layer. The metallisation
pattern is sunk throughout the thickness of the first
insulating layer and hence contacts the underlying
semiconductor zones. Situated on said first insulating
layer and sai.d first metallisation pattern are a
second insulating layer and a second metallisation
pattern which is separated from the first metallisation
pattern by insulating material.
The disadvantage of the said device is
that the first metallisation pattern is sunk in the
first insulating layer throughout its thickness and
hence is in direct contact with the semiconductor body.
This means that the shape of said first metallisation
pattern is strictly limited by the layout of the
- underlying circuit elements; generally, semiconductor
junctions occur herein which are exposed at the surface
and can be shortclrculted by an overlying~part of the
metallisation pattern.
A second disadvantage is that the second
metallisation pattern is~sunk entirely in the second
insulating layer so that an insulated crossing
connection between a conductor track of the first
:: . .i
metallisation pattern and a conductor track of the
second metallisa-tion pattern is not possible as such.
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PHN.8718
20.1.7g
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It is the obJect of the invention to remove
said disadvantages entirely or partly.
The invention is based inter alia on the
recognition of the fact that the first metallisation
pa-ttern can be simply provided in such manner that
no undesired contact occurs with the underlying
semiconductor zones, in which it is even possible
to save a mask in manufacturing such semiconductor
devices.
~ 10 According to the invention,a semiconductor
; device of the kind mentioned in the preamble is
therefore characterlzed in that only the second
metallization pattern contacts at least one semi-
conductor zone belonging to the semiconductor circuit
elements via at least one contact hole in the
underlying insulating layer, and the first metallisation
pattern is sunk in the first insulating layer only
over a part of its thickness.
Since the first metallisation pattern is
sunk in the flrs~t insulating layer only over a part
of its thickness~ this can no longer directly contact
:
the underlying semiconductor zones in undesired places
so that no possibility of undesired~shortcircuit
exists any longer.
Contact windows may be provided in the second
insul2ting layer and may be restricted, for example,
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PHN.871
20.1.78
~Z~23
to said second insulating layer, as is the case,
~or example, when the second metallisation pattern
contacts only the first metallisation pattern via
such a contact window. Advantageously9 however,
a contact window may also be provided through the
two insulating layers.As a result of this, the semi-
conductor zones can be contacted with the second
metallisation pattern via said contact windows and
hence zones o~ various circuit elements can be inter-
connected via said second metallisation pattern.
Since, according to the invention, the second
metallisation pattern overlies the first metallisation
patternand is separated therefrom by insulating material,
crossing connections are possible as such in a semi-
conductor devioe according to the invention. There~ore,
a pre~erred embodiment according to the invention is
I characterized in that at lcast one track of the first
¦ metallisation pattern crosses a track of the second
metallisation pa-ttern.
¦ 20 An elegant improvement of said structure
is furth~rmore obtained when the contact windows,
via which the second metallisa-tion pattern contacts
the semiconductor zones, are provided only in the
second insulating la~er so that a more compact
structure is possible due to smaller tolerances.
Thi~ oan be reali-ed in a partlcular preferred embodilllent
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- PHN.B71g
20.1.78
according to the invention in which the'semiconductor
elements directly underlie the second insulating
layer and are surrounded by the first insulating
layer. Therefore, this preferred embodiment is
characterized in that the first electrically
insulating layer consists of a layer-shaped pattern
of electrically insulating material which lS locally
sunk ln the semiconductor body at leastpartly.
' According to the invention, the metallisation
shapes are'cho'sen to be so that the semiconductor
zones are connected only to the second metallisation
pattern via -the said contact windows. As will become
apparent hereinafter, this may save a mask in the
manufacture of the semiconductor device as compared
I 15 with prior art methods of manufacturing such semi-
`¦ ' conductor devices.
' Alternatively, a part of''the first metallisation
¦; 'pattern may be proportioned so that as a result of this
' a plate-shaped part 15 formed whlch Porms par~ of a
; ? capacitorO Such a capacitor can~often be used effectively
in integrated~clrcuits,~for example, in manufacturing
a memor~ element. A further preferred embodiment
according to the lnvention lS therefore characterized
in that a part of the first metallisation pattern forms
part of a capacitor.
; ~ The invellt~on furthermore relates to a very
sultable method ~f manufacturing semiconductor elemen-ts
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20.1.78
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as described above. Aeeording to the invention, said
method is eharaeterized in that a number of semi-
eonduetor eireuit elements having zones adjoining
a surfaee of the semieonductor body are provided in
a semiconductor body, that the surface of the semi-
' conductor body is provided at least partly with a
first electrically insulating layer, that said first
insulating layer is provided, by a materlal-removing
treatment, with grooves extending only over a part of '
the thiekness of the first insulating layer, that, in
order to form a first metallisation pattern, a first
- eonduetive layer is then provided in the grooves in sueh
a thiekness that the su'rfaee of the first eonduetive
` layer coincides substantially with that of'the first
. .
~ 15 insulating layer, that a seeond eleetrieally insulating
i layer is then provided on the first insulating layer and
l the first conduetor layer,'after which a seeond conductive
!
¦ layer is provided on the second insulating layer'and is
~l ~ given;the shape'of a ~seoond metallisa-tion pat-tern, and
~that contact hDles~are~provlded in the two electrleally
~ ' insulating ~ayers,via~whieh~contaet holes the seeond
I ~ metallisation pattern adjoins one or more zones of
the semleonductor elementsO
The lnvention-~ill now be deseribed in greater
detall wlth reference to a few embodiments and the
~¦~ drawing9 in whieh ~ ~
Fig.1 i6 a plan view of a semiconduetor deviee
accordlng to the lnvention,
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PHN.8718
20.1.78
23
Fig. 2 is a diagrammatic cross-sectional vie~
of the semiconductor device shown in Fig. 1 taken on
the line II-II,
Fig. 3 is a diagrammatic cross-sectional view
5 ~ of another embodimen-t of another semicondùctor device
according to the invention with the same plan view
as shown in Fig. 1 and taken on the same line II-II)
Figs. 4 to 7 are diagrammatic cross-sectional
viewsof the semiconductor device shown in Fig. 1 in
successive stages of a manufacturing method according
to the invention9
FigS. 8 to 11 are diagrammat:ic cross-sectional
views of a semiconductor device with two metallisation
patterns in successive steps of manufacture of a known method.
The figures are diagrammatic and not drawn
to scale in which for olarity in particular the
dimqnsions in the direction of thickness are strongly
exaggerated in the cross-sectional views. Semiconductor
I ~ reginns of the same conductivity type are generally
I ~ shaded in the same directlon in~the cross-sectional views;
in the figures, corresponding components are further
referred to generally by the same reference numerals.
i:
Fig. 1 is a plan view and Fig. 2 a
diagrammatic cross-sectlonal view taken on the llne
II-II of a semiconductor device according to the
invention. The device comprises a-semiconductor
- . .
body 1 having an integrated circuit with a number of
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¦ PHN 8718
~ 1g~ 77
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,
semiconductt?r elements in which at least a part
of the surface 2 of the semiconductor body has a
first electrica.Lly insulating layer 3.and a first
metalli~satio.n pattern 4 which is sunk in the first
electrically insulating layer and the surface of
which coincides substantially with the surface5 of
the first insulating layer,
In this example the semiconductor
body consists of silicon, the first insulating layer
- 10 of silicon oxide and the first metallisation pattern
of aluminium. In this example the semiconductor
circuit elements are formed by bipolar transistors
~ having a collectsr zone 10, a base zone 8, an emitter
: zone 9 and a collector contact zone 11 and by a
capacitor (4b, 7b). The first insulating layer in
thls example is formed by a pattern 3 of electrically
insu].ating ma'-erial, in this example silicon oxide~
. ~ which lS locally sunk at least partly in the semicon-
. , ductor body.
~ 20 .The semiconductor body 1 furthermore
I , comprises alsecond insulatlng layer 6, in this example
, of silicon oxide 3 overlying the first insulating layer
3 and the first metallisation patl,ern 4, and a second
metallisatlon pattern 7 overlying the first metallisa-
,
tion pattern 4 and separated therefrom by the insula-
. ting material o~ the layers 3 and 6, at least one of
~ ~ ,
¦ the metallisation patterns, in this example pattern 7,
,
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PHN 871g
18.8.1977
23
; contacting semiconductor zones (8, 9, 11) belonging
to the semiconductor circuit elements.
I In this example the semiconductor
¦ body 1 consists of a s~lbstrate 1lf~ on which an
epitaxial layer lO is provided. In this example,
the sunken oxide pattern 3 is provided in said
epitaxial layer and extends down to the substrate.
In this example the sunken oxide is also the
first electrically insulating layer. Transistors
are provided in the epitaxial layer. In this example
the substrate 1If~ is ~-type. The collector zones 10
are n-type, in which, in order to reduce the
collector series reslstance, h~hly doped n-type
bur~ied ; layers 15 are provided. The base zones
! 15 8 are ~-type, while the emitter zones 9 and the
.
collector contact zones 11 are n+ -type. The surface
2 which bounds the semiconductor material is not ~lat
1: .
in this example, as show~ ln Flg. 2,but is more or
e 9 8 crenelated. ~
~ ~According ~to the in~ention, the
first metallisation~pattern 4 is not sunk in the
~ :~
first lnsula-ting Layer~throughout its thickness but
onIy over a~part of~its thickness. As a result of
this the important advantage is obtained that the
first~ metallisation pattern can no longer directly
!: : ~ I ~
l contact the underlyLng semlconduotor zones undesirably
¦ and can cause short-circuits therein. In this example,
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PHl'J 871~
18.8.1977
9Z3
contact windows 12 are provided in the insulating
material, v~a which windows parts of the second
metallisa-tion pattern 7 contact semiconductor zones
(8, 9, 11) belonging to the semiconductor circuit
1 5 elements.
¦ In this example the -track 4a of
¦ the first metallisation pattern forms a crossing
connection with the track 7a of the second metallisa-
tion pattern 7.
In this example, only the second
I metallisation pattern 7 is connected to the semicon-
ductor zones of the semiconductor body via contact
¦ windows 12.
- The part 4b of the first metallisa-
tion pattern ln this example constitutes a plate of a
capacitor. A part 7b of the second metallisation pat-
tern forms the second plate of the capacitor, the
second insulating layer 6 s-erving as a die]ectric.
In ~ther embodiment of the same
plan view as Fig. 1 but a cross-sectional view as
shown in Fig. 3, the insulating layer 3 is not formed
by a sunken oxlde pattern but by a thick layer of
silicon oxlde which is provided on the semiconductor
body. In this example the surface 2 is covered
entirely with an ins~lating layer 3. The transistors
are separated by separating zones 13 which may consist,
for example, of sunken oxide. In the example of Fig.3,
,
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PHN 8718
18.8.1977
~Z~;~3
however, said isolation zones consist of ~-type
zones 13 which form a ~-nJunction 16 with the
adjoining semiconductor material, which junction
is reversely biased in the operating cnndition.
In both embodiments the first
metallisation pattern 4 is sunk in the insulation
layer 3 but on;y over a part of the thickness of
said insulation layer 3. Herewith the contact with
~ the underlying sem;conductor zones is avoided, while
¦ 10 the surface of said first metallisation pattern 4
coincides substantially with the surface 50f the
insulating layer. The second metallisation patcern 7
is separated from the first metallisation pat-tern 4
by the second insulating layer 6, which enables
- 15 crossing connections (4a, 7a in Figs. 1, 2, 3).
The device according to the inven~
tion as shown in Figs. 1 and 2 can be manufactured
I as fol~s according to the invention.
I ~ A number of semiconductor circuit
elements having zones adjoining the surface 2 of a
semiconductor body 1 are provided. in the semicon-
~'~ ductor body.
For this purpose, there is started
from a semiconductor body, in this example a ~ t~e
si.licon substrate 14 ~Fig. 4), having a resistivity
bet-~een 2 and 5 Ohm.cm. At the area of the coîlector
¦ zones to be formed, burled layers 15 are provided, for
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I PHN 8718
1 18.8.1977
~L3L'~Z9~3
, example, by arsenic deposition. In this example~
I said buried layers have a thickness of approxima-
tely 3 micrometers and a sheet resistance between
25 and 30 Ohm per square. An n-type epitaxial
~ 5 layer 10 having a resistivity of approximately 1
¦ Ohm.cm and a thickness of approximately 2 micro-
¦ meters is then provided on the semiconductor body.
( An electrically insulating layer 3
¦ is then sunk in said epitaxial layer. This may be
done9 for example, by selectively etching the
silicon down to a depth of approximately 1 micrometer,
for example,in an etching mixture containing hydro-
fluoric acid and nitric acid, or by means of plasma
¦ etching. A silicon nitride mask, for example is
~ 15 used as an etching mask. Local oxidation is then
¦ applied in a wet nitrogen atmosphere at a tempera-
ture of l000C, while masking by the silic~n nitride
mask. The resultlng oxlde pattern has approximat~
twice the volume of the oxidized silicon. This
~ , ~
treatment is continued until the~thickness of the
~ sunken pattern i9 approximately~2~microneters.
¦ ~ The epitaxial layer is now divided into a number
,
of collec-tor~regions lO which are separated from
l each other by th0 sunken oxide 3. The semiconductor
¦ 25 body 1 whoss surface 2 is not flat, as stated above,
but is more or less crenelated is provided herewith
at least partly with an electrically insulating
! layer 3.
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18.8.1977
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~.
Base zones 8 are -then provided
in the collector zones 10, for example, by means of
boron diffusion. The base zones have a thickness of
approximately 0.8 micrometer and a shee-t resistance
between 200 and 800 Ohms per square, in this example
400 Ohms per square.
! Emitter zones having a thickness
of approximately 0.5 micrometer and a sheet resis-
tance of approximately 20 Ohms per square are then
provided in said base zones. Simultaneously with the
provision of said emitter zones which are obtained,
for example, by means of diffusion, collector contact
zones 11 are provided in the collector regions 10.
Herewith the semiconductor device as sho~4~n in Fig. 4
is obtained.
The first electrically insulating
layer 3 is now provided with a pattern of grooves 23
by a material-removlng treatment, for example, by
chemically etching or -plasma etching down to over a
part of the thlckness of the layer 3, in this example
to 0.7/um. A first conductive layer ~, is then pro-
~idedlin said grooves so as to form a first metalli-
sation pattern. This may be done, for example, by
sputtering or vapour-depositing a conductive layer,
~5 for example aluminiumj while using the same mask
which was used for defining the grooves, so that
the~grooves are filled wlth aluminium until the sur-
face o the conductive layer 3 coincides substantially
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p~J ~71~
1~.8.1977
~Z~23
with that of the first insulating layer 3.
As a result of this, the metal
o~ the first metallisation pattern4 can advan-
tageously be provided with the same mask which
is used ~or defining the grooves.
According to a preferred embodiment
¦ of the method, said metallisation pattern may be
provided by providing an auxiliary layer 22 (Fig. 5)
on the first electrically insulating layer. A pattern
23 corresponding to that of the grooves to be provided
is then provided in said auxiliary layer. In this
~ - example said pattern 23 is provided in an auxiliary
¦ ~ layer of photosensitive material by means of known
- photochemical methods in a thickness of approximately
¦ 15 1 micrometer. Using the auxiliary layer 22 as a mask,
¦ grooves are provided according to the pattern 23 in the
I first electrically insulating layer, in this example
¦~ consisting of silicon oxide, by means of a chemical
¦ ~ etching -treatment or ~a plasma etching, down to a
1~ 20 depth of approxi~tely 0.7 micrometer (Fig. 5)~
!
A layer 24 of conductive material,
thickness approxiniately 0.7 mlorometer, is then
.
provided over the whole surface, for example, by vapour-
depositing aluminium from a preferably punctiform
source a-t a substrate temperature of 150C. Said alu~
:: :
minium is deposited in the~grooves in the apertures o~
i
~ the pattern 23, while else-~here on the auxiliary layer
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PHN 8718
~ 8.1977
23
it remains (Fig. 6). Said auxiliary layer is then
removed, for example, by boillng in smoking nitric
acid. The aluminium remains in the grooves and thus
forms the sunken first metallisation pattern 4.
' 5 As an auxiliary layer may also
j be used a layer of metal, for example tantalum or
titanium, or another suitable material which can be
1 etched and be removed by agents ~hich do not attack
; the unde~lying insulating materiaL
Po;ycrystalline silicon may also be
~ used for the sunken metallisation pattern. In this
i case is used as an auxiliary layer, for example,
- aluminium which can be removed by means of a
' mixture of acetic acid and nitric acld.
A~ter removing the auxiliary layer,
a second electrically insulating layer 6 is pro~ided
:i ' ~ ,
on the first insulating layer 3 and the first
conductive~layer 4. Said second electrically insula-
ting layer in ~is example covers the whole surface
and consists in this e~ample of silicon oxide but may
alternatively be silicon nitride.
Contact~holes 12 ~Fig. 7) are then
provided in the second electrlcally insulating layer
6. Said contact holes expose both parts of the
semiconductcr zona~s 8, 9, 11 cf the underlyiIlg transis-
i tors and parts o~ the first metallisation pattern 4.
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PHN 8718
18.8.1~77
A second conductive layer 7 which is brought
inthe form of the second metallisation pattern
is provided on said second electrically insulating
layer. This pattern is provided, for example photo-
chemically, and is connected electricaly, viathe above-mentioned contact holes, to the said
sem:iconductor zones 8, 9, 11 and to the
metallisation pattern 4. The structure sho~Yn in
Fig. 2 is -then obtained.
I 10 The above-described method
saves one mask as compared with the conventional
methods.
Figs. 8 to 10 are cross-eectional
views of the realisation of the semiconductor device
shown in Fig. 11 having a two layer wiring in
successive steps of a known method. This semi-
conductor device has the same elemen-ts as the semi-
conductor device shown in Figs. l and 2 but a
different structure o~ the metallisation.
Starting material in this
example is a sllicon substrate 14 (Flg. 8), in this
~example of ~the ~type having a resistivity bet~Yeen
~ 2 and 5 Ohm.cm. At the area of the collector ~ones
to be formed a buried layer 15 is provided, for
example, by arsenic deposition. An epitaxial
layer of the n-type is then grown on the substrate,
for example, by epitaxia:l growth from -the gaseous
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P~IN 871g
~ 18,~ 77
923
phase. Separation regions 13 (Fig. 8) are provided
in said epitaxial layer so that said layer is
divided into collector regions 10 of the n-type
In kno~ manner, ~~type base zones 8, n-type
emitter zones 9 and n-type collector contact zones
11 are then provided herein by means of, for
l~ example, diffusion or ion implantation (Fig. 4)
According to a conventional method
of providing a multilayer metallisation pattern,
~¦ 10 the semiconductor body is then cover~d with an
insulating layer 17 of, for example, silicon oxide,
in which ?pertures 12 are then etched by means of
a first mask (Fig. 8)~ Via said apertures, the
resulting exposed semiconductor zones are.connected
to a first metallisation pattern 18 (Fig. 9)
which in this example interconnects inter alia
the collector contact zones 11 of two transistors
separated b-y the isolation region 13. Said metalli-
sation pattern may be obtalned, for example, by
vapour-depositing and then selectively etching
alumlnium,~by means of a seoond;mask.~The bod-y is
then covered again with~an insulating layer 19 in
which aperture~s 20 are provided by means of athird
.:
mask (Fig. 10) so that parts of the meta~isation
pattern 18 are exposed which can be contacted to a
second metallisation patter~ 21 (F:ig. 11) via the
. :
aper-tures 20. Said metallisatinn pattern can be
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18.8.1g77
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3;23
obtained by vapour-depositing aluminium and then
selectively etching said aluminium by means of a
fot~h mask.
In the method of manufacturing a
semiconductor device according to the invention,
however, only three instead of four masks are
necessary to manufacture the same semiconductor
device with another metalllsation structure. These
masks are first of all the masks for defining and
etching the grooves in which the first metallisa-
tion pattern ~ is provided (which is comparable to
i
~ ~ the fourth mask of the conventional method), secondly
¦ the mask for defining the contact holes 12 (which is
comparable to the combination of the above-mentioned
first and third masks of the conventional method )
and thirdly the mask for defining the second metalli-
sation pattern (which is comparable to the second
j
mask of the conventional me-thod). The method accor-
dlng to the invention~ enables the saving of one mask
20 in that in this method contact holes to the semicon-
ductor zones 8, 9~, 11 and connections between the
first and the sec~nd me-tallisation pattern are
realised in one step.
. :
It w~ be obvious that the inven-
tion is not restrioted to the examples described, but
that many variations are possible to those skilled in
i
i ~ the art without departing from the scope of this
in~ention.
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PHN 8718
18.8.1~77
ll(~Z9Z3
i For example, the semiconductor
i . body need not necessarily be silicon, but other
~ semiconductor materials, for example germanium and
¦ semiconductor materials of the III-V type, for example
~ 5 gallium arsenide, may alternatively be used. In the
¦ embodiments the conductivity types of all the semi-
¦ conductor zones and semiconductor regions may
(simultaneously) be replaced by their opposite types.
The base and emit-ter zones as well as the collector
¦ lO contact zones may alternatively be provided by ion
implantation instead of by diffusion.
Besides bipolar transistors, the
clrcuit elements may be, for example, MOS transistors
1 or other active or passive elements, for example
;~ 15 resistors, diodes, and so on, in which in the case
¦ of the sunken oxide channel stoppers are provided, if
I ~ necessary, below the lsolation regions 13.
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