SIGNAL EVALUATING EQUIPMENT

TRADUCTION NON-DISPONIBLE

English Abstract

A B S T R A C T
Signal evaluating equipment particularly but not exclusively
useful in reading bar codes on envelopes is disclosed. The equipment includes
a first peak detector circuit to detect and register a first peak value of
a first portion of the signal and a second peak detector circuit to detect
and register a second peak value of a second portion of the signal. These
two values are then compared in a comparator to establish whether they
satisfy a predetermined relationship. The use of this system permits large
amplitude variations between the signals being read and background noise to
be accommodated.

Claims

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. Signal evaluating equipment for evaluating an input signal, trans-
mitted from an input to an output of the equipment, with the help of peak
detector means and comparator means, characterized in that said peak detector
means include a first peak detector circuit to detect and register a first
peak value (Vpt) of a first portion of said signal and a second peak detector
circuit to detect and register second peak values (Vmt) of a second portion
of said signal, and that said comparator means are coupled to said first and
second peak detector circuits and are able to continuously compare said first
(Vpt) and second (Vmt) peak values to check if these values satisfy a pre-
determined relationship and to evaluate said signal in function of the
result of this check, such that said first and second portions both start
at the beginning of said signal, and further including a variable threshold
circuit coupled to said second peak detector circuit and able to establish a
variable threshold which is function of a predetermined fraction of said
second (Vmt) peak value, the portions of said input signal below said thresh-
old being prevented from appearing at said output of the equipment; and
includes a further comparator circuit for comparing the output signals -Vp
and -Vm of first and second subtractor circuits to derive a noise rejection
signal N when Vm is larger than a predetermined multiple n of signal Vp.
2. Signal evaluating equipment according to claim 1, characterized in
that said input signal (Vsl) is provided by reading means when reading a bar
code encoded on an area of an object, said input signal comprising a pedestal
portion related to the background of said area and a plurality of signal
parts superimposed on said first pedestal portion and related to the code
33

bars of said bar code, and that the equipment further includes a third peak
detector circuit able to be effectively connected to said reading means
during a time interval preceding the time interval during which said code
bars are read and to register the thus detected third peak value (Vbg) of
said pedestal portion.
3. Signal evaluating equipment according to claim 2, characterized in
that said comparator means include a first subtractor circuit having inputs
connected to the outputs of said first and third peak detector circuits, a
second subtractor circuit having inputs connected to the outputs of said
second and third peak detector circuits, and a comparison circuit the inputs
of which are coupled to the outputs of said first and second subtractor
circuits, said comparison circuit being so arranged that it generates an error
indicating signal (N) when a first fraction <IMG> of the signal (Vm) appearing
at the output of said second subtractor circuit is larger than the signal
(Vp) appearing at the output of said first subtractor circuit, said error
indicating signal indicating that said predetermined relationship is not
satisfied.
4. Signal evaluating equipment according to claim 3, characterized in
that one input of said variable threshold circuit is coupled to the output
of said reading means providing said input signal (Vsl), another input of
said variable threshold circuit is coupled to the output of said second sub-
tractor circuit and another input of said variable threshold circuit is
coupled to the output of said third peak detector circuit (Vbg) and establishes
a threshold equal to the sum of a second fraction ( ? ) of said second peak
value (Vm) and of said third peak value (Vbg).
5. Signal evaluating equipment according to claim 4, characterized in
34

that said variable threshold circuit includes a summing operational amplifier
the output of which is connected to a limiter circuit, said summing operation-
al amplifier having an inverting input which is connected to the outputs of
said reading means providing said input signal (Vsl) and of said second sub-
tractor circuit via a first and a second resistance respectively and having a
non-inverting input which is connected to the output of said third peak
detector via a third resistance and to ground via a fourth resistance, the
ratio of said second and first resistances being substantially equal to m and
the ratio of said fourth and third resistances being substantially equal to
<IMG> wherein <IMG> is said second fraction.
6. Signal evaluating equipment according to claim 3, characterized in
that the output of said variable threshold circuit is coupled to the signal
input of an automatic gain control circuit; the control input of which is
coupled to the output of said second subtractor circuit in such a manner
that the gain of a signal applied to said signal input is varied so as to
be substantially inversely proportional to said second peak value (Vm).
7. Signal evaluating circuit according to claim 1, characterized in
that it includes a differentiator circuit with an input coupled to the output
of said variable threshold circuit and with an output coupled to the inputs
of a first and a second pulse forming circuit, said first pulse forming
circuit being adapted to transform each said input signal of one polarity
provided by said differentiator circuit into a first pulse (Vdl) and said
second pulse forming circuit being adapted to transform each said input
signal of the opposite polarity by said differentiator circuit into a second
pulse (Vd2), and logic circuitry to check the order in which said first and
second output pulses appear, said logic circuitry providing an output signal

(DO) only when said order is correct.
8. Signal evaluating equipment according to claim 7, characterized in
that said logic circuitry includes means generating a third pulse (Q3)
indicating the occurrence of a said second output pulse, means generating a
fourth pulse (Q1) the leading edge of which coincides with that of said first
pulse (Vd1) and having a predetermined length, means generating a fifth
pulse (?d'l) the leading edge of which coincides with that of said first
pulse (Vdl) but having a duration longer than said first pulse, and means
to calculate the Boolean function (?d'l + Ql).Q3, wherein Q3, Ql and ?d'l
are said third, fourth and fifth pulses respectively, and to provide said
output signal (DO) which may be represented by said Boolean function.
36

Description

4~
The present invention relates to a signal evaluating equipment
for evaluating an input signal, transmitted from an input to an output of
the equipment, with the help of peak detector means and comparator means.
Such an equipment is already known from U.S. patent 3 875 419,
which issued on April 1, 1975 to A. D. Harms, Jr. and is assigned to
E-Systems, Inc., wherein it forms part of a bar code recognition system.
This known equipment also comprises a threshold adjustment network, an output
signal being prevented from appearing at the output when the input signal
does not exceed the adjustable threshold value. No means are disclosed how-
ever enabling an automatic adjustment of the threshold to take care of largeamplitude variations between the input signals and background noise and which
are encountered for instance in reading a bar code on an envelope. Indeed,
the amplitude of such signals then depends on a large number of widely vary-
ing parametersJ such as the nature of the envelope and the ink used to encode
the bars on the envelope, and may for instance vary from 1 to 100.
To solve this problem one might evaluate a delayed version of the
input signal in function of a variable threshold, the latter being function
of the input signal itself. However, for some applications a device provid-
ing a sufficiently large delay corresponding to the duration of the input
signal may be undesirable, e.g. expensive. One may conceive a smaller delay
corresponding only to some initial part of the signal, but one will then
seriously reduce noise immunity as this part may contain a large amount of
spurious information.
Therefore, one object of the present invention is to provide a
signal evaluating equipment of the above type but which, although being
adapted to take care of large amplitude variations between the input signals,
--1--

does not require the use of a delay circuit.
~ ccording to the present invention, there is provided signal
evaluating equipment for evaluating an input signal, transmitted from an
input to an output of the equipment, with the help of peak detector means
and comparator means, characterized in that said peak detector means include
a first peak detector circuit to detect and register a first peak value (Vpt)
of a first portion of said signal and a second peak detector circuit to
detect and register second peak values ~Vmt) of a second portion of said
signal, and that said comparator means are coupled to said first and second
peak detector circuits and are able to continuously compare said first (Vpt)
and second (Vmt) peak values to check if these values satisfy a predetermined
relationship and to evaluate said signal in function of the result of this
check, such that said first and second portions both start at the beginning
of said signal, and further including a variable threshold circuit coupled
to said second peak detector circuit and able to establish a variable thresh-
: old which is function of a predetermined fraction of said second (Vmt) peak
value, the pOTtiOns of said input signal below said threshold being prevented
from appearing at said output of the equipment; and includes a further com-
parator circuit for comparing the output signals -Vp and -Vm of first and
second subtractor circuits to derive a noise rejection signal N when Vm is
larger than a predetermined multiple n of signal Vp.
~ hen an input signal is continuously evaluated as is for instance
required for an input signal resulting from the reading of a bar code on an
~- .

~ 4~
envelope, the above-mentioned predetermined relationship to be continuously
checked may, for instance, consist in checking that the ratio of the second
peak value which has just been registered or which has been registered
previously and the first peak value which has been registered at the begin-
ning of the signal is larger or smaller than a predetermined value. By
proceeding in this way, the signal for which the relationship is found not
- to be satisfied may be considered as a spurious one. However, even when a
portion of this signal contains spurious information which does not satisfy
the above-mentioned predetermined relationship, this will not be detected if
the amplitude of this portion is smaller than a previously registered second
peak value. Indeed, according to the above feature, the registered second
peak value and not the instantaneous peak value is continuously compared
with the first peak value. However, the variable threshold circuit in the
circuit of the present invention overcomes the last mentioned drawback.

f~
_ 5 _ L~ VAN HED~E~EM S
~ he above mentioned and other objects ~nd
feature~ o~ the invention will become more apparent and the
invention it~elf will be be~t understood by referring to the
following description of an e-nbodiment taken in conjunction
~th the accompanying drawings in which :
Fig. 1 is a block diagram of a signal evaluating
equipment and more parti~,ularly an electro-optical bar code
reader according to the invention;
Figs. 2 to 4 represent circuit parts II, III and
IV of Fi.g. 1 in more detflil;
. Fi~. 5 to 7 are diagrRms of pulse6 appearing at
various points of the equipment according to ~ig8. 2 to 4.
Principally referring to Fig. 1, the electro- .
. optical bar code reader Ghown therein includes a power .
. 15 supply 1 for energizing a set of ultra-violet light emitting
. lamps 2 used for exciting a fluorescent!bar code 4 encoded
on the area of an envelope 3. This bar code 4 comprises a :
plurality of code bars of which only three are shown.
Transport equipment 5 is adapted to impart a motion to the
envelope 3 past the area illuminated by the lamps 2. The .
light thsn emitted by the fluore~cent bar code 4 and by
the back~round of the envelope is focused by means of an
. ob~ective lens 6 into a light guide 7 which channels the
light 80 that it impinges on a photo diode 8. -
The response of ~ photo diode 8 to the light
_ _
. ,
-~ v.~ .
:
'

' llV~Zl~ j
¦ - 6 - L. VAN ~EDDEGE~I 5
signal incident thereon, as modulated by the individual code
element~ of the bar code 4, is in the form of an analog
current signal which i~ supplied to a current-to-voltage
converter and amplifier circuit 9. ~his circuit functions
to convert the current ~ignal at it6 input to a correspondin~
voltage ~ignal V~1 with ~ppropriate amplification.
The amplified ~oltage signal Vs1 at the output of
the circuit 9 i~ supplie(l on the one hand to a summing
amplifier 10 and on the other hand through a buffer stage
11, and aa a signal Vs2, to peak detector circuits 12, 13
and 14 which are controlled by read authorization signals
RA1 and RA2 generated by a read authorization circuit 15
after a photodiode 16 has detected the presence of an envelope
~ to be read. The peak detector circuit 13 i8 moreover
controlled by the reader output VP0 on which an inhibit
signal appears a6 ~oon a~ the ~irst code element of the bar
code 4 has been read.
The function of the peak detector circuit or sample-
and-hold circuit 12 i~ to provide an output ~ignal Vbg the
amplitude of which is a measure of the light energy
reflected or emitted by the background of the illiminated
area of the envelope the paper of which generally contain~ -
., p~
fluoreacent material, w~ 1st that of the ~ffh~ detector
circuit 13 is to generate ~n output signal Vpt the amplitude
of which ic related to the suu of the light energy emitted
1~ 1!

. ~ ~ ~
~ :
_ 7 - ~. VAN H~V~EG~M 5
by the irst code element of the bar code 4 or by any ~pot
in the illuminated area ~imulating such a first code element
a~d of the light energy emitted by the illuminated back-
ground of the envelope. Aq soon a~ the fir~t code element
of the bar code 4 has been read the operation of the peak
detector circuit 13 i8 inhibited by the inhibit signal then
appearin~ at the ~tPut VY0 of the reader. ;
~ he function o~ the peak detector circuit 14 is to
generate an ou~t ~ignal Vmt the amplitude of which i8
function of the ~um of ths maximum amoUnt of light energy
emitted by any of the code elements of the bàr code 4 and
by the illuminated background of the envelope.
~ ~he output signals Vpt and Vbg memorized in the
peak detector circuits 1j and 1~ respectively are fed to a
~ubtractor circuit 17 which 6ubtracts the output signal
Vpt from the output signal Vbg and hereby provide6 an output
signal-Vp the amplitude of which i8 a measure of the light
energy emitted by the fir~t code element of the bar code or
by any spot in the illumlnated area simulating such a code
element. ~ikewise, the output signal~ Vmt and Vbg
memorized in the peak detector circuit 14 and in the peak
detector circuit 12 re6pecti~ely are fed to a ~ubtractor
circuit 18 which makes the difference of the signal~ Vbg -
and Vmt and provides an output 6ignal-Vm the amplitude of
which is a measure Or the light energy emitted by the code
~ ' ,

. ' llO~Z:il3 i
- 8 - L. VAN HED~EGEM 5
element which emite the maximum amount of light ener~y.
'~he output ~ignal~ -Vp and -Vm of the subtractor
. circuit6 17 and 18 respectively are further applied to a
comparfltor circuit 19 wh~n they are continuou~ly compared.
In fact the output signel -Vp is continuously compared with
a predetermined fraction of the output signal -Vm.to check
whether or not the ratio of the output signals Vm and Vp
excee~ a predetermined vnlue n. In the positive, the
signal Vs1 is considered ~o belerroneous and therefore a so-
called noise re~ection output signal N is generated when
the amplitude of output ~ignal Vm is larger than a predeter-
mined mult~e n of the amplitude of output signal Vp. ~he
noise rejection output signAl N i8 ~d to a control circuit
~ 20 which in response thereto provides a noise rejection
output signal NROP indic~ting that all information read
until then should be cancelled. ~ .
: For the first bar code element or spurious
information simulating such a first code element read, Vp `
. i8 equal to Vm BO that no output signals N and NROP will be
generated. However, if ~uch a spurious information is
first read it will be detected upon the subsequent reading .
of the first bar code element on condition that the output
signal Vm produced upon reading the latter element is
larger than the above mentioned predeterminedmultiple n of .
. 25 the output ~ignal Vp result ng from the reading of the -
~_
.
.
.
- " ' .

~:~Q~
- 9 - L. VAN HEDDEGEM 5
spuriou~ inform~tion. It i9 therefore imperative to make a
suitable choice of this factor n and in a practieal
embodiment it hAs been cho~en equal to 10.
Although the above de~cribed circuitry is able to
detect the la~t mentioned error, it i8 incapable to detect
for in~tance ~puriou~ inl'ormation which i~ read on an
env~Dpe after at lea~t one bar code element already ha~
been correctly read, i.e. has not given rise to a re~ection
signal and when thls spurious information give~ rise to a
signal which i8 such that the amplitude memorized in the
peak detector circuit 14 is not exceeded. Indeed, only the
latter memorized value and not the amplitude of the spurious :
information is compared with that regi~tered in the peak
deteetor circuit 13. For this reason other measure6 -~
deseribed hereinafter have been taken.
~efore doing 80 it should be noted that theoutput .
signal -Vm of the subtractor circuit 18 is also applied to .
. a control cireuit 21 which provides an output signal Vfet
used to eontrol field effeet devices included in an AGC
eireuit 23. .
Returning now to the summing amplif1er 10, the
latter is not only fed by the outp~ signal Vs1 of the
amplifier circuit 9 but also by the output signal~ Vbg and
-Vm of the peak deteetor circuit 12 and of the subtractor
circuit 18 re~pect$vely. The purpose of this summing
.
. - .
' ' ~'.' ~ ' ' ,:
. '
.

0 4~
- 10 - L. VAN ILEDDE~EM 5
amplifier is to continuously subtract a variable threshold
equal to the sum of the background value Vbg and a
predetermined fraction ( - ) of the value Vm ~om the
amplitude of the output siKnal Vs1. In this way, as soon
as this threshold has beea est~blished all spurious
information having anamplitude below that thresh~d will be
removed in the precision li.miter 22 following the summing
amplifier 10. In this precision limiter 22 part of.the
summing a~plifier output signal i8 c~pped and from there
it i~ fed to an automatic.gain control or AGC circuit 23
: which includes field effect device6 (not shown) controlled .
by the output eignal Vfet Or the control circuit 21.
. The output ~ignal o.l` the AGC circuit is supplied
~ to a differentiator and alnplifi.er circuit 24 wherein these
: ~ 15 signals are first differentiated and then a~plified before
being fed to comparator ci.rcuitry 25. The purpose of this .
comparator circuitry 25 i~ to provide output pulse train~
Vd1 and Vd2 correspondi~g to the positive and negative g~ing
portions Or the differenti.ated siKnals applied thereat as
well as an output pul~e train Vd'1 the pulses of which are
lengthened when ~pared wi.th those of Vd1. ~he output
pulse trains Vd1, Vd'1 and Vd2 are applied to the control
circuit 20 together with the output ~ignal N of comparator
. . circuit 19 and the read authorization ~ignal RAo provided .
by the read authorization circuit 15. The purpose of the
g~
_,
.~_ _ __ _
- ~

~ ~1104;23~ i
~ L. V~N 1~E~EGE~1 5
control circuit 20 i8 to provide a data output pulse train
at its output DO or a noise rejection output pulse at its
output NROP and to generate an inhibit pulse at its output
VPO after the first bar code element has been read. As
already mentioned above this inhibit circuit control~ the
peak detector circuit 13.
Reference is now made to Figures 2 to 4 which
show part;~ II, ITI and IV Or the electrico-optical bar
code reader of Fig. 1 in more detail. Hereby operational
amplifiers are represente1 by triangles and their non-
inverting and inverting i1lputs are indicated by a plus
6ign and a minus sign respectively.
The circuit~ already shown on Fig. 1 include
the following elements which Are interconnected i~ the
manner shown :
,
. .
. . '' . :
' ' ' ' '''
.
. .
, ~_ .

~ Z:~B
,
- 12 - L. VAN llE~D~GEM 5
C~uit ~e~ ~e~istors C~p~tors Diode~ FE~ Other
am~fiers CGm~.
. .
9 30-33 34-47 48-51
61 -65 66 67
11 70 71 _~
12 80-81 82-85 86,270 87-88 89
. 13 90-92 93-104 105-106 107-111 112-114
120-123 124-138 1l~0-143
. __ . .
17 150 151 -154 155
.
18 160 161 -164 165 .
.
19 170 171 -174 .
180-183 184-188 1~9-192 193 194-196
. . _ _
21 200 201-204,20~ 205 207
22 210 211 -213 214-215
23 220 221 -223 224 225-226
24 230 231-233 234-235
240 241 -243 2~t4
26 250-251 25~-26~ 2~ 265 = = .
' ' ' ' ' ' '
' .
.~
,. ;. _ ~_ .
, ~ ~ .
, . .
., `_ _~ ___

l ~ J~
~ L. VAN H~DDEG~M 5
With regard to the control circuitry 20 shown
in ~`ig. 4 it should be noted that circuits 180 to 183 are
mono~table circuits, whil~t the circuit~ 194 and 195 are
bi~table circuit~ and that 196 iB a NAND-gate. The element
193 is ~ Zener diode.
The mono6table circuit~ 180 to 18~ all are of a
type which i8 triggered to its unstable condition when
the input eign~l spplied to it~ 1-input change~ from O
(O Volts) to 1 (+ 5 Volt~). T~le bistable circuits 194 and
1Q 195 are of a type normally in the condition wherein the
O-~put i~ activated and the 1-output i B de-activated and
basculated upon its 1-input being de-activated.
Several of the above circuits are disclosed in
the book "Operational Amplifiers" by Tobey, Graeme and
Huelsman (Burr-Brown) published by Mc Graw-Hill, 1971
and in the ~econd editio~l of the book "~inear applications"
published by National ~emiconductor, August 1973.
When reference is made to these books this will ;
be done as follows :
- for the rirst book e.g. BB, page x, Fig. y
- for the seoond boo~ e.g. page AN20-5, Fig. 2
The detailed operation of the bar code reader
is described hereinafter.
Initially the field effect transistors 89 (Fig.3)
of the pesk detector or sample-and-hold circuit 12; 112
"``' '' _~J_ I
. . .
q~
'

lV~Z1~3 ~
- 14 - L. VAN ~EDI)E(;EM 5
to 114 of the peak detector circuit 1, and those (not shown)
of the peak detector circuit 14 are conductive so that the
~ample-and-hold circuit 1~ is enabled, whereas the peak
detector circuits 13 and 14 are inhibited. The light emitted
by the ultraviolet lamps .~ (Fig. 1) does not influence the
photodiode 8 (Fig. 2) of ~ircuit 9. On thecontrary the photo-
cell 16 (Fig. 4) of circui t 15 is suppo~ed to receive light
from an ad~acent light source (not shown).
First the oper;~tion of circuit 15 (Fig. 4) is
described in detail. When en envelope 3 (~'ig. 1) carrying
a fluorescent bar code 4 ~t a predetermined di~tance from
its leading edge is tran~ported pa~t the photocell 16, the
light from the last mentioned source i8 prevented from
reaching it, whilst the ultra-violet light emitted by
~5 the lamps 2 illuminates the background of the envelope.
The light emitted by this envelope is concentrated by the
ob~ective lens 6 (E'ig. 1) and channeled by the light guide
` 7 (Fig. 1) to impinge on theFhotodiode 8 (Fig. ~). It is
supposed that the speed at which the envelope is transported
is egual to 4 m/eec. and that the bar code is at about 5mm from
the leading edge of the envelope and comprises for ins~nce
four bars ~8 shown in Fig. 1 which are at 3 mm distance
from each other.
Due to light being prevented from reaching the
photocell 16 (Eig. 4) the resistance thereof is increased
. .

~ Zl~
- 15 _ L. ~AN H~EGEM 5
80 that a negative going voltage signal then appears at
the output of the operational amplifier 120 (AN20-3, P`ig. 4).
The bandwidth of this operational amplifier 120 is limited
by the capacitor 140 which thu6 eliminates the effect of
high ~guency ~purious 9i gnal~. ~or
instence , the neg~tive ~oing output s~nal vares b~n
about +15 Volts and about 0 Volt.
This negative ~oing output signal is applied
to the minus input of the operational amplifier 121 which
forms part of an integrator circuit (BB, page 212, Fig. 6.11)
also included in the circuit 15. This integrator circuit
invert~ and increases th~ slope Or the negative going edge
of the ~ignal applied thereat and thus provides a signal
having a positive going leading edge with an increa6ed 6l0pe
and varying between about -15 Volts and ~15 Volts. The
latter 6ignal is fed to the minus input of the operational
amplifier 122 the plus input of which is grounded and
which pro~ides a negative going first read authorization
pulse RA1 varying between about +15 Volts and -15 ~olts.
20 The negative going edge of this pulse occurs at the moment
:~ ~
the input ~ignal exceeds zero Volt, 80 that this pul~e iB
delayed with respect to ~e moment at which the photodiode
16 became obscured. ~he circuit eleme~s have been 80 chosen
that this delay is equal to about 0.6 milliseconds.
The first re~d authorization pulse RA1 is
,.~
''.
- - - . ' .
- - ~ -

l llr~4Z1~3
- 16 - ~. VAN HED~EGE~I 5
applied to the cAthodes ot the diode~ 88 and 111 (k'ig. 3)
forming part of the peak detector circuits 12 and 1~
respectively. These diode~ are thus rendered conductive
since their anodes are conned~d to ground via resistaDce 85
and diode 87 and via resi~tance 101~ re6pectively. As a
consequence, field effect tran~istor~ 89 and 1~3 are blocked
snd the same 1~ true for the field effect transistor (not
shown) which i~ included in th~ peak detector circuit 14
and which l8 the homologue of transi6tor 113. Due to these
FET's being blocked the sample-and-hold circuit 12 i8 blocked,
whereas the peak detector circuits 13 and 14 are prepared
for operatlon.
The first ne~tive going read authorization pulse
RA1 (Fig. 4) is further delayed by about 0.~ milliseconds
by the RC circuit 132, 14~ thu~ providing a second negative
going read authoriz~tion pul~e RA2 which blocks the field
~ffect transistor 112 forming part of the peak detector
circuit 1~ and the homologue field effect trans~tor (not
~hown) included in the peak detector circuit 14. Indeed, the
diode 110 then becomes conductive due to its anode being ~
connected to ground via resistor 10~.
The negative going read authorization pulse RA1
is also further delayed by about 0.6 milliseconds by the
RC circuit 134, 143 and then ~pplied via re~istor 135 to
the input of a voltsge level d tector with hysteresi-
,
-,, ,: - : ~,' '
. ' ~ .
~ ' . ' ~ '

~.~U4Zl~ I
- 17 - ~L. VAN H~DBGEM
includin~ the operational amplifier 1~3. At its output
this amplifier prov;de~ a po6itive going pul~e RAo varying
between O Volts a~d + ~ ~olts, and occu~ng about 1.20
milliseconds a~ter the photocell became ~scured i.e. just
before the first bar code element which ~B at about 5 mm,
corre~ponding to 1.25 milliseconds, of the leadin~ edge of
the envelope iB read. Thi~ si~nal controls thebistable
circuit6 194 and 195 and the monostable ~ircuits 180 and
181 forming part of the control circuit 20 (Fig. 4).
The reason why the ~ 8, such as 106 and 105, of
: each of the peak detector circuits 13 and 14 are made
conductive in succession will be explained later.
The reason of the delay provided by the delay
circuit 1~4, 143 is to prevent spurious signals from -
j5 appearing at the outputs ~0, N~OP ~nd ~PO of the reader, as
will also be explained later. `
Returning now to the photodiod~e 8 ~Fig. 2), when
the travelling envelope 3 is illuminated by the ultra-
~olet light emitting lamps 2 a composite light signal
comprising a background light signal modulated by light
signals each corresponding to a bar ~de element is generated.
When this light signal impinges on the photodiode 8, the
latter generates a composite electrical current si~nal which
is directly proportional to this light signal. This current
signal i8 applied to the current-to-voltage converter
. ~ _ . .
_ ~--~ .
~'
'
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l ~4Z1~3 ~
- 18 - ~. VAN ~DDEGEM 5
(BB pages ~32-233 l~'ig. 6.~2; AN 20-5) which ~cludes the
operation~l amplifier 30 ~nd which provides a po~itive going
~oltaKe output ~ignal V~ that i~ directly proportional to
the current flowin~ through the photodiode. This composite
output signal which may vary be~ween a few and several
hundredR Or multivolts therefore has the bhape of a pedestal,
correspondin~ to the envelope background, with 6everal peaks
corre~ponding to the bar code element~. The resistor-capacitor
networks 34, 48 and 35, 4~3 limit the bandwidth of this output
~ignal. The latter signal Vs i8 applied to the minus input
of the inverting operational amplifier 31 (AN 20-1) which
provides an amplified and negative going signal at its
output. Again the bandwldth of this sign~l i8 lim~ed by -
the resi~tor-capacitor network 37,50.
The la~t mentioned output signal is applied to
the plu8 input of the voltage follower including the non-
inverting operational amplifier 32 (B~ 430-431; AN 20-2,
Fig. 2) which i~olates the current signal eource 8 from the
cable ( not shown) which is supposed to interconnect the
output o$ the opertional amplifier 32 and jhe adJustable
resistor 42 connected to the minu~ input af the operational
amplifier 33. The negative feedback circuit of the latter
amplifier 33 includes the 3eries connected light-dependent
resi~tors 46 and 47. The purpo~e of the~e resistors which
are illuminated by the ultrs-violet lightiemitting lamps 2
~ A . ~ i~ ,
. , ,', ,.
.
"' ",
' ~. ' ' ' ' ~,
, ~'

~ i
l~Z~
- 19 - L. VAN HEDDEGE~i 5
~~ 'ig. 1) is to compensate for the ageing of the6e lamps.
Indeed, when due to such ~Kein~ the intensity of the li~ht
fallin~ on the resistors ~6 and 47 decreases their resis-
tance value and therefore al80 the gain of the operational
amplifier 3~ increases. '~'he po~itive going signal appearing
at the output of the oper~ltionel amplifier 33 w;lich also
constitutes the output of circuit 9 iB applied op the one
hand to the minus input of the summing operational amplifier
60 included in circuit 10 and on the other hand via the non-
10inverting unity ga~n buffer amplifier 70 (AN 20-2, ~ig. 3)
forming psrt of circuit 11 simultaneously to the circuit~
12, 13 and 14 (E'ig. 3). '~he amplifier 70 is used because it
has a high input impedance. The positive going output signals
of the operational ampliier~ ~3 and 70 are indicated by
Vs1 and Vs2 re6pectively.
As long as the 8i 6nal 9 RA1 and XA2 both are
de-activated, i.e. during 0.9 milliseconds, the output
signal V~2 has no effect on the peak detector circuits 13
and 14 (AN31-12) since the FET's, such as 112, 113 included
in circuit13, are then blocked. On the contrary, the output
~ignal Vs2 applied to the peak detector or sample-and-hold
circuit 12 is first de~ayed by the RC ci~cuit ~2, 270 in
order to attenuate possible peaks in the pedestal p~ion
of the ~ignal VB2 and to prevent these peak~ from being
i
simulated with the background of the envelope. The sample-
, . I
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11~14Z1~3 i1
- 20 - L! VAN I~EDV~G~I 5
and-hold circuit 12 which pre~ents some ~imilarity with
th~ ~hown in BB, page 351, Fig. 2, then samples the pede~tal
portion of the signal Vs2 on the capacitor 86 as long as
the E'~T89 i8 conductive, i.e. until the negative going
read authorization signal ~A1 i8 generated. The output
signal of the operational amplifier 81 included in the peak
detector circuit 12 i~ inlicated by Vbg because it is a
mea~ure of the background of the envelope being illuminated.
This signal Vbg has no influence on the conditions of t~e
output~ DO, NROP and VPO (k'ig. 4) of the reader.
At the moment ~e ne~,ative going read authorization
signal RA1 i8 generated the FE'L' of the peak detector circuit
12 is blocked whil6t the h'E~ 113 of the peak detector circuit
13 (Fig. 4) 1~ blocked 80 as to remove the,ground potential
from the plus input of the operational amp~ifier 91 forming
part of this detector circuit. The same happens in the
~ ~ pcak detector circuit 14 (~`ig. 4). Thus both the detector
circuits 13 and 14 are prepared for operation.
At the moment the negative going read authorization
8ignal RA2 i8 generated, i.e. 0.3 millisec!onds after ~A1,
the ~E~ 112 of the peak detector circuit 13 (Fig. 4) is
blocked 80 as to remove the ground potential from the ~8
input of the operational ~mplifier 90. The same is true for
the peak detector 14. In this way both the peak detector
; 25 oirouitH 13 erd 14 ere reHdy for OperetiDr.
:

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- 21 - L. VAN HEDDEGEM 5
q`he P`ET 113 of circuit 1~ i.B blocked before the
~'ET 112 becau~e, when h'~T 112 would be blocked before ~ET 11
the operational amplifier 90 would become conductive before
the operational amplifier ~1 and e8 ~ consequence transients
would appear at the output of the operational amplifier ~1
and there~ore al~o ~t the data output D0 of the reader.
~ 'rom the momen~ at which the read authorization
signal RA2 i~ generated tlle pedestal portion of the signal
Vs2 is applied to the peak detedDr circuits 13 and 1~ and
registered in the capacitors, ~uch as 106 of circuit 13
thereof. However this has no fipecial effect.
At the moment the positive going read authorization
signal HAo is gellerated, i.~. 1.20 millisecond~ after the
photocell 16 became ob~cured, the 0-inputs of the bistable
circuits 194 and 195 (Fig. 4) ure activated 80 that these
circuits are prepared for operntion and also the monostable
circuit~ 180 and 181 (Fig. 4) are prepared for operation.
A time interval e~ual to 1.25 milli~econd~ after
the photocell 16 became obscured, the various bar code
signals which form part of the input signal Vs2 a~d which are
modulated on the pedestal corresponding to the envelope
background are successively applied to the pea~ detector
circuits 13 and 14.
The ~litude of the first of ~hese bar code
- 25 signals i~ registered in the capa¢itors, such a8 106
. ~ ___~__

1104Zll~ I I
22 - ~. VAN ~D~EGEM 5
of the peak detector circuits 13 and 14 which accordingly
generate a po3itive going signal at their~output.
These output signals are indicated by Vpt and
Vmt respectively.
A6 will be expl~ined later, the first bar code
element read gives rise to a corre~ponding data signal at
the output DO (Fig. ~) and to n control signal VPO at the
like named output VPO (~'ig.4). The lntter ~ignal blocks the
FET114 forming part of the peak detector circuit 13 so that
only the amplitude of the first bar code signal can be
registered in the peak detector circuit 1~.
On the con~ary, since the peak detector circuit
14 does not include a FET which is the hdmologue of FET 114,
the amplitude of the bar code si~nal having the maximum
amplitude among all the bMr code signals will be registered
in its capscitor. It iB clear however that for the first
b~r code signal the amplitudes of Vpt and;Vmt are equal.
The signals Vbg and Vpt cppea~ing at the output,
of the peak detector circuits 12 and 13 respect;vely are
applied to the plu6 and n~inu6 inputs of the difference
operational amplifier 150 (AN 20-3) forming part of the
subtractor circuit 17 (Fjg. ~), whilst the signal Vmt
appearing at the output of the peak detector circui,t 14 and
the 6ignal Vbg are applied to the minus ~nd plu8 inputs of
the difference operationnl amplifier 160,(AN 20-3)
.
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~ e~
- 23 - L. VAN ~D~GEM ~
i,ncluded in the subtractor cirouit 18. The signals ap~ ng
at the outputs o~ the subtractor circuitsi17 and 18 are
indicated by -Vp and -Vm which are equal to the difference
~` of Vbg and Vpt ~nd of Vbg and Vmt respectively.
The output signal -Vm i8 applied via the diode 206
and the ~rlable resistor 201 to the minus input of the
operational difference aml)lifi,er 200 forming part of the
control circuit 21 (Fig. ~) which provides at it~ output a
control ~Knal Vfet which i~ proportional to the difference
between the reference voltaKe Applied to the plu8 input of ,
thi~ amplifier and a fraction of the output signal -Vm and
which i8 therefore also proportional to Vm. The u~e of the
control signal Vfet will be ex~lained later.
The output 6i gnals -Vp and -Vm are applied to the
plu~ and minus input~ of the comparator 19 including the
operational amplifier 170 in the way shown. This amplifier
provides at its output an error signal N only when the
amplitude of the signal Vp i8 Bmaller than a predetermine~
fraction Vrlm of the signal Vm, n being for i,nstance equal to '
10. This fraction is determined by the value'of the resis~rs
171 and 172. The use of the error output signal N will also
be explained later. I
, Since Vm 3 Vp for tne first data code 8ignal, it
iB clear that tbs output Or the comparato~ circuit 19
remainR de-activated for this ~ignal.
. ' _ ~_ ' .
. ' ' . .
'
. ~

,. . I
~ ~aT4~
- 2~l - L. VAN I~DDEGEM 5
The 6ignals -Vm and Vbg are applied to the minus
and P1U5 inputs of the operational amplifi^r 60 (E`ig. 2)
forming part of the summirlg amplifier circuit 10. The
negative going ~ al V~3 appe~ring at theloutput of the
ampli~er 60 has ~n amplitude equal to V~1¦_ Vmm _ Vbg
wherein Vbg + Vmm i~ considered as being a~ threshold signal
and m i8 the suitably cho~en r~tio, e.g. equal to m - 10,
~ of the re~ist~nce,values of the refiifitors 63 (47 kilo-ohms)
and 61 (4.7 kilo-ohms), t~l~ re~istance value (4.7 kilo-ohms)
of the re~i~tor 65 being -bout equal to 1Im m times the
resistance value (4.~ kilo-ohm~) of resistor 64.
By ~ub~tractin~, a threshold value Vbg ~ mm from
the signal VB1, all spurious information with an amplitude
below thi6 threshold will be clipped fromlthe negative
going output signal Vs3 in the precision limiter 22 connected
to the output of the operation~l amplifier 10. This preciRion
limiter circuit 22 (BB, page 246, ~'ig. 7~12) includes the
operational ampli~er 210 and realises an approximation of
the ideal diode behaviour. Hereby the li~iting iB realiBed
at zero volts. The re8ultant signal i8 indicated by V84.
However, it should be pointed fUt that in this
way 8purlou8 informatio~ generated e.g. b~ the reading of a
8pot eimulating the firs;t bar code element will n¢ be
prevented from appearing at the output of the reader becau8e
at ~e occurrence of this first informati~n the maximum
~3
:
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1~3~Z1~3 I
- 25 - L. VAN HEDDEGEM 5
amplitude thereof has not yet been determ~ned. To eliminate
such spurious information use is made of the above mentioned
signal i~, as will be expl~ined later.
It should also further be note~ that as soon as
the output ~ the peak detcctor circuit 14¦becomes activated,
i.e. after RA2 ha~ occurred, the output o$ the summing ampli-
fier 10 becomes activated so that a sig~al appears at its
output. 'rhis ~lgnal i~ however prevented from reaching the
data output D0 of the reader because the ~peration of the
mono8table circuits 180, 181 and therefor~ al~o that of
the mono~table circuits 182 and 183 (having the output D0)
i6 inhibited as long as the sil;nal RAo is de-activated.
This is the reason why the delay 134, 143 has been introduced
and why RAo is generated nfter RA2.
The posit1ve going output signal appe~ing at the
~unction point ol the diode 215 and the resistor 213 of the
~miter circuit 22 is applied to the AGC circuit 23 which is
of the type disclosed in the article "~ET-controlled op amp
permits wide dynamic range" by H.E. ~antana, published in
Electronics, April 4, 197'~, pag~e 122. ~his AGC circuit
~hich includes the operational amplifier 2~0 and the ~`ET's
225 ~nd 226 i~ a voltage-controlled ampli~ier which operates
over a broad range of input signal vo~ager '~he k1ET's 225
and 226 which function as voltage-controlhed resistors are
wlred in L bridge cor~iguroti o n Their i _rent re Lise~oe
, ._,~,~

. i L
llU~Zli~3
- 26 - L. VAN HEDDEGEM 5
non-li.ne~ri.ty i8 avoided by limiting each FET's drain-source
voltage range no matter how large the signal voltage becomes.
The FET 226 i~ controlled by t~le above mentioned output signal
Vfet provi.ded by the control ci.rcuit 21 (Fig. 3) in such a
manner that the ~mplifier 220 provides a substantially
. linear amplification varying between 1 when Vm is equal to
-7.5 Volt~ ~nd 5 when Vm is mir-imum (some multivolts). The
control voltage Vfet is a(ljusted by means of the potentiometers
201 and 20~ ig. 3), the diode 207 preventing voltages Vm
. 10 smaller than -7,5 Volt~ from having an effect on Vfet.
The negative going modulated signal at the output .
of the AGC circuit 23 and which has a neg~tivebar code ~ignal
for each code bar read is applied to the ~ifferentiator
circuit 24 (AN20-~, Fig. 6; B13 page 219,!Fig. 6.17) which
includes the ope~tional amplifier 230. The differentiated
and inverted signal appearing at the output of this differen-
tlator i8 fed for further ampli.fication to a further : -
. ope~tional amplifier 240. The signal at the output o~ this
amplifier 240 has for each bar code signal a positive going
signal portion followed by a negative going signal portion.
This output signal is applied *o the voltage
comparatorsor level detectors with hy6teresi6 forming part
of the comparator circuit 25 (k~ig. 1) and'.including the
operational amplifiers 250 and 251 (Yig. 2). These level
detectorY which ere used to decreaoe ~ ere Or e well ¦ ,
. ~ ~

z~
- 26 - h. VAN HEDDEGEM 5
known configuration, the operational amplifiers 250 and 251
being of the type LM311 disclosed on page 3.12 of the book
"Linear integrated circuits" published by National Semi-
conductor, August 1972. The detector including the opera-
tional amplifier 250 transforms the conductive positive andnegative going portions of each signal applied thereat into
negative going pulses substantially coinciding with these
positive going portions. On the contrary, the level detector
including the operational amplifier 251 transforms these
positive and negative going portions applied thereat into
negative going pulses substantially coinciding with these
negative going portions. Both-these negative going pulses
; vary between +5 volts and 0 volts. The pulse trains thus
generated at the output of the operational amplifier 250
and 251 are indicated by Vdl and Vd2 (Fig. 5) respectively.
The positive going trailing edges of the pulses of the
output pulse train Vdl are further delayed by the delay
circuit including the resistors 262, 263 the capacitor 264
and the diode 265. The output pulse train with the thus
lengthened negative going pulses is indicated by Vd'l
(Fig. 5).
From the abo~e, it follows that when a positive
going signal is applied to the differentiatox circuit 24
the comparator ciXcuit 25 pxo~ides two immediately consecu-
tive negative going pulses at its ~utputs Vdl and Yd2. Onthe contrary, if for instance a negatiVe going spurious
- 26
'
-

~142~
_ 27 - L. VAN HEDDEGEM 5
signal is applied to the differentiator cixcuit 24 the
comparator circuit 25 provides two immediately consecutive
negative going pulses at its outputs Vd2 and Vdl, i.e. in
a reverse order. To prevent such spurious signals from
being identified as data signals one proceeds in the
following way.
The pulse trains Vdl, Vd2 and Vd'l are applied
to the monostable circuits 180 to 183 each of which has two
pairs of inputs Al, A2 and Bl, B2 and a pair of outputs
Ql, Ql to Q4, Q4 respectively. These monostable circuits
have a time constant equal to 3/4 T, 3/4 T, 5 micro-seconds
and 10 microseconds respectively, T being the period of
successive pulses of the pulse trains Vdl and Vd2 and being
about equal to 750 microseconds. These monostable circuits
180 to 183 are of a type which will be triggered to its
unstable condition when the trigger conditions which may be
represented by the Boolean functions S = Ql.Vdl.RAo ;
S2 - Q2.Vd2.RAo ; S3 - Q2.Q3 and S4 - Vd'l.Ql.Q3 change
from 0 (0 Volts) to 1 (+5 Volts).
When considering a negative going input pulse
of the pulse train Vdl applied to the monostable circuit
180, a negative going pulse of duration 3~4 T and the
leading edge of which coincides with the leading edge of
this input pulse appears at the output Ql of this ~onostable
circuit 180. Indeed, at that moment the above tx~ggex condi-
tion Sl is satisfied s~nce Ql = 1, Vdl ~ O and RAo = 1.
- 27
,
.
' ' , , ~ ' : - ~ '

- 28 - L. VAN HEDDEGEM 5
The negative going pulse Ql indicating that a negative
going pulse has occurred in the pulse train Vdl.
Likewise, when considering a negative going
input pulse of the pulse train Vd2 applied to the mono-
stable circuit 181, a negative going pulse of duration
3/4 T and the leading edge of which coincides with the
leading edge of this input pulse appears at the output
Q2 of this circuit. Indeed, at that moment the trigger
condition S2 is satisfied because Q2 - 1, Vd2 - O and
RAo - 1. The negative going pulse Q2 indicates that a
negative going pulse has occurred in the pulse train Vd2.
As a consequence of the operation of the mono-
stable circuit 181, the trigger condition S3 changes from
0 to 1 so that the monostable circuit 182 is triggered to
its unstable condition wherein it remains for a time interval
of 5 microseconds. The positive going output pulse Q3
appearing at the like named output of 182 also indicates
that a negative going pulse has occurred in the pulse train
Vd2.
To check the consecutiveness of two pulses of
Vdl and Vd2, it would apparently be sufficient to check the
coincidence of Ql and Q3. Fo~ other reasons, however, the
coincidence of Vd'l.Ql and Q3 (condition S4) or of Vd'l ~ Ql
and Q3 is checked.
In the usual case shQwn in Fig. 5, the condition
S4 is satisfied because Vd'l ~ 1 and Ql - 1 at the moment
Q3 - 1. The use of Vd'l is especially re~uired for the
- 28 -

21&1
-29 ~ L. VA~ HEDDEGEM 5
first signal because when such a first signal is applied
to the AGC circuit its leading portion is ampltfled therein
with the maximum value (5) so that this first signal may be
considerably lengthened. The thus lengthened signal may be
so long that after having been applied to the differentiator
circuit 24 and to the circuitry 25 the pulse Ql is already
finished before the occurrence of the pulse Q3, as shown in
Fig. 6 so that it is impossible to detect this first signal
by checking the coincidence of Ql and Q3. However, in this
case, the condition S4 is also satisfied because Vd'l - 1
and Ql - O at the moment Q3 - 1.
Finally, the condition S4 is also satisfied when
Vd'l - O and Ql - 1 at the moment Q3 - 1. This happens
when the differentiation and subsequent pulse forming leads
to pulses Vdl and Vd2 which are so short and at such a
distance from one another that even the lengthened pulse
Vd'l is finished before the occurrence of the pulse Q3,
as shown in Fig. 7.
If now due to an error an above mentioned
negative going spurious signal is applied to the differen-
tiator circuit 24, two consecutive negative pulses appear
in the pulse trains ~d2 and Vdl. In the same way as
described above, the monostable circuits 180 and 181 will
be triggered by the second and fi~st of these pulses respec-
tively, whereas the monostable circuit 182 will pxovide a
positive going output pulse Q3, the leading edge of which
substantially coincides with the first of these pulses.
~ 29
~. - ,.
' ~
, .

- 30 - L. VAN HEDDEGEM 5
Since the duration of the latter pulse Q3 is very small,
it will be finished before the occurrence of the second
negative going pulse and therefore the monostable circuit
183 will not be triggered. Consequently, no data output
pulse will ~e generated at the data output DO of this
monostable circuit.
It is clear that in the same way also separate
spurious pulses which would appear in the pulse trains
Vdl and Vd2 are eliminated.
Each output pulse appearing at the output Q4 or
DO of the monostable circuit 183 is a data output pulse.
When this monostable circuit 183 is triggered for the
first time, the bistable circuit 194 which has previously
been prepared for operation by the read authorization
pulse RAo is now triggered to its l-condition due to its
l-input being de-activated. In this condition, its l-output
is activated and its O-output is de-activated, so that
the NAND-gate 196 is authorized and via the output VPO an
inhibit signal is applied to the peak detector circuit 13
wherein the FET 114 is then blocked through amplifier 92
and the diode 109. As already mentioned above, this peak
detector circuit 13 normally registers the amplitude Vp
of the first code bar signal and is blocked by the first
output signal DO.
As also already mentioned, it may happen that
spurious information on the envelope simulates the first
- 30 -
:
, .

1~34Z~3
_31 _ L. VAN HEDDEGEM 5
bar code element. This signal is registered in the
circuits 13 and 14 just between a normal first signal.
Afterwards, when the real first bar code
element is then read the peak detector circuit 14
registers the amplitude Vm of the corresponding bar
code signal on condition that this amplitude is larger
than that of the spurious signal. Supposing that the
amplitude Vnm is larger than Vp a positive going
signal N appears at the output of the comparator
circuit 19 (Fig. 3) to indicate that the ratio of Vm
and Vp is larger than the predetermined maximum ratio n,
as described above. This output signal N is applied
to the already authorized NAND-gate 196 (Fig. 4) via
the resistor 188. As a consequence, the output of the
latter gate is de-activated due to which the bistable
circuit 195 is triggered to its l-condition and wherein
its output NROP is activated, thus indicating that all
the information which has been read until then is
erroneous and should therefore be cancelled.
It should be pointed out that instead of
starting the operation of the peak detector circuits 13
and 14 simultaneously, it would be possible to start
that of circuit 14 after that of circuit 13 and to
temporarily establish a threshold equal to a fraction
of the peak value Vpt xegistered in the c~rcuit 13 until
the peak value Vmt has ~een registered in the circu~t 14.
31 -

Z~l 3
- 32 - L.:VA~ HEDDEGEM 5
While the principles of the invention have been
described above in connection with specific apparatus, it
is to be clearly understood that this description is made
only by way of example and not as a limitation on the
scope of the invention.