Note: Descriptions are shown in the official language in which they were submitted.
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BACKGROUND OF THE INVENTION
1~ Field of the Invention
This invention relates to display processors including
refresh memory storage and means for modifying the memory contents
under computer control, and more particularly to such a system
employing a resident processor which initiates a display segment,
and performs display related tasks and also performs communication
and editing functions between the generation of display segments.
2. Prior Art
Cathode ray tubes are commonly employed as output or
display devices in computer systems. When the common type of low
persistence cathode ray tube is employed the display must be
repeated, or refreshed, at a relatively high rate to create the
visual impression of a continuous display. While it would be
technically possible to store the display contents in the com-
puter's random access memory, and to use the computer to select
character codes from the memory and to provide them to the dis-
play device, this high speed, highly repetitious task would re-
quire a large part of the computing capacity of a relatively high
speed computer. Accordingly, special purpose "refresh" memories
have typically been employed to store the character codes to be
displayed on the CRT screen and hardwired circuits have been
developed to perform the task of continuously generating the dis-
play from this memory, and performing certain auxilliary tasks
such as "scrolling" a larger body of text than can be displayed
at one instance to provide successive lines of this larger body
of text for viewing. These refresh memories and associated hard-
ware have been termed "display processors". They are typically
associated with a computer which modifies the refresh memory
contents from time to time as required.
The recent development of low cost, integrated circuit,
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digital numerical micro-processors, has resulted in the sub-
stitution of these processors for elaborate logic arrays in a
wide variety of di~ital equipment. The micro-processors can
often be programmed to perform a given set of digital functions
at a lower cost than building a special purpose logic array of
discrete components. The possibility of using a micro-processor
as a substitute for the logic in a CRT display processor thus
appears superficially attractive, but certain fundamental
obstacles limit this substitution. Primarily, the speeds o~
micro-processors are not sufficient to allow them to per~orm
the entire display generation task and it would be necessary to
still provide some discrete digital hardware along with the
micro-processor in a display processor system, using the micro-
processor to replace only a portion of the processor's discrete
logic. This trade-off is of only marginal economic advantage
and accordingly micro-processors have been used with, but not
as part of display processors.
SUM~ARY OF THE INVENTION
The present invention is directed toward a system
wherein this marginally advantageous substitution of a micro-
processor for some of the discrete logic of a display processor
is made, but the coupling of the micro-processor to the system
is made in such a way as to free up the processor's capacity
during a substantial portion of the time to allow it to perform
other processing tasks typically associated with the display
processor environment; in particular, those tasks associated
with a remote computer terminal having a keyboard and communi-
cating with a central computer as an I/O device. These tasks
include editing the refresh memory on the basis of commands
received from the CPU or the keyboard, monitoring the activity
of the keyboard and encoding keyed signals, and performing the
communication protocol with the CPU. Additionally, a micro-
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proccssor mny be progrnmmed to ~crform certain computational functions associ-
ated with an "intelligent terminal" during that portion of the time when it is
not involved in the display cycle.
A central aspect of the present invention relates to the use of a
single random access memory as both the refresh memory and as working storage
for the micro-processor. While the memory is being used for display purposes
the micro-processor cannot gain access to the memory for its other operational
tasks, so the present system can be viewed as employing a time sharing system
for the random access memory~
In accordance with the invention there is provided a display pro-
cessor, comprising: a digital, program controllable, numerical processor; a
display device; means for repeatedly generating a raster of scans of the dis-
play device; a random access memory connected to the digital processor and to
the display device; a memory address counter connected to the memory and op-
erative to specify the address of a memory location the contents of which are
to be provided to the display device; a control program for the digital pro-
cessor operative to define a plurality of operations to be performed by the
processor including the operation of loading into the memory address counter
the initial memory address of the first of a series of character codes stored
in contiguous memory addresses to be displayed; and means for incrementing
the memory address counter in timed relation to the generation of a display
on the display device.
In accordance with another aspect of the invention there is provided
a display processor, comprising: a digital, program controllable, numerical
processor; a display device; means for repeatedly generating a raster of scans
of the display device; a random access memory connected to the digital proces-
sor and to the display device; a memory address co-mter connected to the mem-
ory and operative to specify the address of a memory location the contents of
which are to be provided to the display device; a control program for the
3~ digital processor operative to define a plurality of operations to be perform-
ed by the processor including the operation of loading into the memory address
counter the initial memory address of the first of a series of character codes
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stored in contiguous me~ory nddrcsses to be displayed; means for incrementing
the memory address counter in timed relation to the generation of a display on
the display devicc; and means for inhibiting processing activity of the digi-
tal processor until the memory has outputted said entire set of contiguous
character codes.
In accordance with another aspect of the invention there is provided
a display processor, comprising: a digital, program controllable, numerical
processor; a display device; a random access memory connected to the digital
processor and to the display device; a chain of dividing counters operative
to pro~ide timing signals to the display device to cause it to repeatedly
generate raster scans; a clock connected to the digital processor and the
divider chain Operative to cause the digital processor to operate in synchro-
nism with the generation of raster scans of the display device; means, con-
trolled by said digital processor, for causing the generation of a predeter-
mined sequence of characters, stored in said random access me ry, on the dis-
play device; and means for inhibiting processing activity of the digital pro-
cessor during the generation of said sequence of characters on the display.
In accordance with another aspect of the invention there is provided
a display processor, comprising: a digital, program controllable numerical pro- !
2n cessor; a display device; a random access memory connected to the processing
unit and to the display device, the memory storing a plurality of sets of
character codes each comprising one segment of the display, with the codes
forming each set stored in contiguous sections of the memory; a memory address
counter connected to the memory and operative to specify the address of the
memory section which is to be generated on the display; a control program for
the digital processor operative to define a plurality of operations to be per-
formed by the processor including the operation of loading the initial memory
address of one of said sets of character codes in the memory address counter;
means for incrementing the memory address counter in timed relation to the
generation of a display on the display device; and means for inhibiting pro-
cessing activity of the digital processor until the memory has outputted said
entire set of character codes.
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In the preferred embodiment of the invention, tlle micro-processor
initiates a display cycle in which a short segment of the total screen is dis-
playedJ preferably one line. This is achieved by providing a memory address
register tllat may be incremented in the manner of a counter. The micro-
processor generates the memory address of the initial character in the dis-
play segment and loads this address into the memory address counter. Incre-
ments are added to the counter in timed relation to the display scan to suc-
cessively address all of the characters in the line, which are stored in con-
secutive me ry locations. This permits the displayed characters to be mapped
into minimum RAM space. This is to be contrasted with prior art systems where-
in it was common practive to leave empty memory locations to compensate for
the fact that the length of a display line was a non-binary value. The address-
ed character codes are provided to a character generator which outputs video
intensity signals for the CRT. A row of text characters is generated by a
series of horizontal lines each representing one horizontal slide through the
row so the counter must go through its address sequence a number of times to
generate a complete row. To accomplish this the micro-processor reloads the
initial me ry address of the text row into the counter a number of times.
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At the end of the generation of a row of the scan
the processor again has access to the RAM and can perform edit-
ing, I/O, or other computational functions during horizontal or
vertical retrace.
If the processor generates the memory address of the
initial character of the next display line and provides it to
the memory address counter by the time the display scan reaches
the point at which that character must be displayed, the next
line of display is generated; if, however, the processor does
not meet that deadline the display is terminated for the balance
of the screen and the processor reinitiates the display when the
scan reaches the time for generation of the first character on
the next display cycle. This aborting of a portion of the
display will result only in minor degradation of the display
appearance, typically unnoticeable; however, it allows the pro-
cessor to gain a relatively large segment of processing time
which may be used to perform longer than normal non display
tasks. This novel arrangement effectively sets up a priority
system between display and non-display activity of the processor
yet maintains the processor activity in synchronism with the
asynchronous display scan process.
Because it defines the next memory segment that is
displayed on the screen at any time, the processor can readily
edit the display on a line-to-line basis without skipping any
display period. The processor also monitors the display process
to perform such tasks as controlling underlining or blinking of
the screen.
The system of the present invention thus couples a
micro-processor to a refresh memory and associated display
hardware so as to obviate the need for display system elements
which would otherwise be required in a discrete display processor
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system, and in such a manner as to free up the processor for non-
display tasks at times which do not degrade the display and
additionally allow it to share the random access memory with the
display processor.
Other objectives, advantages and applications of the
invention will be made apparent by the following detailed de-
scription of a preferred embodiment of the invention. The de-
scription makes reference to the accompanying drawing which is
a partially block, partially schematic diagram of a display pro-
cessor formed in accordance with the present invention.
The present invention employs a digital processing
unit 10. This processor is preferably of the micro-processor
type formed on one or more integrated circuit chips. A wide
variety of these micro-processors are commercially available and
could be employed in connection with the present invention. The
preferred embodiment of the invention uses the micro-processor
Model 8080 manufactured and marketed by Intel Corporation of
Santa Clara, California. In the appended claims processors of
this type will be referred to as "digital, program controlled,
numerical processors".
The program for the micro-processor 10 is stored in
a read-only memory 12 which is also preferably of the integrated
semi-conductor type. Alternatively, the operating program for
the micro-processor 10 could be stored in some form of alterable
memory.
The system also employs a semi-conductor random access
memory 14 which performs the dual ~unction of serving as working
memory for the micro-processor 10 and as a refresh memory for the
display. As a refresh memory it stores the character codes for
at least an entire frame of video data. Preferably the storage
area of the random access memory 14 assigned to refresh memory
will be substantially larger than that required for storing a
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single frame, so that additional lines of text may be stored
allowing the screen to be scrolled.
The micro-processor 10 has bi-directional communica-
tion with the ROM 12 and RAM 14 over an address bus 16 which may
S consist of both a conventional address and data bus. The pro-
cessor may specify an address location in the ROM 12 over the
data bus to read the code stored therein; similarly it may
specify a RAM storage location and either read the code stored
therein or write a new code therein.
The micro-processor 10 interconnects to external de-
vices through an I/O line 18. A keyboard 20 and remote central
processing unit 22 are illustrated as connected on the I/O line.
Other devices, such as cassettes, modems, and printers may also
communicate with the processor 10 over the I/O line 18.
In a typical application, the system may form a remote
terminal of a large computer system having the central processor
22. The keyboard 20 may be associated with the terminal to
allow the operator to provide information to the system.
The timing for the display processor system is derived
from a crystal controlled clock 24. The clock outputs pulses at
a controlled rate which defines the time required for the hori-
zontal scan of an associated cathode ray tube 26 to traverse a
distance which forms the most elementary display element in the
system: a dot. The outputs of this dot clock 24 are provided
to a dividing counter 28 which provides a single output pulse
after eight inputs from the clock 24. These outputs define the
number of horizontal dots in a single character to be displayed
on a screen; the dividers 28 are therefore termed a "character
clock". The output of this character clock is provided to the
micro-processor 10 and defines the micro-processor clock cycle.
This allows the micro-processor to operate in synchronism with
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the generation of the video display and avoids the necessity for
providing separate circuitry to transform signals from one time
base to the other which would be required if separate time bases
were provided.
The output of the character clock 28 is also provided
to a horizontal timing generator circuit 30. This circuit
counts the number of characters contained in one horizontal line
across the display, 80 in the preferred embodiment, and generates
horizontal synchronization signals for a horizontal timing gen-
erator associated with the cathode ray tube 26. The timing
generator 30 also generates a horizontal blank signal which
defines the horizontal retrace time.
The outputs of the horizontal timing generator 30,
which represent the end of a single horizontal line, are pro-
vided to a vertical element counter 32. This counter definesthe number of vertically aligned dots in a character matrix,
as well as the vertical, inter-character spacing. In the pre-
ferred embodiment of the invention a character matrix may con-
sist of five horizontal elements and seven vertical elements.
The height counts of the character clock 28 allow for three dots
of horizontal inter-character spacing. The vertical element
counter 32 counts up to ten, which provides the seven vertical
dots in a character matrix plus three dots of vertical inter-
character spacing.
The vertical element counter 32 provides outputs after
each count of 10 to a row counter 34 which counts the number of
horizontal rows of characters which make up a total frame, 24 in
the preferred embodiment, and generates synchronization signals
for a vertical generator associated with the cathode ray tube 26
and vertical blanking signals that define the vertical retrace
time. The clock 24, and the divider chains 28, 30, 32 and 34
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that receive the outputs of the clock 24, thus control the
generation of the raster of tlle cathode ray tube 26.
The luminance signal for the CRT 26 is derived from
a character generator 36, which contains a memory that stores
the dot patterns for each of the characters that can be dis-
played on the CRT 26. A character code fed to the character
generator 36 on the data bus 16 controls which matrix is out-
putted. An output from the vertical element counter 32 deter-
mines which horizontal line of the matrix is being outputted,
- 10 and the signal from the character clock 28 controls the hori-
zontal element in the matrix which is instantaneously outputted.
Considering next the provision of a particular
character code to the generator 36, from time-to-time the micro-
processor 10, under control of the program in its ROM 12, out-
puts a signal on the bus 16 which defines an address within theR~5 14, and contains a tag command indicating that the RAM 14
should sequentially output the contents of that memory location,
and a series of sequential locations in the RAM, to the character
generator 36. This signal will typically appear on the address
bus portion of the bus 16. Assuming a sixteen bit address
command and a fourteen bit maximum memory address, two bits are
available for use as commands which accompany a memory address.
This operation is substantially simpler than the prior art
techniques of sending a memory address over the address bus and
a command over the data bus.
This initial RAM location stores the character code
for the first character in one horizontal row across the display.
~he character codes for the balance of characters in the row are
stored at sequential memory locations within the RAM.
This initial memory location is provided to a RAM
address counter or buffer 38 and the tag command is provided to
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a ta~ decoder 40. On reco~niæing this display command, the tag
decoder 40 provides a signal to a display state flip-flop 42.
Flip-flop 42 is set by the leading edge of the display command
tag. Previously, flip-flop 42 was in the reset state. When it
is set, an output is provided on line 44 to the micro-processor
10 which indicates that the RAM 14 is under the control of the
RAM address counter 38. This signal inhibits further activity
of the micro-processor 10 and the display command with the
address of the memory location of the initial character code of
the line to be displayed is maintained on the data bus by the
processor. The RAM address counter 38 then controls the memory
location within the RAM 14 that is outputted on the data bus to
the character generator 36. This character code determines the
pattern of dots that is outputted on the video line 46 by the
character generator. As successive outputs are provided from
the dot clock 24, successive horizontal elements in the matrix
are outputted on line 46.
~ fter the dots comprising one horizontal line in a
character have been generated, an output from the character clock
28 increments the RAM address counter so that the character code
contained in the next consecutive location of the R~ 14 is pro-
vided to the character generator 36. This process continues
until the first horizontal line of the characters in a horizontal
line have been generated. At that point a horizontal blank sig-
nal is generated by the horizontal timing generator 30 and pro-
vided to an AND gate 48. A second input to the AND gate 48 is
derived from the high output of the display state flip-flop 42,
on line 44. This indicates that the system is undergoing the
display process. The third input to the AND gate 48 is from the
vertical element divider 32 indicating that the first seven
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vertical lines of a row are being processed; the next three
vertical lines of a row represent inter-character vertical
spacing; and the third input remains low during their occurrence.
When all three inputs to the AND gate 48 are high, an output is
provided to the RAM address counter which causes it to reload
the address of the initial memory location of the line being
displayed from the data bus 16. The processor 10 maintains this
address on the data bus as long as a high output is provided
from the display state flip-flop 44 and the counter 38 is
reloaded with this initial address when the output o the gate
48 goes high. When the horizontal blank signal goes low the
unit 38 is allowed to count in response to character signals
from the clock 28. Accordingly, the same sequence of character
codes are again provided to the character generator 38. Since
the signal from the vertical element counter 32 has changed,
the character generator outputs the second horizontal line in
each character code matrix.
This process continues until the vertical element
counter 32 provides a count of seven, indicating that all seven
horizontal lines of a row of characters have been displayed.
The edge of this signal causes the display state flip-flop 42
to reset, removing the high signal on line 44, and allowing the
micro-processor to regain access to the RAM 14 and continue its
processing. This processing may involve any one of a number of
disparate tasks, such as editing the contents of the RAM 14,
responding to signals from the CPU 22, or attending to input
signals from the keyboard 20 and like devices under control of
the program stored in the ROM.
During this non-display time, the aivider chain
continues its activity, and the three lines of inter-character
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spacing are generated. At the completion of that time, the
vertical element generator 32 provides an output that goes to
the clock input of a D flip-flop 50. The data input to that
flip-flop is from line 44 representing the high output of the
display state flip-flop 42. That flip-flop resets when a count
of seven is reached by the vertical element generator 32 and
will only be in its set state if the micro-processor has out-
putted a display command containing the memory address of the
character code which begins the neYt line to be displayed since
that reset time. If the output on line 44 is high upon
occurrence of a clocking input to the D flip-flop 50 a high
output will be provided to an AND gate 52. This AND gate
receives the video signals on line 46 as a second input. Two
other conditioning inputs come from inverters 54 and 56 which
receive the horizontal blank signal from the timing generators
30 and the vertical blank signal from the row counter 34
respectively. Accordingly, as long as there is no horizontal
or vertical blank signal and the D flip-flop 50 has a high
output, the video signals on line 46 are outputted to the
cathode ray tube 26 to generate the display.
If the output on line 44 is low when a count of 10 is reached
by the vertical element counter 32 a low output will be pro-
vided by the flip-flop 50 and this output will be fed back to
latch the flip-flop in this state. It will stay in this state,
and thus inhibit outputs from the AND gate 52, until it is
reset by a vertical blank signal generated by the row counter
34 at the end of the total frame.
Thus, after the display of any row of characters,
the micro-processor has three line times in which to perform
other processing tasks and to then output the next display
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command to the RAM address counter. If the micro-processor
doesn't meet this deadline, the display is blanked to the end
of a frame and the micro processor can use all of that time to
perform its other processing tasks. This will invol~e a slight
degradation in the display quality, but if only a portion of
one frame is lost it will only result in a hardly noticeable
flicker on the screen. The micro-processor can continue to
preempt time away from the display process, which will result
in more noticeable degradation of the display; however, if the
processor is revising the display this simply means a deteriora-
tion in the display of obsolete data.
The display processing is thus interleaved with other
chores of the micro-processor 10. These non-display tasks may
be performed during the generation of the three inter-character
lines and during the vertical retrace time without interrupting
the continuity of the display processor. If more time is
required for a non-display processing task the processor may
preempt that time, and access to the RAM, by delaying the
generation of a display command.
The micro-processor's operation proceeds in synchronism
with the display process because of their use of the common
character clock 28. The micro processor also receives the
vertical blank signal from the row counter 34. This signal
acts as an indication as to the availa~ility of a relatively
large inter-display time, and also allows the processor to count
frames. It may use the count of frames to control the display
by a cursor or a blinking signal. For example, it may generate
a cursor by substituting a blank for a cursor indicated charac-
ter for a predetermined number of display times. The blank
character may be provided for thirty consecutive display frames
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MRI.-301
and the regular character for the next sixty. The micro-
processor may store the cursored character code during the
generation of the blank and later replace it in its proper
RAM location.
It is therefore seen that the system of the present
invention allows a micro-processor to cooperate in a display
process; to perform non-display tasks in synchronism with the
continuous display; and to preempt display time for these non-
display tasks when required.
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