Note: Descriptions are shown in the official language in which they were submitted.
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Applicant: Robert B. Turner
For: Voltage To Rate Converter Circuit
FIELD OF INVENTIOM
This invention relates to a voltage to rate converter
circuit and more particularly ~o such a circuit whose output
pulse width is precisely det~rmined by voltage levels not RC
timing networks.
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BACKGROUND OF INVENTION
One voltage to rate converter circuit used in an elec-
tronic thermome-ter system, ~.S. Pa~ent Numher 3,972,237, utilizes
an integrator to provide a ramp volta~e output through an RC
network to a unijunction transistor in response to a difference
between an analog temperature signal and a reference signal.
~hen the ramp reaches the unijunction firing threshhold, e.g.
50~ of the base to base voltaget the unijunction transistor
switches on to produce a pulse. This pulse is amplified and the
resulting negative going pulse is fed to a current switch which
provides a positive fixed amplitude, as ~Jell as ~ixed width, puls
t~ a summing point at the analog temperature signal input to ~he
integrator. The presence of this pulse momentarily restores
equality at the integrator input cutting off its ramp output.
The unijunction output pulse is cut of~ followin~ this after
a period established by the RC network. After the pulse
disappears at the s~nming point, if there is still a aifference
at the two inputs to the integrator, the cycle starts again.
The greater the difference at these inputs the greater is the
number of pulses required to equalize that difference. Thus
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the rate of these pulses is a ~easure of the temperature
being sensed.
While this circuit is a good and workable one, it does
have some shortcomings. For example, constant pulse width is
essential; any increase in width artificially decreases the
rate required to effect a particular sensed temperature and
conversely with any decrease. However, the pulse width is
determined by an RC network and capacitors are known to drift
with temperature and age. Less troublesome capacitors are
more expensive and in many applications, such as electronic
thermometers, cost is a very important factor. In addition,
unijunction transistors caused to fire at 50~ of base to ~ase
voltage are necessarily quite susceptible to variations in supply
voltage: a decrease in supply voltage lowers the firing
voltage and thus starts the pulse earlier relative to the inte-
grated output ramp. Feedlng back the pulses to the analog tem-
perature input to the integrator also can drain off some of the
pulse power and artificially increase the pulse rate.
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SUMMARY 9F INVENTION
It is there'ore an object of this invention to provide
an improved, precise, inexpensive, accurate and relia~le
voltage to rate converter circuit.
It is a further o~ect of this invention to provide such
a voltage to rate converter circuit adapted for use in an
electronic thermometer.
It is a further object of this ln~ention to provide such
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a voltage to rate converter circuit which is insensitive e~en ~o
significant variations in supply voltage.
It is a further object of this invention to provide such
a voltage to rate converter circuit which defines its pulse
width temperature independent of RC networks and capacitive
components.
It is a further object of this invention to provide such
a voltage to rate converter circuit which develops its pulse
rate without intermingling of the output pulses wi~h the input
1 n analog signal.
The invention results ~rom the reali2ation that voltage
to rate converter circuits having output pulses of precise
width ~an be constructed by using an integrator to produce a ramF
signal in a first direction in response to a di~ference
between a first integrator reference level and the analog
signal at its input, and a comparator to produce an output pulse
in response to the ramp signal reaching a first comparator
reference level which pulse is used to enable the ~irst referenc
levels to change to second levels, reversing the ram~ signal
~0 slope and causing the output pulse to cease when the second
comparator reference signal is reached.
The invention features a voltage to rate converter circuit
for providing ouput digital pulses at a rate proportional to
an analog input signal. There is an input reference circuit
~ ~ for es blishing ar input reference slgnal of a flrst le~el
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and an integrated circui-t for providing an output ramp signal
proportional to the difference between the analog input s1gnal
and the input reference signal of a first level. The output
ramp signal has a first slope direction which is a function
of the polarity of that difference. The reference modifier
circuit interconnects with the integrated circuit for
shifting the input reference signal to a second level to
reverse the slope direction of the output ramp signal to a
second slope direction. A comparator reference circuit alter-
nately establishes a comparator reference signal of a first
value and o~ a second value. A comparator circuit provides an
output pulse beginning in response to the output ramp signal in
the first slope direction exceeding the comparator reference
signaI of a first value and ending in response to the output
ramp signal in the second slope direction exceeding the compara-
tor reference signal of the second value. Switching means
responsive to the output pulse enable the comparator reference
circuit to shift the comparator reference signal from the first
value to the second value and enable the reference modifier
~ circuit to shift the input reference signal from the first
level to the second level.
In a preferred embodiment the voltage to rate converter
circuit of this invention is used in an electronic thermometer
system including a temperature sensing circuit proviaing an
analog output signal representative of the temperature being
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sensed and means for counting the output pulses from the vol-
tage to rate converter for a predetermined period of ~ime for
providing an indication of the temperature being sensed. The
input reference circuit establishes a first input xeference
signal which is more positive than the analog input signal repre-
senting the temperature. ~n inteyrated circuit provides a nega-
tive slope ramp output signal proportional to the difference
between the analog input signal and ~he first input re~erence
signal. A refexence modiier circuit interconnected with the
integrated circuit establishes a second input reference signal
less positive than the analog input signal to reverse the slope
dixection of the ramp output signal to a positive slope.
The comparator reference circuit alternately establishes a
first comparator reference signal and a second comparator
reference signal more positive than the first. A comparator
circuit provides an output pulse beginning in respons~ to the
negative slope output ramp exceeding the first comparator
reference signal and ending in response to the positive slope
ramp output signal exceeding the second comparator reference
signal. The switching circuit responsive to the output pulse
enables the comparator reference circuit to shift from the
first to the second comparator reference signal and enables the
reference modifier circuit to shift from the first to the second
input reference signal.
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According to a further broad aspect of the present
invention ~here is provided a voltage to ra-te converter for
providing output digital pulses at a rate proportional to an
analog input, comprising a) an input reference circuit for
establishing an lnput reference signal of a first level, b)
an integrator clrcuit for providing an output ramp signal
proportional to the difference between said analog input signal
and said input reference signal and having a slope direction
which is a function of the polarity of that difference, c)
reference modifier means for shift.ing said input reference signal
between said first level and a second level, said first and
second levels having respective amplitudes with respect to the
range of said input signal to insure respectively corresponding
o~posite directions of slope for said ramp signal, said modifier
circuit, by shifting said levels, thereby correspondingly
reversing the slope direction o~ said ramp signal, d) a
comparator reference circuit for alternately establishing a
comparator reference signal of a first value, and o a second
value, said ~irst and second values defining, relatively to said
ramp signal, reference points for switching said input re~erence
signal between said levels, and thereby for reversing the
direction of said ramp signal, and e) comparator me~ans for
switchably controlling the one of said values established by said
comparator reference circuit at a given time, and for comparing
said output ramp signal with said one of said values, said first
and said second values being alt~rnately established as a
comparison re~erence point toward which said ramp slope then is
tending, said comparator means switching said values and said
levels of said input reference signal substantially a,s said ramp
signal matches said one of said values, said comparator means
providing an output pulse signal having binary levels corres- ~
ponding respectively with establishment of said first and second :
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values, wherein one o said binary le~els is of a fixed
duration dependent exclusively on the spread of said first and
second values, and the other of said binary levels is of a
duration ~hich is a function of the difference between said analog
input and said first level, wherein said converter comprises said
comparator means including: f) a comparator for compa.ring said
one value with said ramp signal, and for producing a binary pulse
signal having a state dependent on the relative amplitudes of
said one value and said ramp signal, and g) switching means
responsive to a change of state of said binary pulse signal,
for controllably switching said reference modifier circuit to
alter the prevailing level at said input reference circuit, and
for controllably switching said one value to said other value;
and a converter as described a~ove wherein said integ.rator circult
comprises: h) a dual input amplifier having an output and
respective inverting and non-inverting inputs, i) means for
coupling said analog input to said non-in~erting input; j)
capacitive circuit means in feedback arrangement between said
inverting input and said output of said amplifier, ~) first
~ 20 resistive means between said inverting input and the circuit
datum point, and 1) second resistive means, switchably energized by
said reference modifier means, be-tween said inverting input and
the circuit datum point.
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DISCLOSURE OF PREFERRED EMBODI~IENT
Other objects, features and embodiments wlll occur from
the following description of a preferred embodiment and the
accompanying drawings, in which:
FigO 1 is a block diagram of an electronic thermometer
system using a voltage to rate converter circuit according to
this invention;
Fig. 2 is a more de~ailed block diagram illustrating one
implementation of the system OI Fig. l;
Fig. 3 is a block diagram of a voltage to rate converter
. 15 circuit according to this invention;
Fig. 4 is a graphical illustration of the output signal of
: the-integrator and of the comparator of Fig. 3; and
Fig. 5 is a detailed schematic diagram of the circuit
shown in Fig. 3.
There is shown in Fig. 1 and electronic thermometer system
L0 according to this invention including a temperature sensing
_ircuit 12 which senses the temperature and provides an analog
~ignal representative thereof to the voltage to rate converter
-ircuit 14. Voltage to rate converter circuit 14 provides at its
~utput digital pulses whose repetition rate is proportional to the
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analog input signal representative of the temperature being
sensed. T~lis system is opera-ted with power and control circuit
18.
Temperature sensing circuit 12 may include a probe 20,
Fig. 2, for sensing a temperature to be measured and producing
an analog signal representative thereof which i5 submitted through
internal reference circuit 22 to bxidge circuit 24. Internal
reference circuit 22, immediately upon unplugging of probe 20 .
automatically connects a matching circuit to bridge cIrcuit 24
in place of the input from probe 20, so that khe accuracy and
operation of the system can be verified. 8ridge circuit 24 .
pro~ides a reference output on line 26 and on line 28 provides
a varying output as a function of the bridge imbalance represen-
ting the analog signal which is a function of the temperature .
sensed by probe 20. In this specific embodiment, used primarily
: to take the temperatures of human5, the measurement range is
t~pically from 90 to 110F. Thus reference output 26 of bridge
circuit 24 represents the level of 90F; when output 28 of brid~e
circuit 24 is equal to reference sutput 26 the thermometer pro~e
20 is measuring a temperature of 90F. When output 28 is at a
predetermined deviation from the level of output 2~ the probe
20 iS measuring 110F. Output 28 is fed to anticipation ..
circuit 30 which senses the rate of change of the temperature
being sensed by probe 20 and modifies the signal on output 28
~from bri e circuit 24, thereby providing a signal at output 32
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of anticipation circuit 30 to voltage to rate converter 14
representatlve of the final value of the temperature being
sensed in advance of the actual sensing of that final value.
Counting circuit 16 includes digital counting ana decoding
circuit 42 which counts the digital pulses provided at the output
of voltage to rate converter circuit 14 for A predetermined
period of time and decodes that count to display the measured
temperature on digital display 44.
Power and control circuit 18 includes a power supply 46 ..
and an automatic on-off electronic switch 48 which control~
all power to the system. Precision voltage regulator 50
provides re~ulated voltage, PVR, to bridge circuit 24, reference
current switch 40, integrator circuit 34, vQltage to rate con-
verter 14, and low battery voltage sensing circuit 52. The
~ other input to low battery voltage sensing circuit 52 is the
unregulated power supplied at the output of automatic on~off
electronic switch 48. When the pO~Jer supply volt.age decreases
to a predeterm~ned level low battery voltage sensing circuit 52
provides a signal to digital counting and decoding circuit 42
causing it to extinguish the least significant digi~ of the
temperature appearing in digital display 44.
Electronic thermometer system lQ operates in two modes~ a
time display mode and a temperature display mode. Digital con-
trol logic 54 supervises system performance in each of these
~5 modes and controls the transition hetween them. In the time dis-
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play mode digital control logic 54 passes pulses from clock 56
to digital counting and decoding circuit 42, while in the
temperature display mode diyital control logic 54 directs pulses
from voltage to rate converter circuit 14 to dig~tal counting
and decoding circuit 42. The system is operated by actuation
of start switch 58.
In operation, wl1en start ~witch 58 is actuated, automatic
on-off electronic switch 58 is turned on to supply power from
power supply 46 to the rest of the system, and digital control
~10 logic 54 and digital counting and decoding circuit 42 are reset.
Probe 20 in contact with the patient whose temperature is to
be measured be~ins to sense the temperature. As temperature T,
Fig. 2, sensed by probe 20 increases the resistance R of the ther-
mistor used in probe 20 decreases; the voltage ~t output 28 of
`15 bridge circuit 24 decreases, decreasing the voltage at output
32. The difference in levels of output 26 and output 32 causes
pulses to be generated at a repetition rate which represents the
final value of the temperature being sensed.
In one embodiment voltage to rate converter 14 includes an
input reference circuit 100 which provides an input reference
signal to input 102 of integrator lQ4. The analog temperature
signal on Line 32 is provided to input 106 of integrator 104.
Reference modifler circuit 108 periodically shifts the reference .
siynal at input 102 in response to a signal from switching
~¦cirouit 0 enab1ed by the output pulse on line 112 from cor-
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parator 114. Compar~tor 114 receives one input on line 11~ .
from the output of integrator 104 and the other on line 118
from the output of comparator reference circuit 120. In
operation, as indicated by curve 122, Fig. 3, a~ t'~e temperature
sensed increases the voltage decreases providing a differential
between input 106 and input 102 of integra~or 104. ~ith input
106 going negative with respect to input 102 the ramp output
124, Fig. 4, of integrator 104 has a negative slope. This
negative slope ramp 124 presented on line 116 of comparator 114 .
~ has no ~ee~ until it reaches and exceeds the one volt reference ...
signal being provided at input 118. When that occurs, comparator
114 immediately provides a pulse 125 of high output 126 on line
112. During the period of that positive level 126, switching
circuit 110 enables comparator reference circuit 120 to provide
a higher positive voltage, 2.7 volts, at input 118 of
comparator 114. At this time switching circuit 110 also enables
reference modifier circuit 108 to drive input 102 less positive,.
or more negative, than it was. Previously it was moxe positive
than the analog temperature signal at 106. Now it will be
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~ negative than the analog temperature signal at 106. This.
reversal in polarity at ~he input o~ integrator 104 causes it to .
reverse the slope of its output ramp and begin providing a posi- . :
tive slope 128 ramp, Fig. 4. Comparator 114 continues to provide .
a high level 126 until positive slope ramp 128 reaches and
exceed~ the upper 2.7 voltage level which is provided at input .
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18 by the action of switching circuit 110. At that point
the output of comparator 112 drops down to zero level 130,
~ig. 4 deenergizing switching circuit 110, t'lus causing
~omparator reference circuit 120 to return to its first
eference level o~ 1 volt and disabling reference modi~ier cir-
-uit 108 so that input 102 once again reverts to its condition
~f being more positive than the analog temperature signal at
nput 106. Presuming that analog temperature signal at 106
s now still more negative than the reference signal at input
02 integrator once again begins integrating downwardly with
negative slope ramp and the cycle begins again. The
reater the difference b~tween inputs 102 and 106 the shorteE
s the time that it takes the negative slope ramp output
24 of integrator 104 to move from 2.7 volts down to 1 volt.
hus the pulses occur at a higher rate in response to the
igger difference between inputs 102 and 106: the rate of
?ulses provided by comparator 114 is directly proportional
to the difference between the analog temperature signal at
input 106 and the reference signal at input ln2. The width
f the pulses 125 is determined by the time t2 that it takes
~e positive slope ramp o~tput 128 of integrator 104 to move
rom 1 volt to 2.7 volts. This time may be adjusted simply
~y adjusting the DC voltage levels now set at 1 volt and 2.7
olts and does no~ depend on an RC timing network.
~25 ~¦ Mor pecirically, voltage to rete CoDverter 14 may
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: be constructed as shown in Fig. S, where input reference
circuit 100 includes a voltage divider consisting of resistors
150, 152, and 154 which extend from input 153 to ground- 155~
They axe used to set the voltage at point 156 so that at 90F
: the output pulse rate of voltage to rate converter 14 is
~ero. ~esistors 158 and 160 are trimming resistors used
to set the full scale ou~pu~ of circuit 14. That is, at
: 110F the output pulse rate is 2000 pulses per second. The
resistance of resistor 160 may be changed to provide the tem-
perature readings in degrees Centigrade. Integxator 104 con-
sists of an amplifier 168 ~*~r~ by an integrating capacitor
170. ~he analog temperature signal on input 106 is delivered
. to the positive, high impedance input of amplifier 168 to
prevent any loading of the thermistor, anticipation or o~her
input circuits. Feedback adjustments which function to set
the output pulse rate in proportion to the temperature as .
provided by reference modifier circuit 108 are introduced to
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the reference input terminal 102 of amplifier 168, where they .
. do not lntermingle in any way with the a~alog temperature .
~ ~ signa1 Lnput 106. ~eference modirieF 10a Includes a tr-n-
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sistor 172 whose emitter 174 is connected to ground 155 and
whose collector 176 is connected through resistor 178 to input
102 of amplifier 168. Reference modifier circuit 108 also
includes biasing resistors 180 and 182. The output of ampli-
fier 168 is directed to the input 116 of amplifier 184 in
COMparator 114. The positive input 118 to amplifier 184
is connected ~o comparator reference circuit 120, which includes
a voltage divider comprising resistors 190 and 192 in parallel
with which is resistor 194 and resistors 180 and 182 of refe-
.0 rence modifying ~ircuit 108. Amplifier 184 includes an addi- .
tional biasing resistor 19~6. The output of comparator 114 is
fed directly to bilateral swit~h 200, such as an RCA C-MOS
4016, which includes a numher of semiconductor switch.ing cir-
cuits. One of those circuits 2~2 which includes an input IN,
.5 output O, and control terminal C receives output pulses on line
112 from.comparator 114 on the control terminal C. Durin~ the .
period o the presence of each pulse the input connected to
. the regulated power suppl~ 153,which is 5 volts positive,is
; close~ to output O, which is connected to comparator reference
0 circuit 120 and reference modifier circuit 108.
Thus upon the sensing of i~creasing temperature a signal .
: on input 106 of amplifier 168 decreases. If the input 102 i5
positive with respect to the input 106, amplifier 168 provides
a negative slope ramp output to input 116 of comparator
~S amplifier 184. Input 118 of amplifier 184 is held at 1.0 volt .
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by resistors 190, 192, 194 in comparator reference circuit 120
and resistors 180 and 182 in reference modifier circuit 108.
When the negative going ramp reaches and exceeds the 1.0 volt
level present at input 118 amplifier 184 immediately goes
; 5 positive providing pulse 125 having an amplitude 126 as shown
in Fig. 4. This pulse closes switch 202 and provides +5 volts
to both the comparator reference circuit 120 and r~ference
odifier circui~ 108. Immediately, the input 118 to amplifier
84 moves from 1.0 volt positive to 2.7 volts positive. Simul-
aneously, transistor 172 is made to conduct drawing input 102
. . ore negative, or less positive, so that input 102 is now less
Qsitive than input 106. This switches amplifier 168, reversing
ts output so that it now provides a positive slope ramp which
ncreases without effect until it reaches 2.7 volts. At this . ..
oint amplifier 184 responds by ceasing output so that pulse .
25 drops to the zero level 130, Fig. 4~ This disables switch
02, removes the ~5 volt signal from comparator reference circuit
20 and reference modifier circuit 108 so that input 118 to
: mplifier 184 resumes the 1.0 volt level and input 102 to amplifie~ .
68 xeturns to the condition where it is more positive than the
nput 106. Typically point 156 is held at approximately 2.1 volts
d transistor 172 is off. Capacitor 170 charges through
ransistor 172 as the output of 16~ goes positive and dis- .
harges through resistors 158, 160, 152, and 154 auring the
~egative pe output of ar.plifier 168, period t2, Fiq. 4 of ¦
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ositive slope 128 which precisely sets the pulse width of pulse
¦125 is determined by strictly DC voltage levels which are
. ¦provided at input 118 to comparator 184. The zero level
. 130, Fig. 4, which exists for time t2 between pulses is de-
termined by the reverse slope ramp 124 as it descends from
2.7 volts to 1.0 volt. If the precision voltage regula-to.r
input 153 should fail for some reason the voltage to rate
converter 14 still operates properly to provide a constant
A width pulse when there are signifi~ reductions in voltage,
for example of 10 or possibly 20%. This can be illustrated
with r~spect.to Fig. 4 where the decrease in voltage.has
been exaggerated somewhat to be SO~ 50 that the peak voltage
: is 1.35 volts instead of 2.7 and so the minimum voltage
is 0.5 volts instead of 1.0 volts. ~n that case, as can .
L5 be seen in Fig. 4 positive going ramp 128' increases at
a slower rate but to a lower value and neyative going ramp
: 124' behaves similarly by descending from a lower value .
~aLbeit a~ l~wel rate t 1 and t2 remai~ tle same
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