Note: Descriptions are shown in the official language in which they were submitted.
This invention relates to a multiplex communication
system and is particularly, but not exclusively, intended
for use in motor vehicles.
Conventional practice in motor vehicles has been to
provide each powered device (light, horn/ windscreen wiper
motor, etc.) with its own power lead and associated driver's
control switch, and to provide a number of warning and
indicating instruments (fuel gauge, tachometer, oil pressure
warning, etc.) each connected to an appropriate sensor by
separate wiring. ~his gives rise to wiring looms of con-
siderable complexity and cost. It is also necessary to
fabricate and stock different wiring harnesses for each
model of vehicle.
There have hitherto been a considerable number of
proposals to overcome these problems by using a common
channel interconnecting all electrically powered devices
and monitoring devices with a central control station,
information being passed along the channel by multiplexing
techniques. None of these proposals has yet been put into
practice in volume vehicle production, principally for
reasons of cost~ and/or complexity. The factors which can
be identified as necessary for a commercially viable system
are:
~a~ the system must be mechanically simple and robust;
(b~ the number of difEerent components required must
be kept to a minimum;
~c~ the system must be sufficiently fast to maintain
information such as road and engine speed sufficiently
up to date in real time for the purposes of the
driver;
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(d) it must be possible to control at least 50
functic>ns and to receive informatioll from a similar
number of sensors; and
(e) there must be signal security whlch prevents
spurious signals caused hy interference effecting
erroneous operation of controlled devices.
Of the systems previo~sly proposed, some have been
too slow or have too small a channel capacity to be
suita~le for use in vehicles, while others have achieved the
required speed and channel capacity by using long trains of
pulses at high repetition rates which requires the use
of high frequency components with a-ttendant expense. Other
systems are unsuitable because they require a number of
signal-carryin~ conductors, which increases cost and the
risk of incorrect connection.
British Patent No. 1,427,133 to Clements et al
discloses electrical apparatus for monitoring the operational
parameters and controlling the operational functions of a
motor vehicle. The disclosed apparatus comprises electrical
devices spaced from one another in the vehicle, signalling and
power supply lines, and devices coupled to both lines and
arranged to respond to a respective one of a group of
signals. The information is conveyed along the signalling
line and is coded using pulse width and pulse amplitude
modulation techniques. The apparatus employs a synchronizing
pulse at the beginning of a pulse train and sensors and
operative units respond to the various pulses in sequence.
A ~eri~ying circuit is used to compare the width of
appropriate successive pulses.
U.S. Patent 3,846,639 to Ueda et al discloses a
control system for a vehicle in which a transmitter responds
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to clock pulses to generate a pulse train inclucling an
index pulse and pulse-width-modula,ed pulses arranged in
a predetermined order resulting from respective signal
pulses, one for each device to be cont:rolled or monltored.
The pulse train is transmitted by a single line to a plur-
ality of cletectors. Width discrimination of the received
pulses is utilized to determine whether the associated
electrical device or monitor should be activated.
U.S. Patent 3,651,454 to Venema et al discloses a
multiplex system for communicating control and power between
components and for monitoring certain conditions of other
~- components in a motor vehicle. A cable travelling about
the vehiele has separate power and signal conductors. A
clock signal source is coupled to the signal conductor.
A plurality of transmitters, which have delay means respon-
sive only to the clock signal for transmitting in definite
time channels determined by their delay and a plurality of
receivers which have delay means responsive only to the
cloek signal for receiving in only one of the definit~
channels, are coupled to the cable so that transmitters and
receivers may control and activate different vehicle
eomponents provicded for reeeiving the associated signal
from the corresponding unit. Figure 7 of this patent
diseloses a method and device for connecting the receiving
or transmitting unit of the system to the cable. This
apparatus is used for tapping into the single cable in
parallel to other units by use of a piercing plug.
U.S. Patent 3,864,578 to Lackey teaches a multiplexing-
system for controlling operation of vehicle components in
response to the operation of corresponding controls by the
operator of the vehicle. The system includes encocling
means, decoding means and relay means. The encoding means
provide a timing signal and code signal having signal
components corresponding to the positions of each oF the
vehicle's controls. The decoder means are remote from
the encoder means and are responsive to the signals
selectively to provide a plurality of outputs to the relay
means in response to the respective code signal components.
Other U.S. patents of general interest are 3,964,302
to Gordon et al, 3,544,803 to Taylor, 3,742,447 to
Sognefest et al and 3,842,249 to Geyer et al.
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The invention accordingly seeks to provide a peripher~
al station for use in a communication system which overcomes
or reduces the disadvantages of the prior art proposals.
According to the invention there is provided for use
i.n a communication system having a signal bus, a master
station, and a plurality of peripheral stations controlled
by signals transmitted on the signal bus by the master
station in a time division multiplex manner, the signal
being transmitted cyclically in information frames with
. the information frame for each peripheral station occupying
a given position in the cycle, an improved peripheral
station comprising: address decoding means for identifying ~ :
an information frame for the peripheral station and for
generating an enable signal in response thereto, the
decoding means including means for setting an address and
a counter for counting information frames, the address
setting means and the counter being used in identification
of the information frame; gating means for coupling signals ::
from the signal bus to one or more outputs of the peripheral
station in response to the enable signal; verifying means
interposed between the gating means and the one or more
outputs, the verifying means being arranged to store each
gated signal, compare it with the correspondiny gating
signal resul-ting from the information frame received by
-the peripheral station during the next cycle of transmitted
signals, and allo~ing the one or more outputs to change
when the compared signals agree; and sync detector means
for detecting synchronizing (sync) signals on the signal
bus, for comparing the occurrence of the sync signals with
the count held in the counter, and for disabling the
verifying means on the de-tection of a lack of synchronism
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between the si.gnals on the slgnal bus and the address
decoding means.
An embodiment of -the present invention will now be
described, by way of example, with refe:rence to the
accompanying drawings, ln which:
Figure 1 is a block diagram of an information
handling system for use in a motor vehicle;
Figure 2 is a detailed circuit diagram of one of
the peripheral stations of Figure l;
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Figure 3 shows a typical pulse train used in the
apparatus of Figures 1 and 2;
Figure 4 is a perspective view of a peripheral
station in position on a bus member of the system;
Figure S is a plan view, partly in section, of
the bus and peripheral station of Figure 4 with a top
cover of the peripheral station removed;
Figures 6 to 8 and 10 are more detailed circuit
diagrams of parts of the circuit of Figure 2; and
Figure 9 illustrates waveforms in the circuit of
Figure 8.
With reference to Figure 1, the system has a
power bus 10 in circuit with a storage battery 12. The
power bus 10 is formed by a single conauctor, the return
circuit being provided via vehicle ground. A signal bus
14 is associated with the power bus 10, and also comprises
a single conductor. The buses 10 and 14 are molded into
a single insulating sheath 16 ~Figure 4) to form a unitary
bus member which may readily be passed around a vehicle
in a convenient route.
A master station 18 is connected to the buses 10
and 14, and to a vehicle control panel 20. Sixteen
peripheral stations 22 are each connected to the buses 10
and 14. Each peripheral unit is connected by external
leads to up to four controlled devices and up to four
sensors; k~ way of example, one of the stations 22 in
Figure 1 is shown connected to a heàdlight HL, a direction
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indicator light DL, a temperature sensor TS and an oil
pressure sensor PS. The connections of the other
peripheral stations Z2 are not shown, for clari-ty of the
drawing.
The control panel 20 contains the usual control
switches, warning lights, and instruments for use by the
driver. The master station 18 scans the driver-actuated
controls in a sequential manner and transmits a sixteen-
frame signal which is acted upon by the peripheral stations
to activate or de-activate the devices and sensors. At
the same time, the outputs of sensors for functions such
( as oil pressure, coolant temperature, road speed etc. are
coupled to the corresponding peripheral stations 22 and
are then repetitively called up by the master station 18,
decoded, and displayed as appropriate on warning lights
and instruments on the control panel 20.
Each of the sixteen peripheral stations 20 is
responsive to a particular one of the sixteen frames of
the complete scan signal transmitted by the master station
18. Eight clock pulses occur during each hut the first
frame; a four-bit counter in each peripheral station counts
every eighth of these clock pulses until reset by a synchron
izing pulse that occurs at the beginning of the first frame.
When a clock pulse causes the count in the four-bit
coun~er of a given peripheral station to correspond to
a four-bit address code applied to the station, the
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station responds to the information and control provided
by the master station during the particular frame
initiated by such clock pulse. If the peripheral station
addresses are se¢uential, then each new clock pulse
initiating a frame causes another of the peripheral
stations to respond to the information and control of
such frame. After all ~ixteen stations have responded, the
sixteen-frame scan sequence is repeated.
The manner in which information handling is
accomplished in the peripheral stations will now be
discussed with reference to Figures 2 and 3.
( Figure 3 shows the voltage level of a typical
signal on the signal bus 14. The voltage at any instant
is controlled at one of four levels, labelled A, B, C
and D. Level A is suitably tied to the vehicle voltage.
The master station 18 includes a clock circuit which
cyclically generates synchronizing (sync~ and clock pulses.
Sync pulses are set at level D and occur once per complete
scan (in this case 16 frames). Clock pulses are at level
23 C and subdivide each frame into e~ual time slots, in this
embodiment eight in number. Information is conveyed by
controlling the signals within the time slots at
levels ~ and B.
With particular reference to Figure 2, the
circuit of a single peripheral station 22 is shown. It
should be noted that the stations 22 have identical
circuitry~ This simplifies stockholding and installation
and assists in reducing costs. The circuit of Figure 3
has an input at 24 from the signal bus 14.
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The power bus 10 may be connected to powered devices
via parallel bis-table gates 26 controlled by the remainder
of the circuit. The signal input at 24 passes to an
amplitude discriminator 28 which has foux outputs enabled
respectively by signal levels C, D, (C or D) and (B or C).
The receipt of a signal at level (C or D), i.e. a sync or
clock pulse, causes an output pulse to be passed to an
eight-way selector 30 which in turn passes every eighth
of such pulses to a four-bit counter 32. The bits of
the counter 32 are connected in parallel to a decode
circuit 34. The decode circuit 34 has an address set
( externally, as will be described below, over leads 36.
It will thus be seen that the counter 32 is
incremented by every eighth clock pulse. When the count
held by the counter 32 is that set via the leads 36, the
decode circuit generates an output on line 38 for one
frame period. Line 38 is connected in parallel to gates
Gl-G8. These gates are also connected to sequential
out~uts of the eight-way selector 30, each output being
~0 enabled for one time slot period. Thus, when the particular
station 22 receives an information frame corresponding to
the address code set, the gates Gl-G8 are sequentially
enabled each for one time slot.
Received signals of level (B or C~ are passed
by the amplitude discriminator 28 to a pulse width dis-
~riminator 40 whose function is to separate the clock
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pulses, which are of lesser duration, from time slot
information. Signals at level B are passed by output
42 to gates Gl-G4 in parallel and are then used, via
a con~and and verify circuit 44 to be described, to
enable the gates 26~ Ignoring for the moment the command
and verify circuit 44, the operation is thus that the
controlled devices connected to terminals 1,2,3, and 4
are turned on by B-level siynals in time slots 1,2/3,
and 4 respectively and are turned off by A-level signals
in these slots. Similarly, inputs from sensors connected
~- to terminals 5,6,7, and 8 are sequentially gated by gates
G5-G8. Such inputs may be either on/off or analog. The
gated sensor signals pass to a pulse width modulator 46
which generates an output signal onto the signal bus 14
during time slots 5,6,7, and 8. A typical set of output
signals is shown in Figure 3O Time slots 6 and 7 are
occupied by tell-back signals monitoring the condition
of devices controlled by the signals in time slots 2 and 3.
Slot 6 represents an "off" tell-back signal and is wholly
occupied by an A-level siynal. Slot 7 represents an "on"
tell-back signal and is wholly occupied by a B-level signal.
Slots S and 8 are exemplarily shown as carrying analog
coolant temperature and oil pressure signals. These are
pulse width modulated, the fraction of the time slot
determined full scale deflection for that signal. The
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timing of the output of the pulse width modulator 46 is
synchronized with the time slots 5-8 by C-level or clock
pulses switched by the amplitude discriminator over line
The purpose of the command and verify circuit
44 is to provide signal security. This circuit operates
in conjunction with a sync detector 50 corlnected to receive
sync pulses from the amplitude discriminator 28. The
sync detector 50 is also connected to the four-bit counter
32 by a line 52. On receipt of the sync pu]se, the counter
32 should reset to zero, and the counter is so constructed
that on resetting it transmits a pulse over line 52 to
the sync detector 50. If both pulses arrive simultaneously,
the sync detector emits a gating pulse on line 54 to the
command and verify circuit 44.
The command and verify circuit comprises four
channels, each connected between one of the gates Gl-G4
and the respective output terminals 1-4. One such
channel is shown in Figure 6. The signal from an associated
one of the gates Gl-G4 is supplied cver line 55 and is
held in a resettable store 56, which may for instance be a
bistable multivibrator. The stored signal is compared with
the next signal gated to that channel by a comparator
58. If the two values agree, an enable signal passes by
line 60 to a gate 62. The gate 62 is also connected to
receive the gatlng pulse on line 54 r from the sync detector
50, and to receive signals over line 64 from the pulse
width discriminator 40. The first of these is provided
to block execution of commands where there is a failure
of synchronism in the system, and the second to ensure that
a command signal is passed only during a suitable time slo-t.
Thus a command signal will not be passed by the circuit 44
to the controlled device unless (1) the same signal is
received twice in succession and ~2) the address decode
is operating correctly in synchronism with the ~aster
station. The first of these is principally a safeguard
against a signal which is correctly timed but in which a
( positive pulse is dropped, while the second is of particulax
use in dealing with the case where an interference-induced
spike appears on the signal bus and produces lack of
synchronism. If either of these conditions is not met,
the sign~l to the appropriate gate 24 is blocked and the
controlled device continues in its preexisting state~
The sync detector 50 is also connected to the four-
bit counter 32 to reset the latter on receipt of a
( 20 sync pulse. ~If the system is correctly in synchronism,
the counter 32 will also be recycling to zero o~ its own
accord at the same time).
It will be seen that this embodiment is capable
of controlling 64 functions and a monitoring 64 sensors.
Suitably, each information frame occupies 8 ms, giving a
total cycle ~ime of 128 ms. Since two consecutive identical
signals are required to actuate controlled de~ices, the
maximum delay in switching on or off i5 256 ms. Readouts
to the driver are updated every 128 ms. These speeds are
sufficiently fast to be practically instantaneous from the
driver's point of view while not requiring high pulse
repetition rates.
In Figures 4 and 5, one possible physical form of
peripheral station is shown. The circuitry is encapsulated
in a housiny 64 which is formed with a recess dimensioned
to accommodate the sheath 16. A cover 65 is
hinged at 66 to the housing 64 and may be locked shut by
spring steel arms 67~ Connecting blades 68 extend from
( the housing 64 to effect connection with the buses 10 and
14. In use, slots for the blades 68 are performed at
suitable locations on the sheath 16 and the bus member is
positioned in the vehicle. At each station, a housing 64
is arranged in a position to recei~e the bus member with
the connecting blades in contact with the buses 10 and 14.
The housing is then secured to a vehicle body panel (not
shown~ as by self-tapping screws 69 passed through a metal
strap 70 secured to the housing 64 and supporting the arms
67. The strap 70 and screws 6q suitably act as an
electrical ground connectox and heat sink. When the cover
65 is closed, the peripheral station also acts as a
xetainer for the bus member.
The connection to the associated devices and
sensors is via a flexible printed circuit 71. This is
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located by means of pins 72 on the housing 64 passed
through apertures 73 in the flexible printed circuit 71.
Contact strips 74 on the housing 64 are provided for
connection to the conductors of the circuit 71. The housing
64 is also provided with contacts 75 connected -to the
address decode circuit 34. A corresponding number of con-
ductive strips 77 are formed on the circuit 71 and are
interconnected at 79. The address for a given station is
encoded on its circuit 71 by drilling or punching through
selected strips 77 between the position of the respective
contact 75 and the interconnection 79. In the embodiment
( shown~ five strips 77 are provided, enabling sixteen
addresses to be encoded.
Figure 7 illustrates a preferred form of amplitude
discriminator. A resistor chain 76, 78, 80, and 82
is connected across power supply lines 84 and Y6. Supply
line 86 is grounded and is thus at voltage level A. The
resistors 76l 78, 80 and 82 are selected to give voltage
levels B, C and D at the resistor junctions, and these
(20 are fed as inputs to respective comparators 88, 90, and 92.
The input signal on line 24 is fed in parallel to the
comparators 88, 90, and 92. The presence of voltage levels
B, C and D is thus detected and results in an output at the
respective comparator, these outputs being gated by an
exclusive-OR gate ~4 and OR gates 96 and 98 to give the
required outputs of C,Dt (C or D) and ~B or C).
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A preferred form of pulse width discriminator
is shown in Figure 8. The discriminator is required only
to differentiate wide and ~arrow pulses, and the waveforms
for each of these at various points in the circuit are
shown in Figure 9. The (B or C~ input rom the amplitude
discriminator 28 is applied in parallel to a monostable
multivibrator 100 and an in~erter 102. The monostable
multivibrator 100 is arranged to give an output pulse
dura-tion equal to that of the narrow "C~' pulse. The
outputs of these are coupled to a NAND gate 104. Thus
the input pulses to the yate 104 are of the same duration
(~ for a received narrow pulse and no output lS generated at
the output of gate 104, whereas when a wide pulse is ~:
received, the low signal from the inverter 102 is of
shorter duration than the high signal from the monostable
100, and the gate 104 gives an output pulse for the time
difference between the two. The waveforms 140, 141, 14Z
and 143 in Figure 9 appear at the correspondinyly numbered
points in Figure 8
Figure 10 shows a detailed circuit for the pulse
width modulator ~6. The clock pulses from the amplitude
discriminator 28 are applied by line 48 to a NOR gate 106.
The input signal from the appropriate one of gates G5 G8
passes to the base of a MOS gate 108. This input signal
is:an analog representation of the parameter to be trans- .
: mltted,~and acts to vary the resistance to ground of the
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MOS gate 108 and a serially connected resistor 1.10, thus
varying the time constant of an RC circuit constitu-ted by
these and a capacitor 112. The other input of the NOR
gate 106 is connected by a feedback resistor 114 to the
junction point of the resist~r 110 and capacitor 112. This
point is also connected by a resistor 1]6 to the output
o~ the NOR ga,e 106, both being coupled to the input of an
inverting amplifier 118. The action of the circuit is as
follows. On receipt of a "C" pulse on line 48, the output
of the NOR gate goes low and the circuit output from the
inverting amplifier goes high. After a time delay set by
( the RC constant of -the elements 108, 110, 112 (and thus
by the input signal at the base of the MOS gate 108~, the
output of the NOR gate switches to a high state and the
circuit output goes low. Hence the value of the signal
at the modulator input is represented in the signal bus
waveform ~Figure 31 by the ratio of the high-level signal
duration to the total slot time between the two appropriate
clock pulses.
~'; 20 The master station 18 may readily be realized by those
skilled in the art with well known techniques, and
will therèfore not be described in detail. It w.ill be
appreciated that it includes a suitable clock circuit
generating "C" and "D" level pulses repetitively, and
gating means for scanning control switches on a repetitive
basis. Returning signals from remote analog sensors may
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suitably be demodulated to analog voltage signals and
applied to voltmeter-type ins-truments; this is suitable
for parameters such as road speed, engi.ne speed and fuel
contents.
The ~our-level pulse format of the present invention
permi.ts the required amount of information to be carried
without the use of unduly long pulse trains and/or
repetition rates. Moreover, all signal deteckion can be
based on ratios rather than absolute values, and control
of supply voltages is therefore not critical~
It will be seen that the invefftion permits the
use of identical peripheral stations whose addresses can
be set by simple plug-in means, with consequent simplifi.ca-
t.ion of manufacture, stock holding and production control.
The address setting means may take different forms from
the printed circuit descri~ed abo~e. For example, the
peripheral station may be connected to i~s associated
devices via indivîdual leads and a multi-contact plug and
socket, the address being set by interconnections between
conductors in the plug or socket.
. The invention also provides a peripheral station
including a verifying means which. nullifies the effect of
failures in signal transmission, not only -.
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those where signal pulses are lost or distorted but also
those due to interference causlng sp~rlous pulses or
lengthening of the pulse train.
It will be appreciated that modiEications may
be made to -the embodiment described within the scope of
the invention, as defined in the claims. For instance,
the input on the line 64 to the command and verify circuit
44 may be taken directly from a suitable output of the
amplitude discriminator rather than being derived by pulse
width discrimination. The four-bit counter 32 could be
fed directly by a "D" output of -the amplitude discrirninator.
( The inputs from sensors may be omitted, together with the
corresponding gates and the modulator 46, where only a
control function is desired~
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