Note: Descriptions are shown in the official language in which they were submitted.
17 SUMMARY OF INVENTION
18 A. Field of Invention
mis invention relates to signal converters, and
more particularly to digital to analog convertors fabrica-
21 ted in semiconductor technology.
22 B. Description of Prior Art
23 Digital to analog converter~ (DAC) comprise a
24 digital input, a reference source and a transfer network.
Typically, the transfer network may be a weighted resistor;
26 resistor ladder; inverted ladder or weighted voltage network.
27 The text "Electronic Analog/Digital Conversions" by H.
28 Schmidt, published by Van Nostrand Reinhold Company, New
29 York, 1970, Chapter 7, describes the organization and pro-
blems associated with a DAC. Converters, entirely fabrica-
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1 ted in semiconductor technology, are further limited
from a practical or commercial standpoint to a low order
3 or relatively few digital bits, e.g., less than six.
4 Presently, in transfer networks, resistor ratios, for thei 5 most significant bit (MSB) to the least significant bit
, 6 (LSB) are of the order of 1:15, respectively. High resis-
; 7 tor ratios are impractical for matching, tracking and8 total resistance in a transfer circuit for a weighted cur-
9 rent DAC fabricated in large scale integrated semiconductor
technology. The accuracy and linearity of converters are
11 further diminished by the large tolerances associated with
12 resistors fabricated in semiconductor material. Thermal
13 instability also accompanies converters fabricated in semi-
14 conductor technology. Solution of the resistor problem for
a weighted current DAC will permit (1) high order digital
16 signals, e.g., more than six, to be translated into analog
17 signals and (2) the benefits of large scale integrated
18 technology to be achieved in signal converters.
19 A general object of the invention is a signal
converter for translating high order digital signals to cor-
21 responding analog signals with improved linearity and
22 temperature stability.
23 Another object is a digital to analog converter
24 having a transfer circuit with a reduced number and ratio
of adjacent resistGrs.
26 Another object is an integrated weighted current
27 digital to analog converter that is amenable to fabrication
28 in large scale integrated technology.
29 The number and ratio of adjacent resistors in
a transfer circuit for a DAC may be reduced bv a combination
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1 of multiple parallel current sources for low order or
2 more significant bits and binary weighted current sources
3 for high order or least significant bits. The lower re-
i 4 sistor ratio improves the linearity of the DAC by better
matching of the transistors and resistors in their respec-
6 tive current sources.
7 In an illustrative embodiment, a digital input
8 signal A~ is supplied in parallel to a signal conver-
ter having an output current Io = IREF (Al + A2 + - + AN
~ 2N- l
where IREF is a reference current, N is the number of digi-
11 tal signals being translated and AN is eitherzero (~) or (1)
12 depending upon the absence or presence of a digital signal,
13 respectively. The converter comprises a plurality of stages
14 corresponding to the number of digital input signals. Logic
switches in each stage are responsive to a digital signal
16 in a bit position to connect or disconnect current sources
17 to a summing network. Current sources for more significant
18 or low order digital signals comprise a plurality of identi-
19 cal current sources that are multipled together to define
20 a binary weighted value. Each current source is an active --~
21 element, appropriately biased, and a matching resistor ele- -~
22 ment connected together to provide a unit current, the com-
23 bination of unit currents forming a binary weighted value
24 corresponding to the digital signal. Current sources for
less significant or high order digital signals comprise
26 active elements, appropriately biased and matching resistors,
27 connected together to provide a binary weighted current
28 definitive of a discrete high order digital signal. The
29 digital signals are decoded by the logic circuits and binary
weighted currents are provided from the respective current
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l sources to the summing network. The total current appearing
2 at the summing network represents the analog conversion of
3 each binary weighted bit in the digital signal.
4 A feature of the invention is multiple parallel
current sources connected together to define low order bits
6 of a digital signal.
7 Another feature is a combination of multiple para~
8 llel current sources and binary weighted current sources
9 to define low order and high order significant bits, respec-
tively, of a digital signal ~or conversion into a corres-
ll ponding analog signal.
12 Another feature is a DAC with improved linearity
13 by a transfer circuit that has matched transistors and re- ` `
14 sistors to compensate for voltage differences between adja-
cent transistors.
16 Another feature is a weighted current DAC fabrica-
17 ted in semiconductor technology and having a reduced number
18 and ratio of adjacent resistors in a transfer circuit by the ;,
l9 use of current sources in g~nerating binary weighted currents
correspondi~g to digital signals.
21 BRI~F DESCRIPTI`ON OF THE DRA~INGS
22 m ese and other objects, features and advantages
23 of the inYention will be more fully apprehended from the
24 following detailed specification taken in conjunction with
the appended drawing in which:
26 Figure l is a block diagram of a digital to
27 analog converter responsive to a digital signal, in parallel
28 form, to provide an analog output signal representative of
29 the digital input.
Figure 2 is an electrical schematic of a digital ~'~
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1 to analog converter that practices the principles of the
2 present invention.
3 Figure 3 is a graph of output voltage versus
4 digital input signals for the digital to analog converter of
Figure 2.
6 ~igure 4 is an electrical schematic of another
7 transfer network for the digital to analog converter of
8 Figure 2.
9 Figure 5A is a plan view of a semiconductor incor-
porating the digital to analog converter of Figure 2.
11 Figure 5B is a cross sectional view of Figure 5A
12 along the line B-B'.
13 Figure 5C is a cross sectional view of Figure 5A
14 along the line C-C'.
DEq!AIIEll DESCRIPTION OF PREFE~RRED EMBODIMENT
16 In Figure 1, a plurality of digital signals l.. N
17 are provided as a parallel input to a signal converter 10.
18 The digital signals are defined by the presence of a signal
19 designated as a 0 or plus (+) voltage or the absence of a
signal designated by a 1 or minu~ (-) voltage. This is
called inverted logic. For the purpose of the present
22 description, a four bit digital input signal will be assumed
23 as the input to a four stage converter. It should be under-
24 stood, however, the in~ention is not limited b~ the nu~ber
of digital signals or stages. In fact, the invention is
26 adapted to handle high order digital signals, i.e., more
27 than six bits.
28 The digital signal appearing on line 1 is desig-
29 nated as the most significant bit (MSB) and the digital sig-
nal appearing on line 4 is designated as the least signifi-
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1 cant bit (LSB). The converter 10 accepts the sequence of
2 pulses or bit pattern to control a source (P.S.) to provide
3 an output signal at a terminal 12 which is the analog or
4 sum of the digital pattern on the lines 1 through 4.
Figure 2 shows a four ~4) stage converter 10,
6 in one form, comprising a transfer network 14 and a logic
7 networ~ 6 The lines 1-4 are connected as input to the
8 logic network 6 which controls the transfer network 14.
9 A plurality of current sources comprise the transfer net-
workr one or more current sources being associated with
11 each input line. The current sources for the high order
12 bits (lines 3,4) are binary weighted resistor sources. The
13 current sources for the low order bits (lines 1,2) are
14 multiple parallel current sources of the same binary weight.
The logic section 6 comprises a current switch
16 for each input line. When a digital signal i5 present on
17 a line, current flows through one side of the switch to the
18 transfer network 14. When a signal is not present on the
19 line, current flows through a summing line 16 and the other
side of the switch to the current source. The total current
21 flowing in a transfer network 14 appears on the line 16 and
22 at the output terminal 12.
23 The current source at each stage comprises a
24 high impedance element, typically a transistor 11, 21, 23,
,,, , . ~
23 , 24,... 24 including a reversed biased junction and
26 a resistor of appropriate magnitude. A reference current
27 IREF is generated for the transfer network by a transistor
28 26 and a resistor Rl. A transistor 28 is connected to an
29 appropriate supply voltage to forward bias the transistor
",
26. The transistors 11.... 24 are forward biased by line
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1 35 connecting the respective base electrodes to the bias
2 device 28.
3 The current sources for the least significant
4 bit include resistors which have a ratio of 2:1 for ad-
S jacent stages. Tlle resistor for the lowest order least
6 significant bit has a magnitude of Rl. The resistor.for
? the adjacent or next higher order least significant,digit ~ `
8 has a magnitude of ,Rl, Rl...R1 where M is the number
2 2 2M-l
9 of stages.
The current supply for the more significant bits ~'
11 is obtained by multipling identical current sources. The
12 current source for line 2, which has a blnary weighted value
13 twice ,that of line 3, comprises current sources 23, 23' and
14 their associated resistors Rl. Similarly, the current
source for line 1, which has a binary value quadruple that
16 of line 3, comprises four current sources 24, 24', 24'',
17 and 24''' and their respective resistors Rl. The transfer
18 network 14, therefore, provides binary weighted currents
19 corresponding to digital values 21, 22r 23 and 24 for input
lines 4, 3, 2 and 1, respectivel~.
21 The voltage drop across the emitter base junct~.on ,~
22 of the transistor 26 and,the associated resistor Rl forward '
23 biases the transistors 11, 21, 23, 23 , 24, 24 , 24 and
",
24 24 in a normally conducting condition at the current value
corresponding to the IREF input to the transi5tor 26. `'
26 In one form, the logic circuit associated with ~ ,
27 each stage and/or input line is a current switch. In stage -
28 4, a transistor 13 and a transistor 15 are coupled together
29 at one end to the current source 11. A second end of the
current switch is connected to the input line into a supply
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1 voltage of appropriate polarity and magnitude. A third
2 end of the current switch is connected to the summing l~ne
3 16. Normally, the signal level on the line 4 places the
4 tranqistor 13 in a conducting condition and the transistor
15 in a non-conducting condition. This state of the
6 current switch represents a binary zero condition. An
7 appropriate signal on the line 13 places the transistor
8 13 in a non-conducting condition and the transistor 15 in
9 a conducting condition. This condition of the current
switch is a binary 1 condition. A voltage supply V+ is
11 connected to an appropriate resistor 18 and the line 16 to
12 function as a current supply for the current source 11. A ~-
13 transistor 33 also connected to the resistor 18 provides ~'
14 base current to a line 20 to place the transistor 15 in a
conducting condition when the transistor 13 is non-conduc-
16 ting. m e transistor 33 is appropriately biased by VTH which
17 sets the required input line signal levels.
18 The current switches comprising transistors 17
19 and 19 for line 3, transistors 25 and 27 for line 2 and tran-
sistors 29 and 31 for line 4 operate in a manner identical
21 to that described for the current switch for line 4. The
22 sum of the currents fl~wing through the transistors 15, 19,
23 27 and 31 appears on line 16 and is the analog of the digi-
24 tal input signal appearing on the lines 1, 2, 3 and 4. The
current sum also appears at the terminal 12 or may be trans-
26 lated to a voltage VO by taking an output across a resistor
27 O
28 In the transfer network 14, current flow through
29 the binary weighted resistors associated with lines 3 and 4 -
will be in a 2 to 1 ratio, respectively, only if the same
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1 potential exists across adjacent resistors. It can be
shown that two physically identical transistors operat-
ing at different emitter currents having a fixed ratio
of 2 to 1 will exhibit a finite difference in their
respective base to emitter voltages. The difference (S)
can be shown to be as follows:
S = KT ln 2 ~1)
S = 18 millivolts
where K = Boltzman constant
T = junction temperature in degrees Relvin
q = charge of an electron
The voltage difference S or 18 millivolts between
adjacent stages can be offset by increasing the magnitude
of the larger binary weighted resistor in an adjacent
pair. It can be shown that the following relation de-
fines each binary weighted resistor in the network 14
whereby the voltage across the resistors is the same and
the currents are in a correct binary relation:
n 2 [Rl + (n-l) s ] (2)
where -
n is an integer corresponding to the binary digit
represented by the resistor
Rl is a resistor magnitude selected for the most
significant bit of the work
Il is the current flow through the resistor Rl
Based upon formula 2 and selecting Rl to have a mag-
nitude of 1000 ohms, the resistance of two parallel re-
sistors Rl in Figure 2 can be shown to have a magnitude of
2036 ohms for a current Il of 1 milliamp. The resistors
for additional current sources in the network 14 can be
calculated in a similar manner. Compensating for the volt-
age differences between adjacent binary weighted stages
increases the linearity of the DAC.
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Figure 3 shows the output currents in units
2 appearing at the terminal 12 in Figure 1 or Figure 2 for
3 the respective pulse patterns appearing on the lines 1,
4 2, 3 and 4. A sequence of all binary zeros " (O 1 9) " gener- -
ates no output current in the sum line. A pulse pattern
6 where the least significant bit is a binary "(1)" and all
7 other inputs are a binary "(0)" generates an output current
8 of one unit by reason of the current flow through transistor
9 15 to the current source 11 and the current flow to the base ;~
electrodes of the transistor 15. A pulse pattern where the
11 most significant digit is a binary "(1)" and all other signals
12 are a binary "(0)" generates an output of eight units by `
13 reason of the current flow through transistor 31 to the current
14 sources 24, 24 , 24 , 24 and the current flow to the base
electrodes of the transistor 31. A pulse pattern where all
16 signals are a binary (1) generates an output of fifteen units
17 based upon the sum of 8, 4, 2 and 1 unit of current flowing
18 in the respective current sources. In like manner, it can be ,~
19 shown that the current units in Figure 3 for the respective
pulse pattern can be obtained by the DAC of Figure 2 as the
21 various pulse patterns are presented on the lines 1-4.
22 In Figure 4, a transfer network 14 has the current
23 sources reordered relative to Figure 2 to correct for thermal
~, .
24 gradients across a semiconductor device incorporating the net-
work. It can be shown that the thexmal gradient across a
26 semiconductor substrate can be normalized by e~ually dividing -~
27 the current in high order stages about the current sources
28 of the next lower stage. Thus, in Figure 4, current sources
,, - - - - :.
29 40, 40 , 40 and 40 for the most significant bit are
equally disposed on opposite sides of the current sources 42 and
31 42 for the next least bit. Similarly, the current sources -
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42 and 42 are equally disposed on opposite sides of the
- 2 current source 44 for the second most significant bit.
3 Balancing the current flows for the high valued current sources
4 in the manner described overcomes the problems of thermal
gradient and improves thermal stability of the DAC.
6 The DAC is amenable to manufacture in large scale
7 integrated technology by (1) the reduction of the resistor ratio
8 from the most significant bit to the least significant bit, (2)
9 the reduction in the number of resistors by the use of current
sources in the transfer network in lieu of a resistor
11 ladder network, (3) the improvement in DAC linearity by the
12 lower resistor tolerance associated with the reduced resistor
13 magnitude and (4) the improved thermal stability of the DAC -
14 by the location and order of the current sources in the trans-
fer network. Also, the ratio of adjacent resistors ma~ be
16 adjusted to overcome the VBE differences in adjacent transistors.
17 The elimination of VBE differences achieves better matching
18 of transistor operating points with resultant improved linearity
19 for the DAC. The linearity can be further improved by compressing
20 the emitter currents of the transistors to operate in their
21 respective linear ranges. In Figures 5A, 5B and 5C, a P-
22 substrate 50 of 15 ohms centimeter is suitably prepared to
23 receive an n epitaxial layer 52 of 1. 5 ohms centimeter. P+
24 isolation regions are formed about the respective current
25 switch elements and current sources elements associated with
26 each digital input line. A junction 58 between the substrate
27 50 and the layer 52 completes the isolation of the respective
28 current switch and current source elements from one another`~
29 A subcollector 60, as shown in Figure 5C, is included in the
30 isolation pocket 62 associated with respective curxent switch
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1 or current source element. The subcollector reduces the
collector resistance and improves switching performance, as is ~`
3 well known in the semiconductor art. A base diffusion 64 of
4 p type conductivity is formed in the respective isolation
pockets. An emitter region 66 and collector contact region
6 68, of N+ type conductivity, as shown in Figure 5C, are formed
7 in the isolation pocket 62 to complete the active element.
8 An insulating layer 70 formed on the surface of the epitaxial
9 layer serves as a passivating surface for the respective
active element. The layer 70 supports metallization which
11 interconnects the current source and current switch element
12 as well as providing the connection to the power supply and
13 input/output terminals.
14 In Figure 5A, digital input line 3 is shown connected
to the respective current switch elements. A single isolation
16 pocket 56 is employed for each current switch where the collector~ ~ `
17 terminals of the switching transistors 17, 19 and the like,
18 are operated at different potentials. The current summing line ~ ;
19 16 is connected to the respective transistors of each current
switch. An appropriate connection is made from each current
21 switch to the voltage supply V . The common base line 20 is
22 extended to the respective current switch elements and a con-
23 nection 72 is completed from the current switch element to the
24 associated current source. -
Each current source element is fabricated in a manner
26 similar to that described for the current s~-itch element. The
27 common base line 35 interconnects the base loads of the various
28 current sources. A connection 74 is formed from each current
29 source to the associated resistor element Rl. P type diffused
regions 76~ shown in Figure 5B, are formed as resistors in the
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- 1 layer 5? at the time the base elements 64 are formed. A
2 common connection 37 is made to each resistor to permit
3 connection to a current sink (not shown) to complete the
4 electrical circuit for the DAC.
5 While the DAC has been shown fabxicated with NPN ~ ~:
6 transistor elements, it should be understood that PNP type
7 devices may be substituted, provided the appropriate changes
8 are made in source/sink polarity. Also, the logic circuit ~ ;
9 16 may utilize transistor-transistor logic (TTL), direct
10 coupled transistor logic (DCTL) and other well known logic - *
, .
11 circuits as a substitute for the current switch logic, ~ ,
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12 shown and described in Figure 2. ~`
13 While the invention has been particularly shown : ;
14 to describe with reference to preferred embodiments thereof, ;
it will be understood by those skilled in the art that the
16 foregoing and other changes in form and detail may be made . .
17 therein without departing from the spirit and the scope of
18 the invention.
l9 What is alaimed is:
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