Note: Descriptions are shown in the official language in which they were submitted.
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This invention relates to a circuit for rejecting pulses
of less than a preselected time duration and more particularly to one
which may also provide output pulses of a fixed time duration for those
input pulses which are not rejected.
Background of the Invention
In telephone communications involving d-c pulse signalling,
it is known to provide pulse rejection circuitry which prevents unwanted
spikes or disturbances on the line from erroneously being accepted as
dial pulses. An example of such a circuit is shown in applicants'
United States Patent No. 3,822,385 entitled "Pulse Rejection Circuit"
issued July 2, 1974 and invented by Inanc Kayalioglu.
In addition, pulse duration correction circuits which
are responsive to incoming dial pulses, are also utilized to provide
output pulses of a standardized or fixed time duration. Such a circuit
is shown in United States Patent No. 4,071,781 entitled "Pulse Duration
Correction Circuit" issued January 31, 1978, also invented by Inanc Kayalioglu.
In some applications it may be advantageous to exercise
independent control over the delay intervals and the threshold levels
for both the positive and negative going portions of these pulse signals,
20 particularly when the make-break interval of the pulses is asymmetrical
as is normally the case with dial pulses.
Statement of the Invention
It has been found that these advantages may be obtained
in an improved pulse rejection circuit which is realized by utilizing
two switching amplifiers each of which is coupled to the input of the
circuit by separate coupling networks which provide independent
integrated outputs for signals of opposite polarity. The summed output
of the two amplifiers is coupled to a third switching amplifier which
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has a switching hysteresis so that its output is only switched whenever
the two outputs of the other amplifiers have the same polarity.
By utilizing operational amplifiers each having a pair
of inputs which are inverted with respect to each other, for the switching
amplifiers, and coupling an integrated input signal to each of the
second inputs, the circuit also provides pulse duration correction so
that only input signals of greater than a preselected time duration produce
an output signal which itself is of a constant time duration regardless
of the duration of the input signal.
Brief Description of the Drawings
; Example embodiments of the invention will now be
described with reference to the accompanying drawings in which:
Figure 1 is a schematic circuit diagram of a pulse
rejection circuit;
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Figure 2 is a variation of the embodiment illustrated in
Figure 1 which additionally provides pulse duration correction;
Figure 3 illustrates typical voltage waveforms at various
points of the pulse rejection circuit illustrated in Figure l; and
; Figures 4, 5 and 6 additionally illustrate typical voltage
waveforms at various points of the circuit illustrated in Figure 2, for
incoming signals which are symmetrical pulses, short negative pulses,
and short positive pulses respectively.
Description of the Preferred Embodiment
In both the preferred embodiments, corresponding
components will have the same reference characters where their function
is the same even though the circuit configuration is slightly altered.
In addition, the location of the various waveforms in Figures l and 2
will be identified by corresponding reference characters in Figures 3 to 6.
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The description of the preferred embodiments will now be described inconjunction with the operation.
Referring to the pulse rejection circuit of Figure 1
and the waveform of Figure 3, pulse signals A of varying length are
connected from the input through the coupling networks Nl and N2 to the
respective non-inverting inputs of the operational amplifiers Al and A2.
The network Nl which includes resistor Rl, capacitor Cl, and diode Dl,
provides direct coupling through the diode Dl for positive-going signals
but an integrated output for negative-going signals as shown in B.
Similarly, the network N2 provides direct coupling through the diode D2
for negative-going signals and an integrated output developed across
capacitor C2 in conjunction with resistor R2 for positive-going signals
as shown at C. With the inverting inputs of the amplifiers Al and A2
tied to a common reference point or ground, the square-wave outputs
D and E are positive whenever their respective inputs B and C are also
positive. The outputs D and E are coupled through a summing network N3
including resistors R3 and R4, to the non-inverting input of a third
operational amplifier A3 whose inverting input is also tied to ground.
Positive feedback around amplifier A3 is controlled by
resistor R5 in conjunction with resistors R3 and R4 so as to provide
a switching hysteresis whereby the output G is switched only when the
outputs D and E have both switched and are of the same polarity as shown
in F. Thus, each of the amplifiers Al, A2 and A3 functions as a switching
; amplifier so as to effectively reject pulses of less than a preselected
pulse duration, while passinq all pulses of a longer duration.
Each of the operational amplifiers Al, A2 and A3, is
assumed to have a very high input impedance and low output impedance
relative to the other components in the circuit. As can be seen from
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waveforms B and D, the output of the amplifier Al will go positiYe
immediately for a positive-going input but will go negative only after
a time delay determined by the time constant Tl = Rl.Cl, for negative-
going signals. Similarly, referring to waveforms C and E, the output
will go negative immediately for negative-going input signals but will
go positive only after a time delay determined by the time constant
T2 R2. C2 .
The resistors R3, R4 and R5, form a summing network N3
at the input to the amplifier A3. This network N3 pre-biases the input
of the amplifier A3 depending upon the existing state of its output.
This pre-bias is such that the olitputs from amplifiers Al and A2 must
both change state in the same direction before the pre-bias on amplifier
A3 is exceeded and its output changes state. Because of this action,
the output of the pulse rejection circuit will not change state until
both signals D and E have changed polarity.
- Referring to the embodiment illustrated in Figure 2 and
the waveforms of Figures 4, 5 and 6, an additional integrating network
N4 including resistors R7, R8 and capacitor C3, is coupled from the
input to the second inputs of the operational amplifiers Al and A2.
This circuit in conjunction with the balance of the circuit provides
both pulse rejection and pulse duration correction at the output. In
this optional embodiment, the inverting and non-inverting inputs of
the amplifiers Al, A2 and A3, have been reversed relative to those
shown in Figure 1. This results in upwardly going negative signals
for waveforms D, E and F, the balance of the waveforms A, B, C, G and
H being upwardly going positive signals. However, the basic operation
with respect to pulse rejection remains the same. Since the resistor
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R5 is no longer connected to resistors R3 and R4, an additional
resistor R6 is required to provide the pre-biasing of the amplifier A3.
Figure 4 illustrates a typical case when a symmetrical
pulse signal A is coupled to the input of the circuit. It can be seen
that a symmetrical pulse train is passed undistorted because the
reference voltage H which controls the switching of the amplifiers
Al and A2, remains approximately at ground potential. However, as
illustrated in Figures 5 and 6, an unsymmetrical pulse train will
change the reference signal H in the direction of the longer pulse
segment and consequently produce a longer output pulse of the opposite
polarity. Thus, the input pulse train A is corrected to an output
pulse train of a substantially constant pulse duration. While not
specifically illustrated, further flexibility of the circuit can
be achieved by coupling different threshold voltages to the second
inputs of the amplifiers Al and A2 (i.e. the inverting inputs of
Figure 1 and the non-inverting inputs of Figure 2). Also, a
capacitor may be connected in shunt with resistor R6 to alter the
tlmlng.
In a typical pulse dialling situation, the standard
time interval between pulses is lOOms: comprising 60ms break and
40ms make. This can be readily achieved by altering tne ratio of
the time constants 1l and 12 By doing this, any dial pulse between
about 15 and 80ms break can be readily corrected to one having a
60ms break while ones outside this range are rejected.
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