Note: Descriptions are shown in the official language in which they were submitted.
11~15391~
9D-HL-13374-Slmcoe
Various aspects of the controller embodiment disclosed herein
are the subject matter of a commonly-asslgned Canadian application
Serial No. 3 ~ 0~ , filed -f~/~c~o /~7~ , by Robert
J. Simcoe and Ro6ert C Helfrich, entitled "TIME TO GO AND DIAGNOSTIC
DISPLAY FO~ ELECTRONIC SEQUENCE TYPE APPLIANCE CONTROLLER."
8ACKGROUND OF THE INVENTION
The present invention relates generally to an electronic
seguence type controller and, more particularly, to a sequence type
contro11er suitable for operating var~ous types of sequentially operated
apparatus, including household appliances such as clothes washing machines
or the like, and which has substantial programming flexibility.
In recent years, a number of electronic control circuits for
appliances~ particularly dishwashers and clothes washing machines, have `
- 15 ~een proposed. Such controllers are intended to replace the electro-
mechanical timertsequencers which heretofore have been employed in this
class of household appliances.
Such electronic controllers typically include a sequencer
element in the form of a digital counter, with each counter state repre-
senting a program step. In order to advance the sequencer counter through
its respective counting states, periodic clock pulses are applied to the
counter. For driving various external load devices in the appliance, for
example water valve solenoids, digital decoding logic is typically con-
nected to the sequencer counter to sense the particular state thereof and
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9D-HL-13374-Simcoe
to operate the external load devices when appropriate. Additionally, slnce
different time durations are generally desired for different steps in
operation cycle, a number of prior art controllers have included various
means for altering the time durations of part~cular steps. Lastly,
various controllers have included means for altering the sequence of pro-
gram steps depending on external inputs.
SUMMARY OF THE INVENTION
It ts a general object of the invention to provide a versatile
sequence type controller generally of the class described aboYe.
It is a more specific object of the invention to provide a
general purpose electronic sequence type controller structure which
may be adapted to control a wlde variety of appliances and other appara-
tus operating in a sequential fashion through the provision of a flexible
memory structure whtch allows the basic controller to perform a wide
variety of funct~ons wlth relatively simple and straightforward pro-
gramming.
It is another ob~ect of the invention to provide an electronic
sequence type controller hav~ng a high degree of flexibility in program-
ming the time durations of particular steps in the program.
It is sttll another object of the invention to provide such
an electron~c controller which may be generally programmed to direct the
operation of a particular apparatus such as a clothes washing machine,
but whtch readily accepts user option inputs to vary, for a part~cular
operattng cycle, both the durations of particular steps in the cycle
ti3 ~0
9D-HL-l3374-Simcoe
sequence and the sequence itself.
Briefly stated and in accordance with one aspect of the inven-
tion, these and other objects are accomplished by an electronic sequence
type controller which includes a digital program sequence counter capable
of stepping from one state to the next in response to inputted clock
pulses, each state of the sequence counter representing a particular
program step. Additionally, there is a programmable digital counter
which functfons to esta~lish any one of a plurality of different time
durat~ons. The programma~le timer is generally operable to count inputted
clock pulses and to output a signal when the number of clock pulses cor-
responding to a programmed time duration have been inputted. A timer
setting control is operable to program the programmable timer. A program
memory is responsive to the state of the program sequence counter for
directing the timer setting control to program a time duration desired
for any particular program step into the programmable timer. Finally,
a control logic means for directing the operation of the program sequence
counter and the programmable timer to effect periodic program advancing
operations is provlded. Preferably, the controller includes a basic
clock for producing periodic timing pulses in response to which program
advancing operat~ons occur.
In the event a signal has not been received from the pro-
grammable timer and a program step is therefore in progress, the control
logic means is operable to d~rect a clock pulse to the programmable timer
for each program advancing operation. Where a program step is completed,
~ ~lS3~()
9D-HL-13374-Simcoe
a signal is received from the programmable timer. The control logic
means is then operable to direct a clock pulse to the program sequence
counter to cause steppfng to the next program step, whereupon the program
memory directs the timer setting control to program a new time duration
S into the programmable timer.
To provide a useful output, the program memory has at least
one output connection to activate an external load device during a par-
ticular program step. Additionally, the output connection may include
additional logic means responsive to an external user input for further
control of the output function. For example, the electronic controller
may be adapted to control a washing appliance in which an external load
device controls the temperature of incoming washing fluid and wherein
the external user input may further condition the temperature of the
incoming washing fluid.
In accordance with the flexible programming aspects of the
invention, the timer setting control preferably is capable of selectively
programmlng tne programmable timer either for a time duration determined
by the programming memory means, or for a time duration determined by
an external input. Such a decision depends upon the particular step in
the program, and the timer setting control accordingly responds to an
output of the program memory means for selecting whether the program
time duration is determined by the program memory means directly or by
the external input.
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9D-HL-13374-Simcoe
Additionally, the program sequence counter includes the
capability for selectively either stepping to the next state of a
regular counting sequence, or jumping to a particular arbitrary state
determined ~y the program memory means, again depending upon the parti-
cular program step. For additional flexibility, whether a program jump
from a particular program step to another particular program step occurs
may 6e determfned by an external input.
It is contemplated by the present invention that the entire
controller be constructed using large-scale ~ntegration (LSI) techniques
on a single monolith1c chip. A portion of the controller represents
logic circuitry which is unchanged from particular appl~cation to par-
ticular application. Those portions of the controller which may be
broadly categorized as memory and which vary depending upon the particu-
lar apparatus which is to be controlled and depending further upon the
particular programming desired, are preferably formed as two-dimensional
memory arrays which may readily be programmed with specific instructions
by a suitable masking during manufacture of the chfp as is known in the
art of integrated circuit manufacture.
The specific em60diment which is described ~n detail below
will be understood to be one example only of the various aspects of the
invention. The particular controlled apparatus described is a domestic
clothes washing machine, and particular exemplary programming suitable
therefor is shown. However, ~t is intended that the scope of the 1n-
vention be limited only by the claims appended hereto.
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9D-HL-13374-Simcoe
BRIEF DESCRIPTION OF THE DRAWINGS
While the novel features of the invention are set forth
with particularity in the appended claims, the invention, both as to
organization and content, will be better understood and appreciated,
along with other objects and features thereof, from the following
detailed descrlption taken in conjunction with the drawings, in which:
FIG. 1 is a perspective view of a portion of a clothes
washing machine, illustrating various user-operable controls on the
front control panel thereof;
FIG. 2 is a view in elevation of a portion of the rear control
panel, illustrating a switch for use by service personnel;
FIG. 3 is an electrical circuit diagram of the interface
between various mechanical elements of the clothes washing machine
and the electronic controller described herein;
lS FIG. 4 ls an overall block diagram of the electronic con- troller embodying the present invention;
FIG 5 is a program sequence chart outlining functional steps
through which the electronic controller of FIG. 4, and particularly the
program sequencer portion thereof, directs the clothes washing machine;
FIG. 6 depicts how FIGS 6A and 6B are joined,
FIGS. 6A and 6B together comprise a detailed schematic diagram
of the program sequencer portion of the electronic controller of FIG. 4, :
and associated control logic and program memory matrices;
. . ', "- .. ' -' .. -. . ~ ~. '
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9D-HL-13374-Simcoe
FIG. 7 is a partial schematic diagram illustrating in greater
detail the structure of the memory matrices associated with the program
sequencer of FIGS. 6A and 6B;
FIG 8 is a detailed schematic diagram of the programmable
timer portion of the electronic controller of FIG. 4, and associated
memory matrices;
FIG. 9 ls a chart, similar to that of FIG. 5, showing the
steps through wh kh the programmable timer of FIG. 8 cycles;
FIG. l~depicts how FIGS. lOA and lOB are joined; and
FIGS. lOA and lOB together comprise a detailed schematic
diagram of master control 109ic whlch directs the operation of the various
elements of the electronlc controller of FIG. 4; and
FIG. 11 is a block diagram of an alternative controller suit-
able for general k ed appl~cations.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
Referring first to FIGS. 1 and 2, a clothes washing machine
20 includes a front control panel 22 access1ble by a user of the machine,
~, and a rear control panel 24 intended for access by a service technician.
From the various switches and displays on the control panel 22, together
wlth the indicia associated therewith, the options available to the user
in programming a particular washing cycle may be determined. Before
considering the circuit details of the electronic controller itself,
the various functions it performs, from the viewpoint of the user, will
be described.
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9D-HL-13374-Simcoe
Specifically, a main power ON push switch 26 is provided to
turn the entire machine 20 on. The particular power ON switch 26 employed
is a mechanically latching, electrically delatching switch. To turn the
machine 20 off at any time, there is an OFF pushbutton switch 27 electri-
cally connected to delatch the ON switch 26. A START/STOP pushbutton
swftch 28 is provided to begin the programmed washing cycle after varlous
cycle options have been selected. In the particular embodiment herein
described, a second operation of the START/STOP switch 28 stops and resets
the machine 20, if desired. Additionally, the START/STOP pushbutton switch
28 functions during a "diagnostic" mode, which may be selected by the
technician, to step the machine through its programmed steps one at a
time for servicing purposes. The "diagnostic" mode is enabled when a
SERVICE switch 30 located on the rear panel 24 (FIG. 2) is thrown from
the NORMAL to the DIAGNOSTIC position.
Before pressing the STARTtSTOP switch 28, the user selects the
cycle optlons by means of the various switches located generally within
the six control clusters immediately to the right of the ON/OFF and START/
STOP sw~tches 26 and 28. The user cycle option selection determines in
part the particular program set up within the electronic controller. Opera-
t~on of a SOAK switch 32 selects whether a preliminary soaking (SOAK)
subcycle is to be performed at the beginning of the washing cycle. If
the preliminary soaking sybcycle is selected, operation of a SOAK time
switch 34 selects the time duration thereof. As indicated, either ten,
twenty, forty, or sixty minutes may be selected. Similarly, operation of
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9D-HL-13374-Simcoe
a WASH switch 36 selects whether a wash subcycle is to occur, and user
operation of a WASH TIME switch 38 selects the wash time duration in
m;nutes. An EXTRA RINSE switch 40 is provided to enable selection of
whethe~ an extra rinse subcycle is to occur following the normal rinse
(which is a portion of the wash subcycle). On the lower row, user opera-
tion of a SPIN DRY TIME switch 42 selects the duration in minutes of the
spin dry portion of the wash subcycle. Finally, WASH TEMPERATURE and RINSE
TEMPERATURE switches 44 and 46, respectively, allow user selection of the
water temperatures to be employed during the washing and rinsing portions
of the cycle. As indicated, the wash temperature may be either HOT,
WARM or COLD, and the rinse temperature may be either WARM or COLD.
A display portion 47 is located at the right side of the
user control panel 22. The display portion 47 includes a numerical
display 48 comprising three digital readouts, which are illustrated as
being the seven-segment type. The numerical display 48 indicates, at the
beginning of a washing cycle after the user has selected the cycle options
and pressed the START/STOP switch 28, the time in minutes required to execute
the particular washing cycle programmed. Thus, the user has an immediate
indication of how much time will be required for the washing machine 20 to
complete the particular wash cycle selected. It will be appreciated that
the cycle time varies significantly depending upon which particular cycle
options are selected, and depending upon the length of time selected for
those cycle options having user-selectable duration. In operation, as
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9D-HL-13374-Simcoe
In connection with the prescak, wash, and rinse subcycles, the
clothes washing machine 20 includes an additive dispensing system similar
to that disclosed in U.S. Pat. No. 3,727,434-80chan, the entire disclosure
of which is hereby incorporated by reference. The Bochan patent dis-
closes a system for sequentially dispensing a plural~ty of treating agents~nto the wae~ tub of an automatic washing machine at predetermined times
during the washing cycle. The additives may be a prewash add~ttve for the
presoak operation, a soap or detergent and a 61each for the wash
operation, and a rinsing agent for the rinse operation. The Bochan
dispenser ~ncludes a plurality of comparbments for storing the treat~ng
agents to be dispensed. In the particular dispenser there dlsclosed,
a mechanically-operated water supply device is sequentially controlled
to selectively direct water into the compartments to flush th~ agents
lnto the wash tub at predeterm~ned tlmes. It will be apparent, ho~ever,
that the mechanical linkage there disclosed may be replaced by a
su~table electromechan1cal means employing solenoids. T~erefore, a
simila~ dtspensing system which receives its instructions from an
electronic controller may he constructed, and such an electromechanlcal
dispensing system is included ~n the present clothes washing machine 20.
Controller rnterfacing
Referring now to FIG. 3, an electrical circuit diagram shows
the interfacing between various mechan k al and electromechanical elements
of the washer 20 and an electronic controller 60. These various elements
of the washer 20 include 60th output devlces such as relays, solenoids,
and ind~cator lamps, actuated by the controller 60, and controller input
devlces in the fonn of switches. Preferably, the electronic controller
60 ~s a single large-scale integrated circuit including a relatively large
number of electronic circuit elements on a single semiconductor chip.
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; 9D-HL-13374-Simcoe
In FIG. 3, for clarity of illustration, only the electromagnet
portions of the various water valve and additive dispensing solenoids
are shown. It will be appreciated that the various solenoids and relays
are relatively high current load devices compared to the output capa-
bilities of the electronic controller 60. Accordingly, intermediate loadswitching d~ices are employed ~or ~nterfacing. In the illustrated em-
bodiment9 these intermediate 10ad switching devices are reed re1ays.Each of the illustrated reed relay contacts has associated with it a
correspond~ng coil, for example representative coil 61 which is connected
by means of a representative NPN driver transistor 62 to an output of the
electronic controller 60. Alternatively, the load switching devices may
i comprise solid state switching elements such as triacs.
In FIG. 3, a power plug 63 is provided for connection to a
standard household electrical circuft. Yoltage is therehy supplied across
conductors L and N. The L conductor is connected through a contact 64 of
the ON push switch 26 to supply a conductor 68. Upon user operation of
the switch 26, the contact 64 closes. At the end of a washing cycle, the
release coil 70 of the latching switch 26 is energized by a signal from
the controller 60, suitably interfaced through a driver transistor 72.
This opens the contact 64 to shut off the machine~ Additionally, the
OFF pushbutton switch 27 ~s connected across the collector and emitter
terminals of the driver transistor 72. Thus, the transistor 72 may be
manually bypassed at any time to energize the release coil 70 and shut
off power to the machine 20.
To supply low voltage DC to the electronic controller 60, a step
down transformer 73 is connected across the conductors 68 and N. A conven-
tional low voltage DC power supply 74 connected ~o the secondary of the
transformer 73 supplies the required voltages to the electronic controller
60.
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9D-HL-13374-Simcoe
The washing machine 20 includes an electric motor 75 which
is energized frow the L and N conductors when the switch contact 64 is
closed and a motor relay 76 is energized. Specifically, a circuit ~s
completed from the conductor 68, through a circuit breaker 78, the start
winding 80 of the motor 75, the contacts 82 of a start relay 84, and
the contacts 86 of the motor relay 76, to the N conductor. The motor run
winding 8~ is connected between the circuit breaker 78 and the motor re1ay
76 through motor-reversing relay contacts 90 and 92, which are the contacts
of a spin/ag~tate relay 94. The coil 96 of the motor start relay 84 is
connected in series with the motor run winding 88 so that the relattvely
high starting current for the run winding 88 causes the starting contacts
82 to close and energize the start winding 80 until such time as the motor
74 comes up to speed.
When the coil ~8 of the spin/agitate relay 94 is energized,
the motor reversing relay contacts 9~ and 92 reverse the relative phasing
o~ the start winding 80 and the run winding 88. This effects control of
motor rotat~on direction. A mechani~al transmission ~not shown~, conven-
tiona1 ~n e10thes washing nachines, is responsiYe to the dlrection ofmotor rotation either to cause the agitator and basket (not shown) to
rotate continuously together at relatively high speed for a spin operation
when the tor 75 is rotating in one direction, or to cause the agitator
to move with rotary reciprocating action when the motor 75 is rotating in
the other direction. Specifically, when the coil 98 is not energized and
the contacts 90 and 92 are in the position shown, the motor 75 rotates in
the direction for agitation; when the coil 98 is energized, the contacts
90 and 92 reverse the relative phasing of the motor windings and the motor
rotates in the direction for spin.
The various electromagnetic solenoids in the washing machine
20 and their corresponding reed relay contacts are a hot water valve
solenoid 100 and a corresponding contact 102, a cold water valve solenoid
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~ 9D-HL-13374
104 and a contact 106, a "dispense soak agent" solenoid 108 and a contact
110, a "dispense wash agent" solenoid 112, and a reed relay contact 114,
a "dispense bleach" solenoid 116 and a contact 118, and finally a "dispense
rinse agent" solenoid 120 and relay contact 122. Although not shown, it
will be appreciated that coils, such as the representative coil 61 for the
contact 122, operate each of the above-mentioned reed relay contacts.
Similarly, reed relay contacts 124 and 126 are connected to energize the
spin/agitate relay coil 98 and the motor relay coil 128, respectively.
In addition to the washing machine load devices energized
by the electronic controller 60, several representative inputs to the
electronic controller 60 are shown in FIG. 3. Specifically, there is
a lid switch having two contacts 132 and 133 which close when the machine
lid 134 (FIG. 1) is closed. To prevent operation of the motor 75 unless
the lid 134 is closed, the contact 132 is connected in series with the
motor relay coil 128. To interrupt a low voltage sixty Hz AC timing
signal from which the controller 60 derives its basic clock pulses, the
contact 133 is connected in series between a low voltage AC source and
a controller input line 135.
Similarly, a "full tub" switch has a pair of contacts 136 and
138. The first contact 136 of the full tub switch interrupts current
supplied to the hot and cold water valve solenoids 100 and 104 when the
tub is full, and the second contact 138 supplies a signal to a controller
input line 139 to indicate the tub is full.
The two remaining switch contacts 140 and 142 illustrated
are representative of various contacts associate~ with the user-operable
controls which were discussed above with reference to FTGS. 1 and 2.
General Internal Arrangement of the
Electronic Controller 60
Referring now to FIG. 4, there is shown an overall functional
block diagxam of the electronic controller 60. For convenience, the
numerical display 48 (FIG. 1) is included in the block diagram of FIG.
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9n 90-HL 13374-Simcoe
4, although it will be appreciated that the d1splay 48 is not a part of
the electronic contro11er 60 itself, but rather is connected to an output
thereof.
Generally speak~ng, the controller 60 is a sequence type con-
troller which advances the washing machine 20 through a series of lndiYidualsteps. T~e frequency at which program advancing operations occur depends
upon the particular mode t~e controller 60 is in. For example, dur~ng the
"run" mode, a program advancing operation occurs in response to each bas~c
clock pulse, basic ctock pulses occurring at thirty-second intervals. The
precise sequence of steps and the duration of ~ndividual operations ~s
determlned ~n part by the programming of the controller during manufacture,
and in part by user cycle selections at the beginning of each wash1ng cycle.
The controller 60 includes a program sequencer 150 which is
essentially a digital counter. The program sequencer counter 150 proceeds
through its various states in response to inputted clock pulses, e~ther
sequentially step-by-step or ~n ~umps, dependlng upon the particular wash-
lng cycle opt~ons selected and the particular po~nt in t~e wash~ng cycle.
Control over the operation of the program sequencer 150 is
generally accompl~shed by sequence control log~c 152 wh~ch is connected
both to rece~ve various user cycle selection inputs and to rece~ve, from
the program sequencer counter 150, information ind kating the state of
the counter 150, each counter state corresponding to a particular pro-
gram step.
The program sequencer 150 also has outputs connected to a
program memory 154 which decodes ~nformat~on indlcat~ng the state of
the program sequencer counter 150 to provide su~table output contro1
s~gnals to operate the various load devices of FIG. 4. The program mem-
ory 154 add~t~onally sends signals along an internal time set signal path
156 to a t~mer setting control 158.
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9D-HL-13374-Slmcoe
Exemplary circuitry for and the operation of the program
sequencer 150, the sequence control logic 152, and the program memory
154 are described hereinafter with part~cular reference to FIGS 5, 6A
and 6B.
To determine the duration of particular operations in the
exemplary washing cycle, a programmable timer 160 ~s prov1ded. The
programmable timer 160 also ~s essent~ally a digital counter, and is
connected to receive 1nstructions from the timer setting control 158. It
wtll be appreciated that the duration of many of the particular operations
which compr1se a complete wash cycle ~s much greater than the interval
between successive basic clock pulses, wh1ch interval ~s thirty seconds
1n the embodiment herein described.
The function of the programmable timer 160 is to accumulate
clock pulses untll a predetermined count is reached. Dur~ng ~run" mode
operat10n, a clock pulse for the programmable timer 160 occurs for each
program advancing operation. The predetermined count is determined by
the timer setting control 158, which receives inputs both via the signal
path 156 from the program memory 154 and via a signal path 162 from the
var10us user time select10n switches, for example the SOAK TIME switch
34 (FIG. 1).
The controller 60 also has, assoc1ated with the numer~cal
d1splay 48, an up/down d1gital counter 164~ The counter 164 comprises
conventional un~ts, tens, and hundreds decade counters 166, 168, and
170, respect1vely. The counter 164 has three input lines, a cloc~
pulse lnput 11ne 172, an UP/DOWN control ~nput l~ne 174, and a RESET
~nput l~ne 176. In operation, the counter 164 counts either up or down
1n response to ~nputted clock pulses along the line 172, the d1rection
of count1ng being determined by a signal on the UP/DO~N line 174. The
counter 164 resets to a zero state when a signal is received along the
RESET line 176.
~ O 9D-HL-13374-Simcoe
Outputs indicating the state of the digital counter 164 are
connected in conventional fashion to drive the numerical display 48.
In the particular embodiment herein described, the numerical
display 48 indicates time to go in minutes. However, the interval between
basic clock pulses employed in the controller 60 is thirty seconds. There-
fore, a divide-by-two or binary element 177 ~s interposed between a D CLOCK
line 178 and the actual counter clock pulse lnput line 172, a D CLOCK
pulse occurring for each program advancing operation during "run" mode
operation. The binary element 177 may comprise, for example, either a
J-K type flip-flop, or a D-type flip-flop, suitably connected.
The last element in the overall functional block d~agram of
FIG. 4 is a master control logic 180. The master control logic 180 is
descr1bed in detail below with reference to FIGS. lOA and lOB, At this
point in the description it ls sufficient to state that the master control
logic 180 includes a basic clock 182 for producing basic clock pulses, and
a high speed clock 184 for producing high speed clock pulses relative to
the frequency of the basic clock pulses. Additionally, the master control
logic 180 includes means for suitable interconnection with the other ele-
ments of the controller 60 to direct the proper operation thereof. These
~nterconnections are indicated in a general way by lines with arrows.
From FIG. 4 it can be seen that inputs to the master control logic 180
include connections from the START/STOP pushbutton switch 28 and the
SERVICE switch 30.
General Operation of the Controller 60
Referring, in addltion to the block diagram of FIG. 4, to the
program sequence chart of FIG. 5, the overall opera ~on of the electronic
contro11er 60 will now be described. FIG. 5 depicts a particular wash
program wh~ch is for purposes of example only. It will be appreciated
that many programs are possible and may be programmed into the controller
60. Although in actual operation the controller 60 operates first in a
"compute" mode and then in a "run" mode, its operation will be best
understood from a description first of the "run" mode.
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9D-HL-13374-Simcoe
At the beginning of the "run" mode, the program sequencer
counter 150 has a state corresponding to Step No. 2 ~FIG. 5), the up/
down digital counter 164 has a state correspond1ng to (and the d~splay
48 is indicating) thè time in minutes which will be required to execute
S the selected program, and the controller 60 is enabled to perform pro-
gram advancing operat~ons in response to the basic clock pulses occurring
at thirty-second intervals.
Since the duration of Step No. 2 is zero, the program sequencer
150 is immediately ~ncremented to Step No. 3, whereupon the program memory
154 sends appropriate control signals to the hot an~ cold water valve
solenoids 100 and 104 (FIG. 3) to cause f~lling of the wash tub. Slnce
the time for water filllng operation is indefinite, depending upon external
factors such as water pressure, a filling operation is constdered a special
circumstance. ~ definite time for a filling operation is not programmed
and the numerical display 48 remains unchanged during the operation. However,
as a safety override in the event that water is not entering the tub for
some reason, the programmable timer 160 ~s programmed, via the internal time
set path 156, for fifteen mlnutes. (Specifically, the programmable timer 160
is programmed to count th~rty-one clock pulses, and to output a ~OUNT REACHED
?O signal immediately upon the reaching of the thirty-first count.)
When the tub {s full, the full tub switch second contact 138 (FIG.
3) closes, whereupon the master control logic 180 steps the program sequencer
150 to Step No. 4.
As can be seen from FIG. 5, during Step No. 4 a soak agent is
dispensed and the agitator operates. These two functions are accomplished
by appropriate control signals emanating from the program memory 154 to
the "d1spense soak agent" solenoid 108 and the motor relay coil 28. For
agltation, the sp~n/agitate relay coil 98 is not energized. From FIG. 5,
it can also be seen that the duration of Step No. 4 is one minute. Since
a basic clock pulse occurs every thirty seconds, the programmable timer 160
is set by the timer setting control 158 to count two clock pulses, and then
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9D-HL-13374-Simcoe
to output a COUNT REACHED signal. Two program advancing operations are
thus required. For this particular step, the duration is internally
selected by means of a signal ~rom the program memory 154 along the path
156 to the timer setting control 158.
At the end of the one minute duration of Step No. 4, the master
control loglc 1~0 steps the program sequencer 150 to Step No. 5. It can
be seen from FIG. 5 that Step No. 5 has an ass~gned duration of 3.5 minutes
and it is an ag~tate operation. Accordingly, the progr2m me ry 154 sends
appropriate signals to de-energize the previously energized soak agent
solenofd 108, but maintains the motor relay 76 energized. kdd~tionally,
the program memcry 154 sends an "~nternal time set" signal along the path
156 to set the programmable timer 160 to count seven clock pulses before
outputting a COUNr REACHED signal, thereby to establish the desired 3.5
minute time duration. When the count i-s reached, the programmRble timer
outputs its COUNT REACHED s~gnal, whereupon the master control logic 180
again steps the program sequencer 150.
At this point, the program sequencer 150 is in the state
corresponding to Step No. 6. Step No. 6 is a soak operation, ln which
the machine 20 stands idle with the tub full for a predeterm~ned length
of time. The soak step dlffers from previously described Steps Nos. 4
and 5 in that the time durat~on thereof is selected by the user, rather
than being an lnternally selected tfme. This user time selectton is
accomplished by a direct ~nput from the contacts of the soak select
switch 34 (FIG. 1) along the path 162 to the timer set~ing control 158.
It can be seen from FIG. S that there are four "soakH steps;
namely, Step Nos. 6, 7, 8 and 9. Because the duration of a soak operation
is relatively long compared to other operat~ons, and a design and pro-
gramming compromise was made. Rather than employing a programnable timer
having additional stages so as to be capable of counting to the relatively
high number which otherwise would be required, four successive program
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9D-HL-13374-Simcoe
steps are used for this operation. Specif~cally, the programmable
timer 160 is capable of counting to thirty-one, which corresponds to
a time interval of 15 minutes. Yet a soak duration of up to sixty
minutes may be selected using four successive program steps. The
saving in counter hardware necessitates a~d~tional program memory.
As the cycle continues, the controller 60 proceeds through
the program outlined in FIG. 5 in the manner generally discussed above.
However, an except~on relates to ~he various programp jumps indicated
by the arrows fn the left hand column of the FIG. 5 program sequence
chart. The arrows indicate that a jump from a particular step to a
particular step can occur if appropriate. Whether a particular program
jump actually occurs is determined by means of external user cycle
selection inputs to the sequence control logic 152. The specific user
cycle selection inputs operable ~n the particular embodiment herein
d~sclosed are SOAK, WASH, and EXTRA RINSF.
For example, if SOAK has not been selected, then at program
Step No. 2, the sequence control logic 152 would cause the program
sequencer 150 to immediately ~ump either to Step No. 16 to begin a
normdl wash and rinse operation, to step No. 34 to begin an extra rinse
operation, or to Step No. 38 to begin a spin dry operation, depending
on whether WASH and EXTRA RINSE are selected.
To summarize the above, a clock pulse for the programmable
timer 160 is generated during each program advancing operation, program
advancing operations occurring in response to basic thirty-second clock
pùlses. These clock pulses are counted or accumulated by the programmable
timer 160 until the specific programmed count is reached, thus establishing
the program step time durat~on. The programmable timer 160 then outputs
-~ a COUNT REACHED slgnal to the master control logic 180, which then steps
the program sequencer 150. In response to each new state of the program
sequencer counter 150, new control signals and timer setting control
signals emerge from the program memory 154. For the case of program
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Step Numbers (FIG S) with an assigned duration of zero minutes, the
program sequencer 150 is rapidly stepped through a plurality of program
Step Nuunbers during each prograrn advancing operation. It will be
apparent therefore that a de~inite and predetermined number of basic
clock pulses are required for the controller 60 to proceed through the
entire program.
The operation of the up/down digital counter 164 and the numeri-
cal display 48 associated therewith while all thls is going on will now
be discussed. As mentioned above, at the beginning of the "run" ~de the
digital counter 164 is preset with a state corresponding to the time in
minutes which will be required to execute the particular wash program
selected. Add~tionally, the UP/DOWN control line 174 carries a signal
appropriate to cause the digital timer 164 to count down: At the same
time the master control logic 180 supplies thirty-second inte~val clock
pulses to be counted by the programmable timer 160, it also supplies clock
pulses along the D CLOCK line 178 to the up/down digital counter 164. One
D CLOCK pulse is supplled for each program advancing operation in direct
response to each basic cloc~ pulse. The binary element 177 interposed
between the D CLOCK line 178 and the counter 164 produces an output puise
every one m~nute on the line 172, since the display 48 of the particular
en~odiment illustrated is in minutes.
As the program execution proceeds during the "run" mode, the
numerical readout 48, indicating the state of the up/down digital counter
164, provides a continuous indication of the time remaining in the exe-
cution of the particular program selected. The digital counter 164
reaches its zero state at the same time the program sequencer counter
150 reaches the end of the selected program, which is Step No. 40 of
FIG. 5.
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9D-HL-13374-Slmcoe
Operation of the controller 60 during the "compute" mode, which
precedes the "run" mode, will now be described. It is during the "compute"
mode that the digital counter 164, and thus the numerical display 48, re-
ceives its initial count corresponding to the number of minutes required
to execute the selected program.
When the washing machine 20 is initially energized by means
of the Oh/oFF switch 26, "power on reset" circuitry (FIG. lOA) fn the
master control logic 180 initializes the program sequencer 150 in Step
No. O for an idle condition, presets the up/down digital counter 164 to
a count of zero, and enables a blink mode for the lamps comprisiny the -
display 48. At this time the user selects cycle option by enterfng
the optional user cycle selections and the user time selections. The
"power on reset" circuitry additionally enables the controller "compute"
mode.
When the START switch 28 is pushed, the program sequencer
counter 150 is set to Step No. 1 (FIG. 5), which is the beginning of
actual program execution. In Step No. 1, the blink mode for the dfsplay .`~48 is disabled. Since the time duration for Step No. 1 is zero, the
program sequencer 150 remains in Step No. 1 only momentarfly before
stepping to Step No. 2.
A significant dffference between operatlon during the "compute"
mode and operation durfng the previously-described "run" mode is that,
during the "compute" mode program advancing operations do not occur in
response to pulses from the basic clock 182. Instead, program advancing
operations occur in rapid repetition generally in response to pulses pro-
duced by the high speed clock 184. The frequency of the high speed clock
184 is in the order of 200 KHz and, in the partlcular controller embodi-
ment herein described, program advancing operations occur with approximately
one-slxth that frequency. An additional difference is that the up/down
9D-HL-13374-Simcoe
counter 164 is enabled to count up, rather than down as during the "run"
mode. A similarity of "compute" mode operation to "run" mode operation is
that clock pulses for the programmable timer 160 and D CLOCK pulses for the
display counter 164 occur just the same during each program advancing
operation. During the "compute" mode, the entire selected program thus
executes at an extremely fast rate. To the user, this initial execution
of the selected program appears almost instantaneous.
Considering specifically the up/down display counter 164 and
its associated numerical readout 48, since the counter 164 starts from
zero at the beginning of "compute" operation and is enabled to c~unt up,
at the time program Step No. 39 is reached (FIG, 5), the counter 164 has
àccumulated a count equal to the number of minutes required to execute
the program.
To end the "compute" mode, the program sequencer 150 jumps
from Step No. 39 to Step No. 43 (FIG. 5). In Step No. 43, the "compute"
mode is disabled, and the "run" mode is enabled. The program sequencer
lSO rema~ns only momentarily in Step No. 43, before jumping back to
Step No. 2. "Run" mode operation then proceeds in the manner pre-
viously described.
During the "compute" mode, to prevent operation of the
various solenoids In the washing machine 20, control signals from
the program memory 154 are disabled. However, since the program exe-
cutes so rapldly during the "compute" mode, even if disabling were not
done, the varlous electromechanical components, for the most part, would
have insufficlent time to respond.
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9D-HL-13374-Simcoe
counter 164 is enabled to count up, rather than down as during the "run"
mode. A similarity of "compute" mode operation to "run" mode operation is
that clock pulses for the programmable timer 160 and D CLOCK pùlses for the
display counter 164 occur just the same during each program advancing
operation. During the "compute" mode, the entire selec~ed program thus
executes at an extremely fast rate. To the user, this initial execution
of the selected program appears almost instantaneous.
Considering specifically the up/down display counter 164 and
its associated numerical readout 48, since the counter 164 starts from
zero at the beginning of "compute" operation and is enabled to count up,
at the time program Step No. 39 is reached (FIG, 5), the counter 164 has
accumulated a count equal to the number of minutes required to execute
the program.
To end the "compute" mode, the program sequencer 150 jumps
from Step No. 39 to Step No. 43 (FIG, 5). In Step No. 43, the "compute"
mode is d~sabled, and the "run" mode is enabled. The program sequencer
150 remains only momentarily in Step No. 43, before jumping back to
Step No. 2. "Run" mode operation then proceeds in the manner pre-
viously described.
During the "compute" mode, to prevent operation of the
various solenoids in the washing machine 20, control signals from
the program memory 154 are disabled. However, since the program exe-
cutes so rapidly during the "compute" mode, even if disabling were not
done, the various electromechanical components, for the most part, would
have ~nsufficient time to respond.
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9D-HL-l3374-Simcoe
~ia~nostic Feature
When the "diagnostic" mode is enabled by operation of the SERVICE
switch 30 on the panel rear 24, neither pulses from the basic clock 182
nor pulses from the high speed clock 184 are employed to step the controller
60 through the selected program. Rather, pulses produced by repetitive
operation of the START/STOP pushbutton switch 28 are employed. A service
technician may, therefore, cause the program sequencer lSO to step quickly
through a selected program until a desired step is reached. In the parti-
cular embodlment herein described, the programmable timer 160 is not used
during the "diagnostic" mode.
When a desired step is reached, the technician no longer operates
the START/STOP pushbutton switch 28, and the program sequencer counter lSO
remains in whatever state it happens to be in.
Falrly rapid access to any particular step in the program is
thereby provided. Further, once a particular program step is reached,
the program sequencer 150 remains ~n that state corresponding to that
step for as long as may be desired. These capabilities are quite useful
for checking out the operation of the various elements, particularly the
electromechanical components, of the washer 20.
20-- To provide information useful to the service technic~an, during
the "diagnostic" mode, the up/down digital counter 164 is enabled to count
up, and the numerical display 48 merely indicates program steps. Since,
in the particular embodiment illustrated, the binary 177 is interposed
between the D CLOCK line 178 and the clock input line 172 of the counter
164, the master control logic 180 outputs two successive pulses on the
D CLOCK 1ine for every operat~on of thè START/~TOP switch Z8.
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Detailed Cir~ s~e~
Exemplary circuit details for the various blocks in the FIG.
4 block diagram will now be described. It will be appreciated that the
description herein is intended only to illustrate one particular electronic
controller scheme for a particular appliance, namely the washing machine
20, and is not intended to limit the scope of the claimed invention. The
description below covers all the blocks of FIG. 4, with ';he exception of
the up/do~., digital counter 164 comprising the decade counting units 166,
168, and 170, and with the further exception of the numerical readout 48.
Digital counters and readouts are commercially widely availahle, and a
detailed description thereof is not helieved necessary to a full under-
standing of a manner of practicing the invention.
The controller 60 herein disclosed is described In terms of
an implementation employing a large number of CMOS integrated circuit
logic devices. The partfcular design described is adapted for implemen-
tation as a single large scale integrated ctrcuit using PMOS fabricatton
technology.
Various memory matrices or arrays are described hereinafter, and
exemplary circuits therefor, which model PMOS logic structures, are des-
cribed. It will be appreciated however, that many internal memory structures
are possible. Further, it wi11 be appreciated that the particular programm-
ing described herein is illustrative only, intended to accompltsh par-
tlcular functions in a partlcular machine, and may vary as des~red to
accomplish other functlons for other machines.
The partlcular logic symbols and sign conventions employed
herein are intended to minimize any confusion which possibly could result
in describing a circuit ~hich may be implemented employing either CMOS (a
"positive logic" family) or PMOS (a Hnegative logic" family).
CD4000 series COS/MOS digital integrated circuits manufactured
by the RCA Corporation have been found suitable for providing the logic
functions in the circuitry described herein. Specifically, the NOR
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gates and the low activated AND gates may be those ~ncluded in integrated
circuit type Nos. CD4001A, CD4025A, or CD4002A, depending upon whether
two, three, or four inputs are required. The inverters may be those
included ~n type No. CD4009A.
An additional frequently employed logic circuit element is
a data-type (D-type) flip-flop. An ~ntegrated circu~t type CD4013A mHy
be employed.
Description of the Program Sequencer 150
and Associated Elements
~ ... . .
Referring now to FIGS. 6A and 68, there is shown a detailed
schematlc diagram of the program sequencer counter 150, the sequence
control logic lS~, and the program memory 154 which are shown in block
diagram form in FIG. 4.
In FIG. 6A, the program sequencer counter 150 is a six-stage
digital counter. The indivldual counter stages are designated A, B, C,
D, E, and F. Each stage comprises a D-type M îp-flop. The flip-flops
are generally ser~ally connected in recirculatlng sh~ft register fashion.
To produce sequentlal countfng operation ~nstezd of mere recirculation,
the Q outputs (also des~gnated E and F) of the E and F flip-flops are con-
nected to the inputs of an EXCLUSIYE NOR gate 190. The EXCLUSIYE NOR
gate 190 may comprtse an RCA type No. CD4030A EXCLUSIVE OR gate followed
by an inverter. The output of the EXCLUSIVE NOR gate 190 is fed back to
the lnput of the A counter stage.
A partlcular feature of the program sequencer counter lSO
~s that ~t is capable of e1ther count~ng step-by-step through ~ts sequence
in response to inputted clock pulses, or of being preset to a particular
- state upon receipt of a clock pulse. So that either of these functions
may be accomp1ished, the input of each of the six counter stages comprises
an AND-OR select gate. Each AND-OR select gate comprises two 2-input AND
gates dr~ving a single 2-input OR gate. An RCA type No. CD4019A AND-OR
select gate may be employed. The function of an AND-OR select gate is
to take the input signal applied to its selected side and to present this
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9D-HL-13374-Simcoe
signal at its output. The AND-OR select gate 191 for the first, or A,
counter stage is representative and comprises upper and lower AND gates
192 and 194, and an OR gate 196, the output of the OR gate 196 being con-
nected to the data tD) input of the A flip-flop.
In connection with the AND-OR select gates, an "enable count"
line 198 and an "enable preset" line 199 are associated with the counter
150. The "enable count" line 198 is connected to the lower input of
each of the lower AND gates, such as the representative lower AND gate
194, and the "enable preset" line 199 ~s connected to the lower input of
each of the upper AND gates9 such as the representative upper AND gate
192. An inverter 200 drives the Uenable count" llne 198 from the "enable
preset" line 199, and the "enable preset" line 199 is supplied by a "jump
to" memory matrix 201.
For counting step-by-step in sequence, the upper input of
each of the lower AND gates ~s connected to the Q output of the preceding
flip-flop. An exception ~s the upper ~nput of the lower AND gate 194
for the A counter stage, which input ~s connected to the output of the
EXCLUSIYE NOR gate 190. For presettlng the sequencer counter 150, the
upper input of each of the upper AHD gates is connecte~ to one of the
output llnes of the "jump to" memory matrix 201. Finally, an SC CLOCK
input line 202 is connected to the clock (C) inputs of the flip-flops.
In operation, when a logic "high" appears on the "enable count"
llne 198, the lower AND gates are enabled to permit whatever signal appears
on the upper input of each lower AND to be presented to the corresponding
OR gate, and thence to the D ~nput of the correspondlng flip-flop. Each
flip-flop Q output ls thus ~n effect connected to the D input of the
succeeding flip-flop. This produces the usual shift register configura-
tion. As clock pulses are received along the SC CLOCK input line 202,
logic levels are shifted from one flip-flop to the next.
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9D-HL-13374-Simcoe
Conversely, when a logic "high" appears on the "enable preset"
line 199, the upper AND gates are enabled. In this condition, each flip-flop
stage receives its ~nput condition from one of the output lines of the "iump
to!' memory matrix 201.
Two additional inputs to the program sequencer counter 150 are
a RESET line 208 and a START SC line 210. The idle condition of the
counter 1~ ~s defined as all flip-flop stages being in the logic "high"
condition. Therefore, the RESET l~ne 208 is connected to the set (S)
input of each flip-flop. A logic "high" on the RESET line 208 sets the
counter 150 to a state of all "hig~s." For the first step (FI6. 5) in
the counting sequence, the counter condit~on is def~ned as all "highs"
except for a "low" in the last or F stage. To force the last or F flip-
flop stage to "low" when a logfc "high" appears on the START SC line 210,
the START SC line 210 is connect~d to the "reset" (R) input of the F
fl~p-flop.
The part~cular counting sequence of the program sequencer 150
during the step-by-step mode may best be understood with reference to the
program sequence chart of FIG~ 5, part~cularly the "counter state" column
thereof, in addition to FTGS. 6A and 68. Initially, when the RESET line
208 goes "high," the Q outputs of the counter stages A, B, C, D, E and F
are set to "high." As a result, the counter 150 remains in the idle state
regardless of any clock pulses appear~ng on the SC CLOCK line 202. This
counter state is represented in FIG. 5 as "HHHHHH."
To start the counting sequence, a logic "high" appears on the
START SC line 210. As indicated in FIG. 5, Step No. 1, counter stage F
is then in the log~c "low" state, and the remaining stages are in the
logic "high" state. In Step No. 1, since the two inputs of the EXCLUSIYE
NOR gate 190 are d~fferent, it is activated and its output, fed back to
the first or A stage, is "low."
Assuming the "enable count" line 198 is "high," during the next
five SC CLOCK pulses the logic "low" initially in the F counter state
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9D-HL-13374-Simcoe
simply shifts around, as indicated in FIG. 5, successively to the A, B,
C, D and E counter stages, whereupon the sequence counter 150 is in Step
No. 6. In Step No. 6, the Q output of the counter stage E has a logic
"low" and the Q output of the counter state F has a logic "high." The
EXCLUSIVE NOR gate 190 is again activated and a logic "low" is fed back
and applied to the D input of the A flip-flop, ready to be trans~erred to
the Q outp~ of the A flip-flop upon receipt of the next SC CLOCK pulse.
Upon actual receipt of the next SC CLOCK pulse, the A counter
stage goes to "low." The orlg~nal "lcw" has been clocked all the way
back to the F counter stage. This counter state corresponds to Step
No. 7.
In summary, the feedback arrangement is such that a new logic
"low" is injected into the A counter stage whenever the states of the
E and F stages are different. Each succeeding SC CLOCK pulse causes
the logic "low" to step one stage to the right. It will be seen that,
so long as the "enable count" line 198 is "high," the program sequencer
counter 150 proceeds sequentially through the counter states indicated
in FIG. 5 as SC CLOCK pulses are received.
In order to translate the various possible counter states
into Step Numbers, there is provided a decoding memory array 212 which
comprises an upper decoding memory array 214 and a lower decoding
memory array 216. As shown in FIGS. 6A and 6B, the Q and Q output lines
of each of the six program sequence counter stages are connected to inputs
at the top of the decoding memory array 212. For clarity, actual con-
nections are illustrated only for the first, or A, counter stage. Theupper and lower decoding arrays 214 and 216 function to output an
appropriate signal along a corresponding horizontal Step Number line
when a particular counter state is reached. The upper decoding array
214 has horizontal output lines for program Step Numbers from which
jumps may occur extending to the "iump to" memory matrix. The lower de-
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coding array 216 has a horizontal output line for each of
the forty-three counter states utilized in the particular
controller herein described. The upper decoding array
214 and the "jump to" memory matrix 201 together comprise
the sequence control logic 152 of FIG. 4, and the lower
decoding array 215 comprises a portion of what is termed
the program memory 154 in FIG. 4. However, in one sense
the sequence control logic 152 may also be considered
"program memory".
The "jump from" Step Numbers programmed into
the upper decoding array 214 are indicated in FIG. 5,
left-hand column, by those step numbers having
horizontal lines without arrow heads. As shown,
jumps may be made from Step Nos. 2, 15, 30, 39, and 43
in the particular washing program shown. In FIG. 6A,
"jump from" Step Number designators are drawn to each
of the lines extending from the upper decoding array 214
to the inputs of the "jump to" memory matrix 210.
Since a decision whether to jump to a
particular program step depends not only upon the
particular step which the program sequencer counter
150 is in, but also upon the user cycle selections,
the input portion of the upper decoding array
214 is connected to receive inputs from the
user cycle selection switches (FIG. 1).
Specifically, there are EXTRA RINSE, WASH, and
SOAK lines, each of which is "high" when the
corresponding option is selected. For complete
decoding, three inverters supply EXTRA RINSE, WASH,
and SOAK lines. Additionally, depending on whether
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~ 9D-HL-13374
the controller 60 is in the "run" mode or in the
"compute" mode, the program sequencer counter 150 must
either stop or jump back to the beginning upon xeaching
Step No. 39. To convey this instruction, a COMPUTE
line 217 from the master control logic 180 (FIGS. 4
and 10) is also connected to the upper decoding array 214.
The COMPUTE line 217 is "high" during the "compute"
mode.
As may be seen from FIG. 6A, more than
one of the array 214 output lines may correspond to
the same "jump from" Step Number~ Particular
examples are the lines for jumps from Step Nos. 2
and 15. In normal operation (assuming correct ~:
programming) only one of the array 214 output lines
is "low" at one time, otherwise the "jump to" memory :~
matrix 201 would receive conflicting instructions.
Which one of the array 214 output lines is "low"
depends on the particular state of the external inputs
to the controller 60 via the "User Cycle Selection"
inputs. Thus, the particular controller structure ~
illustrated and described herein permits there to be ~:
multiple jump possibilities from a particular
program step, the particular one, if any, of the jump
possibilities which occurs during any one execution
of the washing program being dependent on the particular
state of the external input. :
The horizontal output lines from the lower
decoding array 216 are connected to the input of an
information memory array 218. Outputs of the information
array 218 extend from the top thereof. Generally,
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9D-HL-13374-Simcoe
these outputs, after passing through additional logic, provide the "Control
Signals" (FIG. 4) to drive the various load devices within the washing
machine 20. Additionally, those outputs designated OCl, OC2, ITl, IT2, and
IT3 provide the "rnternal Time Set" slgnal along the path 156 (FIG. 4) for
the programmable timer 160. The "OC" output bits carry an "Origin Code"
which indicates whether a user-selected time or an internally-selected time
is to be us~d for a part~cular program step. If an internally-selected
t~me is to be used, the "IT" output btts indicate that particular "Inter-
nal Tlme" interval. The lower decoding array 216, the ~nformation memory
array 218, and the additional log~c at the output of the inform2tion
memory array 218 together comprise the program memory 154 of FIG. 4.
An exemplary structure for the var~ous memory arrays will now
be described with reference to FIG 7. The particular structure described
herein is a typ~cal memory structure ~h~ch can be implemented as a portion
of a single large-scale ~ntegrated circuit including the entire controller
60 and us~ng PMOS logic. It will be apprec~ated that any one of the many
possible memory structures may be employed, and the structure herein
described ls not intended to be limiting.
For convenience, the structures of the lower decoding memory
array 216 and the information memory array 218 only are described in
detail herein, these two arrays being exemplary. The various other arrays
are constructed along simllar lines, differing only in size and particular
programming. It will be recognfzed by those skilled in the art that the
memory arrays 216 and 218 together comprise what is often termed a "read
only memory" (ROM), commercially available in various forms.
The memory structure will be best understood with reference
to both FIGS. 6B and 7. Specifically, FIG~ 7 shows greatly enlarged
details of portions of the lower decoding memary array 216 and the infor-
mation memory array 218. The heaYy dots used in the array depictions of
FIG. 6B actually are representative of locations of P-channel MOS transis-
9D-HL-13374-Simcoe
tors in FIG. 7. The specific FIG. 7 excerpts are portions of the first
three rows of both arrays 216 and 218 (corresponding to Step Nos. ls 2,
and 3), of the first four columns of the array 216 (connected to inputs
A, ~, B7 and B) and of columns 5, 6 and 7 of the array 218 (connected
to outputs IT2, IT3, and line 256~. The particular excerpted portlons
were selected arbitrarily tc best illustrate the principles of the memory
arrays.
Considering now specifically the l w er decoding array 216,
Each hor~zontal row functions generally as a NAND gate having an input
at each of the locations marked with a heavy dot (FIG. 68) or a transis-
tor (FI&. 7~. A logic "high" is required on all inputs having heavy dots
to produce a logic "low" output. If any s~ngle input is "low," then the
output is "high."
` The me~ory array 216 comprises vertical input lines 220, hori-
- 15 zontal output lines 223~ load resistors 224 connected between each of
the output llnes 223 and a relatively negative DC supply (logic "low"
voltage), and PMOS transistors 225 to effect the programming desired.
The transistors 225 connect particular crosspoints of the input and output
lines 220 and 223 aocording to the locations of heavy dots in FIG. 6B.
Specifically, the gate term~nals of the transistors 225 are connected to
the input lines 220, the drain termlnals are connected to the output lines
223, and the source terminals are all tied to a relatively positive DC
supply (logic "high" voltage~. As is customary in the fabrication of
PMOS memory arrays7 the load resistors 224 may comprise suitably biased
and doped PMOS transistors on the same substrate as the transistors 225.
As an example of the operation of the memory array 216, if the
program sequencer counter 150 (FIG~ 6A) is in Step No. 1, then the A and
B input lines 220 are "high," and the A and B input lines are "low." In
order to generate a logic "low" output on a given horizontal output line
223, wherever there is a transistor the intersecting input line 220 must
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9D-HL-1337~-Simcoe
be "high" to cut off the transistor, allowing the particular load
~ resistor 224 to pull the output line 223 "low." A conducting transistor
f would clamp its output line 223 to the logic "high" voltage. Thus, for
the Step No. 1 input condition, only the Step No. 1 output line 223 is low.
Each of the other output lines 223 is "high" because at least one transistor
, for each of the other output lines 223 is connected to an intersecting
input line 220 which is "low," causing the transistor to conduct.
~he memory array 218 on the right side of FIG. 7 has the same
general structure, but differs in programming. In view of this same general
structure, corresponding elements are designated by primed reference numbers,
and will not be further described. In the particular logic context, the
operation of the memory array 218 will be better understood if each vertfcal
row is viewed as a low activated OR gate having an input at each of the
~- locatfons marked with a heavy dot (FIG. 6B) or a diode (FIG. 7). The response
is identical to that of a NAND gate.
Considering now the operation of the array 218, it should be
kept in mlnd that all of the fnput lines 220' except for one are "high."
(Which particular one fnput line 220' is "low" depends on the Step Number.)
Since each vertical row of the array 218 functions generally as a low
activated OR gate, the one input line 220' which is "low" causes each
vertical row having an intersecting heavy dot or diode to output a logfc
"high." The other outputs of the array 218 remain "low."
Thus in the overall operatfon of the lower decoding array 216
and the information array 218, logic "high's" from the Q and Q outputs
of the program sequencer counter 150 flip-flops are suitably decoded and
passed through the two arrays to emerge as logic "high's."
While the various memories are described herein as befng in the
form of arrays, it will be appreciated that the identical functfons may be
accomplished by means of equivalent arrangements of logic gates. However,
for maximum flexibility, the array approach described herein is preferred.
A further generalization of the array approach is described hereinafter
! ' with partfcular reference to FIG. 11.
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Returning to FIG. 6B, the previously-mentioned additional
logic at the output of the information array 218 will be described. The
additional logic provides additional functional capability in the parti-
cular application here concerned. The precise form is somewhat dependent
on the particular application. In many applications it will be preferable
to eliminate this additional logic entirely, relying on programming of the
information array 218 to provide all necessary output decoding. In FIG. 4,
the outputs of the program memory 154 were denoted "Interval Time Set" and
"Control Signals." FIG. 6B thus shows these outputs in detail.
Specifically, to inhibit the energization of the various elec-
tromechanical load devices of FIG. 3 during the "compute" mode, eight
output AND gates, each having an enabling input connected to a COMPUTE
line, are provided. COMPUTE is "high" during the "runH mode. These output
AND gates are designated 228 through 235. The functional load device to
which each of these output AND gates is connected can be determined from
the output des1gnation of FIG. 6B. For example, the AND gate 231 operates ;~
the "dispense rinse agent" solenoid 120 (FIG, 3) when activated. This is
accomplished through the representative driver transistor 62 and the
reed relay coil 61.
Each of the output AND gates also has a signal input. For all
except the AND gates 228 and 232, these inputs are supplied directly
from outputs of the information array 218. For motor control, lines
236 and 237 are connected to inputs of the output AND gates 233 and 229.
respectively. For additive dispensing operations, lines 238, 239, 240
and 241 are connected to the output AND gates 234, 230, 235 and 231.
To respond to User Temperature Selection inputs, the signal
inputs of the AND gates 232 and 228 for the hot and cold water solenoids
100 and 104, respectively, are connected to the outputs of a water tempera-
ture decoding memory array 242. The water temperature memory array 242
may be constructed în a manner similar to the arrays 216 and 218, previously
described with reference to FIG. 7. The operation and programming of the
array 242 may be best understood if each-horizontal row is viewed as a NAND
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gate with an input at each of the heavy dot locations. The outputs of the
water temperature memory array 242 are connected to the inputs of upper and
lower low activated OR gates 243 and 244, which are interposed between the
ac+ual outputs of the array 242 and the output AND gates 232 and 228. A
"high" at the output of the upper low activated OR gate 243 is required
to energize the hot water solenoid valve 100, and a "high" output from
- the lower low activated OR gate 244 ~s required for energization of the
cold water valve solenoid 104.
Inputs to the water temperature memory array 242 include User
Temperature Selection ~nput lines A, B and C from the front panel switches
44 and 46. Addit10nal inputs are from the ~nformat~on array 218. Speci-
fically, there is a FILL line 250, a WASH FILL line 252, and a RINSE FILL
line 254.
In addition to the FILL line 250, five addit~onal output lines
from the ~nformRtion array 218 are provided to operate the front panel
indicator lamps 50, 52, 54 and 56 ~FIG. l). Specifically, there ~s a
SOAK llne 256, a WASH line 258, a RINSE line 260, an EXTRA RINSE line 262,
and a SPIN DRY line 264. Each of these lines carries a logic "high" when
the named function occurs. The SOAK line 256 and the SPIN DRY line 264
are simply connected to drive the front panel SOAK and SPIN DRY lamps 50
and 56 through suftable driver circuitry ~not shown), there being no
additional logic associated with these lines.
Since the WASH lamp 52 and the RINSE lamp 54 each indicate a
second condition by blinking, additlonal logic is required. An input to
the additional logic is a BLINK line 266 which continuously alternates
between "high" and "low" approx~mately once per second. In particular,
an OR gate 268 supplies a l~ne 269 connected to energize the WASH lamp
52. One Input of the OR gate 268 is connected to the WASH line 258, and
the other input is connected to the output of an AND gate Z70. The inputs
of the AND gate 270 are connected to the FILL and BLINK lines 250 and 266
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so that when FILL is "high" the AND gate 270 is enabled
to be repetively activated by BLINK, thereby activating
the OR gate 268 to cause the WASH lamp 52 to blink during
a water filling operation.
Similarly, an OR gate 271 supplies line
272 connected to energize the RINSE lamp 54. One
input of the OR gate 271 is connected directly to the
RINSE line 260, and the other input of the OR gate
- 271 receives the output of an AND gate 273 having
its inputs connected to the BLINK line 266 and the EXTRA
RINSE line 262.
Finally, several control outputs of the
memory arrays 216 and 218 are provided for the
master control logic 180, described hereinafter
with particular reference to FIGS. 10A and 10B.
From the information array 218, a FILL line 274 is
` supplied by an inverter 275 having its input connected
to the FILL line 250. A PWR OFF line 276 is supplied
by an inverter 277 connected to the rightmost vertical
output line of the array 218. Two additional outputs
are taken from the Step Number output lines of the
decoding array 216. These are a RESET BLINK line
278 supplied by an inverter 279 having its input
connected to the Step No. 1 line, and a RESET COMPUTE
line 280 supplied by an inverter 281 having its input
connected to the Step No. 43 line. While these
last two outputs may appear in FIG. 6B to be taken
from the array 218, they are actually extensions of
the horizontal Step Number output lines of the array
216.
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~1~r)3~l)
The overall operation of the program
sequencer 150 and associated elements shown in FIGS.
6A and 6B will now be considered. Reference to the
program sequence chart of FIG. 5 is also required.
In FIGS. 6A and 6B, the decoding array 212 senses
the state of the counter 150. For each individual
counter state (corresponding to a program step), a
single Step Number output line of the lower decoding
array 216 goes to logic "low". Additionally, in the
case of program steps from jumps may be made, a
particular "jump from" Step Number output line of the
upper decoding array 214 outputs a logic "low" when
the particular corresponding counter state occurs in
coincidence with a user cycle selection input which
requires a jump at that point in the program.
As previously noted, for a particular program
sequencer counter state for which "jump froms"
are programmed, the particular array 214 output
line which is "low" may be one of a plurality
of possible "jump from" lines for that particular
program Step Number, with the particular array 214
output line which is "low" depending on the state of
the external input.
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Considering the outputs of the arrays 216 and 218 together, it
can be seen that the particular progran~ning shown in FIGS. 6A and 6e
produces appropriate outputs to drive the external load devices during
the proper program steps. T~is operation may be best understood if
5 several examples are considered. For example, for program Step No. 5
(FIG. 5) the counter 150 is in state ''HHHLHH I' For this counter state,
the D sta o has a logic "low" output on ~ts Q output line, and a logic
"high" output on fts Q output line. Thus D is "high" and D is "low." The
five remaining flip-flop stages each have a logic "~igh" at their res~
10 pective Q outputs, and a logic "low" at their respeetive ~ outputs.
In the Step No. 5 horizontal row in the lower decoding array
216, a logic "high" is applied ta every ~ntersection which has a heavy
dot. This condition is not satisfied for any other horizontal row. In
accordance with the row's NAND gate character~stic, a logic "low" output
15 slgnal proceeds to the right along the output line 223 corresponding to
Step No. 5, and only for Step No. 5, and enters the information array
218. Hori20ntal row 5 of the ~nformatton array 218 has four heavy black
dots. In accordance w~th the low activated OR gate characteristic of
the vertical rows, four logic "h~gh" outputs proceed upwardly along the
20 output lines 223'.
Specifically, for the right-most heavy black dot the actual
corresponding output line is designated 236 and is connected to the lower
input of the AND gate 233. Assuming the "run" mode, COMPUTE is "high" and
the AND gate 233 is activated to operate the motor 75. The output line
25 237 does not have a heavy black dot in the memory matrix at the intersection
with the Step No. 5 row. The line 237 is therefore "low." This "low" is
applied to the AND gate 229, which has its output connected to drive the
spin/agitate relay coil 98 (FIG. 3). The spin/agitate relay 94 is not
energized and the motor 74 rotates in a direction to produce agitation.
30 Still considering the Step No. 5 example, the next heavy black dot from
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the right causes a logic "high" output along the SOAK line 256 which
causes the SOAK indicator lamp 50 (FIG 1) to be illuminated. As an
aside, it should be noted that a logic "high" appears on the SOAK line
256 for all program Step Nos. 3 through 15 since there are heavy black
dots in all of the corresponding memory matrix positions. Reference to
the FIG. 5 program sequence chart indicates that these are program steps
correspond ng to the SOAK subcycle.
Consider~ng now the left-most two dots in the line for program
Step No. 5, these two dots are used to indicate the Internally selected0 time according to the code w~ch appears ~n the follow~ng Table I.
Table r. INTERNAL TIME SET CODE
ITl IT2 IT3 Minutes
L L L 0.5
L L H 1.0
L H L 1.5
L H H 2.0
H L L 3.0
H L H 3.5
H H L 15.0
H H H 0.0
From Table I, it can be seen that output lines ITl, IT2, and
IT3 together output a three-bit code which determines the time durations
for program steps which do not allow user-selection of the duration.
This three-bit code is sent to the timer setting control 158 (FIGS. 4
and 8). Considering the speciflc outputted code for Step No. S, it can
be seen that heavy black dots appear in the matrix positions for ITl and
IT3. Logic "high's" result at these outputs. The internal ttme set
code is therefore "HLH." From Table I, this can be seen to correspond
to a duration of 3.5 minutes. Reference to the FIG. S Program Sequence
Chart confirms that 3.5 minutes is the proper time duration for Step
No. S.
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Still considering the outputs from the information memory
array 218, the two-bit time set origin code appearing on output lines
OCl and OC2 indicates to the timer settlng control 158 whether a user
selected tlme or an internally selected time is to be employed to
determine the duration of a particular program step. TaLle II below
gives this code. Since the programming of the array 218 does not place
a heavy bl; k dot in e~ther position OCl or OC2 at the intersection
with the line for Step No. 5, logic "low" outputs appear. From Table
II, ~t can be seen that the time selection is internal. This means that
the time duration for this particular Step No. 5 is always 3.5 minutes,
detennined by the controller's internal programming, and is not variable
by the user.
TABLE rI. TIME SET ORIGIN CODE
OCl OC2 Origin
L L Internal
L H Tl (User SOAK Time Selection ~ 4
H L T2 (User WASH Time Selection~
H H T3 (User SPIN DRY Time Selection)
The operatlon of the array 218 and assoc;ated logic will now
be considered for another examplary program step, in this case Step No.
16. For Step No. 16, the state of the counter 150 is "HHLHLH." In the
lower decoding array 216, logic "high"s" from the sequencer counter 150
correspond to the locations of the heavy black dots in horizontal row
corresponding to Step No. 16. The Step No. 16 horizontal output line
goes "low."
Step No. 16 is the first ff ll operation in the wash and
normal rinse subcycle. In the information array 218, the first heavy
dot results in a logic "high" output on the FILL line 250. This logic
"high," through the AND gate 270 and the OR gate 268 causes the WASH
lamp 52 to blink to indicate a water-filling operat;on.
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; The next two intersections along the row for Step No. 16 in
the information array 218 do not have dots. Therefore, a "LL" time set
origin code passes along the lines OCl and OC2 to the t~mer setting con-
trol 158, to indicate that the tlme duration of Step No. 16 is internally
generated.
Next, the three-bit internal time set code of Table I is
determined ~y the pair of heavy black dots followed by a matrix location
having no dots. An internal tlme set code "HHL" ~s thereby selected.
From Table I, this corresponds to a time duration of flfteen minutes.
As prev~ously mentioned, a FILL operatlon represents a special case tn
that the precise length of t~me requ~red to fill the tub cannot readily
~,
be determined in advance. Thus the fifteen minutes is a "t~me out" time
i and it is expected that the actual duration of the filling operation will
be much shorter. In a manner hereinafter described with reference to
FIGS. lOA and lOB, the master con~rol logic 180 steps the program sequencer
counter 150 to the next step when a FULL TUB s~gnal is receiYed, rather
than walting for the end of the 15-minute time out period.
The last heavy black dot for Step No. 16 results in a logic
"high" signal on the WASH FI~L line 252, to ultimately cause the hot and
cold water valve solenoids 100 and 104 (FIG. 3) to fill the washing
tub with water of appropriate temperature.
The user temperature inputs A, B, and C are generated by the
settings of the user wash temperature selector switch 44 ant the user
rinse temperature selector switch 46 ~both FIG. 1) according to the coding
shown in Table III, below. The coding described is accomplished by means
of suitably arranged contacts on the swttches 44 and 46 in a manner which
will be read~ly understood to those skilled in the art. A DP3T switch
may be employed for the wash temperature switch 44, and a SPDT switch for
the r~nse temperature switch 46~
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TABLE III. USER WATER TEMPERATURE SELECT CODE
User Selection A B C
Wash: Hot H L X
Warm H H X
5Cold L H X
Rinse: Warm X X H
Cold X X L
X - don't care
W~th the foregoing in mind and from a study of Table III
10 together w~th the programm~ng of the water temperature decoding memory
array 242, tt w~ll be seen that the hot and cold water solenoid valves
100 and 104 are appropriately act~vated. One point about the water
temperature decoding array 242 programming that perhaps requires further
mentlon ls the input from the FILL ltne 250. From the prograo~nlng of
the 1nformat~on array 218 ~t can be seen that the FILL line 250 is "h~gh"
only during Step Nos. 3, 16, 27, and 34. However, durtng Step Nos. 13
and 24 where FILL and SPIN operat~ons occur together, the FILL lfne 250
r~nalns "low." The progrann~ng of the water temperature decoding array
242 inh~b~ts operatlon of the hot water solenoid valve 100 under this
20 condltlon, even though a warm rlnse temperature may be seiected.
The renaln~ng aspect of FIGS. 6A and 6B ~s the upper decod~ng
array 214 and tts associated jump array 201. Each hor~zontal row of the
upper decodlng array 214 may be vlewed as a NAND gate, and each vertical
row of the jump array 201 may be viewed as a low act~vated OR gate. A
25 "low" appl~ed to any one of the hortzontal ~nput lines of the jump array
201 results ~n "h19h" outputs at each heavy black dot location for the
purpose of presetting the sequence counter 150. Additionally, the -
rlght-most vertical row in the jump array 201 has a heavy black dot
in every position. Whenever a jump operation is to occur, one of the
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9D-HL-13374-Simcoe
horizontal input lines to the jump array 201 goes low, and the right-
most vertical output line 199, w~ich is the "enable preset" line, goes
"high."
The programming of the upper decoding array 214 is such that
an output appears on one of its output lines only when both a counter
: state corresponding to a "jump from" Step Number is reached, and the
user cycle ~elections are appropriate. For example, if the user has
selected a WASH operation, but has not selected a SOAK operation, logic
"high" SOAK and WASH signals are applied to the first two heavy dot
locations, respectively, in the first horizontal row of the upper decod-
ing array 214. Whether an extra rinse has been selected is irrelevant
to this particular decision. Therefore in the first row there is no
heavy black dot connected to either the EXTRA RINSE line or the EXTRA
RINSE line.
Still assuming a user cycle selection of WASH but not SOAK,
when program Step No. 2 is reached, corresponding to a counter state of
"HHHHHL," then a logic "low" output signal along the uppermost horizontal
output line of the array 214 (lowermost input of the array 201) causes
the jump array 201 to output appropriate signals, including a logic "high"
on the "preset" line 199, to preset the counter 150 to "HHLHLH" for Step
No. 16.
In a similar manner, it can be seen that the programming of
the upper decoding array 214 and the jump array 201 causes the other jump
conditions outlined in the Program Sequence Chart of FIG. 5 to be
accomplished.
Description of the Timer Setting Control 158and the Programmable Timer 160
With reference now to FIGS. 8 and 9, the programmable timer
160 and associated circuitry will now be described, along with the
operation thereof.
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The programmable timer 160 is similar to the previously dis-
cussed program sequencer counter 150 in that it compr~ses a series of
D type flip-flops connected generally as a shift register. Differences
are that the programmable tlmer counter 160 has only f~ve flip-flop
stages, G, H, I, J and K; and the inputs sf the EXCLUSIVE ~OR gate 282
are connected to the Q output of the I flîp-flop and the Q output of the
K flip-flop, rather than to the Q outputs of the last two flip-flops in
the chain. This particular feedback connection of the EXCLUSIVE NOR
gate 282 results ~n the counting sequence shown in the "Programmable
Timer Sequence Chart" of FIG. 9. Another difference ~s that intermediate
counter states are not decoded. Rather, a useful output results when
Count No. 31 (FIG. 9~ ~s reached ~counter state "HHHHL"). An AND gate
286 is provided to decode this state and to output the COUNT REACHED
signal. A similarity is that the progra~ ble timer counter 160 includes
an AND-OR select gate at the tnput of each counter state so that the
counter 160 may e~ther accept a predetermined initial counter state from
the timer setting control 158, or may simply count in response to ~nputted
clock pulses appearing on a PT CLOCK input line 284 in accordance with the
"counter state" sequence of FIG, 9. Which occurs is controlled by the
signal on a SET Pr line 288. The SET PT line 288 ~s directly connected
to enable the upper AND gates of the ANO-OR select gates for presettlng,
and ~s connected through an inverter 289 to the lower AND gates to enable
sequential counting when SET PT is "low."
In the operation of the programmable timer 160, a logic "high"
on the SET PT line 288 enables the upper AND gates in the AND-OR select
gates so that an ~nitial counter state may be loaded into the counter
from the output of a counter setting memory array 290. When the SET PT
line 288 is "low," the output of the inverter 289 is "high" and the
counter counts in response to inputted PT CLOCK pulses according to the
sequence of FIG. 3.
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Lastly, a RESET PT input line 294 is provided to reset the
counter 160 to a Count No. 31 (counter state "HHHHL") at any time. To
accomplish this, the RESET PT input line 294 is connected to the "set"
(S) inputs of the G, H, I, and J flip-flops, and to the "reset" (R)
input of the last or K flip-flop.
Each vertical row of the counter setting memory array 290
may be viewed as a low activated OR gate. Connected to the various
horizontal input lines of the memory array 290 are outputs of an internal
t~me memory array 296, a soak time memory array 298, a wash time memory
array 300, and a spin time memory array 302. In each of these last
mentioned four memory arrays, each horizontal row may be viewed as a
NAND gate.
The internal time memory array 296 receives the three-bit
internal t~me code, I~ , IT2, and IT3, from the informat~on array 218
(FIG. 6B), with the coding as indicated in Table I, above. In a similar
manner, the soak time memory array 298, the wash time memory array 300,
and the spln time memory array 302 receive user time selection lnputs
coded as indicated in the following Tables IY, V, and VI.
TABLE IV. USER SOAK TIME SELECT CODE
User-Selected Time Counter Time
tMinutes) _(Minutes) Sl S2
10.0 2.5 L L
20.0 5.0 L H
40.0 10.0 H L
60.0 15.0 H H
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TABLE V. USER WASH TIME SELECT CODE
User-Selected Time Counter Time
(Minutes) (M~nutes) _ Wl W2 W3
3 1 L L H
3 L H L
7 5 L H H
9 7 H L L
11 9 H L H
13 11 H H L
13 H H H
TABLE VI. USER SPIN DRY TIME SELECT CODE
Selected Time
~Minutes) SDl æ
1.5 L L
2.5 L H
4.5 H L
6.5 H H
To provide these user input signals, the contacts of the
soak tlme select swltch 34, the wash time select switch 38, and the
20 spln tlme select switch 42 ~FIG. 1) are suitably arranged. For full
decodlng, each of these lnput llnes has an lnverter to provide a set
of inverted lnputs to the memory arrays.
An addit10nal lnput to each of the menory arrays 296, 298,
300, and 302 is provided by an orlgin code memory array 310. The origin
25 code memory array 310 recelves the two-bit OCl and OC2 time set origin
code generated by the lnformation array 218 (FIG. 6B) and produces log1c
"low" output signals whlch are lnverted to logic "high" signals to enable
the time memory arrays 296, 298, 300 and 302 one at a time.
In order to handle the special case of the fill time interval
30 during "compute" mode operation, a NAND gate 312 receives the FILL signal
on the llne 250 from the information array 218 (FIG. 6B) and the COMPUTE
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signal from the master control logic 180 (FIGS. 4 and 10). If both FILL
and COMPUTE are "high," the output of the NAND gate 312 goes low to do
two things: First, it prevents the origin code memory array 310 from
enabling the internal time memory array 296, even though the "LL" internal
time set origin code may be coming from the information array 218. Second,
~y means of the line 318 extending dfrectly to the first horizontal row
of the counter setting aray 290, it readies a state of "HHHHL" for Count No.
31 corresponding to a zero time duration for loading into the programmable
timer counter 160 the next time SET PT goes high.
The overall operation of the timer setting control 158 and
the programmable timer together is directed by control signals from the
master control logic 180 (FIGS 4, lOA and lOB). For each program advanc-
ing operation during both the "compute" and the "run" modes, a PT CLOCK
pulse on the line 284 causes the counter 160 to assume a new state. If
at the particular moment the programmable t~mer 160 ~s accumulating PT
CLOCK pulses to control the duration of a particular program Step Number,
then SET PT is "low" and the inverter 289 is enabling the lower AND
gates for sequential counting. If at the time a program advancing
operation occurs the counter 160 reaches Count No. 31 ~n response to
a PT CLOCK pulse, then COUNT REACHE3 goes "high," signalling the master
control logic 180 to, among other things, enter a new program Step
and cause a new time duration to be set into the programmable timer 160.
In this case, SET PT goes high, a new time setting appears at the output
of the counter setting memory array 290, and another PT CLOCK pulse is
received to load in the new time sett~ng. Depending upon the particular
program Step Number, the new time setting may correspond to an internally
selected time duration or a user selected time duration. Thereafter,
additional PT CLOCK pulses are received as program advancing operations
occur, until Count No. 31 is reached, whereupon the cycle repeats.
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Description and Operation
of the Master Control Loq~180
Referring finally to FIGS. 10, lOA and 108, there is shown a
schematic circuit diagram of the master control logic 180 which is inter-
connected, as generally represented in FIG. 4, with the varlous other
elements in the electronic controller 60 to direct the operation thereof.
The master control logic 180 receives a number of inputs from
sources external to the electronic controller 60, for example from switches
In the washing machine 20. A number of these inputs are discussed below.
To provide a timc base, a low voltage sixty Hz AC sine wave is
input along the line 135~ From FI6. 3, ~t can be seen that when the l~d
A switch contact ~ is open7 this t~me base source is interrupted, thereby
halting the operatlon of the controller 60, but not resetting it. In
FIG. lOB, the line 135 is connected to a conditioning clrcuit -~22 which
functions to output a sixty Hz pulse signal from a low activated AND gate
324. In addition to the low activated AND gate 324, the conditioning
circuit 322 comprises a two-stage clocked shift register comprlsing D-type
flip^flops 326 and 328. The clock inputs (C) of the flip-flops 326 and
328 are supplied by the high-speed clock oscillator 184.
In the operation of the conditionlng circuit 322, durlng each
AC cycle when the slxty Hz ~nput goes from a relatively lcw voltage to a
relatlvely high voltage, a log~c "high" is clocked through the flip-flops
326 and 328. Ouring high-speed clocking, there is an interval between
successive clock pulses during which the Q output of the flip-flop 326 and
the Q output of the flip-flop 328 are both "low." The low actlvated AND
gate 324 outputs a logic "high" pulse.
Another input to the master control logic 180 is a pair of DC
power tnputs PWRl and PWR2. PWRl is connected to the DC supply terminal
of an inverter 332, while PWR2 is connected to the input of the inverter
332. The power supply 146 (FIG~ 3) is arranged by means of suitable RC
time delay circuitry such that PWRl comes up before PWR2. The inverter
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9D-HL-13374-Simcoe
332 initially outputs a logic "high" POWER ON RESET signal along a line
334 until PWR2 comes up. This initial POWER ON RESET signal initializes
the controller 60 in a manner hereinafter described.
A third input to the master control logic 180 is from the
SERYICE switch 30 ~FIGS. 2 and lOA). When the SERVICE sw;tch 30 is in
the NORMAL position (closed~, a "diagnostic" (DIA) line 336 goes "low."
An inverter 337 outputs a 'ihigh" on a DIA line. Conversely, when the "diag-
nostic" mode is selected, DIA is "high" and DIA is "low."
A fourth input to the master control logic 180 is from the
START switch 28 (FIGS. 1 and lOA~. The ~nput from the START switch 28
is applied to a transistion detector and debounce network 338, which is
similar to the condition~ng circuit 322. It also comprises a two-stage
clocked shtft register clocked by the sixty Hz pulse signal. The tran-
sition detector and debounce nebwork 338 has as its output stage a NAND
gate 340 which supplies a FB line 342. In response to each operation of
the START pushbutton switch 28, a logic "low" PB pulse is output along
the line 342. The F~ line 342 is normally "high."
Another input to the master control logic 180 is a FULL TUB
signal input along the line 139 from the FULL TUB switch contact 138
~FIG. 3). The line 139 ~s "high" when the tub is full. The FULL TUB
signal is gated through a NAND gate 344 to another debounce network 346,
similar to the previously-discussed debounce network 338. The debounce
network 346 has a low activated AND gate 348 as its output stage. The
low activated AND gate 348 outputs a logic "high" signal along a line
350 whenever both a FULL TUB signal is received and the other conditions
required by the gates 344 and 348 are satisfied.
In addition to the above-described inputs, the master control
logic 180 receives various inputs from other elements of the controller
60 (FIGS. 4, 6A, 6B and 8~. These inputs are described hereinafter as
the description proceeds.
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Clock Pulse Sources
As previously mentioned, the electronic controller 60 includes
means for producing basic clock pulses and a means for producing high
speed clock pulses. The means for producing basic clock pulses is desig-
nated 182 in FIG. 4, and is depicted as a "basic clock." In FIG. 108,
this means is shown more specifically as a "divide by 1800" counter 182.
The "divide by 1800" counter 182 counts sixty Hz time base pulses until
a count of 1800 is accumulated. At this point, a momentary logic "low"
pulse is outputted along a line 351. For a power line frequency of
sixty Hz, 1800 csunts are accumulated every thir~y seconds.
It will be appreciated 6y those skilled in the art that a
counter such as the "divide by 1800" counter 182 may readily be constructed
using flip-flops and appropriate feedback. For example, a shift register
type counter such as the programmable timer counter 160 (FIG. 8) may be
employed, with a gate such as the ~ND gate 286 connected to decode the
particular counter state corresponding to a count of 1800. If this type
of counter is employed, eleven stages are required to accumulate a count
of 1800.
The counter 182 additionally outputs a BLINK signal having a
frequency of approximately one Hz on the BLINK line 266. The precise
frequency is not important as this BLINK signal is merely used to cause
the various indicator lamps and dlsplays to blink when appropriate. It
will be appreciated that the BLINK signal may readily be tapped off one
of the stages of the counter 182.
The means for producing high speed clock pulses is designated
184 in FIG. 4, and depicted as a "high speed clock." More specifically,
in FIG. 10, ~his high speed clock 184 may be seen to comprise quite simply
an oscillator, such as a conventional "555" IC timer set up as an astable
multivibrator having an output frequency of approximately 200 KHz.
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9D-HL-13374-Simcoe
Master Control Logic Shift Register
A six-stage shift register 354 (FIG. lOB) is an important element
of the master control logic 180. The shift register 354 comprises six
serially connected D-type flip-flop stages, designa~ed S0, Sl, S2, S3, S4,
and S5. For convenience, each of the shift register flip-flop output lines
has the same designat~on as the corresponding flip-flop stage. For example,
the Q output of the S2 flip-flop is also designated "S2," and the Q output
of the Sl flfp-flop fs designated "Sl."
The output of the high speed clock 184 is connected along a
clock line 356 to directly and continuously clock the shift register 354.
The shift register 354 has a "reset" line 358 which is connected
to the "set" (S) input of the flip-flop S0 stage, and the "reset" ~R)
inputs of the remaining flve flip-f7op stages. When a logic "h~gh" appears
on the reset line 358, the shfft register 354 is reset to an initial state
of "HLLLLL," and it ~s held in that state so long as the reset line 358
remains "high." Tr~ggering of the shift register 354 is accomplished by
release of the reset line 358 to logic "low," wheneupon the logic "high" in
the S0 flip-flop stage rapidly steps to the right through the remaining
flip-flop stages in response to high speed clock pulses along the
clock line 356. Since the D input of the flip-flop stage S0 is tied to
logic "low," the shift register 354 remains in a terminal state of
"LLLLLL" until such time as another logic "high" appears on the reset
line 358.
In a manner here~nafter described, each time the shift
regfster 354 is thus triggered, the logic "high" stepping through the
various stages produces a momentary flurry of activity throughout the
electronic controller 60. At other times, when the shift register 354
is idltng in the "LLLLLL" state, there is little activity throughout the
controller 60. Each operation of the shift register 354 generally cor-
responds to and in fact controls a "program advancing operation,"
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9D-HL-l3374-Simcoe
previously mentioned. In most cases, the shift register 354 is triggered
once for edch program advancing operation. However, for program advanc-
ing operations which cause a program step to be completed or which cause
a program step having a zero time duration to be entered, additional
triggerings of the shift register 354 occur.
Tied in closely with the shift register 354 is a "count
reached" l~ch 360 (FIG, lOA~ which comprises a D-type flip-flop. The
output of the "count reached" latch is along a CRL line 362. Addit~on-
ally, an inverter 364 provldes a CRL signal along a llne 366. The data
(D) input of the latch 360 ~s connected to receive the logic "high"
COUNT REACHED slgnal from the AND gate 286 (FIG. 8). The COUNT REACHED
line is also tied to the "set" ~S) input of the latch 360. To provide
two clock pulses for the latch 360 during each operation of the shift
register 354, the shlft register S2 and S5 output lines are connected
to the Inputs of a NOR gate 368 which is follcwed by an in~erter 370.
rn the operatlon of the "count reached" latch 360, normally
COUNT REACHED and CRL are both "low." When COUNT REACHED goes "high,"
the latch 360 and CRL are Immediately set to "high." After COUNT
REACHED returns to "low," a "low" is applied to the data (D) tnput,
but CRL remains "hlgh" until the latch 360 is clocked.
Shift Register Steps
The circuitry and events assoc~ated with a logic "high" as
it steps through each of the stages of the shift reglster 354 will now
be consldered. For convenlence of description, the shift register state
which exlsts when the logic "high" is in a particular stage may be re-
ferred to herein simply as a shift register step.
When the logic "hlgh" is set into shift register stage SO,
(shlft reglster step SO~ nothing In particular happens because no outputs
(other than the data ~D) input for the next shift register stage Sl) are
taken from the stage SO, The shift register 354 is held in the state
"HLLLLL" so long as the reset line 358 carries a logic "high."
:
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For shift register step Sl, a number of things can happen. For
one thing, the Sl line carries a logic "low" upwardly to "Full Tub" cir-
cuitry 372 (discussed later). Additionally, a downwardly-extending
portion 374 of the Sl line carries a logic "low" to the upper input of
a low activated AND gate 376. If other conditions are satisfied, the
output of the low activated AND gate 376 goes on to generate a PT CLOCK
pulse for '~e programma61e timer 16Q (FIG. 8~ and additionally a D CLOCK
pulse for the up/down digital counter 164 (FIG. 4).
Other condit~ons which must be sat~sfied for a PT CLOCK pulse
to he produced are sensed 6y a low act~vated AND gate 378, followed by
an inverter 379. Specifically, the upper input of the low activated
AND gate 378 must be "low," which occurs when CRL is "low" and the
programmable timer 160 has not reached the end of its counting sequence.
Additionally, the DIA line 336 connected to the lower input of the low
activatet AND gate 378 must be "low," which occurs when the "diagnostic
mode" has not been selected. When these conditions are satisfied, the
low activated AND gate 376 outputs a logic "high" which is received by
the lower input of a NOR gate 38Q, the logic "low" output of which is
inverted by an inverter 382 to produce a 10gic "high" PT CLOCK pulse.
The logic "high" output of the low activated AND gate 376,
after being inverted to a logic "low" by an inverter 384. is additionally
applied to the upper input of a low activated AND gate 386. The low
activated AND gate 386 is thus enabled to produce a logic "high" output
through a NOR gate 388 and a low activated AND gate 390 to produce the
D CLOCK signal for the up/down digital counter 164 (FIG. 4). To enable
the low activated AND gate 390 when DIA and COMPUTE are not both high,
an AND gate 391 receiving its inputs from the DIA and COMPUTE lines has
its output connected to the low activated AND gate 390. The inputs of
the low activated AND gate 386 also require that DIA is "low" ("diagnostic"
mode not selected), and FILL is "high" (program sequencer 150 is not in
0
~ 9D-HL-13374-Simcoe`
a "fill" step). An inverter 392 is provided to produce the required "low"
on the lower input of the low activated AND gate 386 when FILL is "high."
If the shift register stage Sl has the logic "high" at a time
~; when the programma~le timer 160 nas reached its count and CRL is therefore
"high," then the low activated gate 378 is not activated and the shift
register 354 merely steps to the next state, without either a D CLOCK or
, a PT CLOCK ~ulse being produced.
For shift register step S2, if other conditions are satisfied,
a low activated AND gate 394 produces an SC CLOCK pulse for the program
sequence counter 150 ~FIG, 6A~. h r an SC CLOCK pulse to be produced,
not only must S2 be low, but the output of the low activated AND gate 3?8
applied to the lower input of the low activated AND gate 394, must also
be "low." For the output of the low activated AND gate 378 to be "low,"
either the programmable t~mer 164 must have reached its count so that CRL
is "high," or the "dtagnost~c" mcde must have been selected so that DIA
is "high."
In addition to producing an SC CLOCK pu1se at this time, the
S2 line applied to the upper ~nput of the NOR gate 368 feeding the clock
input of the "count reached" latch 360 permits resetting of the count
reached latch 360 if COUNT REACHED is "low."
If none of the foregoing conditions are satisfied, the logic
"high" merely steps to shift register stage S3 upon receipt of the next
, pulse along the clock input line 356, without either an SC CLOCK pulse
being produced or resetting of the "count reached" latch 360 occurring.
For shift regfster step S3, what can occur, again if other
condltions are satlsfied, ~s the setting of a flip-flop 395 to cause SET
PT to go high. The flip-flop 395 comprises a pair of NOR gates 396 and
398 cross-coupled such that a logic "high" on a set (S) line 400 produces
a "high" output on the SET PT 1ine 288. This enables setting of the
programmable timer 160 (FIGS. 4 and 8) to establish a duration for a
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particular program step. The shift register output line 55 is connected
to the reset (R) input for later resetting of the flip-flop 395.
The flip-flop 395 is set if a logic "high" is produced at
the output of a low activated AND gate 406, which requires not only a
logic "low" on the S3 line applied to the upper input of the low acti-
vated AND gate 406, but also requires a logic "low" output from the
low activated AND gate 378. The output of the low activated AND gate
378 is "low" either if CRL ~s "high" or if DIA ~s "high."
For shtft register step S4, another PT CLOCK pulse can be
produced. This is accomplished through a low activated AND gate 408
having the lower input connected to the S4 line and the output connected
to the upper input of the NOR gate 380. For a PT CLOCK pulse to be
produced at this time requires that the upper input of the low activated
A~D gate 408 connected tû the CRL line 366 be "low." This corresponds to
a condition where the programmable timer 160 is s;tting on "count reached"
wait~ng for a new time duration to be set. Since, SET PT is "high," a
PT CLOCK pulse at this time causes a new time duration to be clocked into
the programmable timer 160 ~FIG. 8).
A low activated AND gate 410 also has an input connected to
the S4 line, with the other input connected to the DIA line. If the
"diagnostic" mode has been selected, then DIA is "low." This enables
the low activated AND gate 410 to output a logic "high" to the NOR
gate 388 to produce a D CLOCK pulse. Thus~ when the controller 60
is in the "diagnostic" mode, O CLOCK pulses are produced during shift
register steps Sl and S4.
Considering finally shift register step S5, the S5 signal
line connected to the lower ~nput of the NOR gate 368 again clor~s the
count reached latch 360 to enable resetting of CRL to "low" if, as a
result of a new time being programmed in, the programmable timer 160 is
now no longer sitting on "count reached."
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Additionally, a logic "high" on the S5 line resets the flip-
flop 395. Lastly, a logic "low" is applied along the S5 line to the
middle inputs of low activated AND gates 412 and 414. This logic "low"
signal along the S5 line enables the low activated AND gate 414 to re-
trigger the shift register 354 in the event CRL is still "low,"
meaning that the new time duration which was programmed into the pro-
grammable timer 160 is zero. When this occurs, the shift register 354
is immediately retriggered to enable, among other things, an SC CLOCK
pulse for the program sequencer counter 150 to be produced so that the
next desired program step may be entered.
By way o~ summary of the foregoing, what occurs during each
cycle of the shift register 354 under various conditions will now ~e con-
sidered. Flrst, it will be assumed that the "diagnostic" mode has not
been selected so that DIA is "low." rt will be further assumed that the
programmable ~imer 160 is part way through a counting sequence but has
not yet reached Its count so that COUNT REACHED and CRL are both "low."
Under these conditions, for shift register step Sl, a PT CLOCK pulse and
a D CLOCK pulse are both produced. This increments the programmable
timer 160 by one, and sends one pulse to the binary 177 (FIG. 4~. During
shlft register steps S2, S3, S4 and S5, nothing happens. When the next
high speed clock pulse is received along the line 356, the shift register
354 goes into the "LLLLLL" state, which is lts idle condition.
Second, it will be assumed that the "diagnostic" mode has still
not been selected so that DIA is "low," and that the programmable timer
160 is at Count No. 30 (FIG. 9), meaning it is just ready to reach its
last count upon the receipt of the next PT CLOCK pulse along the line
284. For shift register step Sl, since CRL initially is "low," both PT
CLOCK and D CLOCK pulses are produced. However, the PT CLOCK pulse
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increments the programmable timer 160 to Count No. 31 so that COUNT
REACHED and CRL both go "high.!'
For shift register step S2, an SC CLOCK pulse is produced.
This causes the program sequencer counter 150 to enter its next step
S according to the sequence of FIG. 5. The next step may, depending
upon the programming, be the result of either a simple increment or a
jump. In either case, a new Internal Time Set signal is sent from the
program memory 154 to the tfmer setting control 158 (FIGS. 4 and 8),
ready to be clocked into the programmab1e timer 160. Additionally,
during shift register step 52, an attempt is made to reset the count
reached latch 360, but since a new time interval has not yet been loaded
into the programmable timer 160, COUNT REACHED and CRL remain "high."
For shift register step S3, the fltp-flop 395 is set9 pro- ~ -
ducing a logic "high" SET PT signal to enable the programmable timer 160
to rece~ve a new tlme duration. However, COUNT REACHED and CRL remain
"high."
h r shift register step S4, another PT CLOCK pulse is produced,
cloc~ing a new program state into the programmable timer 160. COUNT
REACHED immedfately goes "low." CRL remains "high" because the count
reached latch 360 does not yet receive a clock pulse.
For shift register step 55, the flip-flop 395 is reset, and-
SET PT goes back to ''low.U Additionally, the S5 line applies a logic
"high" to the input of the NOR gate 368, producing a clock pulse for the
count reached latch 360. CRL goes "low" and CRL goes "high." The "high"
CRL signal on the line 366 d~sables the low activated AND gate 414, so
that the shift register 354 is not retriggered and enters ~ts idle state.
As a third conditlon if, in the second example discussed
~mmedtately above, the new Step Number (FIG. 5) after shift register
step S1 is either Step No. O, Step No. 1, Step No. 2, or Step No. 43,
then a zero time duration is programmed into the programmable timer
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160 in response to the PT CLOCK pulse during shift register step S4.
In this case, COUNT REACHED remains at log k "high." When shift
register step S5 ~s reached, CRL remains "h19h" and CRL remains "low."
All "low" inputs are applied to ~he low activated AND gate 414, and the
shift register 354 is immediately retriggered for a second operation.
The following briefly outlines the events occurring during this second
operation of the shift register 354/
For step Sl, since CRL is "high," nothing happens.
For step S2, an SC CLOCK pulse ~s produced. An attempt is
made to reset CRL to logic "low." S~nce there has been no opportunity
to clock a new time into the progra~mable timer 160, COUNT REACHED and
therefore CRL remain "h~gh~"
For Step S3, the flip-flop 395 is set to produce a logic
"high" SET PT slgnal.
For Step S4, a PT CLOCK pulse ~s produeed. At this point,
assuming a non-zero time duration ~s now clocked into the programmable
timer 160, COUNT REACHED goes "low," permltt~ng CRL to go "low" during
step S5 when the count reached latch 360 is clocked. The shlft register
354 can then enter the ~dle state "LLLLLL~"
Fourth, it will be assumed the "diagnostic" mode is selected.
DIA is "high" and DIA ~s "low." Each t~me the shift register 354 is
tr~ggered, the following occurs:
For step Sl, nothing happens. For step S2, SC CLOCK and
D CLOCK pulses are produced. For step S3, nothlng happens. For step
S4, another D CLOCK pulse is produced.- rn step S4, a PT CLOCK pulse
may be produced, but it is lrreleYant. Upon reachlng step S~, the shift
reglster 354 goes ~nto ~ts ~dle condition, awaiting another trigger.
Thus, in the "diagnostic" mode, each triggering of the shift
register 354 produces a single SC CLOCK pulse to increment the program
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sequencer counter 150 by one program step, and two D CLOCK pulses are
produced to increment the digital counter 164 (FIG. 4) for the numerical
readout 48. Two D CLOCK pulses are required to increment the counter by
164 one count due to the binary element 177.
Trlggerinq OPeration of the Shift Re~ster 354
The var~ous events which can trlgger an operation of the
sh~ft re~,ster 354 will now be considered. As previously mentioned, a
shift register operation is triggered whenever the reset l~ne 358
goes "h~gh," forc~ng the shtft register to a "HLLLLL" state, and then
returns to "low." An Inverter 415 suppTies the shift reg1ster reset
l~ne 358. Therefore, a logtc "low" followed by a log~c "h~gh" at the
input of the inverter 415 tr~ggers an operat~on of the sh~ft register
354. A NOR gate 416 suppl~es the lnverter 415.
There are actually seven different events wh~eh can trlgger
an operat~on of the shift reglster 354, some of which are alluded to
above. The f~rst three of these trlgger~ng events correspond to the
low act~vated AND gate 412~ the low actfvated AND gate 414, and a low
act~vated AND gate 420 be~ng aettvated, thereby apply~ng a logic "h~gh"
to an ~nput of the NOR gate 416. An ~nverter 422 and another NOR gate
424 (FIG. lOA) collect ~our add~t~onal ~nputs which may be applied along
a l~ne 426 to an ~nput of the NOR gate 416. The NOR gates 416 and 424
are effect1vely a slngle, seven-~nput NOR gate.
The seven events which can trigger an operatlon of the shift
reg~ster 354 w~ll now be considered ~n the order at which the~r Input
llnes are appl~ed to the effect~ve seven-~nput NOR gate just referred to.
The f~rst event corresponds to act~vat~on of the low activated
AND gate 420, and may be cons~dered a normal trtgger. It occurs when the
bas~c clock 182 outputs a 10gic Ulow" pulse along the 11ne 351, the
"d1agnost~c" mode ~s not selected so DIA ~s "low," and the "compute" mode
ls not enabled so COMPUTE is "low."
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9D-HL-13374-Simcoe
The second possible triggering event corresponds to activation
of the low activated AND gate 412, which functions when the "compute"
mode is enabted and COMPUTE is "low." During the "compute" mode, it is
desired that the shift register 354 be retriggered continuously. For
shift register step 55, S5 is "low." Since the high speed clock pulse
line 356 is "low" between h~gh speed clock pulses, the 10W activated AND
gate 412 i^ activated.
The third event which may trigger an operation of the shift
register 354 corresponds to activation of the low activated AND gate 414.
T~is part~cular eYent was prev~ously discussed and corresponds to CRL
being "low" when step 55 of the last preceding shift register operation
Is reached. This occurs when the time which has just 6een clocked into
the programmable timer 160 calls for a zero time duration for the parti- -
cular program step.
The ff fth event which may trigger an operat~on of t~e shift
register 354 to occur fs a log~c "high" on a line 429 connected to an
input of the NOR gate 424. This particular line 429 carries a logic
"high" pulse in response to the first operation of the START pushbutton
switch 28 following a "power on reset" operation. This will be discussed
in greater detail below.
The fourth event which may trigger an operation of the shift
register 354 is controlled by a low activated AND gate 428, the output
of which is connected to an input of the NOR gate 424. The low activated
AND gate 428 is actived whenever the START pushbutton sw~tch 2B is operated
dur~ng the "dlagnostlc" mode.
The sixth event which may trigger an operatîon of the shift
register 354 is a "power on reset" w~ich occurs when the machine 20 is
~nitially turned on. The "power on reset" circuitry is discussed in detail
under a separate heading below. At th~s point, it is sufficient to say an
initial logic "high" pulse appears on a line 430 connected to an input of
the NOR gate 424.
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9D-HL-l3374-Simcoe -
The seventh and last event which nRy trigger the shift register
354 results from the receipt of a logic "high" FULL TUB signal from the
full tub switch contact 138 (FIG. 3) before the progran-nable timer 160
has reached its count. Under these conditions, a logic "high" pulse
appears on the line 350 in a manner discussed next below.
Operation of the Full Tub Circuitry 372
The full tub circultry 372 comprises the previously mentioned
full tub debounce network 346, an RS flip-flop 43l comprising a pair of
cross-coupled NOR gates 432 and 434, and a five-~nput low activated AND
gate 436. The full tub circuitry 372 has three inputs. One input is a
FILL signal from the decoding array 218 (FIG. 6B). FILL goes "low" when
the particular program step according to FI~. S calls for a water-filling
operation. This signal ~s applied to one of the inputs of the low acti-
vated AND gate 436.
Another input to the full tub circuitry 372 is the Sl line
from the shift register 354. Th1s signal is also applied to an input
of the low activated AND gate 436 to enable the low act~vated AND gate
436 during shift register step Sl.
The third input to the full tub ctrcuitry 372 is the FULL TUB
signal along the line 139 from the full tu6 switch contact 138 ~FIG. 3).
FULL TU8 is "high" when the tub is full. During a water-filling operat~on,
FILL ~s "low," and this logic "low" is changed to "high" by an inverter
438 to enable the NAND gate 344. At the same time, the "low" FILL is
applied to the lowermost Input of the low activated AND gate 348, enabling
it as well. The low actfvated AND gate 348 is an element of the debounce
network 346. Thus, when FULL TUB goes "high" and is debounced, the output
of the low activated AND gate 348 is "high."
The full tub circuitry 372 has two outputs. The first output
~s from the low activated AND gate 348 and is applied to the l~ne 350.
The line 350 is connected to the NOR gate 424 to trigger the shift register
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354 (event number seven discussed above), and additionally ls applied to an
input of a NOR gate 440. The NOR gate 440 ~s followed by an inverter 442
which produces the RESET PT signal along the line 294 to reset the program-
mable timer 160 (FIG. 8~ to Count No. 31 (FIG. 9~ ~corresponding to "count
reached"~ when the washing tub fills with water.
The second output from the full tub logic 372 is the output of
tne low activated AND gate 436. This output is connected to a line 444.
A logic "high" on the line 444 t~ ~sed to stop the washing machine 20 fn
the m~ddle of a washing cycle in the event the washing tub has not filled
w~th water wlthin the fifteen minutes allowed. This hould ~e an abnonmal
condition, and the machine 20 would stop as a precaution.
Consldering now the operatlon of the full tub circuitry 372,
usually the tub is not filltng, FILL is "~ig~," and the output of t~e
inverter 438 is "low." The NAND gate 344 is not enabled. Therefore, any
15 FULL TUB signal which may be received does not pass beyond the NAND gate
344. Addltionally, the "high" FILL signa7 applied to the lower input of
the NOR gate 434 sets the flip-flop 431.
When the program sequencer 150 calls for a water-filling
operation, for example du~ing Step Nos. 3, 16, 27, and 34 in FIG. 5, F~--L
is "low." If a "high" FULL TUB signal is received before the programmable
tlmer 160 reaches its count, the low activated AND gate 348 outputs a logic
"high" pulse which resets the flip-flop 430, produces a RESET PT pulse
t~rough the NOR gate 440 to,reset the programmable timer 160 to its "count
reached" state, and triggers an operation of the shift register 354 through
the NOR gate 424.
If, for some reason the tub does not fill during the fifteen
m~nute period allowed, the programmable timer 160 reaches it count
with a FULL TUB remaining "low." In th~s case, t~e low activated AND gate 436
is activated. The resultant logic "high" on a line 444 stops the machine
in a manner hereinafter described.
Power On Reset and Initial Operation
The circuitry related to and operation during the initial power-
ing up of the controller 60 will now be described. Generally speaking,
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9D-HL-13374-Simcoe
when power is first applied, the program sequencer counter 150 ~s set
to Step No. O, the controller 60 is generally placed in an idle con-
dition, and the nu~erical display is blinking. At this time, the
controller 60 is waiting for the user ~o make cycle option selections
and to operate the START pushbutton switch 28. Additionally, the
"compute" mode is enabled.
"hen the user operates the push-to-start sw~tch 28, the
controller 60 then steps rapidly through the entire program in response
to high speed clock pulses. When program Step No. 43 (FIC. 5) is reached,
the "compute" mode fs d~sabled and "run" mode operation immediately pro-
ceeds.
As previously mentioned, upon initial powering up, the inverter
332 outputs a momentary logic "high" POWER ON RESET signal along the line
334. The line 334 ~s connected to the set (S) input of a "power" flip-flop
446 which comprises a pa~r of cross-coupled NOR gates. A POWER OFF line
347 at the output of the "power" flip-flop 44~ goes "low." The POWER OFF
line 347 is connected to the base of the driver transistor 72 (FIG. 3) so
that whenever POWER OFF subsequently goes "high," the coil 70 is energized
to unlatch the sw~tch 26 tFIG. 3) and turn off the machine 20.
A pair of D-type flip-flops 448 and 450 comprise an important
portion of the power on reset circuitry. The data (D) inputs of both flip-
flops are tied together and to the Q output of the flip-flop 448. The
POWER ON RESET line 334 is connected to the set (S) input of the flip-
flop 448 and to the reset (R) input of the flip-flop 450.
The logic c~rcuitry associated with the clnck (C) inputs of
the flip-flops 448 and 450 includes a NOR gate 452, the output of which
is connected to the clock (C) input of the flip-flop 450, and additionally,
through an inverter 454, to the clock (C) input of the ~ip-flop 448.
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9D-HL-13374-Simcoe
The NOR gate 452 has three inputs, the uppermost of which is
connected to the POWER OFF signal line. POWER OFF is "low" when the
machine 20 is on. The middle input of the NOR gate 45Z is connected
to the line 444 from the full tub logic 372. The line 444 is "low" unless
S the full tub logic 372 determines that an abnormal filling condition exists.
The lower input of the NOR gate is connected to the output of a low act~- -
vated AND gate 456, which also supplies the line 429 connected to the NOR
gate 424.
One input of the low activated AND gate 456 is connected to
the PB line 342, which carr~es a mo~entarily "low" PB pulse each time
the START pushbutton switch 28 is operated. The other input of the low
activated AND gate 456 ~s connected to t~e output of a NOR gate 458.
To complete the clock pulse circu~try of the fl~p-flops 448 and 450, the
lower input of the NOR gate 458 is connected to the DIA line, and the ~ ;
upper input of the NOR gate 458 is connected to the Q output of the flip-
op 450.
A number of output connections are mRde to the Q and Q output
lines 430 and 464, respectively, of the flip-flop 448. The Q 7ine 430
is connected to the set ~S~ input of a "compute" flip-flop 466, which
comprises a pair of cross-coupled NOR gates. The outputs of the flip~
flop 466 are the COMPUTE and COMPUTE l~nes. When the flip-flop 466 is
set, COMPUTE is "high," and when the flip-flop 466 ts reset, COMPUTE is
"low." COMPUTE is the inverse. The COMPUTE output line of the flip-flop
466 ~s connected to an input of a NOR gate 468, the output of which is
connected through an inverter 470 to drive the UP/DOWN CONTROL LINE 174
of the counter 164 ~FIG, 4~, When COMPUTE is "high," UP/~WN is "high"
and the counter 164 counts up. So that the counter 164 also counts up
during the "diagnostic" mode, the DIA line is also connected to an input
of the NOR gate 468.
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9D-HL-13374-Simcoe
The Q flip-flop output line 430 is also connected to the set
(S) input of a "blink" flip-flop 471, which comprises a pair of cross-
coupled NOR gates. When the "blink" flip-flop 471 ls set, the BLINK FF
line goes "low." The BLINK FF line is connected to the lower lnput of
a low activated AND gate 472, which outputs the BLANK DIGITS signal when
activated. When BLANK DIGITS is "highN the numerical display 48 (FIGS.
1 and 43 is blanked. To produce a 61inking of the display 48 when BLINK
FF îs "low," the upper input of the low activated AND gate 472 is con-
nected to the BLINK output signal from the "divide-by-1800" counter 182.
To produce a RESET PT signal to initially set the programmable
timer to its "count reached" condftion, the flip-flop Q output line 430 is
also connected to an fnput of the NOR gate 440. Thus, either a logic "high"
along the line 350 from the full tub circuitry 372 or a logic "high" on
the line 462 produces a "high" RESET PT pulse.
The Q output line 430 of the flip-~ op 448 is also directly
connectet to the RESET line 208 which, when "high," resets the program ~
sequence counter 150 to Step No. O and the up/down digital counter 164
for the numerical dlsplay 48 to zero.
The output line 430 is also connected to an input of a low
activated AND gate 474. The other input of the low activated AND gate
474 is supplied by an inverter 476 having its input connected to the
output of the low actfvated AND gate 456. When activated, the low
activated AND gate 474 produces a logfc "high" START SC signal to start
the program sequence counter 150 ~FIG. 6A) by forcing the counter 150
into the state corresponding to Step No. 1.
Lastly, for ~nitial triggering of the shift register 354, the
output line 430 is connected to an input of the NOR gate 424. This
corresponds to the shift register triggering event discussed above.
The Q output line 464 of the flip-flop 448 is connected to
an tnput of a low activated AND gate 478, the output of which is con- -
nected to the reset ~R) input of the power flip-flop 446. The other
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input of the low activated AND gate 478 is connected to receive the
PWR OFF signal from the information memory array 218 (FIG. 6). This
connection permits the programming of the memory 218 to turn off the
machine 20 at a particular Step Num~er. In the exemplary programming,
S Step No. 40 turns off the machine.
The operation of the power on reset circuitry, and particul-
arly that associated with the D-type flip-flops 448 and 450, will now
be described. The "normal" operation will be described first, and
then operation during the "diagnostic" mode.
Initially, when the main power switch 26 is operated, the
POWER ON RESET line 334 goes "high," setting the flip-flop 448 and
resetting the flip-flop 450. The power flip-flop 446 is set and POWER
OFF goes "low." The Q output line 430 of the flip-flop 448 goes "high,"
which sets the "compute" flip-flop 466; sets the "blink" flip-flop 471;
resets the programmable timer 160 (FIG. 8~, the program sequence
counter 150 (FIG. 6A), and the up/down digital counter 164 (FIG. 4)j and
puts a logic "high" on the shift register reset line 358 to set and
hold the shift register 354 ~n the "HLLLLL" state. The output of the
low activated AND gate 340 is "high;" the outputs of the NOR gate 458,
and the low activated AND gate 456 are "low;" the output of the NOR gate
452 is "high;" and the output of the inverter 454 is "low."
At this time the user inputs the various desired cycle
selections and time durations.
Thereafter, a first operation of the START pushbutton switch
28 produces a "low" pulse on the PB line 342. The leading edge of the
PB pulse results in a "low" to "high" transition at the output of the
low activated AND gate 456, and the logic "high" signal is conducted
along the line 429 to the NOR gate 424 to continue to hold the shift
re~ister reset line 358 "high." Additionally, on the leading edge of
the PB pulse, the output of the inverter 454 goes from "low" to "high"
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to clock the flip-flop 448. Since the data (D) input of the flip-flop
448 is initially "low," the flip-flop 448 toggles. The Q output llne
430 goes "low." This "low" and a "low" output of the inverter 476
activate the low activated AND gate 474, beginning a "high" START SC
pulse to set and hold the program sequencer counter lSO in Step No. 1.
The trailing edge of the PB pulse (a "low" to "high" transition)
causes th~ output of the low activated AND gate 456 to go "low" and the
output of the NOR gate 452 to go "high." This clocks the f1ip-flop 450.
Since the data (D) input is "h;gh," the flip-flop 450 toggles. Addition-
ally, the output of the inverter 476 goes "high" causing the output ofthe low activated AND gate 474 to go "low." The START SC pulse thus ends,
releasing the program sequence counter 15Q. The program sequencer counter
150 remains in Step No. 1 ~ecause no SC CLOCK pulse is produced at this
point. Lastly, on the trailing edge of the PB pulse, the line 429 goes
"low," deactivating the NOR gate 424 and releasing the shift regfster
reset llne 358.
At this point, the controller 60 is operating in the "compute"
mode as previously descr~bed. In Step No. 1, the "blfnk" flip-flop 471
is reset 6y a logic "high" RESET BLINK signal from the memory 218 (FIG.
6B~. In Step No. 43, the "compute" flip-flop 466 is reset by a logic
"high" RESET COMPUTE signal from the memory 218. Resetting of the "compute"
flip-flop 466 causes COMPUTE to go "low" and COMPUTE to gp "high," putting
the controller 60 in the "run" ~ode. This includes letting UP/DOWN go
"1 ow . "
During normal operation, the controller may be stopped and
reset at any time. There are three ways this may occur, correspond-
ing to the three ~nputs of the NOR gate 452. Considering first what
happens when the NOR gate 452 ~s activated during normal operation, the
inverter 454 agaln cloc~s the flip-flop 448. Since the data (D) input
is initlally "high," the flip-flop 448 toggles. At this point the same
events occur as occur when the flip-flop 448 is initially set by a logic
"high" on the POWER ON RESET line 334, previously discussed.
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Now, the three ways in which the NOR gate 452 may be activated
to reset the controller 60 will be described. First, there îs a normal
end of program execution. This corresponds to the upper input of the
NOR gate 452 and occurs when the "power" flip-flop 446 is reset by a
logic "low" PWR OFF signal from the memory 218 ~FIG. 6B) applied to the
low activated AND gate 478. PO~ER OFF goes high. ThP second way the
NOR gate 452 may be activated occurs when an abnormal condition is sensed
by the "full tub" circuitry 372. When activated, the "full tub" circuitry
outputs a logic "high" on the line 444 connected to the middle input of
the NOR gate 452. The third way in which the ~OR gate 452 may 6e acti-
vated to reset the controller 60 during normal operatl`on is a second
operation of the START pushbutton switch 28. This corresponds to the
lower input of the NOR gate 452. Thus, the user may at any time terminate
execution of a washing program by operat~ng the START switch a second tfme.
Operation of the power on reset circuitry durfng the "diagnos-
tic" mode wlll now 6e described. The response to the "high" on the POWER
ON RESET line 334 ~s basically the same as for normal operation. One
difference is that, during the initial Ncompute" mode operation, no D CLOCK
pulses are produced and the Up/Down Digital Counter 164 and the numerical
display 48 remain in a ZERO count state. Producing of D CLOCK pulses is
prevented b~ the AND gate 391 which has a "high" output to disable the low
activated AND gate 390 when both D~A and COMMUTE are "high." An initial
run through the "compute" mode is required so that the output gates asso-
ciated with the information arra~ CFIG~ 6B~ are enabled, permitting
operation of the various soleno~ds in the machine 20.
In the "diagnostfc" mode, however, the response to operations
of the START pushbutton switch 28 is quite different. During the normal
operation previously described, a flrst operation of the START pushbutton
switch 28 starts the machine 20, and a second operation at an~ time stops
the machine 20 through a sequence which begins with clocking the flip-flop
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448. ~n contrast, during "diagnostic" mode operation, a second and
subsequent operations of the START/STOP pushbutton switch 28 step the
sequence controller counter 150 and do not stop the machine 20. This
difference in operation is effected by preventing clocking of the flip-
flops 448 and 450 on all but the first operation of the START~STOP
pushbutton switch 28.
Specifically, this difference in operation is accomplished
by selectively disabling the low activated ANO gate 456 to prevent
passage of PB pulses to the NOR gate 452. During normal operation,
10 DIA applied to the lower input of the NOR gate 458 is always "high"
and activating the NOR gate 458. The resultant "low" gate output always
enables the AND gate 456. During "diagnostic" mode operation, DIA is
"low" and any activation of the NOR gate 458 must be the result of a
"high" Q output of the flip-flop 450. Following the initial "power on
15 reset," the ~ output line of the flip-flop 450 is "high." Thus the
NOR gate 458 is initially enabled. However, following the trailing
edge of the first PB pulse, the Q output line of the flip-flop 450
goes "low" and remains "low."
Additionally, following the trailing edge of the first PB
20 pulse, the "low" Q output line of the flip-flop 450 enables the low
activated AND gate 428 which is connected through the NOR gate 424 to
trigger the shift register 354.
Subsequent PB pulses during "diagnostic" mode operation are
then routed through the low activated AND gate 428 to the NOR gate 424.
25 As a result~ "high" pulses are produced on the shift register reset line
358 to trigger an operation of the shift register for each operation
of the START pushbutton switch.
Diagnostic Mode Operation
Other aspects of the operation during the "diagnostic" mode
30 which are not directly related to the "Power ON Reset" circuitry will
now be discussed.
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During "diagnostic" mode operation, the program sequence
counter lSO progresses through the wash program in response to manual
operations of the START/STOP switch 28, with PB pulses 6eing routed
through the low activated AND gate 428 as previously described. The
thirty second pulses from the low speed clock 182 along the line 351
are not used at all. They are interrupted by the low activated AND
gate 420 which has a "high" DIA signal applied to its middle input.
At the same time, the up/down digital counter 164 and the
numerical display 48 increment 5y one ~or each operation of the START/
STOP switch 28. DIA applied to the NOR gate 468 causes the UP/DOWN
line 174 to be "high" so the counter 164 counts up. As previously
mentioned under the heading "Shift Register Steps," each triggering
of the shlft register 354 duriing the "diagnostic" produces two D CLOCK
pulses (during shift register steps S2 and 54~ so that the binary
element 177 outputs a single clock pulse for the counter 164. Thus,
the numerical display 48 prov~des meaningful infonmation to a service
technician. By referring to the Program Sequence Chart of FIG. 5 and
taking into account the options selected, the service technician can
determine, from the numerical d~splay 48, what Step Number t~e controller
60 is in and which electromechanical loads in the washing machine 20
should be energized.
The programmable timer 160 is not employed during t~e
"diagnostic" mode operation. As also previously mentioned under the
heading "Shift Register Steps," each tr~ggering of the shift register
354 during the "diagnostic" mode produces an SC CLOCK pulse during
shift register step S2. Th~s occurs independently of the state of the
programmable tlmer 160.
Program jump as well as increment instructions are recognized
during "diagnostic" mode operation. rf a program jump is required from
a particular program Step Number, the sequence control logic 152 compris-
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ing the upper decoding memory array 214, the "jump to" memory matrix
201, and the AND-OR select gates (e.g. 191) shown in FIG. 6A causes the
jump to occur upon receipt of an SC CLOCK pulse.
Alternative Controller Embodiment
Referring now to FIG. ll, an alternative controller archi-
tecture is generally depicted in block diagram form. The FIG. 11 structure
is more generalized, and ~s intended to provide greater flexib~lity in
programming for various applications, For convenlence, the FIG. 11 em-
bodiment ~s described below in terms of how it differs from the previous
embodiment. It will be appreciated that many aspects are substantially
the same, and these aspects are generally not mentioned. There are two
primary differences compared to the previous embodiment: First, the way
in which the program jumps and variable times are stored is altered. The
memory locations for a particular program Step Number have either a jump
address, or a new variable time, 6ut not both, While this requires tWQ
Step Number memory locat~ons to e~fect a program jump to a Step Number
which has a non-zero time duration, added flexibility is achieved. Second,
the various separate memories employed to store the jump conditions and
the variable time conditions are combined into a more general purpose
structure. For each program Step for which a functional-result such as
a jump or a time duration may vary from one execution to the next depending
upon conditional inputs, a unique "multiple condition code" is assigned.
In FIG. ll, the programmable timer 160 of FIGS. 4 and 8 and the
program sequence counter 150 of FIGS. 4 and 6A have the same general
structure and function as before. A difference is that the present inputs
of the programmable timer 160 and the program sequence counter 150 are both
connected to a common six-bit data bus 502. This sharing of the bus 502
is possible because, upon the entering of a new program Step, modified
master control logic 180' directs either a SET PT signal to the programmable
timer 160 to cause the programmable timer to load in a new time, or a LOAD
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SC signal to the program sequence counter 150, but not both. The LOAD
SC signal is equivalent to a logic "high" on the "enable preset" line
199 extending from the "jump to" memory matrix 201 of FIG. 6~.
~n the memory structure of FIG. 11, a sequence counter decoder
504 corresponds directly with the lower decoding memory array 216 of
FIG. 6B. Each horizontal row of the decoder 504 may be viewed as a NAND
gate, and one of the decoder 504 output lines 505 goes "low" in response
to each partfcular program Step. In FIG. 11, the particular programming
is not shown and the heavy black dots are thus omitted.
An information memory array 506 is connected to the decoder
504 output lines 505. Each vertical row of the array 506 may be viewed
as a low-activated OR gate. The information array 506 comprises four
separate sections: a multiple condition coder 508 having four output
lines supplying a four-bit data bus 509, a jump/time table 510 supplying
the data bus 502, a jump/time control bit section 512, and an output
section 514. Compared to the previous embodiment, the multiple condition
coder 508, the jump/time table 510, and the jump/time control bit section
512 are generally new; and the output section 514 corresponds directly
with the information memory array 218 of FIG. 6B.
The programmfng of the multiple condition coder 508 is such that
a unique code is assigned to each program Step for which a functional re-
sult may vary from one execution of the program to the next. Examples
of such program Steps from the particular program sequences of FIG, 5 are
Step Nos. 2, 15 and 30, where jumps may occur conditioned on user cycle
selection inputs; and Step Nos. 6, 21 and 38, where the time duration is
conditioned on user time select~on fnputs. For program Steps not requir-
ing a multiple conditfon code, there fs no entry in the multiple con-
dition coder 508.
The jump/time table 510 has an entry for each program Step
which fs not assigned a multiple condition code. The table 510 entries
are either unconditional iump addresses or unconditional step time dura-
tions.
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9D-HL-13374-S~mcoe
The jump/time control bit section 512 has a single bit for
each Step, the single bit indicating whether the jump/time table 510
entry is a time or a ~ump address. The output of the jump/time control
bit section 512 is received by the modified master control logic 180',
which in response generates either a SET PT signal or a LOAD SC signal
at the appropriate time.
The FIG. 11 structure also has a condition decoder 516 which
includes ~o sections: an input decoder section 518, and a multiple
condition decoder section 520. The input decoder section 518 receives
external inputs such as the "user cycle selection," the "user soak time
select," the "user wash time select," and the "user spin dry t~me select."
For added flexibility, the input decoder section 518 may receive internally-
generated inputs which can affect program execution. One example is an
input from the "full tub" clrcuitry. The multiple condition decoder section
520 receives the multiple condition codes carried by the four-bit bus 509
from the multiple condition coder section 508. The multiple condition
decoder section 520 has multiple entries for each particular multiple
condition code, there being one entry for each possible condition. How-
ever, due to the input decoder section 51B, only one of the multiple entries
for each multiple condition code is fully decoded at a time. Each hori-
zontal row of the condition decoder 516 may be viewed as a NAND gate, and
only one of the decoder 516 output lines 521 goes "low," at a time in res-
ponse to a decoded condition.
An information memory array connected to the horizontal output
lines 521 of the condition decoder 516 compr~ses another jump/time table
522. The table 522 entries are either jump addresses or step time durations,
to be directed along the six-bit data bus 502 to either the programmable
timer 160 or the program sequence counter 150. Although both of the jumpt
time tables 510 and 520 supply the same data bus 502, no conflict arises
because only one of the tables has an entry for each particular program
Step.
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The condition decoder 516 and the jump/time table 522 together
contain all the programming inforrnation which was scattered about a num-
ber of different memories in the previous embodiment. Specifically, the
information in the upper decoding array 214 and the "jump to" matrix 201
(FIG. 6A), and the time tables 298, 300, 302 and 290 (FIG. 8) is included.
The result is a highly flexible structure.
In the operation of the FIG. 11 structure, whenever the program-
mable time^ 160 times out and generates a COUNT REACHED signal, the master
control logic 180' increments the program sequence counter 150. The new
Step Number is decoded by the sequence counter decoder 504, and one of the
output lines 507 goes low.
If the new Step does not have a multiple condition code, then
the information in the jump/time table section 510 is directed for loading
into either the programmable timer 160 or the program sequence counter 150,
but not both, depending upon the entry in the jump/time control bit section
512. If a time is loaded, the controller remains in the Step until the
programmable time 160 times out. If a jump address is loaded, the sequence
counter 150 jumps to the new Step, which is immediately decoded by the
sequence counter decoder 504 to begin the process again.
If, on the other hand, the new Step does have a multiple con-
dition code, then the multiple condition coder 508 outputs a code along
the bus 509 to the multiple condition decoder section 520. One output
line 521 of the multiple condition decoder 516 goes low, and the infor-
mation in the jump/time table 522 is directed to either the programmable
timer 160 or the program sequence counter 150, but not both, depending
upon the entry in the ~ump/time control bit section 512.
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CONCLUSION
It will be apparent, therefore, that the foregoing descr~bes
a versatlle electronic sequence controller concept and two embodiments
thereof. While certain details of the first embodiment disclosed pertain
closely to the particular application, namely a controller for a domestic
clothes washing machine, it will be further apparent that the overall
approach and concept of the invention is much more general. It is realized
that modifications and changes will occur to those skilled in the art. It
is therefore to be understood that the appended claims are intended to
cover all such modifications and changes as fall within the true spirit
and scope of the invention.
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