Note: Descriptions are shown in the official language in which they were submitted.
This application is a division of our Canadian patent application
Serial No. 272,405 filed February 23, 1977.
This invention relates to a modulator for use in a single side-band
frequency division multiplexed (SSB-FDM) communication system for carrying out
conversion between a plurality of baseband channel signals, each having a
predetermined band-width, and an SSB-FDM signal.
In a sophisticated communication system of the type specified, the
conversion is carried out by the use of analog modulator, demodulator, and
band-pass filters. Recent developments in integrated circuit techniques and
digital signal processing have enabled digital conversion to be resorted to.
The digital conversion renders the system compact and economical, facilitates
manufacture and maintenance of the systems, and raises the performance and
the uniformity of operation characteristics. Besides the enumerated merits,
the digital conversion makes it readily possible to carry out connection bet-
ween a time division multiplexed (TDM) digital communication network and an
FDM analog communication network. The compactness and the cost of manufacture
of a system for digital conversion, however, are dependent on the frequency or
rate of multiplication to be carried out in the system per unit time.
An example of the systems of the digital conversion type is dis-
closed in an article contributed by M. G. Bellanger and J. L. Daguet to "IEEE
Transactions on Communications," Vol. COM-22, No. 9 (September 1974), pp.
1199-1205, under the title of "TDM-FDM Transmultiplexer; Digital Polyphase and
FET," particularly with reference to Figure 8 of the article. In the dis-
closed system, input sample sequences are converted to sequences of complex
samples. The complex samples are supplied to an inverse discrete Fourier
transform (IDFT) processor having N pairs of input terminals for the complex
samples and 2N ouput terminals for real signals. The real signals are sup-
plied to 2N real filters, whose output signals are converted into an output
-- 1 --
l~.lS~4
SSB-FDM signal by a delay circuit. Inasmuch as the input sample sequences
are converted to complex signals before the IDFT processing, the disclosed
system has to carry out multiplication at a considerable rate, gives rise to
accumulation of errors, is bulky, and has a slow speed of operation.
It is therefore an object of the present invention to provide a
modulator for use in a digital SSB-FDM communication system wherein use of
complex signals is avoided as far as possible.
An SSB-FDM communication system in which the invention is used is
derived from a fundamental complex band-pass digital filter bank concept later
described with reference to a few figures of the accompanying drawing and by
a filter breakdown process which is described in the above-referenced Bellanger
et al article and adapted to complex band-pass digital filters of the bank as
will be clarified hereunder with reference to several figures of the accom-
panying drawîng.
In accordance with a broad aspect of this invention, there is provid-
ed a modulator for modulating input sample sequences of real samples derived
with a first sampling frequency fs from baseband channel signals, respectively,
of a plurality of baseband channels, N in number, into a real single side-band
frequency division multiplexed sequence of samples corresponding to said real
samples and sampled at a second sampling frequency equal to Nfs, said baseband
channels including a predetermined number of dummy baseband channels, said
predetermined number being less than N, each of said baseband signals having
a bandwidth equal at most to fs/2, said modulator comprising: means for sub-
jecting said sample sequences to offset discrete Fourier transform to convert
said sample sequences into complex sample sequences, N in number; complex band-
pass digital filter means for digitally filtering said complex sample sequences
into filter output signals, said digital filter means being mathematically
derived from a complex filter operable at said second sampling frequency, means
-- 2 --
l~.lS~
for digitally processing said filter output signals into a time division
multiplexed signal with said second sampling frequency; and means for convert-
ing said time division multiplexed signal into said single side-band frequency
division multiplexed sequence of samples.
The invention will now be further described in conjunction with the
accompanying drawings, in which:
Figure 1 is a block diagram of a first complex band-pass filter bank;
Figure 2 is a block diagram of a second complex band-pass filter
bank;
Figure 3 shows frequency spectra of several signals appearing in the
first and second filter banks;
Figure 4 is a block diagram of a fast real low-pass filter;
Figure 5 is a block diagram of a fast real low-pass filter compris-
ing a plurality of slow real low-pass filters;
Figure 6 shows impulse responses of the filter illustrated in Figure
4 and the filters depicted in Figure 5;
Figure 7 is a block diagram of an SSB-FDM communication system
according to a first embodiment of the present invention;
Figure 8 is a block diagram of a spectrum reverser to be used, if
desired, in an SSB-FDM communication system according to this invention;
Figure 9 is a block diagram of a minus-one multiplier used in the
spectrum reverser;
Figure 10 is a block diagram of a real band-pass filter;
Figure 11 is a block diagram of a complex band-pass filter which
provides a recursive section of slow complex band-pass filters used in com-
munication system according to this invention;
Figure 12 is a block diagram of a complex band-pass filter which
i~ lS~$~
provides a non-recursive section of the slow complex band-pass filters;
Figure 13 is a block diagram of an SSB^FDM communication system
according to a second embodiment of this invention;
Figure 14 is a block diagram of a post-processor used in a communi-
cation system according to the second embodiment;
Figure 15 is a block diagram of a pre-processor used in a communi-
cation system according to the second embodiment;
Figure 16 is a block diagram of a complex multiplier used in the
post-processor and pre-processor;
Figure 17 is a block diagram of an SSB-FDM communication system
according to a third embodiment of this invention; and
Figure 18 is a time chart of several signals used in a communication
system according to the third embodiment.
It is to be understood that the complete system is disclosed here
for convenience but is claimed in the aforementioned parent application Serial
No. 272,405.
It is to be understood at first that a sequence of samples means,
in the following, a sequence of digital code words. This does not restrict
the generality of the present invention because it is readily possible to con-
vert the digital code word sequence into a sequence of analog samples, namely,a pulse amplitude modulated ~PAM) signal, by a digital-to-analog converter and
further into a continuous analog signal by causing the analog sample sequence
to pass through a filter of pertinent characteristics. Furthermore, it is
possible to convert a continuous analog signal into a sequence of digital
samples by sampling the former into a PAM signal and thereafter subjecting
the PAM signal to analog-to-digital conversion. Also, the word "slow" refers,
in the following, to a slow sampling rate of a first sampling frequency, f5,
while the word "fast" relates to a fast sampling rate of a second sampling
l~.lS~3~;;4
frequency Nf where N represents the numher of separate channels multiplexed
into a multiplexed signal. The frequencies are in Hertz. The separate chan-
nels are numbered from O to N-l. The channel numbers are generally indentifi-
ed by a symbol k. For simplicity of description, a slow sampling period,
namely, an inverse quantity of the first sampling frequency f will be re-
presented by T. On the other hand, let Z represent an operator for advancing
a sample sequence by one fast sampling period of the second sampling fre-
quency Nfs. The operator Z is defined by:
Z = exp(j2~f/tNfs]) = exp(j2~fT/N),
where f represents frequencies of the input signal components contained in the
sample sequence. Incidentally, n represents indices of sampling instants.
Referring to Figures 1 and 3 with reference to Figure 2 deferred for
a short while, a first complex band-pass digital filter bank will be described
for a better understanding of this invention. The filter bank comprises a
plurality of input terminals 20k, namely, 200, 201, 202, ...., and 20N 1' N
being four in the example being illustrated, for input baseband sample sequen-
cey xk(nT) of k-th or zeroth through (N-l)-th baseband channels. The first
sampling frequency fs is naturally selected so that each of the baseband chan-
nel signals has a bandwidth equal to or narrower than fS/2. As exemplified
in Figure 3 at (A), each of the sample sequences has a frequency spectrum of
a period of the first sampling frequency f5. The filter bank further compri-
ses an output terminal 21 for an output sample sequence y(nT/N), to be pre-
sently described, and a spectrum reverser unit 22 comprising, in turn, spect-
rum reversers 222 and 223, described later, for converting the input baseband
sample sequences of predetermined one or ones of the channels, such as the
N/2-th through (N-l~-th baseband channels, into spectrum-reversed sample
sequences xk'(nT), each having a reversed frequency spectrum shown in Figure
3 at (B~, by multiplying the samples of each predetermined channel succes-
S~
sively by factors (-l)n. The filter bank still further comprises a plurality
of fast complex band-pass digital filters 23k, described later, for producing
complex filter output signals in response to the spectrum-reversed and un-
touched sample sequenceS and a conventional adder 24 for summing up the filter
output signals. Let the fast complex band-pass filters 23k have transfeT
functions Hk(Z) having passbands between kf and kf + f /2 as shown in Fig-
ure 3 at (C), (D), (E), and (F). Comparison of the frequency spectra depicted
at (A) through ~F) will readily reveal that the filter output signals, when
merely summed up, result in a sum signal which has a frequency spectrum de-
picted in Figure 3 at (G). That real part of the sum signal which is derived
when the adder 24 is connected to the fast complex band-pass filters 23k so
as to sum up only real parts of the filter output signals, has a frequency
spectrum shown in Figure 3 at (H) and is the output sample sequence of samples
sampled at the second sampling frequency Nfs from an SSB-FDM signal having a
bandwidth between 0 and NfS/2 into which the baseband channel signals are
SSB-FDM'ed. The output sample sequence, when subjected to digital_to-analog
conversion and to pass through an analog low-pass filter or an analog band-
pass filter having a passband between NfS/2 and Nfs (not shown), has frequency
spectra illustrated in Figure 3 at (I) and (J), respectively.
From the frequency spectra depicted in Figure 3 at (G) through (J),
it is seen that the samples of the respective baseband channel signals are
not arranged in the SSB-FDM signal in the order of the channel numbers k.
This, however, is not inconvenient in practice. If desire,d, the transfer
functions of the fast complex band-pass filters 23k may be interchanged so as
to arrange the samples in the order of the channel numbers k. The spectrum
reverser unit 22 is dispensed with when it is unnecessary for the samples
depicted at (I) or (J) to have one and the same frequency dependency. It will
also be seen that the number N of channels need not be an even number. On the
S~
other hand, it is to be pointed out here that the baseband channels should in-
clude at least one dummy baseband channel, such as that numbered 2 for the
frequency spectrum depicted at (I) or those numbered 0 and 2 for the spectrum
in (J), so as to enable the above-mentioned analog low-pass or band-pass fil-
ter to have not a sufficiently sharp cutoff characteristic.
Referring now to Figures 2 and 3, a second complex band-pass digital
filter bank comprises an input terminal 25 for an input SSB-FDM sample se-
quence y(nT/N) produced in the manner described herinabove and depicted in
Figure 3 again at (K), and a plurality of output terminals 26k for output
baseband sample sequences which are reproductions of the sample sequences
xk(nT~ of the respective baseband channels for the first filter bank. The
second filter bank further comprises a plurality of fast complex band-pass
digital filters 27k, similar to the filters 23k of the first filter bank, for
producing those complex filter output signals in response to the input SSB-FDM
sample sequence, of which real parts are discrete samples of the respective
baseband channel signals as exemplified in Figure 3 at (L) and ~M), a sampler
28 symbolized by switches operable at the first sampling frequency fs for
sampling the discrete samples into successive samples shown in Figure 3 at (N)
and (0), and a spectrum reverser unit 29 comprising, in turn, spectrum rever-
sers 292 and 293 for reversing the frequency spectra of the successive samples
of the above-mentioned predetermined channels back into frequency spectra of
the baseband channel signal examples exemplified in Figure 3 at (P~.
Referring to Figures 4 and 6 with reference to Figure 5 postponed
for the time being, a fast real low-pass filter of a transfer function GtZ)
and of a bandwidth fs/4 will be described in order to derive the above-mentio-
ned fast complex band-pass filters 23k and 27k of the transfer functions Hk(Z)
and of a common bandwidth f ~2. According to the filter breakdown process
described in the above-cited ~ellanger et al. article and to those frequency
_ 7
shifts of (4k + l)fs/4 which are the center frequencies of passbands of the
respective band-pass filters 23k and 27k,
Hk(Z) = G(exp~j2~(f - ~4k ~ l~fS/4)TtN~)
= G(Zexp[-j2~(4k + 1)/(4N)~). (1)
The low-pass filter comprises an input terminal 30 for an input signal sampled
by the use of the first sampling frequency fs, an output terminal 31 for an
output signal sampled with the second sampling frequency Nfs, and a digital
filter 32 having the transfer function G(Z). Let an impulse response, namely,
the output signal produced at the output terminal 31 when an impulse is sup^
plied to the input terminal 30 as the input signal, be as depicted in Figure
6 at (A). It is to be pointed out here that a filter is mathematically com-
pletely equivalent to another when the two have one and same impulse response.
Referring now to Figures 5 and 6, a composite fast real low-pass
filter comprises an input terminal 30 and an output terminal 31, both being
equivalents of the corresponding terminals 30 and 31 described with reference
to Figure 4. The composite filter further comprises a plurality of slow real
low-pass filters 33i, N in number, of transfer functions Gi(Z ), where i re-
presents input or output points specified by integers between 0 and N-l as is
the case with the channel numbers k. Let impulse responses of the filters 33i
be composed of samples sampled at the first sampling frequency fs from impulse
responses of ZiG(Z), namely, those which are identical in outline to the im-
pulse response shown in Figure 6 at (A) and have phases advanced by i fast
sampling period or periods iTtN, as depicted in Figure 6 ~t (B), (C), (D),
and (E). The composite filter still further comprises a parallel-to-series
converter 34 for time division multiplexing output signals of the respective
filters 33i by delaying the output signals by i fast sampling period or
periods. The time division multiplexed signal is supplied to the output
terminal 31. The fast real low-pass filter described with reference to Fig-
~.15~;4
ure 4 is now equivalent to the composite fast real low-pass filter comprising
the slow real low-pass filters 33i. It is clear that:
G(Z) = ~ Z-iG (ZN)
i=0 (2)
from the structure of the composite filter. By substituting Equation (2) in-
to Equation (1),
N-l
k(Z~ i~0 (Zexp~-j2~(4k + 1)/(4N)])
x Gi ( zNexp E ( - j2~(4k + l)N/(4N)~)
= ~ z ieXp[j2~(4k + l)i/(4N)~ Gi(-jZN) (3~
where Gi(-jZN) represents transfer functions derived for slow complex band-
pass filters of center frequencies f5/4 described later, by substituting
-jZ for Z in the transfer functions Gi(ZN) of the slow real low-pass fil-
ters 33i.
It is now possible to derive several formulae representative of or
equivalent to operation of the first filter bank described with reference to
Figures 1 and 3. Inasmuch as a Z transform Y(Z) of the output SSB-FDM sample
sequence is the real part of the sum signal, the Z transform is given by:
N-l N
Y(Z) = Re[ Hk(Z)Xk(Z )]~ (4)
where Xk(ZN) represents Z transforms of the input baseband sample sequences
supplied to the fast complex band-pass filters 23k with the frequency spec-
trum or spectra reversed as the case may be. Substitution of Equation (3)
into Equation (4) gives:
Y(Z) = Re[ ~ Z iGi(-jZN)Ai(Z )~, (5)
1~.15~
where Ai(ZN) represents output-point complex sample sequence defined by:
Ai(Z ) = ~ Xk(ZN)exp(j2~!4k + l~ 4N,). (6)
The operation in Equation (6) for the Z transforms Xk(ZN) will herein be cal-
led inverse offset discrete Fourier transform ~IODFT) because of its similar-
ity to IDFT (inverse discrete Fourier transform). More pa~ticularly, IODFT is
equal to IDFT accompanying multiplication by phase offset factors exp(j2~i/
r4Nl) as will be discussed hereunder.
As for the second filter bank illustrated with reference to Figures
2 and 3, Z transforms Xk(Z) of first real sample sequences supplied from the
fast complex band-pass filter 27k to the sampler 28 are:
Xk(Z) = Re[Y(Z)Hk(Z)],
where Y(Z) represents a Z transform of an input SSB-FDM sample sequence sup-
plied to the input terminal 25. Inasmuch as the transfer functions Hk(Z) are
given by Equation (3) and inasmuch as it is possible to decompose the input
sample sequence into a plurality of constituent sample sequences Yq(ZN)~ N in
number, sampled from baseband channel signals, respectively, at sampling in-
stants spaced by the slow sampling period T with successive delays Z q, namely,
q fast sampling period or periods, the Z transforms are given by:
Xk(Z) = R~[ ~ Z qYq(Z )Hk(Z)-
= Re~ ~ exp(j2~14k + l i/~4N,)Gi(-jZ ) ~ Z Pyp i(ZN)],
where p = q I i. When it is presumed that the sampler 28 samples the first
real sample sequence simultaneously at a sampling instant specified by p = N-l,
Z transforms Xk(ZN) of second real sample sequences produced by the sampler 28
are:
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S~?fi ~
Xk(ZN) = Ret ~ exp(j2~4k 1 l]i/[4N~)Gi(-jZN)YN 1 i(Z )]
= ~ ([Bi(Z ) - jBN i*(Z )~/2)exp(j2~4k + l]i/~4N~ 7)
where Bi(ZN) is defined by:
Bi(Z ) = Gi(-jz )YN 1 i(Z )'
herein called input-point complex sample sequences, and Bi*(Z ) represents
conjugate complex quantities of the input-point sample sequences. Operation
in Equation (7) for the input-point complex sample sequences is again called
IODFT.
It is now understood that the first and second filter banks are
realized by circuits for carrying out calculation of Equations (5) and (7).
More particularly, input baseband sample sequences, N in number, are obtained
for conversion thereof to an output SSB-FDM sample sequence by sampling base-
band channel signals at the first sampling frequency f5. With the samples of
predetermined ones of baseband channels multiplied by (-l)n if desired, the
baseband sample sequences are subjected to IODFT for producing output-point
complex sample sequences Ai(Z ) in accordance with Equation (6). The output-
point complex sample sequences are multiplied by transfer functions Gi(-jZN)
and thereby turned into filter output signals. After subjected to delays of
predetermined integral multiples of one fast sampling period TJN, the filter
output signals are summed up into the output SSB-FDM sample sequence. On the
other hand, an input SSB-FDM sample sequence is decomposed into those con-
stituent sample sequences, N in number, which are picked out of baseband
sample sequences at sampling instants spaced by the slow sampling period with
successive delays of predetermined integral multiples of one fast sampling
period. The constituent sample sequences are multiplied by transfer functions
Gi(-jZ ) for der;ving input-point complex sample sequences Bi(Z ). The input-
- 11 -
5~$4
point complex sample sequences are now subjected to IOD~T for producing the
above-mentioned second real sample sequences according to Equation ~7). The
second real sample sequences, when those of the predetermined baseband chan-
nels are multiplied by (-l)n, become reproductions of the baseband sample
sequences. Incidentally, conversion between the baseband channel signals and
the SSB-FDM sample sequence includes the sampling processes and consequently
the amplitude modulation and demodulation processes.
Turning now to Figure 7, an SSB-FDM digital communication system
according to a first embodiment of this invention comprises a modulator 40A
and a demodulator 40B. The modulator 40A comprises, in turn, a plurality of
input terminals 20k, an output terminal 21, a spectrum reverser unit 22 for
producing the above-mentioned input baseband sample sequences Xk~ZN), and a
parallel-to-series converter 34, all described with reference to Figures 1
and 5. The modulator 40A further comprises an IODFT processor 41, described
shortly hereunder, having complex input terminals Xk and complex output ter-
minals Ai. Each complex terminal consists of a pair of terminals for the
real and imaginary parts of a signal. Supplied with input baseband sample
sequences at the real ones of the complex input terminals Xk, the IODFT pro-
cessor 41 carries out IODFT of Equation (6) to produce output-point complex
sample sequences Ai(Z ) at the complex output terminals Ai. The complex
sample sequences are supplied to a slow complex band-pass filter unit 42
comprising a plurality of slow complex band-pass filters 42k having transfer
functions Gi( jZN) for producing slow filter output sign~ls which correspond
to Gi(-jZN)Ai(ZN) in Equation (5). The real parts of the slow filter output
signals are supplied to delay circuits 44k of the parallel-to-series conver-
ter 34 to be multiplied by Z (delayed by i fast sampling period or periods
iT/N), respectively. The delayed signals are summed up by the adder 24 and
delivered to the output terminal 21 as an output SSB-FDM sample sequence.
- 12 -
~s~
The adder 24 and tlle delay circuits 44k serve as the parallel-to-series con-
verter 34.
Further referring to Figure 7, the demodulator 40B comprises an in-
put terminal 25, a plurality of output terminals 26k, a sampler 28, and a
spectrum reverser unit 29, described with reference to Figure 2. After mul-
tiplied by Z at delay circuits 46k, an input SSB-FDM sample sequence is
broken down by the sampler 28 into the respective constituent sample sequen-
ces YN 1 i(ZN)- The delay circuits 46k and the sampler 28 serve as a series-
to-parallel converter 47. The constituent sample sequences are supplied to
a real input terminal member of a slow complex band-pass filter unit 48 hav-
ing transfer functions Gi(-jZ ), namely, to real input terminals of slow
complex band-pass filters 48k in the example being illustrated, and thereby
turned into input-point complex sample sequences Bi(ZN), which are now sup-
plied to complex input terminals Bi of an IODFT processor 49 for carrying out
IODFT of Equation (7). Real parts of the IODFT'ed signals produced at com-
plex output terminals Xk of the IODFT processor 49 are converted by the spec-
trum reverser unit 29 into reproductions of the baseband sample sequences.
In connection with the SSB-FDM communication system described with
reference to Figure 7, it should be noted here that a broken-line connection
between the modulator 40A and demodulator 40B may include the above-mentioned
digital-to-analog converter, analog filters, and analog-to-digital converter.
Also, the IODFT processor 41 or 49 is realized by a combination of multipli-
ers and adders for calculating Equation (6) or (7). When it is possible to
give the number of baseband channels N by a product of prime numbers, the
number of multipliers is drastically reduced by the use of fast Fourier
transform (FFT) algorithm with decimation in frequency or in time. The FFT
algorithm is described in many publications, such as, for example, in Chap-
ters 6 and 10 of a book "Theory and Application of Digital Signal Processing"
- 13 -
~.lS~
written by L.R. Rabiner and B. Gold and published 1975 by Prentice-Hall, U.S.A.
Inasmuch as the signals supplied to the IODFT processor 41 of the modulator
40A or derived from the IODFT processor 49 of the demodulator 40B are only
real signals, it is possible to reduce the number of calculation elements of
the processors 41 and 49 to a half as compared with a processor of the type
for complex input and output signals.
Referring to Figure 8, a spectrum reverser 22k or 29k has a sample
sequence input terminal 50, an output terminal 51, and a timing signal input
terminal 52. When the samples of each sequence are either given by two's
complements or converted into two's complements before application thereof to
the sample sequence input terminal 50, the spectrum reverser 22k or 29k com-
prises a two's complement circuit 53, described hereunder, connected to the
sample sequence input terminzl 50 and a selector or switch 54 responsive to
the timing signal for selectively supplying the samples untouched or bypassed
and the two's complements of the samples to the output terminal 51. The tim-
ing signal is representative of even or odd frames of a sampling pulse se-
quence of the first sampling frequency fs. When the samples of each sequence
are given by signed magnitudes, a spectrum reverser 22k or 29k may be an in-
verter responsive to a timing signal for inverting the sign bits of the sam-
ples at every other sampling instant.
Referring to Pigure 9, a two's complement circuit 53 has a samplesequence input terminal 50A, an output terminal 51A, and a timing signal in-
put terminal 52A. When the samples of each sequence are given by two's com-
plements, the two's complement circuit 53 is a minus-one multiplier which
comprises an inverter 56 connected to the sample sequence input terminal 50A,
an OR gate 57 connected to the timing signal input terminal 52A, a half adder
having input terminals connected to the inverter 56 and the OR gate 57 and an
output terminal connected to the circuit output terminal 51A, and a one-bit
- 14 -
l~.i5r~
delay circuit 59 interposed between a carry output terminal of the half adder
and the OR gate 57. With a logic "1" value, the timing signal specifies the
least significant digit of each sample supplied to the input terminal 50A.
Whcn each sample is supplied to the input terminal 50A serially with the least
significant digit supplied first, the inverter 56 supplies the half adder 58
with a one's complement of the sample, namely, the sample with all bits in-
verted. Only when the bit supplied to the input terminal 50A is the least
significant digit of the sample, is the half adder 58 also supplied with a
logic "1" signal through the OR gate 57 to produce a two's complement of the
sample.
Turning now to Figures 10 through 12, description will be made of
slow complex band-pass filters 42k and 48k together with the filter breakdown
process adapted to the present case. Let the result of design of a fast real
filter satisfying the in-band and cross-talk rejection ratio specifications
be a transfer function G(Z) which has M poles and M zeroes and is accordingly
given by:
G(Z) = ~ ~(l - amZ )Em/(l - bmZ 1)~,
m=l
where am, bm, and Em represent constants determined by the specifications. By
the use of an identity:
(1 - X) = (1 + x + x2 + + xN-l) (1 - xN) l,
where N represents the number of slow real band-pass filters into which the
fast real Mth-order filter is broken down, the transfer funtion is rewritten
into:
G(Z) = tl + ~ c N(Z~N)m]/ ~ (1 - b NZ-N)
m=l m=l
1 Z Cm o CmN+i( ) ~/m-l( m )~ (8)
where cmN represents constants given by rational formulae of the above-men-
- 15 -
tioned constants a , b , and E and the number N. From comparison of Equation
(8) with Equation ~2), the transfer functions Gi~ZN) of the slow real band-
pass filters are:
Go~Z~ 1 + cmN(Z N)m~ bm Z ) (9)
m=l m=l
and for 1 < i_ N-l:
Gi(z ) = ~ cmN+i~Z ) ]/ ~1 ~1 - bm Z )' (10)
wherein it is generally possible to rewrite each of the denominators into a
product of one or more quadrature formulae (a linear formula being a specific
case of a quadrature formula). The transfer functions Gi(-jZN) of the slow
complex band-pass filters 42k and 48k are obtained by substituting _jZN for zN
in the right-hand sides of Equations (9) and (10).
Referring more specifically to Figure 10, a real filter comprises an
input terminal 60, an output terminal 61, an adder 62 connected to the input
terminal 60 to supply a filter output signal to the output terminal 61, a
first delay circuit 631 for delaying the filter output signal by one slow sam-
pling period T, a second delay circuit 632 for delaying the delayed filter
output signal further by one slow sampling period, a first multiplier 641 for
multiplying the one-sample delayed signal by a factor -bl to supply the multi-
plied signal to the adder 62, and a second multiplier 642 for multiplying the
two-sample delayed signal by another factor -b2 to supply the product signal
to the adder 62. The filter has a transfer function F(ZN) given by:
F(ZN) = (1 + b z-N + b2z
being that portion of the transfer functions given by Equations (9~ and (10
in which the denominator is a quadrature formula and the numerator is equal
to unity.
Referring to Figure 11 in particular, a complex filteT comprises
similar elements designated by like reference numerals without primes and with
- 16 -
S~ 3`~
primes as in Figure 10. The elements indicated by reference numerals with
primes are for the imaginary part of the filter input signal. It is to be
noted here that the first multipliers 641 and 641' supply the product signals
to the adders 62' and 62, respectively, and that the second multipliers 642
and 642' are for multiplying the two-sample delayed imaginary and real filter
output signals by a common factor b2 rather than by a factor -b2 as was the
case with the corresponding element described with reference to Figure lO.
The filter has a transfer function F(-jZN), namely:
F( iZ ) ( i l 2
It is now understood that the illustrated filter realizes at least partly the
denominator of the transfer functions Go(-jZN) and Gi(-jZ ) for 1 < i_N-l,
namely provides at least partly the recursive section of the slow complex
band-pass filters 4Zk and 48k.
Referring now to Figure 12 more in detail, a non-recursive section
of the slow complex band-pass filters 42k and 48k, namely, the numerator of
the transfer functions Go(~jZ ) and Gi(-jZ ) for l ~ i~ N-l, is realized in
the so-called direct form by the depicted circuit which comprises a pair of
input terminals 65 and 65' for the real and imaginary parts of a complex fil-
ter input signal, a pair of output terminals 66 and 66' for the real and imag-
inary parts of a complex ~ilter output signal, a pair of M-input adders 67 and
67' having output terminals connected to the respective output terminals 66
and 66', and a pair of delay circuits 68 and 68' connected to the respective
input terminals 65 and 65'. Each of the delay circuits 68 and 68' has a plu-
rality of taps 68m or 68m'. The real and imaginary filter input signals are
successively delayed by m slow sampling period or periods mT and produced at
the taps 68m and 68m', respectively. A plurality of multipliers 69m for mul-
tiplying the successively delayed real signals by the factors cmN~i of Equa-
tions (9~ and (10) arc connected to the respective tap 68m, where C0N is equal
1~ 15~i4
to unity. A plurality of similar multipliers 69m' are for the successively
delayed imaginary signals. Product signals derived from even-numbered ones
of the multipliers 69m and 69m' are supplied to the adder 67, while those
from odd-numbered ones, to the other adder 67'.
From Figures 10 through 12, it will be understood that the slow com-
plex band-pass filters 42k and 48k are realized by cascade connections of the
circuits illustrated with reference to Figures 11 and 12. When only one of
the real and imaginary parts of the filter input or output signal is necessary,
it is possible to dispense with circuit elements for the unnecessary one of
the real and imaginary parts to simplify the circuitry. Furthermore, it is
possible to expand that section of the filter 42k and 48k into filters of the
direct form which is for the denominators of the right-hand sides of Equations
(9) and (10~ and to realize, by expanding the denominators and numerators in
Equations (9) and (10) into polynomials of Z, those sections of the filters
42k and 48k in the so-called canonical form which are related to the denomin-
ators and numerators. With a filter of the canonical form, the number of the
delay circuits is reduced to a half. It is also possible to factorize the
numerator into quadrature (linear inclusive) formulae and to realize each of
the slow complex band-pass filters 42k and 48k by a cascade connection of bi-
quad filters.
Turning now to Figure 13, a digital SSB-FDM communication system
according to a second embodiment of this invention comprises similar parts
designated by like reference numerals as in Figure 7. Instead of the IODFT
processor 41 described with reference to Figure 7, the modulator 40A comprises
an IDFT processor 71 and a post-processor 72 which will shortly be described.
Likewise, the demodulator 40B comprises a pre-processor 73 and an IDFT proces-
sor 74. In this connection, it is to be noted that Equations (6) and (7) may
be rewritten as:
- 1~ --
Ai(Z ) = exp~j2~i/L4Ni) ~ Xk(ZNlexp(j2~ki/N) (6')
and Xk(ZN) = ~ Ci(Z )exp(j2~ki/N), (7')
where:
Ci(Z ) = [BiZN) - jBN-i*(ZN)~exp(j2~i/L4N~)/2. (11)
In other words, IODFT is carried out by the conventional IDFT processing ac-
companying multiplication by phase offset factors exp(j2~ 4N7) which are in-
dependent of k but dependent on i. The IDFT processor 71 or 74 for carrying
out the known IDFT processing.
Referring to Figure 14, the post-processor 72 is for carrying out
multiplication by the phase offset factors exp(j2~ 4N~) and therefore com-
prises, in principle, multipliers, N in number. The depicted post-processor
72 has a plurality of input terminal pairs 750~ 750'~ 751~ 751 " ' 75N/2 1'
75N/2 1 " 75N/2~ and 75N/2 " N/2-1 pairs in number, and a plurality of output
terminal pairs 760, 760', 761, 761'J ..., 76N/2-l~ 76N/2-1 ' 76N/2' 76N/2 '
76N/2+1, 76N/2+1', ..., 76N 1' and 76N 1 " N pairs in number. The terminals
numbered without primes and with primes are for the real and imaginary parts,
respectively, of input and output signals. Inasmuch as the baseband sample
sequences Xk(Z ) are real signals, Equation:
AN i(Z ) = jAi*(z )
follows from Equation (6'), where Ai*(Z ) represents conjugate complex quanti-
ties of the input-point complex sample sequences Ai(Z ). It is therefore
possible, when the input-point complex sample sequences numbered from O to
N/2-1 are known, to derive other sequences numbered from ~2 to N-l. Use is,
however, made in the illustrated example of both signals Ao(Z ) and AN/2(ZN).
The zeroth real input terminal 750 is directly connected to the zeroth real
- 19 -
output terminal 760. Use is not made of the signals for the zeroth imaginary
input and output terminals 750' and 7~0' and for the N/2-th imaginary input
terminal 75N/2' The post processor 72 further comprises complex multipliers
781, ..., 78N/2 1' and 78N/2 for multiplying the first through N/2-th channel
signals by the phase offset factors exp(j2~/r4Nl), ..., exp(j2~LN/2~ 4N])~
and exp(j2~/4), respectively. It is now understood that the number of the
multipliers for the phase offset factors is reduced to N/2 in the depicted
example.
Referring to Figure 15, the pre-processor 73 is for calculating
Equation (11) and has a plurality of real and imaginary input terminals 800,
800'~ 801, 801 ~ ~ 8oN/2 1, 80N/2_1 , 80N/2~ 80N/2 ~ 80N/2+1~ 80N/2+1 ~
..., 80N 1' 80~ 1' and plurality of real and imaginary output terminals 810,
0 1 1 ' N/2-1' 81N/2_1 , 81N/2, 81N/2', 81 / 81
..., 81N 1' and 81N-l'. The zeroth real input terminal 800 is connected dir-
ectly to the zeroth real output terminal 810. Use is not made of the signals
for the zeroth imaginary input and output terminals 800' and 810' and for the
N/2-th imaginary output terminal 81N/2'. Inasmuch as:
CN i(Z ) = Ci*~Z )~
the subtraction Bi(ZN) -jBN i*(ZN) in Equation (11) is carried out by subtrac-
t r 821, 821 ~ ~ 82N/2-1' and 82N/2_1~ N-2 in number, connected as shown
to produce difference signals representative of the respective results of the
above-mentioned subtraction. The difference signals and the signals supplied
to the N/Z-th input terminals 80N/2 and 80N/2' are multiplied at multipliers
831, ..., 83N/2 1~ and 83N/2 by the phase offset factors exp(j2~/r4N~)/2,....
exp(j2~rN/2-11/~4N~)/2, and exp (j~/4)/2, respectively. Imaginary parts of
the signals produced from the respective multipliers 83k are multiplied at
minus-one multipliers 84N/2+1, ..., and 84N 1' described with reference to
Figure 9, and then delivered to the imaginary output terminals 81N/2+1', ....
- 20 -
1~ 15~4
and 81N 1 ~ respectively.
Referring to Figure 16, each of the complex multipliers 78k and 83k
comprises a pair of real and imaginary signal input terminals 85 and 5', real
and imaginary output terminals 86 and 86', and real and imaginary factor input
terminals 87 and 87' for Rerexp(j~i/;4N )~ and Imlexp(j2~ 4N )l or halves
thereof, respectively. The multiplier 78k or 83k further comprises real multi-
pliers 91, 92, 93, and 94, a real subtractor 96, and a real adder 97 connected
as shown. The real multipliers 91 through 94 may be those described with ref-
erence to Figures 10 and 11 of an article contributed under the title of "An
Approach to the Implementation of Digital Filters" by Leland B. Jackson et al.
to "IEEE Transactions on Audio and Electroacoustics." Vol. AU-16, No. 3
(September 1968~, pp. 413,421.
Referring finally to Figures 17 and 18, a digital SSB-FDM communi-
cation system according to a third embodiment of this invention is for serial-
ly processing the sample sequences by the use of circuit elements, each being
one or less than the number of the baseband channels in number for all base-
band channels, rather than processing the sequences in parallel as in the com-
munication systems according to the first and second embodiments. Similar
parts are designated by like reference numerals. In the example being illus-
trated, use is made of only one each of the modulator input terminal 20, out-
put terminal 21, spectrum reverser 22, demodulator input terminal 25, output
terminal 26, slow complex band-pass filter 42, and so forth.
In the modulator 40A depicted in Figure 17, baseband samples for the
baseband channels, N in number, are supplied to the single input terminal 20
as a time division multiplexed sequence shown in Figure 18 at (A) by the use
-of channel numbers CHk. With a first timing signal Tl supplied to the selec-
tor 54 illustrated with reference to Figure 8 to control the same, the single
spectrum reverser 22 is cyclically energized as symbolized in Figure 18 at (~)
~ t~
to reverse the frequency spectra of the baseband samples for the predetermined
baseband channels and to produce a sequence of the above-mentioned input base-
band samples Xk(Z ) in sequence as shown at ~C). Responsive to a second tim-
ing signal T2 of the slow sampling rate and to a cyclically varying sequence
of the phase offset factors exp(j2~i/L4Nl), the IODFT processor 41 produces a
sequence of IODFT'ed output-point complex samples Ai(ZN) depicted in Figure 18
at tD). The single slow complex band-pass filter 42 has a variable transfer
function which cyclically assumes the value Gi(-jZN) as shown in Figure 18 at
(E). More particularly, the factors bl, b2, and cmN are supplied to the fil-
ter sections exemplified in Figur~s 11 and 12 as sequences of slgnals T3 in
synchronism with the second timing signal T2. This time division multiplexed
use of a single filter is known in the art of digital signal processing, being
described, for example, in Chapter 9 of the above-cited book written by L. R.
Rabiner and B. Gold or in the above-referenced Jackson et al. article with
reference to Figures 12 and 13 thereof. Responsive to the IODFT'ed sample se-
quence, the slow complex band-pass filter 42 supplies the single output termi-
nal 21 with a sequence of real-part filter output signals Yi(Z) depicted in
Figure 18 at (F). The parallel-to-series converter 34 shown in Figures 7 and
13 as hardware is unnecessary in the example illustrated in Figure 17.
In the demodulator 40B also depicted in Figure 17, the input termi-
nal 25 is supplied with a sequence of those constituent samples Yi(Z), again
shown in Figure 18 at (G3, into which an input SSB-FDM sample sequence is de-
composed by the analog-to-digital converter included in t~e broken-line-con-
nection as pointed out hereinabove. As in the modulator 40A, the single slow
complex band-pass filter 48 has a transfer function Gi(-jZ ) varied cyclically
in a time division fashion illustrated in Figure 18 at (H) to produce a se-
quence of complex filter output signals Bi(ZN) depicted at (I). The filter
output signal sequence is processed by the IODFT processor 49. Only real
- 22 -
5~
parts Xk(Z ), shown in Figure 18 at (J), of the IODFT'ed signals are supplied
sequentially to the single spectrum reverser 29 and processed thereby in a
manner exemplified in Figure 18 at (K) to be supplied to the single output ter-
minal 26 as a sequence of time division multiplexed baseband samples shown at
~L). The series-to-parallel converter 47 is unnecessary.
In connection with the example of serially operable SSB-FDM communi-
cation systcms illustrated with reference to Figures 17 and 18, the number of
the circuit elements may be increased to ..., N/4, or N/2 in ccnsideration of
speeds of operation of the IODFT processors 41 and 49 and the single slow com-
plex band-pass filter 42 or 48. It is immaterial whether or not the number of
baseband channels is an integral multiple of 2, 4, ... Conversely, the real
and imaginary parts may be dealt with in a time division manner when the hard-
ware is operable at a sufficiently high speed. The IODFT processor 41 or 49
used in the serially operable SSB-FDM communication systems according to the
third embodiment may be changed to a cascade connection of a conventional IDFT
processor 71 or 74 and a post-processor 72 or a pre-processor 73 illustrated
with reference to Figures 13 through 15. An FFT processor suitable to time
division multiplexed operation of the IODFT processors 41 and 49 is described
as a pipeline-type FFT processor in the above-mentioned book written by L. R.
Rabiner and B. Gold. For time division multiplexed operation of the post-pro-
cessor 72 and pre-processor 73, the factor input terminals 87 and 87' describ-
ed with reference to Figure 16 should be cyclically supplied with the phase
offset factors exp(j2~ 4N]).
While a few preferred embodiments of this invention and several mod-
ifications thereof have thus far been described, it is to be understood that
two principal steps of IODFT and of slow cvmplex digital band-pass filtering
are carried out according to the preferred embodiments without that further
step of carrying out conversion between the baseband channel signals and the
~l.lS~
equivalent complex signals which is indispensable in the system disclosed in
the above-cited Bellanger et al. article. The reduction in the number of steps
facilitates design, manufacture~ and maintenance of the communication system
and reduces, in turn, accumulation during signal processing of errors and the
time required for carrying out the conversion between the baseband channel sig-
nals and the SSB-FDM signal.
In order to illustrate the reduction achieved by this invention in
the rate of multiplication, let 60-channel baseband channel signals, each hav-
ing a bandwidth between 0.3 and 3.4 kHz, be converted to an SSB-FDM signal hav-
ing a bandwidth between 8 and 248 kHz. Use may be made of four additional dum-
my baseband channels. Furthermore, let the first sampling frequency fs be 8
kHz. For a modulator 40A depicted in Figure 13 and comprising a 64-point IDFT
processor 71 fsr real input signals of radix-two, the rate of multiplication
has been calculated in accordance with a method described by Glenn D. Bergland
under the title of "A Fast Fourier Transform Algorithm for Real-Valued Series"
in "Communications of the ACM." Vol. 11, No. 10 (October 1968), pp. 703-710.
With eight ~8) selected as the order M, each of the slow complex band-pass fil-
ters 42k is composed of recursive sections described with reference to Figure
11 and a non-recursive section, with elements related to the imaginary filter
output signal omitted, illustrated in conjunction with Figure 12. Under the
circumstances, the frequencies of real multiplication per period of the 8 kHz
signal in the IDFT processor 71, post-processor 72, and filters 42k are 166,
128, and 1,536, respectively. The total rate per second is 14,640 x 106, which
value is about 75% of the rate of real multiplication of 19,392 x 106 required
per second for a modulator disclosed in the often-cited Bellanger et al article.
It is now reminded that the preferred embodiments described with ref-
erence to Figures 7, 13, and 17 have been derived from the fundamental filter
bank comprising the fast complex band-pass digital filters 23k or 27k whose
_ 24 -
transfer functions Hk(Z~ may be deriYed from a fast real low-pass filter of
Figure 4 or 5 having a transfer function G(Z~ by frequency shifts of ~4k + l)
f /4. It is possible to use another set of frequency shifts, such as ~4k + 3)
f5/4, t4(N-k) - l~f5/4, and 14(N - k~ 3Jf5/4. In this e~ent, the transfer
functions Gi(jZN) of the slow complex band-pass filters 42 and 48 may become
Gi(jZ ), IDFT may become DFT (discrete Fourier transform), and the phase off-
set factors may become exp(-j2~i/14Nl) or exp(+j6~i/[4N]).
- 25 -
