Canadian Patents Database / Patent 1118048 Summary

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(12) Patent: (11) CA 1118048
(21) Application Number: 316941
(54) English Title: DIGITAL DEVICE FOR CHECKING STEADYSTATE VALUE OF ANALOGUE SIGNAL
(54) French Title: DISPOSITIF DIGITAL POUR VERIFIER LA VALEUR D'ETAT STABLE D'UN SIGNAL ANALOGIQUE
(52) Canadian Patent Classification (CPC):
  • 324/63
(51) International Patent Classification (IPC):
  • G01R 21/06 (2006.01)
(72) Inventors :
  • SKURIKHIN, VLADIMIR I. (USSR)
  • FAINZILBERG, LEONID S. (USSR)
  • ZHITETSKY, LEONID S. (USSR)
(73) Owners :
  • INSTITUT KIBERNETIKI AKADEMII NAUK UKRAINSKOI SSR (Not Available)
(71) Applicants :
(74) Agent: MARKS & CLERK
(74) Associate agent:
(45) Issued: 1982-02-09
(22) Filed Date: 1978-11-27
(30) Availability of licence: N/A
(30) Language of filing: English

English Abstract





ABSTRACT OF THE DISCLOSURE
A digital device for determining a steady-state value
of the analogue signal comprises an analog-to-digital converter
for converting the analogue signal into a numerical pulse code
connected through a synchronization unit to inputs of threshold
counters, a clock pulse generator connected through a synchroni-
zation unit to the inputs of the threshold counters and to inputs
of a time interval discriminator and through a frequency halver
to the inputs of a reversible counter, and a digital display
unit connected to digital outputs of the reversible counter.
The device also comprises decoders of zero state of the threshold
counters, having their inputs connected to the respective thres-
hold counters and their outputs connected to subtract count block-
ing inputs of the respective threshold counters to the inputs
of the reversible counter and to a control input of the digital
display unit. Overflow inputs of the threshold counters are
connected to initial setting inputs of the time interval dis-
criminator. An information output of the time interval dis-
criminator is electrically connected to the input thereof and to
the inputs of the threshold counters to those of the reversible
counter, and to the control input of the digital display unit. In
addition, the device includes seven AND circuits and three NOT
circuits by means of which logical control of electric communi-
cation between the units of the device is effected. The fore-
going design of the device permits the steady-state value of the
analogue signal to be determined more accurately. In the device
an error in determining the steady-state value depends exclusively
on the resolution ability of the analog-to-digital converter and
not on the level of noise. The use of simple elements and units
of the digital-computing technique in the device ensures high
reliability, low cost and small dimensions.


Note: Claims are shown in the official language in which they were submitted.



THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A digital device for checking a steady-state value
of the analogue signal, comprising: an analogue-to-digital con-
verter for converting the analogue signal into a sequence of code
pulses the number of which corresponds to an increment of the
analogue signal, provided with a first output of the code pulses
corresponding to a positive increment of the analogue signal and
with a second output of code pulses corresponding to a negative
increment of the analogue signal; a clock pulse generator having
an output; a synchronization unit for distribution in time of code
and clock pulses, having a first, a second and a third input, an
output of synchronized clock pulses, a first output of synchro-
nized code pulses corresponding to a positive increment of the
analogue signal and a second output of synchronized code pulses
corresponding to a negative increment of the analogue signal;
a time interval discriminator for selecting intervals between
two sequence instants of time when a local increment of the ana-
logue signal assumes a predetermined value, having a count in-
put, a first and second input of initial setting and an informa-
tion output; a first and second threshold counter designed for
determining local increments of the analogue signal, each having
an add input, a subtract input, an additional subtract input,
an input of subtract counting blocking, an overflow output and
digit outputs; a first and a second decoder designed for de-
termining a zero state of the first and the second threshold
counters, respectively, each said decoder being provided with
inputs and an output; a frequency halver having an input and an
output; a reversible counter for generating a parallel code of
calculation result, having an add input, a subtract input, an
additional add input, an additional subtract input and digit
outputs; a digital display unit for displaying the calculated



24


result and having an information input and a control input; a
first AND circuit having a first and a second input and an output;
a second and a third AND circuit, each having a first, a second,
a third, a fourth input and an output; a fourth AND circuit
having a first, a second and a third input and an output; a
fifth, a sixth and a seventh AND circuit, each having a first and
a second input and an output; first, second, and third NOT cir-
cuits, each having an input and an output; said first input of
said synchronization unit being connected to said first output
of said converter of the analogue signal into a numerical pulse
code; said second input of said synchronization unit being connec-
ted to said second output of said converter of the analogue sig-
nal into a numerical pulse code; said third input of said syn-
chronization unit being connected to said output of said clock
pulse generator; said first inputs of said first, second, third
and fourth AND circuits and said input of the first NOT circuit
being connected to said information output of said time interval
discriminator; said second inputs of said first and fith AND cir-
cuits being connected to said first and second outputs of said
syncronization unit, respectively; said first input of said fifth
AND circuit being combined with said second inputs of said sixth
and seventh AND circuits and connected to said output of said
first NOT circuit; said add input of said first threshold counter
said subtract input of said second threshold counter and said add
input of the reversible counter being connected to said output
of said-sixth AND circuit; said subtract input of said first thres-
hold counter, said add input of said second threshold counter and
said subtract input of said reversible counter being connected to
said output of said seventh AND circuit; said additional subtract
inputs of said threshold counters being connected to said output
of said first AND circuit said inputs of a subtract count block-
ing of said first and second threshold counters being connected






to said outputs of the first and the second decoders, respecti-
vely; said inputs of said first and second decoders being connec-
ted to said digit outputs of said first and second threshold
counters, respectively; said count input of said time interval
discriminator being connected to said output of said fifth AND
circuit; said first and second inputs of initial setting of
said time interval discriminator being connected to said overflow
outputs of said first and second threshold counters, respectively;
said second inputs of said second and third AND circuits being
connected to said output of said frequency halver; said third in-
put of said second AND circuit being connected to said output of
the second NOT circuit; said forth input of said third AND cir-
cuit being connected to said output of said third NOT circuit;
said input of said second NOT circuit, said third input of said
third AND circuit and said second input of said fourth AND cir-
cuit being connected to said output of said first decoder; said
fourth input of said second AND circuit, said input of said third
NOT circuit, said third input of said fourth AND circuit being
connected to said output of said second decoder; said output of
said second AND circuit being connected to said additional sub-
tract input of said reversible counter; said output of said third
AND circuit being connected to said additional add input of said
reversible counter; said digit outputs of said reversible counter
being connected to said information input of said digital display
unit; and said output of said fourth AND circuit being connected
to said control input of said digital display unit.




26

Note: Descriptions are shown in the official language in which they were submitted.

The present invention relates to digital computers
and, in particular, to digital devices for determining a steady-
state value of the analogue signal.
The present invention can be employed for preliminary
processing of information received from sensors during
production processes, and, more particularly, for digit
representation of the molten steel temperature measured by
means of an immersion thermocouple.
~ n preliminary processing of information there exists
a problem in estimating against bac~ground noise, a steady-state
valwe with a final result to be represented in a digital form.
Such a problem exists in measuring temperature
of molten metal, for example steel, by means of a temperature
sensor which is immersed in the melt for a short period of time,
when it is re~uired to determine in a digi-tal form the
signal value received from the sensor, which is set after
termination of a transient process caused by the drift of
temperature sensors.
Known in the art is a digital computing device designed
for checking parameters of a molten metal.




" ",,.
. ~

~8~

The above device can be employed for determining in a digital
form a steady-state value of the analogue signal, for example
for determining a molten metal temperature measured:by means of
an immersion thermocouplè.
The device comprises an analogue-to~digital converter
for converting an analogue signal into a numerical pulse code,
having an output of code pulses corresponding to a positive in-
crement of the analogue signal and an output of code pulses
. corresponding to a negative increment of the analogue signal, a
clock pulse generator, a synchronization unit for distribution
in time of code and clock pulses, connected with the inputs and
outputs of the analogue-to-digital converter and to an output
of the clock pulse generator. For determining local increments
of the analogue signal there are provided first and second
threshold counters, digit outputs of which are connected to inputs
of decoders of the zero state of threshold counters, outputs of
said decoders being connected to subtract count blocking inputs
of the respective threshold counters. The device also comprises
a time interval discriminator designed for selecting time
intervals between sequence instants of time when a local incre-
ment of the analogue signal assumes a predetermined value.
Initial setting inputs of the time interval discriminator are con-
nected to overflow outputs of




~ - 2 -



said threshold counters. An output o~ s~nchronized elock
pulses of the synchronization unit is elec-trically connec-t-
ed to a count inpu-t o~ -the time int-erval discriminator. Syn-
chronized code pulse outputs o~ -th~ s~nchronization unit are
elec-trically connected to -the threshold counters and to a
reversible counter designed ~or generati~g a parallel code
o~ the resul-t. A register connected with i-ts in~orma~tion
input to digit outputs o~ ~the reversible counter, and with
its control input to the outpu-t o~ the time interval dis-
crimina-tor provides for a s-torage o~ the computed result
wQich is displayed in a digital form in a di~ital display
uni-t.
Durin~ the process of determining -temperature O:e molt-
en inetal~ in the reversible counter -there is ~ormed a code
proportional -to the current readings of the analogue sign-
~1 reeeived :Erom the temperature sensor. I~ ~ositive or ne-
ga~tive incremen-ts o~ the signal e~eeeds a predetermined thre-

shold o of non-sensitivi~y to the 3ignal deviations ~rom
ef~e ~fs
it~ steady-state value, cau~ed by inter~erence ~ e~ there
appear pulses a-t -the over~low outputs of the -threshold co-
unters. ~aeh such pulse sets into the initial state -the time
interval discriillina-tor which coun-ts up a number o~ s~nchro-
nizecl clock pulses. I~ ~ithin a predeterminecl time inter~
val ~ O set wi-th -the aid o~ -the time interval discriininat-




or, an increment o:~ the signal does not e~ceed the predeter-
rl~ined ~threshold o~ there appears a signal at the output
of the time interval discriminator, which indica-tes that
-the analo~ue signal has assumed its steady-sta-te value. The
parallel code con-tained in this instant o~ time in the re-
versible counter enables said ready-state value of the ana-
logue signal to be es-timated. '~he signal, which is fed to
the con-trol input of the register from -the outpu-t of -the
time interval discriminator, contains inforrnation indica-
tive of the steady-state value of the analogue signal.
It should be notecl that the parallel code fed -to -the
register may vary from -the code of the steady-state value
0~ -the analogue signal by a va;Lue o~ -~0.5 ~ O. Thus, the
maximum error in determining a steady-state value of -the
analogue signal With the aid o.P the above clevice cannot
be less than 0.5 ~ o.
With the increase of the noise level the non-sensi-
tivity -threshold ~o has to be increased, which brings
about an increase in the ma~imum error in determi~ing the
7~
B ready-state value of the analogue sigllal. '~hus, ~n accu-
racy in determining -the s-teady-state value of the anal~gue
signal by means o~ the above device considerably depends
on -the noise level~
~or e~ample, when determining molten steel tempera~



ture is done by means o~ the existing temperatuxe sen~ors,
which are dipped in the melt ~or a short period o~ time,
the noi~e lavel rnay be equivalent to the deviation of` the
analogue signal value in the order o~ 10 C. This being -the
case,the threshold ~o of non-sensitivi-ty has to be equal
to 10C which may cause an error in determining mol-ten
steel temperature wi-thin ~5C. In smelting and casting ~
~ig~-cluality steel such an error in determining its tempe-
rature is not permissible.
The principal o~jec-t o~ this invention is to provide
a digital device encorporating simple elements and units
o~ the digi-tal-computing technique eor determining a steady-
~tate value o~ the analogue signal, enabling saicl s-teady-
state value of the analogue sij~nal to be determined as the
average o~ the maxil~um ancl minimum values o~ the analogue
signal variations o~' which within a prese-t time interval
do not exceed a predetermined ~alue.
Another object o~ the invention is to provide such
a digital devi'ce ~or determining a steady-s-tate value o~
the analogue ~ignal, error o~ which does not depend on the
noise level.
Yet another object o~ the invention is to improve
an accuracy in determining a ~teady-sta-te value o~ the ana-
logue signal.




.

413

These and other ob~ects of the invention are accompli-
shed by that a digital device for determining a steady-state
value of the analogue signal, comprising an -analogue-to-digital
converter for converting an analogue signal into a numerical
pulse code, having an output of code pulses corresponding to a
positive increment of the analogue signal and an output of code
pulses corresponding to a negative increment of the analogue
signal, a clock pulse generator, a reversible counter for`genera-
ting a parallel code of the computed result, a digital display
unit for displaying the calculated result, electrically connected
to digit outputs of said reversible counter, first and second
thrèshold counters for determining local increments of the ana-
logue signal, decoders of the zero state of the first and.second
threshold counters, said decoders being connected with their in-
puts to digit outputs of said threshold counters and with their
outputs to substract counting blocking inputs of sald first and
second threshold counters, a time interval discriminator for
selecting intervals between two sequence instants of time when
a local increment of sa~:d analogue signal assumes its predeter-

mined value initial setting inputs of said dis~riminator beingconnected to overflow outputs of said threshold counters, a
synchronization unit for time distrlbution of code and clock




-- 6 --

~130~8


pulses, connected with its two inputs to outputs of said
analogue-to-digital converter and with its third input to the
output of a clock pulse generator, outputs of synchronized code
pulses of said synchronizer unit being electrically connected
to said threshold counters and said reversible counter, whereas
the output of synchronized clock pulses of said synchronization
unit being electrically connected to said discriminator of time
intervals, said digital device having, according to the invention,
a frequency halver, three NOT circuits, seven AND circuits, a
time interval discriminator provided with an information output
connected to first outputs of first, second, third, fourth
AND circuits, and through a first NOT circuit to a first input of
a fifth AND circuit, an output of synchronized clock pulses of
said synchronization unit being connected to a second input of
said first AND circuit, the threshold counters being provided with
additional substract inputs whereto there is connec-ted an output
of said first AND circuit, synchronized code pulse outputs of
said synchronization unit being electrically connected to said
threshold counters and said reversible counter through a sixth
and a seventh AND circuit respectively, the output oE synchronized
code pulses corresponding to a posi- :
~ .




:




- 7 -

!

~L8~8

tive increment of the analogue signal, being connected to a first
input of the sixth AND circuit whereas the output of synch~oni~ed
code pulses corresponding to a negative increment of the analogue
signal, being connected to a first input of the seventh
AND circuits, second inputs of the sixth and seventh AND
circuits being combined with the first input of the fifth AND
circuit whereas the output of the sixth AND circuit is connected
to add inputs of said reversible counter and said first threshold
counter and to a subtract input of the second threshold counter,
and output of the seventh AND circuit being connected to subtract
inputs of said reversible counter and said first threshold counter
and to the add input of said second threshold counter, an output
of synchronized clock pulses of the synchronization unit being
electrically connected to said time interval discriminator through
the fifth AND circuit, said output of said synchronization
unit being connected to the second input of said fifth AND circuit
the output of which is connected to a count input oE said time
interval discriminator, second inputs of the second and third
AND circuits being connected to said output of synchronized clock
pulses of said synchronization unit through a frequency halver,
an output of the decoder of zero-state of said first threshold
counter being connected to a third input of




~ - 8 -

48

the third AND circuit, to a second input of the fourth AND cir-
cuit, and, throu~h a second NOT circuit, to a third input of the
second AND circuit, an output of the decoder of zero state of -
the second threshold counter being connected to a fourth input of
the second AND circuit, to a third input of the fourth AND cir-
cuit, and, through said third NOT circuit, to a fourth input of
the third AND circuit, outputs of thè second and third AND cir-
cuits be;ng connected to an additional subtract input and to an
additional add input of the reversible counter, and a digital
display unit provided with a control input connected to an output
of the fourth AND circuit.
The invention will no~. be described in more detail, by
way of example only, with reference to the accompanying drawings,
wherein:
Fig. 1 is a block diagram of the digital device for -.
determining a steady-state value of the analogue signal in accor-
dance with the invention;
Fig. 2 illustrates a representative portion of the ana-
logue signal variation curve for the case when the point of the
representatlve portion of the curve, at which the time interval
discriminator is triggered, is located on the midline between the
maximum and minimun values of the analogue signal;




g

~:: L18~8

--10--

~ ig. 3 illuskrates substan-tially the same as in
~ig. 2 but for -the case when the point o -the representative
portion o~ the curve, at which the tima interval c~iscrimi~
nator is triggerecl, is located above the midline be-tween
the ma~imum and mini~um values of the analogue signal;
Fig, ~ illus-tra-t~s the same as that in ~ig. 2 bu-t
f OI' -the case when the point o~ the represen-ta-tive portion
OI` the cu~ve, at which -the time in-terval discriminator
is -triggered, is Located belo~ -the midline between -the ma-
ximum and minimum values o~ the analo~ue sig~al.
A digital device for determining a steady-sta-te value.
0~ the analogue signal as illustrated in Fig. 19 comprises
an analogue-to-digital converter 1 ~or converting an ana-
logue signal into a numerical pulse code, a clock pulse ge-
nerator 2, a synchroniza-tion unit 3 ~or distribution in
time af code and clock pulses, threshold counters 4, 5,
a decoder 6 of the zero-state o~ the threshold counter 4~
a decoder 7 o~ the zero~state o~ -the threshold cou~ter 5,
a time i~terval disc.riminator 8, a reversible counter 9, a
digital display unit 10, -three ~OT circuits 11, 12, 13~
seven A~D circuits 14, 15, 16, 17, 18, 19, 20, and a frew
quency halver 21.
The converter 1 of analogue signal in-to numericaL
pulse code has an input 22, a~ outpu-t 23 for transmitt-



. . .^ O




.
, ~ ,, ,
., -, ' , , :
.





in~ code pulses corresponding to a positive incremen-t o~
-the analogue si~nal, and an output 24 for transrnitting
code pulses corresponding -to a negative increment of the
analogue signal. The outputs 23 and 24 are connected to
the synchronization uni-t 3. hn ou-tput 25 o~ the cloc~
pulse generator 2 i~ also connected to the synchroniza-
~tion unit 3. An output 26 o~' synchronized clock pulses
o~ the synchrorliza-tion unit 3 is connected to an input
o~ -the A~D circuit 14, to an input o~ the A~D circuit 15
and to an input of the ~re~uency halver 219 An outpu-t 27
of the synchroniza-tion unit 3, intended ~or transmitting
synchronized code pulses corresponding to a positive in-
crement o~ the analogue signal at the inpu-t 22 o:~ the
converter 1, is connected to an input of the AND circuit
19. An output 28 o~ the synchronization unit 3, intended
~'or trans~itting synchronized code pulses corresponding
-to a negative increment o~ -the analo~jue signal at the in-
put 22 o~ the conver-ter 1, is connected to an input of
the A~D circuit 200 Inputs 29, 30? 31 o~ the respective
A~D circui-ts 20, 19, 14 are combined. An outpu-t 32 of the
A~D circuit 14 is connected to a count input o~ the time
in-terval discriminator 8. An output 33 o~ the AND eircuit
15 is connected -to addi-tional subtract inputs of the thre-
shold counters 4, 5~ An outpu-t 34 o~ -the ~D circuit 19 is




. .

~8~4~

~12-

connected to an add input o:~ the threshold counter 5, -to
a subtract input of the -th,reshold colmter 4 and to an add
input o e the reversible counter 9. An output 35 o~ the AND
circuit 20 is connected -to a subtrac-t inpu.t ol -the thre~
shold counter 5, to an add inpu-t of the thre3hold coun-ter
4 and to a subtrac^t input o~ the reversible counter 9.
Digit output3 36 of the threshold coun-ter 4 are connected
to the outputs o~ the decoder 6. An over~low output o~
-the -threshold counter 4 i9 connected -to an initiaJ. se-ttir,g
input ~7 of the time interval discriminator 8. An out-
put o~ the decoder 6 is connected -to an inpu-t ~8 OI' sub-
-tract count blockin~ o:~ the -tl~eshold coun-ter 4, -to an in-
put 39 o~ the A~n circuit 16, to an input 40 o~ -the N0~
circuit 13 and to an input 41 of -the A~D circuit 18. Di-
git OlltpUtS 42 o~ the threshold counter 5 are connec-ted
to inputs of the decoder 7. An overf'low input o~ -the thre-
shold coun-ter 5 i~ connected to an input 43 o~ initial
~etting o~ the time interval discriminator 8. An ou-tput
of the decoder 7 is connected to an input ~ o~ subtract
count blockin~ o~` the -threshold coun-ter 5, to an inpu-t 45
o~ the NO~ circuit 12, to an inpu-t 46 o~ the AND circuit
17 and bo an input 47 0~ the AND cirouit 18. An in~orma
tion ou-tput of the -time interval discriminator 8 is con-
nected to an input 4~ o~ the N01' circuit 11 and to i~puts




~ . .


. ., . ~ . .,
- ~; i'-:,.

~8~8

49, 50, 51 ofthe ANDcircuits 16, 17, and 18, respectively. An out-
put of the NOT circuit 11 is connected to the input 31 of AND cir-
cuit 14, an output of the NOT circuit 12 is connected to an inpu-t
52 of the NOT circuit 16 and an output of the NOT circuit 13 is
connected to an input 53 of the AND circuit 17. An output of
the frequency halver 21 is connected to inputs 54,55 of the AND
circuits 16 and 17, respectively. An output 56 of the AND circuit
16 is connected to an additional subtract input of the reversible
counter 9 whereas an output 57 of the ~ND circuit 17 being connec-

ted to an additional add input of the reversible counter 9. Anoutput 5~ of the AND circuit 1~ is connected to a control input of
the digital display unit 10. Digit outputs 59 of the reversible
coun-ter 9 are connected to an information input of the digital
display unit 10.
The threshold counters 4,5 are scaling circuits set to
a scaling factor corresponding to a predetermined threshold
Eo of non-sensitivity to the signal dev;iations from a steady-
state value, caused by interference.
The time interval discriminator 8 is a scaling circuit
whose scaling factor corresponds to a dùration of the predeter-
mined time interval.
The foregoing digital device for determining the steady-
state value of the analogue signal functions as follows.




~ - 13 -

L 8 a~ L~ 8



'I'he analogue signal i5 ~ed to the inpu-t 22 o~ the converter
1 o~ the analogue si~nal into a numerical puls~ code. De-
pending on the increment sign of the analogue signal, code
pulses are ~ormed either a-t the ou-tput 23 or at -the o~t-
put 24 o~ the analogue-to-digital converter 1 for convert-
iny, the analo~ue signal into a numerical pulse code, the
number o~ the code pulses being proportional to -the icre-
ment of the analogue signal. ~he code pulses from the out-
puts 2~ a~d 24 are ~ed to -the ~irst and second inputs o~
the synchronization unit 3, while to the third input o~ the
synchroniza-tion unit 3 are ~ed clock pulses from the output
~5 o~ the clock pulse ~;enerator 2. In the synchronization
unit 3 the code and clock pulses are distributed in time.
'l'he synchronized code and clock pulses are ~ormed at the
inputs 26, 27 and the output 28 of the synchronization
unit 3, respec-tively.
A-t -the moment o~ startin~ the device, the time in-ter-
val discriminator 8 is set in ltS initial state either with
the initial set-ting key (not shown) or automa-tically, in
response to which blockin~ potential is ~ormed at the in-
~orma-tion outpu-t o~ the time interval discriminator 8/ w~ich
blocks ~he A~D circui-ts 15~ 16 9 17 and 18 9 and opens, thro-
ugh the N0~ circuit 11, the AND circuits 14, 19 and 20.
~ rom the synchronization unit 3 the synchronized code




:
L
'.
: ~
" ~:' ' , ,


-15-

pulses are ~ed, through the released AND circuits 19, 20
either to the add input or to the subtract input o:E the
reversible counter ~ to generate a pa:rallel code o~ the
analogue signal current value. ~he same code pulses are ~ed
to -the add and sub-tract inputs of -the threshold counters 4,
5~ In this case, i~ an incroment o~ the analogue signal
is positive, the code pulses ~rom the out~out 34 ol the AND
circuit 19 are ~ed to the add input o:E the revers,ible counter
5 and the sub-tract input o~ the threshold counter 4. In
case the incrernent o~ the analogue signal is negative, -the
code pul~7es .~rom the output 35 o~ the AND circuit 20 are ap-
plied -to the subtract input o~ the reversible coun-ter 9,
the subt.ract inpu-t o~ the threshold coun-ter 5 and ~t the add
input o~ the threshold counter 4. I~ in the -threshold co-
unte.r 4 a z~ro is ~ormed a ~rthe.r .subtract counting~ in
said counter is blocked b~ -the decoder 6~ Similarly, i~ a
zero is ~ormed in the threshold counter 5, a ~urther sub
tract counting in -this coun-ter is blocked by t~e clecoder 7.
Thus, the threshold counter 5 generates a code proportional
to a local positive increment o~ the analogue signal rela-
-tive to the local minimum o~ the VariatiOrl curve of said
signal, whereas threshold counter 4 genera-tes a code pro-
portional -to a local negative increment o~ the analogue
signal relative to the local ma~imum on the variation curve


.~,.




: :.,.

48



of said signal. If ei-ther of said local incremen-ts exceeds
a prede-termined -threshold ~0, at -the overflow output of
-the respec-tive threshold coun-ter -there is for~ecl a pulse
setting the time in-terval discriminator 8 in its ini-tial
state. The count input o~ t~e time interval discriminator
8 is fed wi-th synchronizea clock pulses through -the AND
circuit 14. A release ~/oltage at the in~orma-tion ou-~put
of the.time interval discririlinator 8 ca~ be ~orrned only if
within a preset time interval ~ said discrimina-tor is not
reset in i-ts initial state by a pulse received from -the
overflow output of either of the threshold coun-ters 4 or
5. ~hus, as the analogue signal variates, the time inter-
val discrimina-tor 8 is se-t in its ini-tial state each time
when the increme~t of the analogue signal wi-thin a preset
-time inter~al ~ o exceeds ~ o value. Nhen the analogue
signal assum~s its steady-state value, its nega-tive a~d po-
sitive incremen-ts do not e~ceed ~o value. As soon as -the
time interval ~ o calcula-ted from the moment o~ the last
initial rese-tting of the time interval discriminator 8 ter
mina-tes at the information output of said discriminator there
appears a release potential. In this case a blocking poten-
tial formed at the outpu-t of the N0~ circuit 11 blocks the
AND circuits 14, 19, 20, w~ich in turn blocks passage of' the
code pulses -to -the reversible counter 9 and -to the threshold


.~ _


. . .


.:


counters 4 and 5. Simultaneously, feeding the clock pulses to the
count input of the time interval discriminator 8 ceases due to
which release potential at the information output thereo~ is main-
tained till the next cycle determininy the steady-state value of
the analogue signal. Also the permitting potential formed at
the information output of the time interval discriminator 8, opens
the AND circuit 15, and the synchronized clock pulses from the out-
put 26 of the synchronization unit 3, are fed through said AND
circuit 15, to the additional subtract inputs of the threshold
counters 4 and 5.
If a value o E the analogue signal, at which the rever-
sible counter 9 and the threshold counters 4 and 5 have been
blocked by a signal of the time interval discriminator 8, is found
in the midway between the maximum and m:inimum values of the
analogue signal on the representative portion of the curve re-
presenting a time dependence of the analogue signal value (Fig. 2),
the contents ~Xl of the threshold counter 5 at the moment of
blocking is equal to the contents AX2 o:E the threshold counter 4.
Clock pulses, which are fed through the AND circuit 15 to the addi-

tional subtract inputs of the threshold counters 4 and 5 r cause thecontents of said threshold counters to vary. As soon as a zero
is formed in said threshold counters, the decoders 5 and 7 of zero




~' - 17 -
, ~



-lS~

state of the threshold counters 4 and 5 block the subtract
inputs of said counters simultaneously applying release po-
tentials to the input3 41 and 47 of the ~ND circuit 18. In
so far as said circuit 18 i5 also ied through its input 51
wi-th the release potential from the information output of
the time interval discrimina-tor 8 9 at its output 58 -there
is formed release potential which, being fed to the control
input of the digital display uni-t 10, causes transmission
of' information ~rom the reversible counter 9 to said digi-t-
al display unit 10 wherein a steady-stat~ value of -the ana-
logue signal is numerically displayed corresponding to the
average between -the ma~imum and minimum values o.~ the ana~
logue signal on said representative portion of the varia-
tion curve of said analogue signal,
If -the point on the variation curve (Fig. 3) o~ the
analo~ue signal, at which the reversible counter 9 has been
blocked by a potential at the information output o~ the time
interval discriminator 8, is located above the midline bet-
ween the maximum and minimum values of the analogue signal
on a representative portion of the curve, the con-tents ~Xl
of the -t'areshold counter 5 at the moment of signal formation
a-t the informatio~ output of the time in-ter~al discriminator
8 will be greater than the conten-ts ~ of the threshold
countar 4, a~d the vAlue ~ ~0 of -the blocking point devia-


4 !3
_ lC3_




tion relative to the midline be-twsen the maximvm and mini-
mum values of the analo~ue signal of the representative por-
tion of' the curve ~ay be determined by relation

11 g1 X2
X
~ (1)

Synchronized clock pulses fed from the output 33 o~
the AWD circuit 15 to the additional subtrac-t inputs of the
threshold counters 4 and 5 cause the con-tents o~ said t~re-
shold coun-ters 4 and 5 to var,y in a manner si~i:Lar to above,
however a zero is ~irst ~ormed in the threshold countar 4
while in -the threshold coun-ter 5 there is a code corresporld
to -the difference be~twee-n values ~ ~1 and ~ ~ ~ At -the mo-
ment, when a zero appears in th.e threshold counter 4, the
decoder 6 of -the zero-st;a-te -thereo~ blocks the threshold
coun-ter 4 and sends release potentials to the AND circuits
16 and 180 The d~coder 7 o~ -the zero state of ~he threshold
counter ~ sends through the ~OT circuit 12 release po-tential
to -the input 52 o~ the AND circuit 16, In ~o far as at the
input 49 of saicl ~N~ ci~;cuit there also exists a release
poten-tial formed at ~e.in~ormation output of the time
interval discriminator 87 synchronized cloc~ pulses; whose
requency is divided in two b~ the ~requency halver 21~
are fed through the A~D circui~t 16 to the additional sub-




- ,


-2C-

tract input Oe the reversible counter 97 said pulses be-
ing :Eed to said ad~-li-tional subtract inpu-t o~ -the reversible
counter 9 until a zero is formed in the threshold counter
5 as in -the threshold counter 4. A-t this time release po-ten-
tial at -the ou-tput o~ the decoder 7~ passing through the
NOT circui-t 12 locks the ~ND circuit 16. '~he number o~ puls-
es being :eed to -the reversible counter 9 corrasponds to the
value ~ X'O determined by tha expression 19 which enables
the conten-ts Oe -the reversible coun-ter 9 to be corrected
au-tomatically to a required valua corresponding -to the aver-
age between the ma.~imum and min.imum values of the analogue
signal on the representa-tive po:r-tion of -the curve. As soon
as a zero appears in the threshold counter 5 the ~3 cir-
cuit 18 gets released so as -to transmi-t information indi-
cative O:e -the steady-state value o e the analogue slgnal to
the digital display unit 1OD
In case the point, at which the reversible counter 9
has been blocke~ by a potential at tlle in~ormation output o~
the time interval discrimina-tor 8, is located belol.~J the
midline between the maximum and minimum values o~ the ana-
logue si~nal on tha repre.sen-tative por-tion OL the curve
(~ig~ 4)9 the conten-ts ~ X1 of the -threshold coilnter 5
at -t, he momen-t o~ signal ~orma-tion at the in:Corlnation out-
pu-t Oe the -time interval discriminator 8 will ~e smaller


than the contents QX2 of the threshold counter 4. The value
QXo of the blocking point deviation from the midline between the
maximum ana minimum values of the analogue signal on the represen-
tative portion of the curve, is determined by the following re-
lation:

xll .= 2 1 (2)
o 2

Synchronized clock pulses fed to the additional subtract
inputs of the threshold counters 4 and 5 cause the contents there-

of to vary. As soon as the zero is formed in the threshold counter5, in the threshold counter 4 there will be a code corresponding
to the difference between values QX2 and QXl. At this instant
of time the decoder 7 blocks the subtract input of the threshold
counter 5 and opens the AND circuit 17. Synchronized clock pulses
are fed, through the frequency halver 10 and AND circuit 17 to the
additional add input of the reversible counter 9, feeding said
pulses to said additional add input of the reversible counter 9
being ceased when zero is formed in the threshold counter 4 as
in the threshold counter 5. In this case the decoder 6 blocking
the subtract input of the threshold counter 4 locks the AND
circuit 17 through the NOT circuit 13. Simultaneously, said de-
coder 6 opens the




- 21

530~8

-22-

AND circuit 18~ Thus, the reversible counter 9 will be ~ed
with a number o~' pulses corresponding~ to tha value ~ ~O
determined by e~pression 2, which causes -the contents o~
the reversible counter 9 to be automatically corrected to
a required value corresponding to the point on -the midline
between the maximum and minimum values o~ the analogue.sig-
nal on the representa-tive portion o~ the curve. On signal
received ~rom the outpu-t 58 of -the ~ND circuit 18 the cor-
rec-ted conten-ts o~ tlle reversible counter 9 is transmitted
to the digital display unit 10 to be numerically displa~ed
therein.
The above design o~ a digital device for checking a
steady-s-tate value of the analogue signal enables said ste-
ady-state value o~ the analogue signal to be cle-termined
more accurately. In said device an error i ~etermining the
stead~-state value o~ -the analoglle signal. depends e~clusive
ly on the resolu-tion abilit~ o~ the converter o~ analogue
signal in-to numerical pulse code and not on the noise level.
Tha use o~ simple elements and units of digital-compu~ing
techni~ue in the device ensures a hi~h reliability, as well
as a low cest and small dimensions thereo~. The employment
OI' said di~ital device ~or determini~g the steady-sta-ta va-
lue of the analogue signal~ ~or example, ~or detarmining
in the numerical form a temperature of the molten steel~




:. .:.,, ' , i :



-23-

meas~ed by means o~ a -thermocouple whicil is dipped in -the
melt .t'or a sLlor-t time, provides lor a high .accuracy o~ mea-

surements O
For e~ample,-when said device encorporates an analo-
gue-to-digi-tal converter I'or converting an analogue signal
into a numerical pulse code, having resolution ability 1C,
the maximum error caused by this device in -tha measuring
sys-tem does not e~ceed -~0.5C~
While the inveL~tion has been described herein in terms
o~ the prePerred embodimen-ts, i-t ~ill be readily understood
by those skilled in the art that numerous variations may
be made in the dip,ital device :eor checking a steady-state
value o~ the analogue signal herein described ~ithout de~
parting erom -the inven-tion as s,s-t eor-th in -the appended
claims ~

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Admin Status

Title Date
Forecasted Issue Date 1982-02-09
(22) Filed 1978-11-27
(45) Issued 1982-02-09
Expired 1999-02-09

Abandonment History

There is no abandonment history.

Payment History

Fee Type Anniversary Year Due Date Amount Paid Paid Date
Application Fee $0.00 1978-11-27
Current owners on record shown in alphabetical order.
Current Owners on Record
INSTITUT KIBERNETIKI AKADEMII NAUK UKRAINSKOI SSR
Past owners on record shown in alphabetical order.
Past Owners on Record
None
Past Owners that do not appear in the "Owners on Record" listing will appear in other documentation within the application.

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Document
Description
Date
(yyyy-mm-dd)
Number of pages Size of Image (KB)
Drawings 1994-02-02 2 56
Claims 1994-02-02 3 148
Abstract 1994-02-02 1 48
Cover Page 1994-02-02 1 16
Description 1994-02-02 23 867