Note: Descriptions are shown in the official language in which they were submitted.
8~9~
Back~ro~md of the Invention
This invention relatcs to semiconductor logic or memory devices and
a method for making same.
In United States Letters Patent No. 4~003,036 which is assigned to
the assignee of the present application, a single IGPET memory cell with a
buried storage element is disclosed for use in a semiconductor read-write
memory device. Briefly~ this prior art memory cell utilized a buried storage
element of a first conductivity type (N~) located within a substrate of another
conductivity type ~P+) material. An etched recess having a V-shaped cross-
section had a lower end that extended into the buried element which formed
the source o a VMOS transistor. The recess also extended through another
region of the first conductivity type material that formed the drain of the
V~OS transistor near its upper end. The recess walls were provided with a thin
gate oxide material and this oxide was covered by a conductive material serving
both as a gate and also forming a portion of a word line for the device. In
operation, the buried N+ source elemen~ formed the storage device for the cell
and the drain region formed a portion of buried bit lines. The aforesaid prior
art single transistor cell provided an improvement in the art with significant
advantages over previously developed three transistor and six transistor planar
type memory cells. However, it also required the ~ormation of transistor drain
regions and the charge capacity of the device was limited by the size o~ the
buried N~ storage element.
One object of the present invention is to provide an improved semi-
cQnduc~or memory cell that also utilizes an etched recess but which furnishes
new and unobv:Lous advantages over tlle prior art.
Another cb~ect of ~he lnven~ion is to provi~e a semiconduc~or Memory
cell u~ilizing a single etched groove or recess ~hat requires a relativ~ly small
--1 -
''
8~9Z
area on a substrate so that the density of cells per unit area can be extremely
high in a memory device.
Another object of the invention is to provide a semiconductor memory
cell utilizing a single groove or recess that does not util;ze buried drain
regions in combination with a buried source region to form a transistor, but
which utilizes a single buried bit line and a thin layer of material in the
walls surrounding the recess as a charge storage area.
Another object of the invention is to provide a semiconductor memory
device comprising an array of cells formed at the cross-over locations of sur-
face word lines andtransverse buried bit lines with each cell providing an
increased charge storage capacity and greater speed than prior single trans-
istor memory cell devices.
Still another object o~ the invention is to provide a semiconduc~or
memory cell utilizing a single groove type of recess that is less complicated
and requires fewer steps to manufacture.
Yet another object o the present invention is to provide an improved
and more efficient method for making a semiconductor memory device.
Summary of the InventLon
According to one broad aspect of the invention there is provided a
semiconductor memory device comprising:
a substrate of a irst conductivity type material;
a plurality of elongated regions of a second conductivity type mater-
ial within sQid substrate forming bit lines;
cm epitaxial layer Oe lLgh~ly doped ~lrsk conduckivity kype ma~erial
covering said ~ub~krate and said ~longated reg-ions;
a serles oE recesses extendLng erom the surface Oe said epitaxial
layer and spaced apart along salcl elongated regions, each said reccss eormed
-2-
8~2
by sidewalls that extend into a sa:id elongated region;
a relatively thick field oxide layer extending over said epitaxial
layer and surrounding each saicl recess, said thick oxide layer forming a field
threshold barr:ier around the upper end of each said recess;
a series of parallel, spaced apart and elongated regions of conductive
material forming word lines on said field oxide layer, each said word line
extending transverse to said buried bit lines and between a series of recesses
and each said aligned recess;
means on said elongated bit lines near the lower end of each said
recess forming a cliffusion barrier;
and charge storage regions formed in the side walls of each said
recess between its said diffusion barrier and said field threshold barrier.
~ccording to another broad aspect of the invention there is provided
a method for manufacturing a semiconductor memory device including the steps
of:
providing a substrate of crystalline silicon material having P~ type
conductivity;
forming a series of spaced apart diffused strips of N~ type conducti-
vity material within said substrate to provide buried bit lines;
forming a diffusion barrier layer over said buried bit lines of P
type material that is less heavily P doped than said substrate;
forming an epitaxial layer on said substrate having a lightly doped P-
type conductivity that is less heavily doped than said diffusion carrier layer;
a~chin~ a plurality o~ spacqd ap~rt recesses w.lthln khe surface of
sald device which are align~d gc ~hat each rec,ess extends throu~h said epik~x-
ial layer into a said bit llne;
formln~ a relakively thick layer Oe o~lde material arouncl khe u~per
-3-
edges of said recesses; and
forming a series of conductive lines of conductive material on said
oxide material which are transverse to said buried bit lines, each said word
line interconnecting an aligned series of said recesses and covering the
sidewalls o:f each aligned recess.
A presently preferred embodiment of a memory device according to the
present invention and which accomplishes the aforesaid objectives comprises one
having an array of cells wherein each cell comprises an etched recess having
a V or U-shaped cross-section extending into the upper surface of a semicon-
ductor substrate The substrate,of a first conductivity type~ has at least one
buried bit line o~ an opposite conductivity type and the lower end of the re-
cess extends into it. Surrounding the lower end of the recess adjacent to and
above the b.uried bit line is a diffusion barrier for preventing the leakage of
charge from the remaining area around the sides of the recess. Within the re-
cess its sides may be covered with a thin gate-oxide layer in an IG~ETtype
structure. Alternatively, the walls of the recess could be covered directly
with a conductive material which forms a junction field effect transistor
(JFET)-like device. ~or the IG~ET device~ the oxide is covered with a conduct-
ive material that may be metal or poly-crystalline silicon. This conductive
material (for either case) forms a gate for the memory cell and also forms
a portion of an "X" line or word line that runs transversely to the buried bit
line or "Y" line. When used in a semiconductor device comprised of a large
number of word lines and buried bit lines a memory cell may be formed at each
intersec-kion or orQ~sover 4:~ ~hese lines. In e:Efec~, the area :~orming the walls
surr~unding each V or ll-shapc(l r~cess becomes a rela~ively large charge st~rage
region .~or th~ cell and the charge is kept within this area by an isolating
892
threshold barrier near the top and the diffusion barrier near the bottom of
each recess. In use, when it is desired to write into the cell, a voltage
is applied to the buried bit line and thereaEter another voltage is applied
to the word line, the latter vol~age being of such a nature that it will lower
the surface potential on the recess walls. This causes a thin layer of epitax-
ial material around the recess walls to function as a storage element and attain
a surface potential equal to that of the bit line below. When the surface pot-
ential on the word line is removed, the diffusion barrier between the buried
bit line and the charge storage region is now cut off so that the charge stor-
age region in the walls of the recess is isolated and separate. I'his charge
remains in storage until such time as the cell is read. To sense the charge
or read the cell a voltage of the proper polarity is once again placed on the
word line and causes an electrical connection between the charge storage region
and the bit line through the diffusion barrier. Thus, a certain amount of
charge determined by surface potentials and geometric factors is transferred to
the bit line which causes a certain potential differential between the existing
level and the original bit line level, which may be sensed by a differential
amplifier.
Other objectsJ advantages and features of the invention will become
apparent from the following detailed description presented in conjunction with
the accompanying drawing.
Brief De ~ e Drawing
~igure 1 is a schematic plan view of a portion of a semiconductor
memory device utilizing charge storage cells according to tho present invention;
~igure 2 is a viqw in cross section of one memory cell e~bodylng ~he
principles o~ the presqn~ invention;
~ig~lro~, 3a - 3~ are a series of views in crcss section showing the
5 .
, .
8~3~Z
method steps ~or constructing a memory cell according to the principles of the
invention;
~ igures 4a - ~c are a series of views in cross section showing some
alternate method steps for forming the lower diffusion barrier region according
to the invention;
Figure S is a view in vertical cross section of a modified form of
memory call according to the invention; and
Figure 6 is a view in vertical cross section showing another alternate
form of memory ceLl embodying the principles of the present invention and
utilizing a U-shaped recess.
Detailed Description of Embodiments
With reference to the drawing, Figure 1 shows a schematic plan view
of a semiconductor memory device 10 embodying the principles of the present
invention. The portion of the device illustrated comprises an array of memory
cells 12 formed at the intersections of parallel word lines 1~ and a series of
buried bit lines 16 oriented in a direction 90 to the word lines. Thus, in
the array, the memory cells are closely packed because the parallel word lines
and bit lines may relatively close together using conventional semiconductor
design rules, and each memory cell requires essentially only the area formed
by a word line and bit line intersection or crossover.
In Figure 2, the structure of a typical single memory celL 12 accord-
ing to the invention is shown in vertical cross-section. The entire memory
device is formed as an integrated circuit on a base semiconductor substrate
1~ of P nr N material. In the embodiment illus-~rated, the base substrQ~e is
crystalline silicon material having a generally uni~o*m thic~ness ~e.g~ ~S0
mier~ns). This ma~erial is provided with a P~ type conductivity by doplng it
with boron to lov~l of around lOLS ~o loL~ a~oms per eublc eontime~or.
-6-
892
The yarallel bit lincs 16, having an essentially uniform width and
spacing are formed of N+ material within the base substrate 1~. The thickness
of these bit lines is essentially uniform (e.g. around 2 microns) and the N~
type conductivlty, preferably with a concentration of around 1019 to 102
atoms per cubic centimeter, may be provided using a dopant with a small
diffusion coeffi~ient such as arsenic or antimony.
Covering the base substrate 18 and ~he buried bit lines 16 is an
epitaxial layer 20 of lightly doped P or P- material formed by`a standard
chemical vapor deposition (CVD) type of process. Along the interface o~
this layer 20 and the base substrate 18 is an intermediate layer 22, also of
P material, but more heavily doped P material than the epitaxial layer 20.
Extending downwardly from the surface of the epitaxial layer 20 at
each cross-over area of a word line and a bit line is a recess 2~ having a
V-shape in its vertical cross-section. These recesses are formed by an anis-
otropic etching process which has a low rate of attack along ~ planes and
a high attack rate on [100] planes, as described in United States Patent
No. 3,924,265. This etching process thus forms recesses 2~ with downwardly
converging side walls, and the lower edge of each recess formed by its con-
verging side walls extends into a buried bit line 16. With V-shaped recesses
the horizontal cross-section of each recess has a square or rectangular shape
and all of its sloping walls are covered with a thin gate oxide layer 26 of
silicon dioxide which also extends below the upper surface of a buried bit line
16. The word lines 1~ are ~ormed o~ a conductive material such as a suitable
matal or polycrystalline sillcon and each recess is subs~an~ially ~illed wlth
such conduct:ive materi.al.
The epitaxlal li~h~ly doped P-material 20 formin~ the sloping ~ide-
walls of ea~h V-shaped reGess 2~ comprise a char~e s-torage regiorl 2~ kllat
-7-
~118~392
cxtends completcly aro~nd the recess acljacent to the thin gate oxide layer 26.
As indicated by the dotted line in Figure 2, this charge storage region 28
may llave a shallow depth, but its charge capacity is relatively large since
it covers the area of all four sloping walls of each recess.
The upper edges of the gate oxide layer 26 te:rminate around the edges
of each V-shaped recess and at this point the thickness of the oxide increases
abruptly to form a relatively thick insulative oxide layer 30 that covers the
epitaxial layer 20 around the various recesses 24. This relatively thick oxide
layer 30 forms a barrier (indicated by the numeral 32) around the upper end
of each recess to help retain charge concentration within the sloped charge
storage region 28. This retention is based upon the effective surface poten-
tial under the thick insulator region 30 for the voltages used during the
operation of the cell.
Surrounding the lower end of each recess the relatively higher P
doped intermediate layer 22 tas compared with the epitaxial P-materlal) forms
a lower barrier for the charge storage area. I'hese upper and lower barriers
serve to retain the charge concentration of electrons within the storage re-
gions 28 formed in the sloped side walls of each recess. In accordance with
well known principles of field effect devices, the layers 22 and 30 are efect-
ive as barriers because of the quasi Fermi level in the silicon which prevent
the e].ectrons rom moving away from the walls of each recess, either along the
top surface 30 or into the top surface of the buried bit layer 16 at the
bottom of the recess.
In addi.tion to its barrier unction the interm~dia~e P layer 22 ser-
ves ~s a ~r~nsfer -region that helps to control the flow o~ elcctrons from th~
bit line into and out Oe the charge storage r~glon 28~ MoreoverJ ~his trans-
eer region or di~ usion ba~rier 22 is modul~,~ed ~y the ga~e portion of ~he
. ,~, "t
~i~L889Z
worcl line coverirlg the gate oxide layer within the recess.
In the operation of a memory cell 12 accord:ing to the invention,
wilen -it is desired to write into the cell a voltage is first appl;ed to the
appropriate b;t l;ne. Thereafter, a voltage ;s appl;ed to the word l;ne of
such a nature that ;t w;ll actually physically lower the surface potential of
the transfer region. That is, the positive voltage on the word line (and thus
on the gate of the cell) acts in essence to turn on the transfer region bet-
ween the bit line and the charge region 28. When this occurs, the charge
storage region will attain a surace potential equal to tha~ of the bit line
and thus the charge becomes stored there. Now, the surface potential in this
charge storage reg;on ;s controlled by the b;t l;ne 16. When the voltage or
surface potent;al on the word line ;s removed, thc flow of electrons between
the bit line and the charge storage region ceases. At this point, the surface
potential is isolated with;n this storage region. Since the charge storage
region 28 extends completely around the recess on all of the sloping wallsj
it thus covers a relatively large area, and accordingly its charge capacity
is also relatively high. Thus, when this write procedure is complete, a
strong, durable signal is locked into the memory cell.
When it is desired to sense the stored charge in a "read" mode for
the cell, to determine whether a "1" or an 1l0l- is present therein, the unction
of the elements is similar. At this point, the bit line is essentially "float-
ing" or at some intermediate potential that is predetermined and from which all
relative changes will be made. A positive value voltage is applied to the
worcl line which again causes the bit line to connec~ with the charge storage
reglon 2~. This causes ~he circuit to ~.ome to equilibrium wi~h some ~oten~ial
~:L~ecren~iail ~rom i~s origlnal po~ential occurrlng on the bi~ line which is
detec~abl~ by a suitable di~ferential sense circui-t on the dovlco.
,c)
',i
. ~ ,
389Z
Such a sense amplifier circuit is well known in thc art o~ memory devices
and therefore will not be described here in detail.
The aforesaid write and read functions o~ the memory cell 12 can
be expressed mathematically by applying the rules of conservation o~ surface
potential during the write-in phase and the conservation of charge during the
read-out phase and then the sensing of differential voltage in reading.
One method for producing the memory device 10 according to the pre-
sent invention may be best described by reference to Figures 3a to 3f. It
; is first necessary to provide the substrate 18 of crystalline silicon material
having a P~ type conductivity concen~ration of 1015 to 1019 atoms/cc. This
material must also have a crystallographic orienkation with the flOO] plane
at its surface so the V-type grooves or recesses can be ~ormed therein by an
anisotropic etchant.
To form a first mask, the substrate 18 is provided with a layer 34
of silicon dioxide which may be formed by oxidizing the substrate surface in
steam at 800 - 1,200 C. The oxide layer is then treated with a suitable
etchant (e.g. buffered hydrofluoric acid) to remove the oxide at the areas on
the substrate surface where the buried bit lines 16 axe to be formed. As
shown in Figure 3a, a dif~usion of N~ material (e.g. antimony~ in~o the sub-
strate is now per~ormed to ~orm a buried N~ layer 16 having a th:ickness o~
around 2 microns. The oxidation layer 3~ is then removed leaving the substrate
with a series o~ parallel N~ strips with the desired spacing on the substrate.
In the next step of the method, as shown in F;guxe 3b, an epitaxial
layer 20 of lightly doped P- material is ~ormed on tho substra~e sur~ace and
ovcr the N~ regions 16, This layer can h~ Porme~ by the ~hermal decomposi~ion
o~ silane ~Si~l~) at a t~mpera~ure o~ around ~00 - l,000C. in an cpitaxial
reac~or to a ~hickness oP a~ound 2.5 microns. During the applicatlon o~ this
-10-
f~,
519~
epitaxial layer 20 including the simultaneous heat treatment, an out-diffusion
of P matcrial from ~he P type substrate occurs which forms the interface bar-
rier layer 22 that extends for about 0.5 microns above the N~ buried layer.
Now, another oxide layer 36 is applied over the device and a second
mask is used to define spaced apart openings 38 directly above and in line with
the buried N+ regions. Vsing an anistotropic ctchant (e.g. hydrazine and water)
a V-type recess 24 is formed in the device at every opening above an N~ region~
the bottom of each recess penetrating into the buried N~ region, as shown in
Figure 3c.
Using a conventional oxidation procedure, a thin gate oxide 26 with
a thickness typically 500A to lOOOA is now grown within the recess 24. (See
Figure 3d).
Now the V-groove recess areas are masked, as further oxidation is
accomplished to provide the field oxide layer 30 surrounding each recess
(See Figure 3e).
Thereafter, another mask ~not shown) is utilized to form the conduc-
tive word lines 14 as shown in Figure 3f that extend from recess to recess and
perpendicular in orientation to the buried bit lines 16. Thc word lines may be
polycrystalline silicon or metal and covering them may be a suitable passiva-
tion layer (not shown) of some ef~ective insulative and protective material.
Contacts (not shown) may be provided from the surface of the device
by vias through the epitaxial layer 20 to the various bit lines where necess-
ary, ar~d in accordance with well known design principles.
As previously dHscri~od, the lnkereace layer 22 Oe P ma~erial provides
khe diefuslon harrior eor the charge region 2~. Other forms Oe khls die~usion
barrier may be provided wi~hin the scope Oe th~ present invention utilizing
some o~her diPeeron~ mekhod skeps. ~or examplel as shown in ~ rcs 4a to 4c~
-11-
;'
1118~9Z
the d;ffusion barrier may be formed by the diffusion or ion implantation of a
th;n P layer 40 clirectly on the N~ regions 16. This would be done just after
the N+ regions are formed using tho same mask 34 and before the epitaxial
layer 20 is grown thereon ~See Figure 4a~. Thereafter, the epitaxial layer
20 may be applied as previously clescribed (See Figure ~b). When the V-shaped
recesses are formed, the P layer ~0 on each N~ bit line 16 surrounds the lower
portion of each recess thereby performing its barrier function ~See Figure 4c).
Another form of diffusion barrier may be formed by providing a layer
of P material on all areas of the substrate other than the N~ regions. This
procedur0, however, requires the application of an additional mask after the
N+ regions have been formed. Subsequent heat treatment will cause the P
material to diffuse over the N~ regions surrounding each recess, thereb~ form-
ing another form of lower diffusion barrier.
In an alternate form of the invention the insulated gate field effect
transistor (IGFET) embodiment, just described, may be replaced by a junction
field effect transistor (JF~T) arrangement. In this latter embodiment, as
illustrated in Figure 5, no thin oxide layer is provided within the recess for
the cell. Insteacl, a suitable conductive material 14a, such as platinum or
some other metal is used for the word lines. Within each recess the metal is
applied directly to the recess walls and provides a Schottky effect to trans-
mit charge carriers. Here the function of the upper and lower barriers and the
surrounding charge storage regions is exactly the same as with the previously
described IGP~T version.
~l~hough khe inven~ion has been described in ~erms o~ embodimen~s
whe~eln s~id rqcesses Eormed anisentropic etching are V-shaped in cross-section,
i~ may al50 be em~odied in a $emiconductor clevice l~b wherein recesses 24b are
Eormed havlng a U-shapqd cros~ seG-~ion wi~h parall~l~ rathor ~han downwarclly
-12-
89Z
converging side walls. Such recesses are formed when the silicon wafer is
first cut with its hori7ontal surface in the rllO] crystalline plane and its
[111] planes perpendicular to the horizontal plane. As sho~ in Figure 6, the
U-shaped recess 24b, like the previous V-shaped recess 24 extends through an
epitaxial layer 20b and into a bit line 16b formed within a substrate 18b. The
device may have a thin oxide layer 26b within the recess as shown in the IGFET
version or it may have the Schottky type JFET construction similar to that
shown in Figure 5. Within the U-shaped recess is a layer of conductive
material 14_, such as polycrystalline silicon which provides a gate portion
of a word line. In the same manner as the V-shaped cell embodiment, an upper
charge barrier 32b is formed around the open end of each recess by a relatively
thick insulating oxide layer 30b. Also, a lower charge barrier is formed by
a thin P layer 22_ that covers the buried bit line region 16b around the lower
end of each recess. These upper and lower barriers control the charge storage
region in the parallel side walls of the recess 24b in the same manner as with
the V-shaped recesses 24, previously described.
To those skilled in the art to which this invention relates, many
changes in construction and widely differing embodiments and applications of
the invention will suggest themselves without departing from the ~pirit and
scope of the invention. The disclosures and the description herein are
purely illustrative and are not intended to be in any sense limiting.
r
