Note: Descriptions are shown in the official language in which they were submitted.
This invention relates to a multiplex communi-
cation system and is particularly, but not exclusively,
intended for use in motor vehicles.
Conventional practice iIl motor ~ehicles has been to
provide each powered device (light, horn, windscreen wiper
motor, etc.) with its own power Lead and associated drivex's
control switch, and to provide a number of warniny and
indicating instruments (Euel gauge, tachometer, oil pressure
warning, etc.) each connected to an appropriate sensor by
separate wiring. This gives rise to wiring loom~ of consi-
derable complexity and cost. It is also necessary to fabri-
cate and stock different wiring harnesse~ for each model o~
vehicle.
There have hithexto been a considerable number of
proposals to overcome these problems by using a common chan-
nel interconnecting all electrically powered devices and
monitoring devices with a central contxol station, informa~
tion being passed along the channel by multiplexing
techniques~ None of these proposals has yet been put into
2~ practice in volume vehicle production, principally for
reasons of ccst and/or complexity~ The factors which can
be identified as necessary for a commercially viable system
are: ~
(a) the system must be mechanically simple
and robust;
(b) the number of dif~erent components re-
quired must be kept to a minimum; -~
(c) the system must be sufficiently fast to
maintain information such as road and engine
speed sufficiently up to date in real time for
the purposes of the driver;
(d) it must be possible to control at least 50
Eunctions and to receive information from a sim~.lar
number o:E sensors; and
(e) there must be signal ~ecurity which prevents
spurious signals causecl by inter~erence effecting
erroneous operation of controlled devices.
Qf the systems previously proposed, some have been
too slow or have too small a channel capacity to be ~uitable
for use in vehiclas, while others have achieved the required
speed and channel capacity by using long trains o~ pulse3
at high repetition rates which requires the use of high
~requency components with attendant expense. Other systems
are unsuitable becau~e they require a number of signal-
carrying conductors~ which increases cost and the risk of
incorrect connection.
British Patent No. 1,427,133 to Clements et al
discloses electrical apparatus for monitoring the operational
parameters and controlling the operational functions of
a motor vehicle. The disclosed apparatus comprises electri-
cal devices space~d from one another in the vehicle, signaling
and powsr~supply lines, and devices coupled to both lines
and arra~lged to respond to a respective one of a group
of signals. The lnformation is conveyed along the signaling
line~and is~coded using pulse width and pulse amplitude
modulation tech~iques. The~apparatus employs a synchronizing
pulse at the beginning of a~pulse train and sensors and
operatlve uni~ts respond to~the varlous pulses in sequence.
A veri~fying cir~uit is used~to compare the width of appro-
prlate~successive~pulses. ~ ~
~; 30 ~ V.S. Patent~3,846,639 to Ueda et al discloses
a control system for a vehicle in which a transmitter re-
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sponds~to~clock pulsec to generate a pulse train including
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an index pulse and pulse~wid-th-modulatecl pulses arrangedin a
predetermined order resulting form respective signal pulses,
one for each device to be controlled or monitored. The
pulse train is transmitted by a single line to a plurality
of detectors. Width discrimination of the received pulses
is utilized to determine whether the associated electrical
device or monitor should be activated.
U.S. Patent 3,651,454 to ~enema et al discloses
a multlplex system for communicating control and power
between components and for monitoring certain conditions
of other components in a motor vehicle. A cable travelling
about the vehicle has separate power and signal conductors.
A clock signal source is coupled to the signal conductor. A
plurality of transmitters, which have delay means responsive
only to the clock signal for transmitting in de~inite time
channels de~ermined by t~eir delay and a plurality o~ re-
ceivers which have delay means responsive only to the clock
signal for receiving in only one of the definite channels,
are coupled to the cable so that transmitters and receivers
may contxol and activate different vehicle components pro~
vided for receiving the associated signal from the corres-
ponding unit. Figure 7 of this patent discloses a method
and device for connecting the receiving or transmitting unit
of the system to the cable. This apparatus is used for
tapping into the single cable in parallel to other units by
use o~ a pierclng plug.
U.S. Patent 3,864,578 to Lackey teaches a multi-
plexing system for controlling operation of vehicle com-
onents in~response to the operation of corresponding controls
by the operator of the vehicle. The system includes encod-
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ing means, decoding means and relay means. The encoding
means provi~e a timing signal and code siynal having signal
components corresponding to the positions of each of the
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vehicles's controls. The decoder means are remote from the
encoder means and are responsive to the signals selectively
to provide a plurality of outputs to the relay means in
response to the respective code signal components.
Other U.S. patents of general interest are
3,964,302 to Gordon et al, 3,544,803 to Taylor, 3,742,447
to Sognefest et al and 3,842,249 to Geyer et al.
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The invention ~ccordingly seeks to provide a communi-
cation system which overcomes or redllces the disadvantages
of the prior art proposals.
According -to -the invention there is provided an irnprvve-
ment in an information handling system of the type ~hich com-
prises a sign~ bus, a master s~tion arranyed to trans~it on the
signal bus pulse signals divided int~ serial information
frames, a plurality of sensors or controlled devices, a
plurality of peripheral stations having address decoding
circuitry, each connected to the signal bus for actuation in
response to a given information frame, and a connector
connecting each of the peripheral stations to at least on~
of the sensors or controlled devices.
The improvement comprises an address setting means in
the connector, the address setting means setting a code de
termining the information frame to which the peripheral
station associated with the connector responds, the
connector comprising a housing through which the signal
bus passes to facilitate electrical connection thereto, the
connector further including a printed circuit having
conductive strips located within the connector housing, the
conductive strips being drilled or punched to set the code
for the pexipheral station, and the connector housing having
contacts cooperating with the conductive strips and address
~;~ decoding circuitry of the peripheral station.
~; An embodiment of the present invention will now be
described, by way of example~ with reference to the accompany
ing drawings, in whicho
Figure 1 is a block diagram of an information handling
30~ ~ system for use in a motor vehicle;
~ igure ~ is a detailed circuit diagram of one of the
peripheral stations of Figure l;
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Figure 3 shows a typical pul~e train used in ~he
apparatus of Figures l and 2;
Figure 4 is a perspective view of a peripheral
station in posi~ion on a bus me~ber of the system;
Figure 5 is a plan vie~w, partly in section, o~ the
bus and peripheral station oE Figure 4 with a top cover of
the peripheral station removed;
Figures 6 to 8 and lO are more detailed circui~
diagrams o~ parts of the circuit of Figure 2; and
Figure 9 illustrates wave~orms in the circuit o~
Figure 8.
With reference to Figure l, the system has a power
bus lO in circuit with a storage battery 12. The power bus
10 is formed by a single conductor, the return circuit being
provided via vehicle ground. A signal bus 14 is associat~d
with the powex bus lO, and also comprises a single conductor~
The buses 10 and 14 are molded into a single insulating
sheath 16 (Fig. 4) to form a unitary bus member which may
readily be passed around a vehicle in a convenient route
A master station 13 i5 connected to the buses 10
and 14, and to a~vehiele control panel 20. Sixteen peri- ,
: pheral stations 22 are each connected to the buses lO and
14.: Each peripheral unit is connected by external leads to
up to four contro~11ed devices and up to foux sensors; by way
: of examplel one of the stations 22 in Figure l is shown
connected to a headlight HL, a direction ind1cator light DL~
: a temperature sensor TS and an oiI pressure sensor PS. The
conneations of the other peripheral stations 22 are not
shown,~for~clari~ty:of the drawing~
The contr~l panel 20 contains the usual control
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switches, warning lights, a~d instruments for use by the
driver. The master station 18 scans the driver-actuated
controls in a sequential manner and transmits a sixteen-
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frame si~lal which is acted upon by the perip~ral station~ to
activate or de-activate the devices and sensors. At the
same time, the outputs of sensors for functions such as oil
pressure, coolant temperature, road speed etc. are coupled
to the corresponding peripheral stations 22 and are then
repetitively called up by the master station 18, decoded,
and displayed as appropriate on warning lights and instru-
ments on the control panel 20.
Each of the sixteen peripheral stations 20 is res-
ponsive to a particular one o the sixteen ~rames of the com
plete scan signal trangmitted by the master s~ation 18.
Eight clock pulses occur during each but the first frame;
a four-bit counter in each peripheral station counts every
eighth of these clock pulses until reset by a synchronizing
pulse that occurs at the beginning of the first frame. When
a clock pulse causes the count in the four-bit counter of a
given peripheral station to correspond to a four-bit address
code applied to the station, the station responds to the
information and control provided by the master station during
the particular frame initiated by such clock pulse. If the
peripheral station addresses are sequential, then each new
clock pulse initiating a frame causes another of ~he peri-
: : pheral stations to respond to the information and control
of such framæ. After all sixteen stations have responded, the
sixteen-frame scan sequence is repeated.
:~ : The manner in which information handling is accom-
plished in the peripheral stations will now be discussed w~th
reference to Figures 2 and 3.
Figure 3 shows the voltage level of a typical
signal on the signal bus 14, The voltage at any instant
is controlled at one of four levels, labelled A, B, C and
D. Le:vel A is suitably tied to the vehicle voltage. The
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master station 18 includes a clock circuik which cyclically
generates synchronizirlg (sync) and clock pulses. Sync
pulses are set at level D and occur once per complete scan
(in this case 16 frames). Clock pulses are at level C and
subdivide each frame into equal time slots, in this
em~odiment eight in num~er. Information is conveyed by con-
trolling the signals within the time slots at levels A and
B.
With particular reference to Figure 2, the circuit
of a single peripheral station 22 ls shown. It ~hould be
noted that ~he stations 22 have identical circuitry. This
simplifies stockholding and installation and assists in
reducing costs. The circuit of Figure 3 has an input ~t
24 from the signal bus 14. The power bus 10 may be connected
to powered de~ices via parallel bistable gates 26 controlled
by the rem~er of the circuit. The signal input at 24
passes to an amplitude discriminator 28 which has four out-
putæ enabled respectively by signal levels C, D, (C or D),
and (B or C). The receipt of a signal at level (C or D),
i.e. a sync or clock pulse, causes an output pulse to be
passed to an eight-way selector 30 which in turn passes
every eighth of such pulses to a four-bit counter 32. The
bits of the counter 32 are connected in parallel to a decode
circuit 34. The decode circuit 34 has an address set exter-
nally, as will be described below, over leads 36.
It will thus be seen that the counter 32 is incre-
mented by ~very~eighth clock pulse. When the count held by
the counter 32 is that set via the leads 36, the decode
circuit generates an output on Iine 38 for one frame period.
~30 ~Line 3S is connected in parallel to gates G1-G8. These
gates are also connected to sequential outputs of the eight-
way selector 30, each output being enabled for one time
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slot pexiodO Thus, when the part:Lcular station 22 receives
an information frame corresponding to the address code
set, the gates Gl-G8 are sequentially enabled each for
one time slot.
Received signals of level (B or C) are passed by
the amplitude discriminator 28 to a pulse width discriminator
40 whose function is to separate the clock pulses, which are
of lesser duration, from time slot information. SignalB at
level B are passed by output 42 to gates Gl-G4 in parallel
and are then used, via a command and verify circuit 44 to be
described, to enable the gates 26. Ignoring for the moment
the command and verify circuit 44, the operation is thus
that the controlled devices connected to terminals 1, 2, 3,
and 4 are turned on by B-level signals in time slots 1, 2, 3,
and 4 respectively and are turned off by A-level signals in
these slots. Similarly, inputs from sensors connected to
terminals 5, 6, 7, and 8 are sequentially gated by gates
G5-G8. Such inputs may be either on/of~ or analog. The
gated sensor signals pass to a pulse width modulator 46 which
generates an output signal onto the signal bus 14 during time
slots 5, 6, 7, and 8. A typical set of oukput signals is
shown ~n Figure 3. Time slots 6 and 7 are occupied by
tell-back signals monitoring the condition of devices con-
trolled by the signals in time slots 2 and 3. Slot 6 repre-
sents an "off"tell-back signal and is wholly occupied by an A-level
signal. Slot 7 represents an "on" tell-back signal and is
wholly occup~ied by a B-level signal. Slots 5 and 8 are
exemplarily shown as carrying analog coolant temperature
and oil pressure signals. These are pulse width modulated,
~30~ the fraction of the time slot determined full scale de-
flection for that signal. The timing of the output of the
pulse width modulator 46 is synchronized with the time slots
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5-8 by C level or clock pulses switchecl by the a~plitude
discriminator over line 48.
The purpose of the command and verify circuit 44
is to provide signal security. This circuit operates in
conjunction with a sync detector 50 connected to receive sync
pulses from th.e amplitude dis~riminator 28. The sync
detector 50 is also co~nected to the four-bit counter 32 by
a line 5~. On receipt of the sync pulse, the counker 32
should reset to zero and the counter i9 gO canstructed that
on resetting it transmits a pulse over line 52 to the sync
detector 50. If both pulses arrive simultaneously, the sync
detector emits a gating pulse on line 54 to the command and
verify circuit 44.
The command and verify circuit comprises four
channels, each connected between one o~ the gates Gl-G4 and
the respective output terminals 1-4. One such channel is
shown in Figure 6. The signal from an associated one of
the gates Gl-G4 is supplied over line 55 and is held in a
resettable store 56, which may for instance be a bistable
multivibrator. The stored signal is compared with the next
: signal gated to that channel by a comparator 58. If the
two values agree, an enable signal passes by line 60 to a
gate 62. The gate 62 is also connected to receive the gat-
ing pulse on line 54 rom the sync detector 50, and to re-
~ ceive signals over line 64 from the pulse width discriminator
:~ :40. The ~irst of these is provided to block execution of
: ~ :commands where there is a failure of synchronism in the sys-
: tem, and the s~cond to ensure that a command signal is
passed only during a suitable time slot. Thus a command
signal will not be passed by the circuit 44 to the con-
trolled device lmless ~1) the sam~ signal is received twice
~:~ in succession and (2) the address decode is operating
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correctly in synchroni~m with the master station~ The
first of these is principally a safeguard against a signa.l
which is correctly timed but in which a positive pulse is
dropped, while the second is of particular use in dealing
with the case where an interfererlce induced spike appears
on the signal bus and produces lack of synchronism. If
either of these conditions is nol: met, the signal to the
appropriate gate 24 is blocked and the controlled device
continues in its preexisting state.
The sync detector 50 is also connected to the
four-bit counter 32 to reset the latter on receipt of a sync
pulse. (If the system is correctly in synchronism, the
counter 32 will also be recycling to zero of its own accord
at the same time).
It will be seen that this embodiment is capable
of controlling 64 functions and a monitoring 64 sensors.
Suitably, each information frame occupies 8ms, giving a
total cycle time of 128ms. Since two consecutive identical
signals are required to actuate controlled devices, the
maximum dPlay in switching on or off is 256 ms. Readouts to
the driver are updated every 128 ms. These speeds are
: sufficien~ly fast to be practically instantaneous from the
driver's point of view while not requiring high pulse
repetltion rates.
In Figures 4 and 5, one possible physical form
of peripheral station is shown. The circuitry is encapsula-
: ted in a housing 64 which is formed with a recess dimensioned
to accommodate the sheath 16. A cover 65 is hinged at 66 to
the houslng 64 and may be locked shut by spring steel arms
~; : 30 67. Connecting blades 68 extend from the housing 64 to
effect connection with the buses 10 and 14. In use, slots
~or the blades 68 are performed at suitable locations on
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hhe sheath 16 and the bus member i~ positioned in the ve-
hicle. At each sta-tion, a housing 64 is arranged in a
position to receive the bus member with the connectiny blades
in contact with the buses 10 and 14. The housing is then
secured to a vehicle body panel (not shown) as by self-
tapping screws 69 passed through a metal strap 70 secured
to the housing 64 and supporting the arms 67. The strap 70
and screws 69 suitably act as an electrical ground connector
and heat sink. When the cover 65 is closed, the peripheral
station also acts as a retainer Eor the bus member.
The connection to the associated devices and sen-
sors is via a flexible printed circuit 71. This is located
by means of pins 72 on the housing 64 passed through aper-
tures 73 in the flexible printed circuit 71. Contact strips
74 on the housing 64 are provided for connection to the
conductors of the ciruit 71. The housing 64 is also pro-
vided with contacts 75 connected to the address decode cir-
cuit 34. A corresponding number o~ conductive strips 77 are
formed on the circuit 71 and are interconnected at 79. The
address for a given station is encoded on its circuit 71 by
drilling or punching through selected strips 77 between the
position of the respective contact 75 and the interconnection
79. In the embodiment shown, ~ive strips 77 are provided,
enabling sixteen addresses to be encoded.
Figure 7 illustrates a preferred form of amplitude
discriminator. A resistor chain 76, 78, 80, and 82 is
connected across power supply lines 84 and 86. Supply line
86 is grounded and is thus at voltage level A. The resi.s-
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tors 76, 78, 80 and 82 are selected to give voltage levels
~ B,~ C and D at the resistor junctions, and these are fed as
inputs to respective comparators 88, 90, and 92. The input
signal on l1ne 24 is fed in parallel to the comparators 88,
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~l9687
90, and 92. The pre~ence of voltage levels B, C and D
is thus detected and results in an output at the respective
comparator, these outputs being gated an an exclusive-
OR gate 94 and OR gates 96 and 98 to give the requixed
outputs of C, D, (C or D) and (B or C~.
A preferred form of pul~3e width discriminator
is sho~n in Figure 8. The discriminator is required only to
differentiate wide and narrow pulses, and the waveforms
for each of these at warious points in the circuit are shown
in Figure 9. The (B or C) input from the amplitude dis~
criminator 28 is applied in parallel to a monostable multi-
vibrator 100 and an inverter 102. The monostable multivi-
brator 100 is arranged to give an output pulse duration equal
to that o the narrow "C" pulse. The outputs of these are
coupled to a NAND gate 104. Thus the input pulses to the
gate 104 are of the same duration for a received narrow
pulse and no output is generated at the output of gate 104,
whereas when a wide pulse is received, the low signal from
the inverter 102 is of shorter duration than the high signal
from the monostable 100, and the gate 104 gives an output
pulse for the time difference between the two. The waveforms
140, 141, 142 and 143 in Figure 9 appear at the correspond-
ingly numbered points in Figure 8.
Figure 10 shows a detailed circuit for the pulse
width modulator 46r The clock pulses from the amplitude
discriminator 28 are applied by line ~8 to a NOR gate 106.
The input signal from the appropriate one of gates G5-G8
passes to the base of a MOS gate 108. This input signal is
an analog representation of the parameter to be transmitted,
and acts to vary the xesistance to ground of the MOS gate
I08 and a serially connected resistor 110, thus varying the
.
~ time constant of an RC circuit cvnstituted by these and a
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capacitor 112. The other input of the NOR gate 105 is
connected by a feedback resistor 114 -to the junction point
of the resistor 110 and capacitor 112. This point is also
connected by a resistor 116 to the output of the NOR
gate 106, both being coupled to the input of an
inverting amplifier 118. The action of the circuit is as
follows. On receipt of a "C" pu.lse on line 48, the output
of the NOR gate goes low and the circuit output from the
inverting amplifier goes high. After a time delay set by
the ~C constant o~ the elements 108, 110, 112 ( and thus by
the input signal at the base of the MOS gate 108), the out-
put of the NOR gate switches to a high state and the circuit
output goes low. Hence the value of the signal at the mod-
ulator input is represented in the signal bus waveform
(Figure 3) by the ratio of the high-level signal duration
to the total slot time between the two appropriate clock
pulses.
The master station 18 may readily be realized by
those skilled in the art with well known techniques, and
will therefore not be described in detail. It will be
appreciated that it includes a suitable clock circuit
generating "C" and "D" level pulses repetitively, and gating
means ~or scanning control sw.itches on a repetitive basis.
Returning signals from remote analog sensors may
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sui-l-ably be demo{~ ated to analog vo].taye siynals ~nd
a~plied to voltmeter-type instrumeIIts; this is suitable
for parame-ters such as road speec1, engine speed a~d fuel
contents.
The four-level pulse format of the present invention
permits the required amount of information to be carried
withou-t the use of unduly long pulse trains and/or repetition
rates. Moreover~ all signal detec-tion can be based on
ratios rather than absolute values, and control of supply
voltages is there~ore not critical.
It will be seen that the invention permits the use
of identical peripheral sta-tions whose addresses can be
set by simple plug-in means, with consequent simplification
of manufacture, ~tock holding and production control.. The
address setting means may take different forms from the
printed circuit described above. For example, the peripheral
station may be connected to its associated devices via
individual leads and a multi-contact plug and socket, the
address being set by interconnections between conductors
in the plug ox socket.
The invention also provides a peripheral station
including a verifying means which nullifies the effect
of fai.ures in ~ ignal t ranSmi ~s ~c~n, not c~nly
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those where signal pulses are lost or di'~torted but also
those due to interference causing spurious pulses or length-
ening of the pulse train.
It will be appreciated that modifications may be
made to the embodiment described within the scope of the
invention, as defined in the clalms. For instance, the input
on the line 64 to the command and verify circuit 44 may be
taken directly from a suitable OlltpUt of the amplitude
discriminator rather than being derived by pulse width dis~
crimination. The four~bit counter 32 could be fed directly
by a "D" output of the amplitude discri.minator. The inputs
from sensors may be omitted, together with the corresponding
gates and the modulator 46, where only a control function is
desired.
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