Note: Descriptions are shown in the official language in which they were submitted.
$~3'7
Backgro _d and Summary
Prior art logic analyzers provide merely for enabling
the storage of input data states in response to a selecked
number of satisfactions of a single pre~elected ~ualifier
state condition and for the storage of data states satisfying
a second qualifier state condition. Display modes have
comprised formatted listLngs or cerkain vector mappings based
solely on the entire data state stored.
The preferred embodiment of the present invention
incorporates multiple triggering circuits known in the art as
pattern recognition circuits (see, for example, U. S. patent
4,100,532, William A. Farnbach, issued 3uly 11, 1978). These
triggering circuits provide output signals in response to an
input data state satisfying one o~ the pre-selected qualifiex
state conditions. A counter and related sequencing loyic is
coupled to a first set of triggeriny circuits to deterrnine
when the stora~e of input data stat~s should be enablecl. A
~eparate triggering circuit provide~ a signal to the sequenc-
ing logic for restarting the enabling sequence in response
to the detection of a restart state condition. Storage of
data states is further qualified by a second set of trigger-
ing circuits. The output of this set is logically OR'ED
and supplied to the memory logic so that only data state~
meeting one of the pre-selected state conditions are stored.
A second memory is loaded in parallel wi~h the storage of
a data state into the first memory. The data loaded into
the second memory comprises the content of a binary counter.
The binary counter can be coupled to either an internal clock
so thak the time relationship between stored states cc~n
be determined, or alternatively, to a count trigger circuit so
.. '~., ~
that the counter can count occurrences of a predeflned
data state. The count triggering circuit allows for
the determination of the number of occurrences of the
input data states satisfying a count qualifier state
condition intermediate to the storage of selected data
states.
Input data states can be formatted by assigning
certain contiguous sets of bits to letter labels. Each
label is subsequently treated as an independently addressable
field and an independent radix can be selected for each
label. Subsequent operation and references to the input
data are now made by referring to these labels. In the
tabular display the label fields are concatenated in
alphabetical oraer.
An alternate graphical display plots the binary
magnitude of the stored bits corresponding to a selected
label field as a function of the respective location
in storacJe.
In accordance with one aspect of this inventlon
there is provided apparatus for displaying a digital
signal representing a sequence of data states, the apparatus
comprising:
input means coupled to receive the digital signal
for producing output signals representative of the data
states of the digital signal;
selection means for selecting a ~ualifying state
condition;
qualifier means coupled to receive the output
signals from said input means and coupled to the selection
means for producing an output signal upon the occurrence
of a data state exhibiting a s~lected qualifyin~ state
condition;
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storage means having a first input coupled to
receive the output signals from said input means and
having a second input for receiving the output signal
from said qualifier means for storing signals represen-
tative of the signals appearing on the first input in
response to a signal appearing on the second input;
format control means for selecting sets of con-
tiguous bits of each data state as logical fields, con-
catenations o~ the logical fields, radices for the res-
pective logical fields and for producing an output indicativeof the selections;
converter means coupled to said storage means
and to the format control means for producing a formatted
signal representing the stored signals of said storage
means formatted in response to the output of said format
control means; and
display means coupled to the converter means
for providing a visual di.splay of the formatted signal.
In accordance with another aspect of this invention
there is provided a method for displaying selected data
states of a digital signal in logical fields, the method
comprising the steps of:
selecting a qualifying state condition;
detecting a data state satisfying the selected
qualifying state condition;
storing signals representative of digital signals
having a predetermined relationship to the detected data
state;
selectively as~igning bits of the stored signals
to logical fields; and
displaying representations of the assigned bits
in a format distinguishing the selected logical fields.
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Description o the Fi~
Figure 1 illustrates the interactive format
specification display.
Figure 2 illustrates the interactive txace
specification display.
Figure 3 illustrates a trace list display of
the stored data statesO
Figure 4 illustrates a trace graph display of
the stored data states.
Figure 5 illustrates a trace compare output
display list.
Figure 6 illustrates the input keyboard.
Figure 7 illustrates a block diagram of the
present invention.
Figure 8 illustrates the distributed memory
addressing of the present invention.
Figure 9 illustrates the relationship between
physical and loglcal addresses of the distributed memory
of Figure 8.
Figure 10 is a block diagram of the acquisition
system.
Figure 11 illustrates a multiple pattern recog-
nition unit.
Figure 12 illustrates a simplifie~ sequential
triggering circuit.
Figure 13 illustrates the measurement and control
module.
Figure 14 illustrates the data format of the
data memory.
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Figure lS illustrates the forlnat of ~he label ~ormat ~
Figure 16 illustrates the logic flow of the display formatting logic.
Format Specification
Data formatting permits the partitioning of 32 input data channels
into parameters of interest. Contigious data channels which behave as a
single paramete; may be assigned to one of six labels (A-F). For example,
. in Figure l, illustrating the interactive format specification display, 16
bits of an address bus have been assigned to label "A"~ 8 bits of a data
bus have been assigned to label "D", 1 bit of data on pod l has been assigned
to label "F"7 and 7 bits have been left unassigned (labeled "X"). Further
specifica~ions and data manipulations are made by referencing these labels.
Each assigned label may be independently declared to have a posltive or
negative "logic polarity" and converted to an independently selected radix
which can be binary, octal, decimal or hexedecimal. Further, the slope of
the positive or ne~ative clock transition at which time ~he input data
channels are sampled can be selected ("clock slope").
Keyboard entries to the microprocessor 800, as shown ln Figure 16,
permit the constructlon of the label format filei shown in more deta~l in
Figure 15 which,contalns the -format speclfication parameters. Th1s is used
to process the stored data states in the construction of the alphabetically
cancatenated ASCII display data file and the graphic display data file.
Either of the display data files is subsequently selected and used for dis-
play purposes by the display control module 700 and the CRT display looo.
Trace Specification
The assigned input data channels are sampled at the specified clock
transitions and are treated as one sampled state. The trace specification
defines which of the sampled states are to be stored for display and which
sampled states are to be counted for count measurements. The trace speci-
fication comprises a definition of state conditions specifying the trace
position, the selective trace, and the count measurement. Each state
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condit;on deFines a state of the assigned input data channels 1n any combin-
,ation of l's, O's, and/or X's (don't care). In octal, decimal or hexedecimal
bases the definition is defined in terms of the appropriate alphamumer;cs
and X's.
A trace position may be selected to a start, center or end the select-
ive trace in response to the input data satisfying a predefined state sequence.
In this description it will be assumed that the trace position starts the
selective trace. A state sequence of up to seven state conditions must
be satisfied in a specified order~ ignorins intermediate states which do
not satisfy the state sequence. The simplest state sequence is a single
state condition. Specific segments of branched, looped or nested Forms of
state flow may be directly located by properly defined state sequences. In
addition5 each state condition in a state sequence may be specified to
occur from 1 to 65536 times before the state condition is satisfied. This
form of positioning will locate the nth pass of a loop beginning at a give
state condition. Clock delay may be incorporated by defining the nth
occurrence of any state (an all don't care state specification). The trace
logic may also be specified to restart the satisfaction of the predeflnecJ
state sequence if it is not satisfied before or concurrently with the
;20 location of a predefined restart state condition. A restart on "any state"
requires that the s~ate sequence be satisfied without any unspecified inter-
mediate states. For example, Figure 2 illustrates the interactive trace
specification display for a trace position starting upon the satisfaction
of 4 state conditions in sequence. A restart state condition is also defined.
The selective trace is a qualification of which sampled states will
be stored for display. One to seven state conditions may be "OR" specified
for collection. Selectively tracing only sampled states of interest elim-
inates the clutter of unneccessary states and magnifies the apparent si~e
of the trace beyond its 64 terms. Also, an occurrence term may be specified
so as to store only every nth satisfaction of an "OR" specified state cond-
ition. Flgure 2 illustrates the selective trace of every occurrence of d
single state condition.
The count measurement performs a "~ime" or a "state" count associated
with each of the (64) states stored and can be displayed in one of t~lo for-
mats:
absolut~ -- the count from the trace position
relative -- the count from the previous trace state
The time count is performed by counting the occurrences of an internal
clock betweén sequentially stored states and the display is in the units of
seconds. A state count similarly counts the number of occurrences of a
specified state condition ("count") between sequentially stored states. For
example, specifying "any state" would result in a count of the selected clock
transitions of the input data. In Figure 2, a state count is performed on
the occurrences of a specified state condition intermediate to each sampled
state stored.
Internal Measure~ent Storage
One complete measurement of 64 sampled sta-tes, which includes the
sampled states satisfying the state conditions defining the state sequence
and specifications of the ~ormat, trace, and display, may be internally
stored. The "current measurement" may be stored or exchanged
with a "stored measurement" for later analysis. A "trace compare" (described
more fully below) compares results of a previously stored trace with the
current measurement and may be utilized as a further qualifier on data storase.
Display Speci~ication
The output display format of the current measurement may be selected
from a trace list, a trace graph, or a trace compare.
A trace list, illustrated in Figure 3, displays a listing of the
stored states in their order of occurrence. Twenty trace states, (one per
line) are simultaneously presented on the CRT display. The "ROLL" keys allow
scanning of the 64 stored states. Each line comprises a line number, the
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stored state alphabetically sorted into assigned labels in thelr nulner;cal
base, and the time or state count if selectedO
A trace graph, as shown in Figure 4, presents a graph of the data
magnitude of a specified label versus the storage location for all 64 stored
states. Each state is given a vertical displacement corresponding to its
binary magnituae and an increasing horizontal displacement for successive
states in order of their occurrence. The result is a waveform analogous
to osc;lloscope displays of voltage magnitude. The label to be graphed is
selected by specifying the "graphed label". Scaling of state magnitude is
controlled by specifying the "upper limit" and "lower limit" on the vert-
ical axis. Limits can be specified directly or dynamically varied with
logrithmic autoranging controls. These facilities allow any portion of a
graph to be magnified to a full scale presentation. The 20 points corres-
ponding to the lines viewed in the trace list are in~ensified. The inten-
sified poriton also responds to the "ROLL" controls, and their corresponding
absolute value may be read in the trace list.
A trace compare as illustrated in Figure 5 presents a tabular 1isting
of the difference between results in the "current measurement" and the data
in the "stored measurement". The listing is formatted and rolled as ln the
trace list. The results of the two measurements are exclusive "ORED" such
that identical corresponding bits are displayed as zeros and unequal bits
are displayed as ones. In an octal base a "~3" is equivalent to a binary
"~0p ~ll" and indicates that the right two bits are different in the two
measurements. Trace compare also offers a "compared trace" mode which re-
runs a measurement until the current and stored measurement are either
equal or not equal. (STOP =, or STOP ~) For example, in Figure 5 of the
instrument has rerun trace measurements until the "current measurement"
equaled the "stored measurement", as indicated by the "STOP =" specifi-
cation and revealed by the array of "O"'s in the comparison.
TRACE MODES
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Three trace mode opt10ns are provided. "Trace" executes a sing1e
current measurement. "Continuous trace" repeats the execution of a current
measurement continuously. "Compared trace" repeats the execution of a current
measurement until the desired comparison with the stored measurement is ob-
tained.
CLOCK ENABLE AND TRIGGER OUTPUTS
A trigger output provides a triggering pulse for external instrumenta-
tion such as oscilloscopes. A 50 ns pulse is generated each time the trace
position is found. The clock enab1e output is useful for gating clocks or
~10 interrupting the devlce under test. A high signal level indicates that the
instrument is actively searching for the trace position. It remains at the
high signal level until the trace position has been found or the halt key is
depressed. Both outputs are suspended when the format specification is
displayed to allow measurement of channel activity.
KEYBOARD AND SPECIFICATION DESIGNATION
Referring to Figure 6, an illustration of the keyboard, the keys are
functionally segregated into four bloc~s, the "current measurement display",
"entry", "edit", and "execute". A power up sequence Initially defines a
; default set of specifications, displays the default format specification~
then automatically selects a hexadecimal trace list display. Activation
of the "ROLL DISPLAY" keys permits the presentation of any portion oF the 64
states stored. To change the format specification, the "FORMAT SPECIFICATION"
key is pressed. The cursor keys in the edit block are used to move the
cursor, designating a selectable entry field by a blinking inverse video
field on the interactive display.
The trace specification can be edited by selecting the trace specifi-
cation interactive display by activating the "trace spec1fication" key.
Editing is accomplished in the same manner as the format specification is
edited. A general description of the functions of the individual keys is
given in Appendix A. A detaiTed description of the interactive display entry
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fields ~s given in Appendix B.
DETAILED DESCRIPTION
Input states are sensed thro~gh 32 high impedance variable ~hreshold
data probes a~ rates up to 10 MHz. The data probes 100, illustrated in
Figure 7, are segmented into four 8 bit data pods and a fifth pod for clock
sensing. Each pod may be preset to TTL logic threshold or variably adjusted
in the range of +10 to -10 volts to interpret input logic levels.
The 32 input data channels and the clock signal from the data probes
100 are input to the state recognition module 200. An internal sampling
c10ck is generated in response to the selected clock slope~ the input data
signals are compared to the selected threshold voltages and interpreted,
and the data signals are latched in response to occurrences of the internal
sampling clock. The state recognition module 200 outputs the sampled state
to the high speed acquisition system bus 500. The index module 300 accesses
the sampled state on the acquisition system bus 500, compares the sampled
state to the selected state conditions and determines the trace position,
selective storage events and state count events. The measurement control
module 400 also accesses the acquisltion system bus 500 and stores state or
time counts and sampled data states in response to the events detected by the
index module 300.
The modules of the acquisitlon system 250 communicate with other
system modules via the communications bus 600, which prevides a means for
addressing selected modules and for transferring selected data. The entire
system functions as a distributed memory, as illustrated in Figure 8. For
instance, addresses between 1800 and lFFF on the communications bus 600
access the state count measurements and the sampled data states stored in
the measurement control module 400 memories. Figure 9 shows another re
presentation of the system architecture~ illustrating the relationship between
the physical couplings of Figure 7 and the logical addresses of Figure 8.
Referring to Figure 10, the index module 300 detects the trace
position by first comparlng the sampled stake on the
acquisition system bus 500 with a ~ualifier state condltion
stored in the multiple pattern recognition unit 315.
The muItiple pattern recognition unit 315 comprises a
digital pattern triggering circuit as described in U.S.
Patent No. 4,100,532, William A. Farnbach~ issuea July
11, 1978. As illustrated in Figure 11, the multiple
pattern recognition unit 315 comprises 2 pairs of 8 sixteen
by four bit memories providing for the detection of up
10. to eight qualifier state conditions, where each qualifier
state condition is identified by a 1, 0, X input, format
(in binary). Pattern selector 325 of Figure 10 selects
; one of the eiyht lines output from the multiple pattern
recognition unit and passes the selected output to the
occurrence counter 345. The occurrence counter 345 counts
the occurrences of the selected ~ualifier state conditions
and provides an output in response to counting a speci~ied
number of occurrences of the selected qualifier state
condlt:lon. This output is termed a "break event" and
the seguencer logic 350 in response requests the pattern
selector 325 to select the next sequential qualifier
state condition and requests the occurrence counter
345 to select the corresponding count~ The sequencer
logic 350 also outputs a "N-l" event flag in response
to detection of the occurrence of the "MEXT TO LAST BREAK
EVENT". A simplified sequential triggering circuit is
illustrated in Figure 12 where the multiple pattern recog-
nition unit 316 incorporates the functions of the multiple
pattern recognition unit 315 and of the pattern selector
3250 The sequence logic 351 incorporates the functions
of the se~uence logic 350 except that the final tri~ger
is output in response to the completion of the state
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se~uence. Another method of implementing the rnultiple
pattern recognition unit 316 would be to have 3 selector
bits be the most significant bits in the address, allowing
the comparator to sequénce through various segments of
memory when comparing sequential state conditions of
the state sequence.
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; lL ~ilrZ~ ~ 37
Referring again to Figure lO, the se1ective trace is incorporated in
a similar manner except that the trace selector 320 of Figure lO can "OR"
any combination of the A~lE lines. A trace occurrence counter 340 ou~puts
a trace event flag upon counting each "nth" "ORED" AME event.
The restart unit 310 causes the sequence logic 350 to restart the
satisfaction of the state sequence subsequent to the detection of a selected
restart state condition. The restart unit is disabled for the da~a state
corresponding to the detectlon of a break event by sequencer logic 350 which
; permits the state sequence to be sa~isfied without any unspecified inter-
~ediate state by setting the restart state condition to "any state".
The state count unit 305 strobes a counter in the measurement control
module 400 each time the selected state condition to be counted is detected.
The measurement and control module 400 is illustrated in Figures 10 and 13.
The event flags from index module 300 are input to the high speed control
460 and determine which sampled states on the acquisition system bus 500
are to be stored. The high speed control 4~0 addresses the data memory 410
and the coun~ memory 420 accordingly. F~gure 14 illustrates the dàta for~at
; of the data memory AlO. The sampled state conditlons resulting in break
events are sequentially stored in locations l- (N-1). Upon detection of the
"N-l" event flag, sampled state conditions are sequentially written into
the remaining memory locations, writing over the oldest data when the me~ory
is filled. The trace position address of the memory location containing
the state condition resulting in the final trigger is stored in a register
and sampled states are written into the appropriate number of remaining
storage locations. For example, if the trace was defined to end on the
detection of the trace portion, no sampled states would be written sub-
sequent to the detection of the trace position. The order of occurrence of
the stored data is easily reconstructed by recovery of the trace position
address appearing on the communications bus 600 as illustrated in Figure 8.
Count selector and synchronizer 450 controls the measurement counter 430,
,
`s ~
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whose contents are stored in count men~ry 420 upon update o~ the melTIory
address. The low speed control 480 provides a low speed interface for
programming the high speed control 460 and for selecting and latching
data for the comnlunications bus 600 interface.
The strobe generator 400, illustrated in F;gures 10 and 13, generates
a sequence of strobes which, when coupled with a series of data lakches
(not shown) and timing logic (no~ shown) effectuate the orderly performance
of machine tasks. In effect, a number of sampled states are simultaneously
in various stages of processing at any one time and are "pipelined" through
the required loyic blocks.
Active Channel Determination
Referring to F~o7~rZr, the symbol "!" appears below certain assigned
input data channels in the format specification. Approximately once every
millisecond the sampled state is compared to a "last sample" buffer. The
states are exclusively "ORED" to detect any bit changes. The result is
then "ANDED" with an activ;ty buffer and the sampled state input to the
"last sample" buffer. After 100 samples the activity buffer ls sampled for
display purposes. Only the assigned channels are displayed. Absence of a
"!" indicates low channel activity and is a yood indicator that a pod clip
~y have fallen off during the measurement or the channel is otherwise sus-
pect.
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APPENDIX A
GENERAL DESCRIPTION-KEYBOARD
CURRENT MEASUREMENT DISPLAY
LINES 3 THROUGH 24 ARE DEPENDENT ON DISPLAYED MENU CHOSEN, WHICH MAY BE
SELECTED BY KEYS IN CURRENT MEASUREMENT BLOCK:
FORMAT SPECIFICATION SELECT CLOCK SLOPE AND FORMAT 32 CHANNELS
INTO LOGICAL LABELS AND DESIRED LOGIC
POLARITY AND NUMERICAL BASE.
TRACE SPECIFICATION DEFINE TRACE POSITION, SELECTIVE TRACE
AND COUNT MEASUREMENT.
LIST DISPLAY RESULTANT CURRENT TRACE AND COUNT
DATA.
GRAPH GRAPH RESULTANT CURRENT TRACE DATA FOR
SELECTED LABEL. THE 20 INTENSIFIED DOTS
CORRESPOND TO TRACE LIST DATA.
COMPARE DISPLAY "EXCLUSIVE OR" OF VALID CURRENT
VS DATA WITH VALID STORED DATA, AND SELECT
STORE COMPARED TRACE MODE.
ROLL DISPLAY VIEW TRACE LIST OR TRACE COMPARE DATA.
TRACE GRAPH SHOWS INTENSIFIED DOTS THAT
GRAPH GRAPH REPRESENT THE TRACE LIST DATA DISPLAYED.
ENTRY
ALL PROGRAM ENTRIES ARE MADE IN INVERSE VIDEO FIEl.DS AT THE BLINKING
; CURSOR, AND MAY BE CHANGED BY ENTRY BLOCK OF KEYS:
FIELU SELECT ~ ALL FIELDS ENCLOSED WITH BACKETS ~ ARE
CHANGED BY THIS KEY. THE 161~A SELECTS
ONLY ALLOWED CHOICES.
0-9~A-F,X ALL OTHER FIELDS MAY BE CHANGED USING
THESE KEYS.
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GENERAL DESCRIPTION-KEYBOARD
EDIT
DISPLAYED MENUS MAY BE EDITED BY EDIT BLOCK OF KEYS:
DELETE INSERT USED IN TRACE SPECIFICATION MENU ONLY
TO OPTIONALLY DELETE OR INSERT STATES
TO SPECIFY TRACE POSITION AND SELECTIVE
TRACE. A MAXIMUM OF 6 STATES MAY BE USED
BETWEEN TRACE POSITION AND SELECTIVE
TRACE.
DEFAULT RETURN DISPLAYED MENU TO KNOWN ~PRESET,
TRACEABLE) CONDITION.
INOR DECR USED IN TRACE GRAPH ONLY TO AUTOMATICALLY
CHANGE UPPER OR LOWER GRAPH LIMITS.
TO MOVE BLINKING CURSOR TO DESIRED FIELD.
EXECUTE
THE REMAINING KEYS ARE THE EXECUTE BLOCK OF KEYS:
-~ CURRENT MEASUREMENT KEY SA~ES CURRENT SPECIFICATION AND~-~ DATA MEASUREMENT IN A STORED FILE. THE
STORED MEASUREMENT CURRENT SPECIFICATION AND DATA REMAINS
UNCHANGED.
;~ KEY EXCHANGES CURRENT AND STORED
MEASUREMENT FILES.
, .
PRINT PRINT CURRENT DISPLAY, EXCEPT TRACE GRAPH
ON AN HP 9866 LINE PRINTER USING CONNECTOR
ON REAR OF 1610A. TRACE LIST AND TRACE
COMPARE WILL PRINT CURRENT PAGE AND ANY
REMAINING DATA IN MEMORY.
` TRACE EXECUTES CURRENT SPECIFICATION, AND IF DIS-
PLAY IS FORMAT SPECIFICATION OR TRACE
SPECIFICATION, THE 1610A SWITCHES DISPLAY
TO TRACE LIST.
IF TRACE IS HELD DOWN, THE MEASUREMENT IS
; TRACED CONTINUOUSLY.
IF COMPARE TRACE MODE IS SET FOR [STOP=]
OR [STOP#] THE MEASUREMENT IS TRACED
UNTIL COMPARED CONDITION IS MET. THE
INSTRUMENT STATUS (lST LINE) IS
"COMPARED TRACE-FAILED", IMPLIES CONDITION
NOT MET, OR "COMPARED TRACE-COMPLETE",
IMPLIES CONDITION MET.
STOP STOPS ANY MEASUREMENT TRACE, COMPARED TRACE
OR PRINT IN PROCESS.
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APPENDIX B
DETAIlED FIELD/S DESCRIPTION
CLOCK SLOPE:
EXAMPLES: CLOCK SLOPE [+~
CLOCK SLOPE ~-]
PURPOSE: TO SELECT CLOCK TRANSITION TO STROBE POD DATA INTO 1610A.
A -15~
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1~6~3~7
DETAILED FIELD/S DESCRIPTION
LABEL ASSIGNMENT AND ACTIVE CHANNELS:
EXAMPLE: POD4 POD3 POD2 PODl
7~ 7------0 7--- - ~ 7 0
M AAAM A M M AAAA DDDDDDDD XXXXXXXF
!!!!!!!! !!!!!!!! !!!!!!!! !
ACTIVE CHANNELS
PURPOSE: TO ASSIGN LABELS A, B, C, D, E OR F TO ANY NUMBER OF
CONTINUOUS CHANNELS INDEPENDENT OF POD BOUNDARIES.
IN THE ABOVE EXAMPLE THE LABEL A
IS ASSIGNED TO 16 BITS OF POD3 AND POD4, AND MAY
REPRESENT A 16 BIT ADDRESS. LABEL D IS ASSIGNED 8 BITS
ON POD2 AND MAY REPRESENT AN 8 BIT DATA BUS. LABEL
F IS ASSIGNED TO BE A SINGLE BIT QUALIFIER (READ,
WRITE) AND IS ASSIGNED TO LEAST SIGNIFICANT BIT ON
; PODl.
ANY UNUSED CHANNELS MAY BE TURNED OFF BY PUTTINGAN "X"
IN GIVEN CHANNELS.
- COMMENT: AS MANY AS SIX LABELS OR AS FEW AS ONE MAY BE ASSIGNED
ACROSS THE 32 CHANNELS. IF A LABEL IS SPLIT, SUCH AS
,~
AABBBAAA (LABEL IS NOT CONTINUOUS)
THEN AN ERROR MESSAGE "ERROR-SPLIT LABEL" IS DISPLAYED
AND THE CURSOR IS LOCKED TO LABEL ASSIGNMENT FILEDS UNTIL
THE ERROR IS CORRECTED.
PRESSING UEFAULT KEY WILL ASSIGN LABEL F TO ALL 32
CHANNELS.
ACTIVE CHANNELS ARE SHOWN BY "!~' MARKS FOR EACH ASSIGNED
CHANNEL. ABSENCE OF "!" INDICATE LOW CHANNEL (BIT)
ACTIVITY, AND ARE GOOD INDICATORS OF POD CLIPS THAT MAY
HAVE FALLEN OFF. CHANNEL ACTIVITY IS NOT
DISPLAYED WHILE 1610A IS TRACING.
IF POD IS CONNECTED TO DATA PORT ON REAR OF 1610A,
THE CHANNEL ACTIVITY "!" FOR LEAST SIGNIFICANT 2 BITS
IS NOT SHOWN (DUE TO SYNCHRONOUS 8 BIT COUNT AND
1610A).
.
r
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DETAILED FIELD/S DESCRIPTION
LOGIC POLARI N :
EXAMPLE: LABEL A D F
LOGIC POLARITY (-) (-) (+)
(, )
PURPOSE: TO SEL~CT A IOGIC POLARITY FOR E~CH ASSIGRED LABEL.
: ~
.
~ -17-
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DETAILED FIELD/S DESCRIPTION
NUMERICAL BASE:
EXAMPLE: LABEL A B F
NUMERICAL BASE(HEX) (OCT) (BIN)
(BIN,OCT DEC,HEX)
` PURPOSE: TO SELECT A NUMERICAL BASE TO BE HEXIDECIMAL (HE~),
: OCTAL (OCT~, DECIMAL (DEC), OR BINARY (BIN) FOR
EACH ASSIGNED LABEL.
'`,
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X~3r7
DETAILED FIELD/S DESCRIPTION
TRACE POSITION:
EXAMPLE: (START ) TRACE
~CENTER) TRACE
( END ) TRACE
PURPOSE: TO SELECT TRACE POSITION TO BE SOME GIVEN STATE
AND ITS POSITION IN RESULTANT DATA TRACE FILE
SHOULD BE AT (START) FOLLOWED BY SELECTIVE TRACE
: STATES, OR AT ~CENTER~ SHOWING ANY SELECTIVE STATES
BEFORE AND AFTER "CENTER STATE", OR AT (END)
SHOWING ANY SELECTIVE STATES BEFORE THE "END STATE".
` EXAMPLE LABEL A OCCUR
BASE HEX DEC
FIND IN SEQUENCE 10 00001
THEN 2p 00001
THEN 30 00005
(START~ TRACE 40 0
SEQ. RESTART (ON) 50
COMMENr: THIS EXAMPLE HAS THE FOLLOWING MEANING FOR DEFINING
TRACE POSITION:
FIND IN SEQUENCE ~0001 OCCURRENCE OF STATE 10~ THEN
THE 0~0~1 OCCURRENCE OF STATE 20, THEN THE 00pP5 OCCURRENCE
OF STATE 30, AND (START) TRACE AT 0~001 OCCURRENCE OF
STAT,E 40.
IF DURING THIS SEQUENCE THE RESTART 5TATE 50 XS
ENCOUNTERED BEFORE REACHING THE 00~01 OCCURRENCE OF
STATE 40, THE MEASUREMENT RESTARTS, ro FIND IN SEQUENCE
THE 00001 OCCURRENCE OF STATE 10, THEN 00001 OCCURRENCE
OF STATE 20 ETC.
NOTE: IF A SEQUENCE STATE IS DEFINED TO BE THE SAME AS THE
RESTART STATE9 THE SEQUENCE STATE DOMINATES.
IF (CENTER) OR (END~ ~ERE SELECTED, SELECTIVE
TRACE STARTS AT COMPLETION OF 5 OCCURRENCES
OF STATE 30 (SEE SELECTIVE TRACE~.
~r
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~ DETAILED FIELD/S DESCRIPTION
; SELECTIVE TRACE:
: EXAMPLE: LABEL A OCCUR
(ALL STATES)
; PURPOSE: TO TRACE ALL STATES.
.~ EXAMPLE: LABEL A OCCUR
BASE HEX DEC
: TRACE
(ONLY STATE) 60 00001
OR 7X
OR 8X
PURPOSE: TO SELECTIVELY TRACE DESIRED STATES.
` COMMENTS: THE ABOVE EXAMPLE HAS FOLLOWING MEANING:
DO A SIMULTANEOUS TRACE OF 00001 OCCURRENCE
OF STATES 60 OR 7X (70 TO 7F) OR
8X (80 TO 8F).
-20-
DETAILED FIELD/S DESCRIPTION
COUNT:
EXAMPLE: LABEL A
BASE HEX
COUNT ( OFF )
COUNT (STATE) 7X
COUNT (TIME )
URPOSE: TO SELECT COUNT MEASUREMENT TO BE (OFF), OR COUNT (STATE)
OR COUNT ~TIME).
COMMENT: WHEN COUNT IS ~OFF), THE TRACE LIST DOES NOT SHOW
COUNT DATA FOR THE NEXT TRACE MEASURMENT.
WHEN COUNT (STATE) IS SELECTED9 A 32 BIT COUNT OF
SELECTED STATE 7X (70 TO 7F) IS STORED IN MEMORY
WITH EACH POD DATA STATE STORED. THE RESULTANT COUNT
DATA IS DISPLAYED IN TRACE LIST FOR NEXT TRACE
MEASUREMENT.
WHEN COUNT (TIME) IS SELECTED, A COUNT VALUE OF TIME IS
STORED FOR EACH POD DATA STATE STORED IN MEMORY. THE
RESULTANT TIME DATA DISPLAYED IN TRACE LIST FOR NEXT
TRACE MEASURMENT.
21
_
DETAILED FIELDtS DESCRIPTION
STATE COUNT OR TIME (ABS)~ (REL):
EXAMPLE: LABEL A STATE COUNT
`~ BASE HEX DEC
- (ABS)
SEQUENCE 10 - 1043
SEQUENCE 2p - 1033
SEQUENCE 3p - 1023
START 40 0
+01 60 + 20
~02 70 + 3
+03 71 + 31
* * *
LABEL A STATE COUNT
BASE HEX DEC
tREL)
SEQUENCE 1~
SEQUENCE 20 10
SEQUENCE 3~ 2~
START 40 1023
+01 60 2~
~2 7~ 10
~3 71
* * *
LABEL A TIME
BASE HEX DEC
(AeS)
SEQUENCE 10 - 208.3 US
SEQUENCE 20 - 20~.2 IJS
SEQUENCE 30 - 185.1 US
START 4~ .p US
.~01 60 ~80.0 US
+02 70 +120.9 MS
~03 71 ~122.5 MS
* * *
PURPOSE TO VIEW TRACE LIST AND SELECT (ABS) OR
(REL~ FOR STATE COUNT OR TIME DATA.
COMMENTS: WHEN ABSOLUTE (ABS) IS SELECTED THEN STATE COUNT
OR TIME IS DISPLAYED IN +/- ABSOLUTE VALUES WITH
RESPECT TO START STATE 40~ ALL STATES BEFORE START
STATE 40 ARE SHOWN WITH "-" CCUNT VALUES. START
STATE 40 IS SHOWN AS ALWAYS 0. ALL STATES SHOWN
AFTER START STATE 4~ ARE SHOWN WITH "~" COUNT
VALUES.
WHEN RELATIVE (REL) IS SELECTED~ THEN STATE COUNT
OR TIME IS DISPLAYED SHOWING COUNT VALUES RELATIVE
TO PREVIOUS STATE COUNT VALUE (IE VALID)
WITHOUT SIGN.
.,j~,
~,
-22-
~ 3~
DETAILED FIELD/S DESCRIPTION
GRAPHED LABEL:
EXAMPLE:
GRAPHED LABEL (A)
GRAPHED LABEL (F)
PURPOSE: TO SELECT A DEFINED LABEL A, B, C, C, E OR F TO BE
GRAPHED.
-23-
DETAILED FIELD/S DESCRIPTION
UPPER/LOWER LIMITS:
; EXAMPLE
- UPPER LIMIT
177
LOWER LIMIT
000
PURPOSE TO CHANGE UPPER OR LOWER GRAPH LIMITSo
COMMENT GRAPH LIMITS MAY BE CHANGE USING ENTRY KEYS OR
THE LIMITS MAY BE AUTOMATICALLY INCREMENTED OR
DECREMENTED USING INCR OR DECR KEYS
IN EDIT BLOCK~
THE UPPER LIMIT MUST BE GREATER THAN LOWER LIMIT~
ELSE AN ~ERROR-OVERLAPPING LIMITS~ IS DISPLAYED
AND GRAPH DOTS ARE NOT DISPLAYED~
~r
24-
DETAILED FIELD/S DESCRIPTION
COMPARED TRACE MODE:
EXAMPLE:LABEL A COMPARED
BASE HEXTRACE MODE
(OFF)
SEQUENCE 00
SEQUENCE 00
SEQUENÇE ~0
START 00
+01 30
+02 ~
PURPOSE: TO SHOW THE "EXCLUSIVE OR" OF CURRENT DATA WITH
STORED DATA, ALL 0'S IMPLIES SAME DATA IN BOTH FILES
AND NON P'S (3~) SHOWS THAT DATA STATE DOES NOT
COMPARE (BITS 4 AND 5, ASSUMING LSB IS BIT ~).
EXAMPLE:LABEL A COMPARED
BASE HEXTRACE MODE
~STOP=)
LABEL A COMPARED
BASE HEXTRACE MODE
(STOP#)
PURPOSE: TO SELECT COMPARED TRACE MODE TO BE STOP WHEN EQUAL
(STOP=), OR STOP WHEN NOT EQUAL (STOP#).
COMMENTS: WHEN (STOP=) IS CHOSEN THE MEASUREMENT IS TRA~ED
UNTIL VALID CURRENT DATA EQUALS (=) VALID STORED
DATA, THE STATUS OF INSTRUMENT WILL BE:
"COMPARED TRACE-FAILED"
WHICH MEANS CURRENT DATA DOES NOT EQUAL STORED
DATA, THE 1610A THEN TRACES AGAIN SHOWING:
"COMPARED TRACE-IN PROCESS"
AND COMPARES ANOTHER SET OF DATA. THIS PROCESS
CONTINUES UNTIL:
"COMPARED TRACE-COMPLETE"
WHICH MEANS VALID CURRENT FILE EQUALS VALID STORED FILE
DATA.
A SIMILAR OPERATION EXISTS FOR (STOP#), EXCEPT THIS
MEASUREMENT CONTINUES UNTIL FIIES DO NOT COMPARE.
NOTE: THIS IS NOT A REAL TIME MEASUREMENT, BUT RATHER
A "SAMPLED COMPARED MODE" THAT IS DEPENDENT IN PART
UPON DATA CLOCK RATES9 TRACE SPECIFICATION.
THIS MEASUREMENT MODE MUST BE TURNED (OFF)
TO OBTAIN SINGLE OR CONTINUOUS TRACE MODE.
..~
-25-
