Note: Descriptions are shown in the official language in which they were submitted.
~Z27~1
Background of the Invention
1. Field of Invention
This invention relates generally to the digital
data processing art and more particularly to a new and im-
proved method and apparatus for encoding and recovering
binary digital data. The invention is particularly appli-
cable to digital data communication systems and to magnetic
storage and retrieval systemsj and will be described herein
with reference to the latter.
2. Description of the Prior Art
In the course of development of binary data ~ -
magnetic storage and retrieval systems, it has been of
primary interest to increase the system data capacity by
packing as much data as possible into a given time interval
or length of the recording medium such as a disk or tape.
This objective is met by encoding the binary data so as to
place or store signal changes or transitions representative
of the respective ones and zeros of the binary data as close
together as is practical. Various constraints instrinsic to
such systems impose a limitation, however, on what is in
fact practical, insofar as data packing density is concerned,
with respect to accurate recording and reproduction of the
data. One such constraint is a phenomenon commonly refer-
red to as bit shift which occurs in the course of reproducing
the binary data from the encoded signal recorded on the
storage medium. It is characterized by a shifting of the
reproduced signal transitions from their nominal locations
and is caused by the close proximity or crowding of adjacent
transitions recorded on the storage medium. More specifi-
cally, bit shifting occurs as a consequence of the inter-
ference or interaction of each reproduced signal txansition
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with adjacent reproduced signal transitions when reading the
recorded signals from the storage medium. The amount of
shift which occurs for each reproduced signal transition
is determined by the packing density and the degree of asym-
metrical disposition of the transitions adjacent both sides
of each reproduced signal transition, with the amount of
shift being proportionally greater in accordance with in-
creased packing density and asymmetry of the respective
signals.
Bit shift is of considerable concern because it
directly relates to the ability to accurately reproduce the
binary data as will become apparent from the following com-
ments. When data is to be recorded it is encoded, as prev-
iously mentioned and as will be explained subsequently in
greater detail, and then applied to the storage medium on
a clocked basis so that each signal transition is recorded
in a prescribed interval or segment of the storage medium.
Recording on a predetermined time basis is essential to en-
able detection of the respective one and zero data bits when
reading from the storage medium for the purpose of reproduc-
ing the binary data stream. Typically, a gated oscillator
or preferably a phase locked oscillator is employed to
create a time oriented window for recovering the binary data
from the reproduced signal transitions. The phase locked
oscillator, for example, usually functions in a manner,
as is well known to those skilled in the art, such that it
runs at a nominal frequency which is a selected harmonic of
the frequency corresponding to the fundamental period of the
encoded data signal and thereby produces a gating window
signal associated with each reproduced signal transition
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for recovering the binary data from the encoded data signal.
At this point it should be understood that the recovery
window has associated with it a feature commonly referred to
as timing tolerance. It will be appreciated that when the
signal transitions are packed closer together, the recovery
window must be narrowed to preclude detection of a repro-
duced signal transition at a nonassociated window. Natural-
ly, as the recovery window is narrowed, the amount of bit
shift which can be tolerated is reduced proportionally. A
phase comparator included in the phase locked oscillator
serves to compare the phase of the reproduced signal trans-
itions read from the storage medium with a signal supplied
from the phase locked oscillator to produce a signal for
controlling the oscillator so as to cause it to track the
reproduced signal transitions. A filter circuit of the
phase locked oscillator functions to enable the oscillator
to track average time locations of the reproduced signal
transitions while remaining insensitive to instantaneous
variations thereof. In this way, the recovery window is
maintained in general alignment with the reproduced signal
transitions. In the case of any abrupt bit shift in excess
of a predetermined amount, however, the reproduced signal
transition will be positioned outside its recovery window
with resultant failure of detection and erroneous data
recovery.
From the foregoing comments it will be appreciated
that bit shift must be reduced to enhance data recovery and
that reduction of bit shift in turn is dependent on avoidance
of inordinate crowding of adjacenttransitions of the encoded
data signal. To satisfy such criteria and others which
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will be discussed subsequently, various encoding techniques
have been devised in the development of the art. Some of
the desired characteristics of a suitable encoding tech-
nique will be discussed briefly at this point and explained
more fully hereinafter in connection with the detailed des-
cription of the instant invention and selected prior art
codes illustrated in the appended figures. One of the de-
sired characteristics, of course, is that the encoding be
such as to avoid undue bit shift. This is achieved by pro-
viding sufficient spacing between successive signal transi-
tions recorded on the storage medium, but must not be done
at the expense of reducing the recording density. Another
desired characteristic of any encoding technique is that
it avoid such large spacing between recorded signal trans-
itions as would preclude the ability to achieve self-clock-
ing during data recovery. Self-clocking is a feature where-
by the encoded signal recorded on the storage medium and
the related readout or reproduced signals possess such
qualitites as to provide the required control of the phase
locked oscillator for data recovery as previously discussed.
In the absence of a self-clocking capability, a separate
clock channel must be provided on the recording medium and
this is undesired, among other reasons, for the reason that
it requires maintaining alignment of the read/write head of
the clock channel relative to the heads associated with
the data channels. The requirement, on the one hand, of
sufficient minimum spacing between successive signal trans-
itions so as to preclude undue bit shift and the requirement,
on the other hand,for a limited maximum spacing between
successive transitions so as to achieve self-clocking is
essentially equivalent to the criterion that the number of
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recorded transitions per data bit be minimized or conversely
that the number of data bits represented by each recorded
transition be maximized.
The various encoding techniques commonly used in
the present state of the art are generally deficient in one
respect or another relative to the above indicated character-
istics. So called NRZ or NRZI codes, for instance, are
characterized, in the case of a succession of serveral one
or zero bits, by long intervals between recorded signal
transitions thereby precluding self-clocking. Frequency
modulation (FM) and phase modulation ~PM) codes, on the
other hand, while providing a self-clocking capability, are
characterized by close spacing of the recorded signal trans-
itions and thus limited in data packing density and timing
tolerance as required to avoid undue bit shift and assure
accurate data recovery. The close transition spacing of the
FM and PM encoding techniques occurs because of the periodic
insertion of clock transitions into the stream of data tran-
sitions for the express purpose of achieving self-clocking
and thus these codes are degraded with respect to the de-
sired criterion of minimizing the number of recorded tran-
sitions per data bit.
A more recently developed code known as modified
frequency modulation (MFM) overcomes the limitations of the
FM, PM and NRZ type codes to some extent and has in fact
been in popular use for the past several years because of
its self-clocking capability and the provision of substantial-
ly twice the packing density of the FM and PM codes without
aggravating the bit shift problem or reducing timing toler-
ance. The MFM encoding technique does not employ additionalclock transitions but instead uses the data transitions for
clocking purposes and thus provides
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enhancement with respect to the criterion of minimizing the
number of recorded transitions per data bit. Nevertheless,
the binary data packing denisty which can be achieved with MFM
code is limited by the minimum spacing which it provides be-
tween the successive signal transitions recorded on the
storage medium. This limitation of the MFM code relative to
the instant invention will be understood more fully from a
reading of the su~sequent detailed description of the pre-
sently preferred embodiment of the invention.
Accordingly, it is a principal object of the present
invention to provide a new encoding and concomitant recovery
technique which provides for self-clocking while simultaneously
affording substantially a fifty percent or greater improvement
in data packing density over present state of the art
techniques without diminution of timing tolerance. Another
principal object of the invention is to provide a new
technique for encoding binary data which substantially in-
creases the number of data bits represented by each trans-
ition of the encoded data signal relative to that attained0 with present state of the art encoding techniques.
Summary of the Invention
The present invention consists of apparatus for con-
verting binary data in the form of a series of data bits
occurring at spaced intervals to a series of signal changes
each located at a discrete selected signal change position
of a plurality of signal change positions that are spaced
from one another by an increment such that the selected
signal change positions are spaced relative to one another at
least a prescribed minimum amount greater than the increment,
said apparatus comprising: data storage means for receiving
the binary data and grouping data bits to form a plurality
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of data words~ code signal generating means coupled to the
data storage means and responsive to the data words for
generating code signals each of which corresponds to a
signal change, and means coupled to said code signal gener-
ating means and responsive to code signals generated thereby
for merging plural code signals that correspond to signal
changes at divers signal change positions spaced from one
another less than the prescribed minimum amount into at
least one code signal corresponding to a signal change at a
signal change position different from said divers signal
change positions such that all signal changes are spaced from
one another by at least the prescribed minimum amount.
The invention also provides a method of converting
binary data including a series o data bits occurring at
spaced intervals to a series of signal changes each located
at a discrete selected signal change position of a plurality
of signal change positions that are spaced from one another
by an increment such that the selected signal change positions
are spaced relative to one another at least a prescribed
minimum amount greater than the increment, said method com-
prising the steps of: receiving the binary data and grouping
the data bits to form a plurality of data words, generating
code signals representative of the data words, each code
si~nal corresponding to a signal change, and merging plural
code signals that correspond to signal changes at divers
signal change positions spaced from one another less than
the prescribed minimum amount into at least one code signal
corresponding to a signal change at a signal change position
different from the divers signal change positions such that
all signal changes are spaced from one another by at least
the prescribed minimum amount.
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The foregoing and other desired objectives are achieved
in accordance with a presently preferred method for recording
on a magnetic storage medium by dividing a binary data stream
consisting of a sequence of one and zero bits, each occurring
at an interval T, into respective data groups or words each
containing three data bits. The respective data words are
recorded in succession by representing each data word in
turn, referred to herein as the present data word, by a code
signal or combination
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of two code signals uniquely representative of the data word.
The code signal or combination of code signals corresponds
to a signal transition or combination of signal transitions
which is recorded as a transition or combination of transi-
tions respectively at a selected position or positions of
only the first five of six uniformly spaced predeterminèd
transition positions occurring sequentially in the order
Pl, P2, P3, P4, P5, P6 on a specified segment of the
magnetic storage medium, referred to as a data cell, having
a length corresponding to three T intervals, the recording
being such that combinations of transitions are recorded
at positions having a prescribed minimum spacing there-
between equal to 1.5T.
Concurrently with the encoding of the present data
word being recorded, a look ahead is made to the following
or next data word to be recorded to determine whether it
contains a bit pattern which, when encoded for recording,
will produce a code signal corresponding to a transition at
the position Pl in its data cell closest to the boundary of
the present data cell. Under such condition, if the present
binary data word is producing a code signal representative of
a transition at the position P5, a transition will not be
recorded at position P5 in the present data cell but instead
will be recorded at position P6 corresponding to the boundary
between the present and following data cells.
Also concurrently with the encoding of the present
data word, a look back is made to the preceding or previously
recorded data word to ascertain whether it contained a bit
pattern which, when encoded for recording, produced a code
0 signal corresponding to a transition at position P5 which
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was replaced by a transition at P6. Under such condition,
if the present data word relates to a code signal represent-
ative of a transition at Pl, such transition is not recorded.
The net result therefore is that, where adjacent data words
relate to code signals representative of a transition at
position P5 for one data word and a transition at position
Pl for the immediately following data word, neither transi-
tion is recorded and both are effectively merged into or
replaced by a single transition at the boundary between the
data cells associated with the respective words.
Apparatus for carrying out the preferred encoding
method comprises: a first shift register for storing the
data bits in discrete storage locations for sequential en-
coding of respective data words; a first encoder and assoc-
iated logic circuit coupled with the present data word to
be encoded for providing a code signal or combination of
code signals representative of the present data word; a
second shift register for storing at discrete storage loca-
tions a transition signal or combination of transition sig-
nals corresponding respectively to the code signal or com-
bination of code signals where the transition signals of
eombinations of transition signals are spaced a prescribed
minimum number of storage locations and each transition
signal corresponds to a transition position in a data cell
oeeupying a given segment of a storage medium; a second
encoder and associated logic circuit coupled with the follow-
ing data word to be encoded for inhibiting storage in the
second register of a transition signal corresponding to the
transition position P5 in the present data cell adjacent
the boundary of the following data cell and substituting in
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place of the inhibited transition signal another transition
signal at transition position P6 located at the boundary of
the present and following data cells, under the condition
where the following data word relates to a code signal cor-
responding to a signal transition in its data cell at the
transition position Pl adjacent the boundary of the present
and following data cells; a third encoder and associated
logic circuit coupled with the preceding data word for in-
hibiting storage in the second register of a transition sig-
nal corresponding to the transition position Pl in the pres-
ent data cell adjacent the boundary of the preceding data
cell, under the condition where the preceding data word
relates to a code signal corresponding to a signal transition
in its data cell at the transition position P5 adjacent the
boundary of the present and preceding data cells; and clock
signal generating means for appropriately stepping the
shift registers to provide an encoded signal at the output
of the second shift register suitable for application to
data communications means or magnetic means.
It will be appreciated that the second and third
encoders and associated logic circuits can be modified so
that the second encoder and logic circuit acts to inhibit
a code signal corresponding to a transition at position P5
in the present data cell adjacent the following data cell
when the following data word relates to a code signal cor-
responding to a transition in its data cell at the position
Pl adjacent the present data cell, while the third encoder
and logic circuit acts to inhibit a code signal correspond
to a transition at position Pl in the present data cell
adjacent the preceding data cell and simultaneously produces
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llZ2711
a signal at position P6' located at the boundary between
the present and preceding data cells when the preceding data
word relates to a code signal corresponding to a transition
which was inhibited in its data cell at the position P5
adjacent the present data cell. It will also be appreciated
that two transitions spaced less than the prescribed minimum
amount could be replaced by or merged into one of such trans-
itions at its original position and further that such trans-
itions need not necessarily be disposed on opposite sides of
a data cell boundary.
The invention further relates to a method and
apparatus for recovering data encoded as described above.
Briefly, the recovery apparatus comprises a read shift re-
gister for storing in respective positions thereof signals
representative of the signals recorded in the present data
cell being read out together with any signal recorded at
the boundary of the present and preceding data cells in
oombination with logic circuit means coupled to the read
shift register for producing the combination of bits of the
present word as represented by the signals at the discrete
locations of the shift register.
Brief Description of The Drawings
FIG. 1 depicts encoded signal waveforms illustrative
of various prior art codes and the code of the instant in-
vention with reference to common binary data occurring at a
predetermined rate of l/T;
FIG. 2 is a chart of properties of the prior art
codes illustrated in Fig. 1 for a data bit rate of l/T;
FIG. 3 is a chart of the properties of the code
of the instant invention for a data bit rate of l/T;
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FIG. 4 is an illustration of a data cell of the
instant invention showing the selective signal transition
positions used in the invention code;
FIG. 5 depicts an illustrative binary data pattern
and the related encoded signal waveform produced in accord-
ance with the instant invention;
FIG. 6 is a circuit partially in block and partial-
ly in logic form for encoding data according to the instant
invention;
n; FIG`. 7 is a truth table useful for obtaining an ~
understanding of the encoding process of the inventlon; ~ ~ -
FIG. 8 is a truth table for the circuit of FIG. 6;
FIG. 9 is a circuit partially in block and partial-
ly in logic form for decoding data according to the instant
invention;
FIG. lO is a truth table for the circuit of Fig.9;
FIGS. lla and llb are timing diagrams useful for
,~ understanding thé operation of the circuits of Figs. 6 and ~-~
',~ 9 respectively;
FIG. 12 is a recording and recover~,~ system incorp-
orating the circuits of FIGS. 6 and 9 for recording and
- recovering binary data encoded in accordance with the instant
invention; and
FIG. 13 is a table depicting another arrangement
of code signal positions in accordance with the encoding
technique of the instant invention wherein each data word
corresponds to two successive data cells having three signal
positions per cell.
Description of the Preferred Embodiment
An illustrative binary data pattern which will be
used for describing the operation and features of the
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invention relative to prior art codes is shown in Fig. 1
wherein each data bit, represented by either a one or a
zero, is indicated as occurring in an interval T with uni-
form spacing between the bits as is typically provided by a
clock generator. The interval T is representative of a unit
of time or a corresponding unit of length on a storage
medium. The various prior art codes shown in Fig. 1, namely
NRZI, FM, Gabor and MFM, each have the objective of encoding
the binary data. It will be recognized that the various
codes are all presented on a common scale corresponding
to the indicated binary data rate. In the case of the NRZI
code the binary data is encoded such that a signal change
or transition occurs in the encoded waveform at the center of
an interval T to represent a one bit whereas signal changes
do not occur for the zero bits. Fig. 2 indicates various
properties of the prior art codes shown in Fig. 1. The
NRZI code has the advantage of a relatively wide recovery
window (+ 0O5T) which obtains because of the fact that the
closest adjacent signal transitions are spaced an amount
equal to T. In other words, a transition gating pulse or
so-called recovery window centered on each data bit interval
and having a width of approximately + 0.5T will only detect
a transition occurring in the associated interval. The
NRZI code also has serious disadvantages, however, in that
it is not capable of self-clocking and in addition has a
very broad bandwidth as indicated by the ratio of S MAX to
S MIN where S MIN and S MAX represent respectively the min-
imum and maximum distances between encoded signal transitions.
This results because no signal change occurs in the case of
a long sequence of zero bits. To obtain self-clocking,
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the spacing S MAX must not be too large because, as previously
explained, the phase locked oscillator of the recovery system
is controlled by the reproduced signal transitions. If the
spacing S MAX exceeds a predetermined interval, the oscilla-
tor will run freely without clocking (synchronization) and
as a result, the recovery window which is generated by the
oscillator may not track the reproduced signal transitions
as is required for recovering the binary data.
For the FM code a signal change or transition occurs
in the encoded waveform at each boundary between adjacent
data bit intervals T and at the center of each interval in
which a one bit appears. Transitions occurring at the cent-
ers of the T intervals are data transitions while those occur- -
ring at the boundaries are clock transitions inserted specifi-
cally for àssuring self-clocking, and since the maximum spac-
ing between the signal changes is equal to T, self-clocking
is easily achieved. Moreover, the system bandwidth is sub-
stantially reduced compared to the NRZI code as indicated by
the ratio of S MAX to S MIN. The clock rate of 2/T indicates
that a full cycle of the recovery window signal occurs in
each interval T with one half cycle thereof required to be
centered in the T interval in order to discriminate between
data and clock transitions, and as a result, the recovery
window for the FM code is reduced to half of that for the
NRZI code. The reduction of S MIN has the adverse effect,
as indicated in Fig. 2, of reducing the number of data bits
encoded per S MIN, that is, per transition, to one half of
what can be obtained with the NRZI code.
The Gabor code, which is described in United States
30 Patent 3374475, High Density Recording System, issued
March 19, 1968 to A. Gabor as inventor, is characterized
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by encoded signal transitions occurring either at the T
interval boundaries or the one-third and two-thirds positions
between the boundaries. The Gabor code provides certain
improvements over the FM code in that the number of data
bits encoded per S MIN is increased and the recovery window
is increased by~ virtue of increased minimum spacing between
the signal transitions whereby the binary data packing densi-
ty is increased relative to the FM code but not as much as
is possible with NRZI code.
The MFM code is characterized by encoded signals
either at the center or at the boundaries of the data bit
intervals and therefore has the same clock rate as the FM
code since a recovery window must be produced both at the
center of each data bit interval T and at the boundaries of
data bit intervals in order to detect all encoded signals
for self-clocking purposes and to be able to discriminate
between one and zero bits which are represented in the en-
coded signal by transitions occurring at unique locations,
for example, ones at the centers of T intervals and zeros
at the boundaries thereof. The MFM code affords the ad-
vantage relative to the Gabor code of increased data bits
encoded per S MIN, in fact, being equal to the NRZI code
as indicated in Fig. 2, while maintaining a suitable re-
; covery window and S MAX so as to have a self-clocking cap-
ability. Further, because of the increased minimum spac-
ing between the encoded signals, the binary data packing
density obtainable with MFM code is better than what can
be obtained with the FM or Gabor codes and in fact is sub-
stantially double that of the FM code. In other words, if
T/2 is the acceptable minimum spacing between signal
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transitions for tolerable bit shift relative to the width of
the recovery window, than the binary data may be presented
for MFM encoding at a rate approximately double that which
is permissible for the FM code, that is, the interval T of
the binary data may be reduced to T/2 in the case of MFM
encoding. It is recognized, therefore, that the MFM code
possesses many desirable qualities for binary data encoding
applications.
The method and means for implementing the present
invention will be described shortly hereinafter but for the
moment the salient features of the invention will be appreci-
ated by reference to Figs. 1 to 3. In accordance with the
invention, a novel code, referred to as 3PM, ~three position
modulation or three phase modulation) is provided which
further improves over the MFM code particularly with regard
to the minimum spacing of signal transitions of the encoded
waveform and the number of data bits encoded per minimum
spacing between transitions as indicated by a comparison of
Fig. 3 with Fig. 2. More specifically, in view of the
increased minimum spacing between signal transitions, the
binary data packing density is seen to be increased by
fifty percent relative to MFM code. Thus, if T/2 is the
minimum acceptable spacing between adjacent transitions, the
3PM code enables compression of the binary data by a factor
of three relative to FM coding and by fifty percent relative
to MFM coding. From Fig. 3 it will also be noted that the
recovery window for the 3PM code is maintained equal to that
for the MFM code; and although both S MAX and the ratio of
S MAX to S MIN are increased the parameters obtained are
nevertheless satisfactory for self-clocking recovery with
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ll'ZZ711
circuits presently available in the state of the art.
Since transitions occur at both the midpoints and boundaries
of T intervals for the 3PM code, the clock rate is 2/T
corresponding to the clock rate for the FM and MFM codes.
The foregoing features of the 3PM code are achieved by divid-
ing the binary data words and encoding each data word such
that it is represented by a signal transition or combination
of signal transitions spaced at least a presecribed minimum
amount and occurring in a data cell having a length equal
to the sum of the number of intervals T corresponding to
the number of bits in each data word. Generation of the
code is further based on determining when signal transitions
in one data cell are spaced less than the prescribed minimum
spacing from signal transitions in an adjacent data cell
and, in the event of such occurrence, providing for such
closely spaced signal transitions to be replaced by a lesser
number of transitions.
The preferred encoding circuit, which is shown
in Fig. 6 and will be discussed a little later, provides
for dividing the binary data into sets of three data words
with each data word including three data bits whereby each
data word may be any one of eight possible data words, that
is each data word corresponds to one of the eight possible
combinations of data bits in a word. Each data word in
-~ turn corresponds to either a single code signal or combin-
ation of code signals which relate respectively to a signal
transition position in a data cell of the storage medium
or a combination of signal transition positions in the data
cell spaced from one another at least a prescribed minimum
distance S MIN = 3T/2 as indicated in Fig. 1. Fi~. 4
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~lZZ711
indicates the location of the signal transition positions
Pl through P6 which are equally spaced an amount T relative
to one another in a data cell which has a length equal to
3T for the case of three data bits per data word, the
positions P6 being aligned with the boundaries of the data
cell.
The third and fifth columns of Fig. 7, entitled
respectively BINARY DATA WORD and TRANSITION POSITION IN
DATA CELL, indicate the correlation of the eight possible
data words with the six data cell transition positions.
Other correlations of the data words and transition positions
can be used, if desired, as long as the encoding criteria
of the invention are satisfied in the manner as will now be
explained. For the indicated correlations it will be noted
that a single transition position is used for the binary
data words 000, 001, 010, 100 and 101 whereas two signal
transition positions are used for the binary data words
011, 110 and 111. It will also be noted that in those
instances where two signal transitions are used, the transi-
tions are spaced by at least three positions which fromprevious comments will be understood to be equal to 3T/2,
the prescribed minimum spacing. It is apparent though that
where transitions occur at position P5 in one data cell
and at position Pl in an immediately following data cell,
the spacing between transitions will only be an interval T
and thus the prescribed minimum spacing will not be attained.
Accordingly, it is provided that where such transitions are
called for, they will in fact not be produced but instead
will be replaced by a single transition at position P6
intermediate the inhibited transitions. More specifically,
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in a case where the present binary data word being encoded
corresponds to a signal transition to be produced at position
P5 in the present data cell and is followed by a binary data
word associated with a signal transition to be produced at
position Pl in the following data cell, the signal transition
at position P5 in the present data cell will be inhibited
and replaced by a signal transition at position P6 located
at the trailing boundary of the present data cell. In
addition, when the present binary data word being encoded
corresponds to a signal transition to be produced at position
Pl in the present data cell and was preceded by a binary
data word associated with a signal transition to be produced
at position P5 in the preceding data cell (and which, under
the assumed conditions, was replaced by a transition at
position P6), then the transition will be inhibited at
position P1 in the present data cell. Thus, it is assured
;; that encoding signals will not occur spaced less than three
positions apart. In other words, it is a rule of the inven-
tion encoding technique that a transition to be produced at
position P5 in a present data cell followed by a signal tran-
sition to be produced at position Pl in the immediately fol-
lowing data cell will be merged into a single signal transi-
tion produced at the position P6 located at the boundary
between the present and immediately following data cells.
, This is accomplished when encoding each binary data word
in sequence by simultaneously looking at the immediately
preceding and following data words as will be described
more fully hereinafter with reference to Figs. 6,7 and 8.
First though, attention is directed to Fig. 5 which depicts
a binary data pattern and the related encoded signal
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produced in accordance with encoding technique of thepresent invention.
As shown in Fig. 5, the first binary data word
001 produces a signal change or transition at position P4
in the first data cell Zl. The binary data word 111 of the
second binary data group produces signal transitions at
positions Pl and P4 in data cell Z2, the signal transition
being made at position Pl in data cell Z2 since a signal
transition did not occur at position P5 in the preceding
data cell Zl. The third binary data word 010 produces a
signal transition at position P2 in data cell Z3. The
fourth binary data word 110 corresponds to signal transitions
to be produced at positions Pl and P5 in data cell Z4, but
only the signal transition at position Pl is actually produc-
ed. The signal transition at position P5 in data cell Z4
is inhibited because the following binary data word 101 is
associated with a signal transition at position Pl in cell
Z5. Thus, in accordance with the encoding rule of the in-
vention, a signal transition is not made at position P5 in
data cell Z4 but in place thereof a signal transition is
made at position P6 coinciding with the boundary intermediate
data cells Z4 and Z5. Further, since the signal transition
at position P5 in data cell Z4 has been replaced by a signal
transition at position P6, a signal transition is not made
at position Pl in data cell Z5 corresponding to the binary
data word 101.
Referring to Figs. 6 and lla, a signal represent-
ative of the binary data to be encoded is applied to data
input terminal 14 of write data shift register 15 which has
Q sufficient capacity for storing three binary data words
- 18 -
1~2Z'~ll
each including three data bits and referred to hereafter,according to their instantaneous position in the register,
as the present, preceding and following data words. The
binary data signal may, for instance, comprise a series of
pulses obtained by representing each one bit by a pulse
and each zero bit by the absence of a pulse at discrete
time increments. A series of bit clock pulses occurring at
the data rate are applied to bit clock terminal 16 to shift
the binary data one register stage in response to each such
pulse. At this point it should be understood that a condi-
tion of no data in the register is equivalent to an absence
of pulses in the respective register stages or, in other
words, to a sequence of zero bits. Now it will be noted
from Fig. 7 that the binary data word 000 corresponds to a
signal transition at position P5 which in fact will be trans-
lated to position P6 as previously described. Thus, it will
be assumed that encoding commences when the first binary
data word to be encoded is aligned with binary to octal
encoder 17. This condition obtains at the occurrence of the
sixth bit clock pulse after the application of binary data
to input terminal 14, namely, bit clock pulse 18a, at which
time the three right side stages of register 15 have no data
loaded in them. Consider more specifically the sequence of
events commencing after the fifth bit clock pulse 18b, that
is, after the first five data bits have been loaded into
register 15. First, the record signal applied to record
terminal 19 of write signal shift register 20 changes from
a high level to a low level whereupon register 20 is enabled
in readiness for signals to be loaded into its respective
stages Sl through S6 which correspond respectively to
-- 19 --
~n .
ll'ZZ71~
positions Pl through P6 of a data cell. Actual loading of
signals into the stages of register 20 does not occur, how-
ever, until the instant the leading edge of word clock pulse
21a applied to word clock terminal 22 changes from a high
to a low level. In any event, the signals loaded into stages
of register 20 are only transient at this instant and do not
stabilize for writing purposes until the occurrence of the
sixth bit clock pulse 18a at which time the sixth data bit
is loaded into register 15 and the first data group to be
encoded is aligned with binary to octal encoder 17. Thus,
when the data word 001, referring to Fig. 5 for example, is
the present binary data word which is to be encoded, a
signal is supplied from the Bl terminal of encoder 17, as
indicated in Fig. 7, and transmitted through OR gate 23 to
stage S4 of register 20. The signal at the output of OR
gate 23 is the code signal for the present data word 001.
Simultaneously, the three zero bits in the preceding stages
of register 15 aligned with binary to octal encoder 24
function through logic circuit 25 including OR gate 26,
inverter 27 and AND gate 28 to inhibit storage of a signal
in stage Sl of register 20 in the event a signal is being
provided at terminal B5, B6 or B7 of encoder 17, but which,
in fact, is not the case for the present binary data word
001. Also simultaneously, the following data word which, in
this instance, is 111 and which is located in the following
three stages of register 15 aligned with binary to octal
encoder 29, functions through logic circuit 30 including OR
gate 31, inverter 32 and AND gates 33 and 34 to inhibit
storage of a signal at stage S5 and cause storage of a sig-
nal at stage S6 in the event a signal is being provided at
- 20 -
~2Z~l~
terminal B0, B3 or B6 of encoder 17, but which again is not
the case for the present binary data word 001. The net re-
sult therefore is that the data word 001 presently being
encoded produces a signal in stage S4 of register 20 but
not in any of the other stages of register 20. At the
trailing edge of word clock pulse 21a further signal loading
into stages Sl to S6 of register 20 is inhibited.
During the time between the trailing Pdge of word
clock pulse 21a and the trailing edge of the next word clock
pulse 21b, a total of six position clock pulses 35a through
35f occur at a rate twice that of the bit clock pulses and
slightly leading the bit clock pulses in time. As each
position clock pulse is applied to position clock terminal ;~
36 of register 20, the contents of the respective register
stages are shifted one stage. Thus, at the occurrence of
position clock pulse 35a, the signal in register stage Sl
i is applied as an input trigger pulse to bistable flip flop
37, the signal in register stage S2 is shifted to stage Sl
and so on with the signal in stage S6 being shifted to
stage S5. For the assumed binary data word 001, only stage
S4 contains a high level signal and therefore flip flop 37
does not switch state until the signal originally stored
in stage S4 is applied to the flip flop input. This swit-
ching of state in flip flop 37 can be used to produce a
magnetic flux transition in a magnetic storage medium as
is well understood by those skilled in the art and as will
be further explained subsequently with reference to Fig. 12.
At the occurrence of the leading edge of position clock
pulse 35f the signal originally stored in stage S6 is appli-
ed to the input of flip flop 37 and then shortly thereafterbit clock pulse 18e occurs which causes new code signals
- 21 -
llZ2711
to be applied to stages Sl to S6 of register 20 in view ofthe fact that the word clock signal is low again at this
time as indicated by pulse 21b. It will be noted that during
the time position clock pulses 35a to 35f have been occurring,
bit clock pulses 18c to 18e also occur thereby causing the
signals in register 15 to be shifted three positions with
the result that the data bits originally in the preceding
stages are shifted out of register 15, and the data bits
originally in the present stages are now shifted into the
preceding stages. Likewise, the data bits originally in
the following stages are shifted into the present stages
in readiness for encoding, and the next binary data group
010 (Fig. 5) is loaded into the following stages. The slight
time lag of bit clock pulse 18e relative to position clock
pulse 35f assures that the signals for one data word are
transferred out of register 20 to flip flop 37 before the
signals corresponding to the next data word are loaded into
register 20.
As previously mentioned, the bit clock rate is
equal to the data rate and the position clock rate is twice
that of the bit clock rate. It should be understood and will
be appreciated therefore that it is the position clock rate
which determines the recording rate and associated minimum
spacing between signal changes on the recording medium,
hence, once a desired minimum spacing between signal trans-
itions is established, the position clock rate must be suit-
ably set in accordance with the relative speed between the
recording medium and recording head and the bit clock rate
; then appropriately set to one-half the position clock rate.
- 22 -
i ~
l~ZZ~711
Encoding of successive binary data words continues
in the afore described manner. Thus, with binary data word
111 in the present encoding stages of register 15, a signal
is produced at terminal B7 of encoder 17, as indicated in
Fig. 7, and transmitted through OR gates 23 and 38 to
stages Sl and S4 of register 20. The signals at the outputs
of OR gates 23 and 38 are the code signals for the data
word 111. Likewise, with binary data word 010 in the pres-
ent encoding stages of register 15, a signal is provided at
terminal B2 of encoder 17 which in turn produces a code sig-
nal at the output of OR gate 39 coupled to stage S2 of regis-
ter 20. Next, data word 110 provides a signal at terminal
B6 of encoder 17 which in turn produces code signals at the
outputs of OR gates 38 and 40 coupled respectively to stages
Sl and S5 of register 20. In this instance, however, a sig-
nal is not loaded into stage S5 but instead a signal is
loaded into stage S6 because of a signal supplied from en-
coder 29 and acting through logic circuit 30. More specifi-
cally, referring to Fig. 5, it is seen that the data word
20 101 follows the data word 110 presently being encoded.
Since encoders 24 and 29 are identical to encoder 17, encod-
er 29 provides a signal at terminal C5 in response to the
binary data word 101 applied to its input. The signal at
terminal C5 is transmitted through OR gate 31 and inverter
32 to produce a low level signal at the input to AND gate 34
which inhibits passage of the signal supplied to AND gate
34 from encoder 17. At the same time, the signal supplied
from terminal C5 is also transmitted to AND gate 33 where
it combines with the high level signal derived from terminal
B6 via OR gate 40 and thus loads a signal into stage S6 of
- 23 -
.~
liZZ'~ll
register 20. This operation corresponds to the serial numb-
er twelve combination of Fig. 8. Finally, when the binary
data word 101 reaches the present encoding stages of register
15, the binary data word 110 is shifted into the preceding
stages and another word (not shown in Fig. 5) is loaded into
the following stages of register 15. In this instance, en-
coder 17 provides a signal at terminal B5 which produces a
code signal at the output of OR gate 38 coupled to AND gate
28 for loading a signal into stage Sl of register 20, but
lQ this action is inhibited by a signal provided at terminal
A6 of encoder 24 in response to the binary data word 110
applied thereto. The signal at terminal A6 transmits
through OR gate 26 and inverter 27 to produce a low level
signal at the input of AND gate 28 to inhibit any signal
passage therethrough. This operation corresponds to the
serial number nine combination of Fig. 8. The action of
encoders 17, 24 and 29 and associated logic components of
Fig. 6 for the various other possible combinations of
binary data words in the present, preceding and following
2Q stages of register 15 are also indicated in Fig. 8.
Before proceeding to a discussion of the recovery
apparatus is should be noted in Fig. 8 that the serial
number nine, eleven, thirteen and fifteen combinations
indicate instances in which a signal transition that was
to be made at position Pl in a data cell was in fact not
made because of a transition having been made at position
P6 of the immediately preceding data cell. This is a signif-
icant feature which must be duly considered when recovering
the binary data from the encoded signal as will become
apparent from the ensuing description of the recovery
- 24 -
llZZ7'1~
apparatus.
Referring to Figs. 9 and 11, the reproduced encodedsignal pulse stream from which the binary data is to be re-
covered is applied to input terminal 41 of read signal shift
register 42. The reproduced encoded signal pulse stream is
derived from the analog signal read from the magnetic storage
medium on which the originally encoded signal, representative
of binary data, was recorded in the form of a sequence of
magnetic flux transitions each corresponding to a signal
transition of the encoded signal and consists of a sequence
of pulses each corresponding to a signal transition of the
encoded signal. Position clock pulses applied to position
clock terminal 43 of register 42 increment the encoded
signal pulses through the register at the same rate at which
the encoded signal transitions were produced during record-
ing. Stages Sl to S6 of register 42 correspond respectively
to positions Pl to P6 in each data cell of the recording
medium and stage S6' corresponds to position P6 of the data
j cell immediately preceding the present data cell rom which
data is being recovered. The signals are read from the
storage medium in the same order as recording or writing
thereon and therefore, for the purpose of data recovery, a
pulse corresponding to a transition recorded at the trailing
boundary of the data cell preceding the present data cell
is stored at stage S6' of register 42 while a transition
recorded at the trailing boundary of the present data cell
is recorded at the stage S6 of register 42 in readiness for
data recovery.
Referring again to Fig. 5, consider the recovery
of the first binary data word which was recorded, namely
001. This word produced a signal transi~ion at position P4
- 25 -
llZZt~il
during the encoding and recording process, and now duringrecovery produces a high level signal at stage S4 and a low
level signal at all the other stages of register 42 at
completion of reading the first data cell of the storage
medium, which occurs at position clock pulse 44a. Shortly
before the occurrence of position clock pulse 44a, the read
gate signal applied to read gate terminal 45 of read data
shift register 46 changed from a high to a low level to
enable the register for receiving signals at terminals D0,
Dl and D2 which correspond to respective stages of register
46. The occurrence of the leading edge of word clock pulse
47a applied to word clock terminal 48 of register 46 causes
the actual loading of signals at terminals D0, Dl and D2;
and it will be appreciated that those signals are in a trans-
ient state and do not stabilize until the occurrence of the
leading edge of position clock pulse 44a. As in the case
of recording, the bit clock pulse rate is half that of the
position clock rate, and the bit clock pulses are delayed
slightly with respect to the position clock pulses. Thus,
at the occurrence of bit clock pulse 49a applied to bit
clock terminal 49' of register 46, the signal in the stage
associated with terminal D0 of register 46 is shifted out
of the register onto binary data line 50 and the signals
in the stages of Dl and D2 are likewise incremented one
stage to the right. Word clock pulse 47a then changes back
to a high level to inhibit further signal input to terminals
D0, Dl and D2 and thereafter until the occurrence of word
clock pulse 47b, bit clock pulses 49b and 49c respectively
shift the original signals at the stages of terminals Dl
and D2 out onto binary data line 50 while simultaneously
position clock pulses 44b to 44g shift the encoded pulses
- - 26 -
112Z711
corresponding to transitions of the following data cell into
register 42.
The logic used for recovering the original binary
data words from the pulses in register 42 will now be ex-
plained with reference to Figs. 9 and 10. In the case of
the first binary data word 001 which produced a pulse at
stage S4 of register 42, a signal is applied through OR gate
51 to terminal D0. Since a pulse is not simultaneousiy pro-
duced at stage Sl or S6 of register 42, the signal level at
the output of OR gate 52 is low and accordingly, the signal
from stage S4 is inhibited from passing through AND gate
53 into OR gate 54. The result therefore of a pulse only
in stage S4 of register 42 is an output of 001 on binary
data line 50 as indicated by the serial number three combin-
ation of Fig. 10. The next binary data word 111 produces
; signals in stages Sl and S4 of register 42. The signal at
stage S4 is again loaded into terminal D0 of register 46 via
OR gate 51 and also to an input of AND gate 53 while the
signal at Sl is transmitted through OR gate 52 and OR gate
20 56 to terminal D2 of register 46. The signal provided at
the output of OR gate 52 is also applied to an input of
AND gate 53 where it combines with the signal from stage
S4 to provide a signal via OR gate 54 to terminal D1 of
register 46. The net result is a signal stored in each
stage of register 46 whereby the binary data word 111 is
reproduced in response to the signals at stages Sl and S4
of register 42 as indicated by the serial number fourteen
combination of Fig. 10.
A signal is stored at stage S2 of register 42
when the next binary data word 010 is being recovered.
- 27 -
, " ~
,,~,. . .
ll'Z27i~
The signal at stage S2 is transmitted through OR gate S4
to terminal Dl of register 46, and no further decoding takes
place during reading of this cell, so the data word 010 is
readily reproduced on binary data line 50. The following
binary data word 110 is represented by signals at stages Sl
and S6 of register 42. The signal at stage Sl is transmitted
through OR gate 52 to an input of AND gate 57 and through
OR gate 56 to terminal D2 of register 46. Simultaneously,
the signal at stage S6 is transmitted through OR gate 58 to
an input of AND gate 59 and to the other input of AND gate
- 57 whereby a signal is applied through OR gate 54 to terminal
Dl of register 46. Thus, the word 110 is provided on binary
data line 50 in response to signals at stages Sl and S6 of
register 42 as indicated by the serial number thirteen
combination of Fig. 10. Finally when recovering the last
binary data word 101 a signal is stored only in stage S6'
of register 42. This is the same signal that was stored in
stage S6 when recovering the preceding binary data word.
The signal at stage S6' is transmitted through OR gate 52
to an input of AND gate 55 which simultaneously receives a
high level signal at its other input from inverter 60 in
~iew of the absence of a signal in stages S5 and S6 of
register 42, whereby a signal is applied through OR gate
51 to terminal D0 of register 46. Thus, the signal at S6'
of register 42 results in signals at the stages associated
with terminals D0 and D2 of register 46 to provide the word
101 on binary data line 50 as indicated by the serial number
nine combination of Fig. 10.
The binary data words recovered by the circuit
of Fig. 9 in response to other signal combinations in the
stages of register 42 are indicated in Fig. 10 which, it
- 28 -
'~
~lZZ~il
will be noted, corresponds to the encoding truth table ofFig. 8.
Some other features of the invention code, in
addition to those previously mentioned, are of interest and
can be appreciated at this point. Referring to Fig. 10, it
is seen that a total of twenty-three ones representative of
signal transitions are produced at various positions for all
of the possible combinations. Sixteen of these ones (enclosed
by dashed lines)occur in double windows, that is, either at
positions P6' or Pl or at positions P5 or P6 which are re-
dundant positions as indicated by the combinational logic
which may be expressed in logic equation form as follows:
D0 = P4 + P2-(P5 + P6) + (Pl + P6')-(P5 + P6)
Dl = P2 + (Pl + P6')-(P5 + P6) + (Pl + P6')- P4
D2 = (Pl + P6') + P3
where a dot signifies AND, + signifies OR and a bar signi-
fies NOT. Thus, approximately two-thirds of the transitions
are positioned so as to alleviate timing tolerance. Further,
the serial number five, six, ten,fourteen and fifteen combinations,
for which the double window condition exists, are relatively
more crowded than the other combinations in that only three
or four position spaces exist between the ones of such com-
binations. A total of ten transitions exist under these
relatively more crowded conditions and of this total, six
or, again, approximately two-thirds occur in double windows
thereby further alleviating timing tolerance.
A data recording and recovery system incorporating
the encoding and decoding circuits of Fig. 6 and Fig. 9 is
shown in Fig. 12, where encoding circuit 61 corresponds to
Fig. 6 and decoding circuit 62 corresponds to Fig. 9. The
timing unit 63 provides the various clock signals and the
- 29 -
~, .
llZZ711
record and read signals used respectively for data recordingand recovery. As previously mentloned with reference to
Figs. lla and llb, the position clock rate defines the data
recording and reading rate. In the recording mode the posi-
tion clock signal supplied from timing unit 63 is derived
from a write clock generator 64 which may be a constant
frequency crystal oscillator, for example, or an oscillator
synchronized to the speed of the magnetic storage medium on
which the data is to be recorded. The binary data to be
recorded is applied to encoding circuit 61 which produces
the 3PM encoded signal as hereinbefore explained. The en-
coded signal is then transmitted through write signal proces-
sing circuit 65, write driver 66 and read/write switch 67
to magnetic head 68 which records each signal transition of
the encoded signal in the form of a corresponding magnetic
flux transition on storage medium 69. Write signal proces-
sing circuit 65 may include signal processing circuits which
cooperate with the write driver to enhance the quality of
the magnetic recording.
In the recovery mode, magnetic head 68 produces a
signal in response to each magnetic flux transition on
storage medium 69 for transmission through preamplifier 70
and read signal processing circuit 71 to the input of de-
coding circuit 62. The signal supplied by the magnetic head
is in analog form and includes positive and negative going
portions representative of the successive flux transitions
on the storage medium. Read signal processing circuit 71
functions to convert the analog signal to an encoded signal
pulse stream wherein each pulse corresponds to a flux
transition on the storage medium. The time of occurrence
of the individual pulses of the encoded signal pulse stream
- 30 -
~lZZ~ll
are not identical with the signal transitions of the record-
ed encoded signal because of bit shift and other distortions
inherent in the recording and recovery process. For this
reason the encoded signal pulse stream is applied not only
to decoding circuit 62 but also to read clock generator 72.
The read clock generator may include, for example, a phase
locked oscillator synchronized by the encoded signal pulse
stream to run at a frequency that is a harmonic of the fre-
quency corresponding to the period of minimum spacing between
signal transitions, or more precisely, at a frequency equal
to 2/T which is equivalent to the position clock rate. With
the position clock rate, thus being controlled by the encoded
signal pulse stream, decoding circuit 62 operates in the
aforedescribed manner to reproduce the original binary data
at its output.
While the presently preferred embodiment of the
invention has been described with reference to an encoding
scheme in which each binary data word consists of three
bits and is represented by signal transitions at one or two
selected positions of a total of six positions in a data cell,
it should be recognized that other logic configurations may
be used within the ambit of the invention. For instance,
each binary data word may be represented by a transition
in one or both of two adjacent data cells each having a
length equal to 1.5T and wherein each cell corresponds to
one and a half binary data bits. An~ encoding scheme of this
type is shown in Fig. 13. It will be noted that in this
case the data cell boundaries coincide with the P3 signal
transition positions. In order to maintain the desired min-
imum spacing of 3T/2 between signal transitions, the one bitsat positions P2 and Pl of cell one and cell two respectively,
- 31 -
llZZ711
corresponding to bi.nary data word 100, will have to be mergedinto a transition at position P3 of cell one, that is at the
boundary between cells one and two. Likewise, merging will
be re~uired in the case of binary data words 000, 011 and 110,
for which a transition occurs at position P2 of cell two,
when followed by any of the words 101, 110 or 111 for which
a transition occurs at position Pl of cell one.
In addition to changing the data cell arrangement
relative to a data word as explained in the preceding para-
graph, it should be understood that other encoding circuitconfigurations may be used. For example, a write data
shift register responding to a bit clock signal and having
a capacity of only one data word may be used in combination
with encoding and logic circuits means which is actuated by
a word clock signal to receive the data word from the data
shift register and generate the code signals which in turn
are applied to a modulator comprising a modified shift regis-
ter controlled by a multiphase clock signal for performing
the merging feature of the invention together with the
storing and shifting functions of the write signal shift
register.
While the invention has been described in detail
with reference to a specific embodiment, it will be apparent
that improvements and modifications may be made within the
purview of the invention without departing from the true
spirit and scope thereof as defined in the appended claims.
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