Note: Descriptions are shown in the official language in which they were submitted.
~__~NTS
~he pres~nt invention i~ closely related to UrS-
Patent 4,096,395 issued June 2û, 1978 to George F. Bs~gel
20 a~d Robert M. Oa~es entitled "Automatic TransIer Control
Device And Voltage Sensor" and U.S. Patent 4,090,090 issued
May 16, 1978 to Paul M. Johnsto~ entiMed "~utomatic T:rans~er
Control Device And Frequency Sensor't~ Both of the above-
mexltioned tJ.S. patents are assigned to the assignee of the
present ~nvention.
~ ~r ~ ~r~
The i~ve~tion relates in general to eleetrical
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.
'~; '
. ~
. ~ , .
r~ 4 6 ~ 6 7 2
apparatus and, more particularly, to automatic transfer
control devices for selectively energizlng an electrical
dlstribution sy~tem from a plurality of electrical power
sources.
,~ ~ o r ~ o ~ r~
In supplying electrical power to industrial ~nd
commercial facilitles~ it ls often desirable to provlde
alternate sources of electrical power to insure continuity
of service. Sometimes these sources may comprise separate
feeder circuits ~rom the electric utility company. In
other situations one or more dlesel generators may be pro-
vided as alternake sources. Means must be provided to
switch the distribution system between the alternate sources,
and it is o~ten desirable to provide this switching capabl-
` lity as an automatic function. Thus, i~ the primary power
source should fail, the transfer control device will auto-
matically switch the distributlon system from the primary
to the alternate source.~ In order to provide the desired
~eatures for each individual installation many options are
o~ten specified, including automat~c retransfer when the
primary source once again returns to normal~ time delay
before switching, interlocking to prevent the load ~rom
being connected on a transient basis to both sources at the
same time, automatic startup o~ diesel generat~rs, division
of the load between the æourcesjand others.
In providing an automatic trans~er control device
~or a æpeci~i.c application, it was usually necessary to
engineer a custom design ~or each application, selecting
various relays and components to provide the desired features.
Prior art automatic trans~er control devices have sometimes
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~ 6~672
provided a certain degree of flexibility, but have often
required auxiliary relays and components. In additlon,
prior art automatic control transfer devices employing
electromechanical logic components have required substan-
tial amounts o~ power. It would be desirable to proYide
an automatic transfer control device having sufficient
flexiblity to handle a wide variety of transfer control
applications including both two-breaker schemes and three-
breaker schemes having two sources and two loads.
In addition, in prior art devices it was often
difficult to verify the operability of the device without
initiating a transfer. It would therefore be desirable to
provide an automatic transfer control de~ice including means
for testing the device without actually initiating trans~er.
SUMMARY OF ~HE INVENTION
In accordance with the principles o~ the present
inventlon, there is provided an automatic transfer control
device for generating signals to cause associated clrcuit
interrupters to selectively energize an electrical distribu-
tion network from a plurality of electrical power sources.The device includes means ~or senslng electrical conditions
on each of the electrical power sources, a plurality of
means ~or generati.ng output control signals to operate
associated circuit interrupters, and electronic digital
logic means ~or activating the s:Lgnal generating means ln
response to electrlcal conditions detected by the sensing
means. Means are also provided for programming the logic
means to cause the slgnal generating means to selectively
produce any of a predetermined set of output control signal
combinations in response to a predetermined set o~ electrical
--3-
~ ~ ~S"~3,r~ 3 4 6 1 6 7 2
condition~ upon the electrical power sources. Means are
also provided for supplylng the status of as~ociated circuit
interrupters to the logic means in order to provide lockout
and interlocking functions.
Each of the control signal generating means
includes an lndicator light for continuously indicating
the control signal being supplied from the electronlc digi-
tal logic means to the signal generating means. A mode
selector switch ls provided to enarglze the control devlce
in either manual, automatic, or live test mode. In the
live test mode, the output control signal generating means
are defeated, allowlng a test ~utton to simulate a ~ailure
upon either of the electrical power sources, causing the
automatic transfer control device to lnitiate a transfer
operation which is complete except for actually commandlng
the assoclated circuit interrupters to transfer the dlstrl-
bution system from one source to another. The logic signal~
provided to the output control signal generatlng means during
the test function are shown by the indicator lights, but
with a flashing rather than a continuous indication to show
that the control device is in khe test mode.
BRIEF DESCRIPTION OF THE DRAWIMGS
The novel and distinctlve features of the inven-
tion as set forth with particularity in the appended claims.
The invention, together with further ob~ects and advantages
thereof, may be best understood, however, by reference to
the ~ollowing description and accompanying drawings, in
the several figures of which like reference characters iden-
tify like elements, and in which:
~igure 1 is a block dia~ram of an electrical dis-
-4-
~ 46,672
tribution system having two alternate sources o~ electrical
power and utilizing two circuit interrupters to suppl~ a
single load;
Fig. 2 is a block diagram of an electr~cal dis-
tribution system employing two alternate sources o~ elec-
trical power and three circuit interrupters to supply two
loads;
Fig. 3A is a schematlc drawing showing external
connections to an automatic tran~er control device employ-
.
ing the principles of the present invention;
Fig. 3~ is a functional schematic drawing show-
. v ~ c ~
ing signal flow through the de~c~ o~ Flg. 3A3
Fig. 3C i5 a detail functional schematic drawing
showing the signal flow through the voltage, ~requency, and
timing logic o~ the device shown in Figso 3A and 3B;
Fig. 4 is a schematic diagram of the power supply
circuitry of the automatic transfer control device o~
Fig. 3~;
Fig. 5 is a schematic diagram o~ the voltage sen-
sing logic circuitry o~ the device of Fig. 3B,
Fig. 6 is a phasor diagram of the voltages sensed
by the circuitry o~ Fig, 5;
Fig. 7 is a schematic diagram of the ~requency
senslng logic clrcuitry;
Fig. 8 i8 a schematic d-lagram of the main breaker
logic circuitry;
Fig. 9 is a schematlc dlagram o~ the timing logic
circuitry;
Fig. 10 is a schematic diagram o~ the tie breaker
logic circuitry;
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~69670 ~6,67~ ~6,672
Fig. 11 is a schematic diagram of the ATG
control logic circuitry;
Fig. 12 ~s a schemat~c diagr~m o~ the inter-
~ace circuitry; and
Fig~ 13 is a per~pecti~e ~iew af the a~to-
matic trans~er control deviceO
D~SCRIPTION OF THE P~FERRED E~BQ~DMENT
lo General Descri~tion~
In Figure 1 there is shown a multiphase
electrical distri~u~ion ~y~tem 10 including an auto~
mat~c transfer control device 12 (hereina~ter re~err~
~o as an ATG) embod~ing the principles o~ the present
inve~tion. The system 10 i~cludes a multipha~e electri-
cal load 14 which could be a single piec~ o~ apparatus
such as a comput0r or a much larger load such as a
fac~o~y~ hospital~ o~ shopping cen~er. The l~ad 1~ is
supplied ~rom either c~ two alberna~e m~ltiphase elect~1-
cal sources 16 and 1~, whlch could be tr~nsformer~ or
die~el-powered electrlcal generakors. The source~ 16
and 1~ are 3electively connected to th~ load 1~ through
~irst and second main circuit breakars 52 1 and 5~2~
The clrcuit breaker~ 52-1 and 52-2 are operated by the
ATC device 12 accordi~g to the sta~us o~ the sources 16
and 1~. The ATC 12 senses alectrical cond~tions upon
~he source~ 16 and lg through con~ection~ 24 and 26~
The parameters sensed by khe ATC include ~oltage on each
phase, phase seq~ence~ and ~requency. Logic circuitry
within the ATC acts to select the highest quali~y source
to supply power to the load 140
Figure 2 shows a multiphase electrical
distribution system 11 simllar to the system 1.0 shown
in Figure lo In the
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system 11 t howe~er7 there are t~ electrical load~ 2~ and
30 connected by a tie connection 32. A tie breaker 52-T
i5 pro~ided to selec~ively interconnect ~he kwo loads 2
and 30.
In the system 11 shown in Flg~re 2 a variety of
con~igura~lons are possible~ With both mai~ breaXers 52~1
and 52-2 closed and the tie breaker 52~T ~pen~ ~he first
load 2~ ~11 be connected to the ~irst source 16 and the
~econd load 30 ~11 be connected ~o ~he second ~our~e ~g.
Alterna~i~ely, with the ~ir~t main breaker 52-1 ope~ a~d
the second main breaker 52-2 and the tie breaker 52-T ~losed~
both of ~he loads 2~ and 30 will be supplied through the
source 1~. W~th main breaker 52~1 a~d tie breaker 52-T
closed a~d mai~ breaker $2~2 open~ both loads 2~ ancl 30
will be supplied through ~he source 16.
: The AT~ 12 comprises ~ol~age an~ ~requency sensors
for each source~ the sensors being conne~ed ~o the asso-
cia~ed sour~e through potential transformers. A plurality
o~ input and outpuk te~minals are provided to supply the
ATC with in~ormation concernlng th~ status (open or closed~
o~ as~ociated circuit breakers~ the desired action ~o be
taken ~pon ~ailure of the source~ the tgpe of distribu~ion
system being corltrolled, etc~ Outputs from t,he ATC include
CLOSE and TRIP signals for eaoh breaker9 and GE~RATOR ~TA~T
signals. Each input signal i~ 120 volts A.G. ~or high noise
in~nun:lty and i9 conve:r~ed by inte~c~ circuitry to 12 volts
D.C. ~or compatibility with logic circuitry. Outpu~ signals
~re also 120 ~olts A~C.
The ATC is connected through power transfo~mers to
ea~h source and contains logic ~o select the best source at
h~.~ 3~ 6,670 1~6~671 ~l672
any given time to suppl~ control power to the ATC.
A plurality of timing func~ions are pro~ided ko
per~ election of a ~de range of ~me delay trans~er and
control actions. These timing functions are provided by a
plurality of oscillator~, one o~cillator associated with
each ~unction7 each being connectsd to a common digikal
counterO
In Figures 3A, 3B7 and 3C there ls shown a sche-
matic functional diagram o~ ~he ATC 12 connected to a three-
breaker, four~wire ele~trical distribu~lon networ~ as shownin Flgure 2. The ATG 12 is connected ~hrough three-phase
; potential trans~ormers ~0, ~2 and phase and neutral conduc~
tors 46, 44 to ~he firs~ and second el0c~rical sourc:es 16
and l~ (not shown in Figo 3A~ A mode selector switch 43
shown in the lower legt o~ ~lgure 3A ls provided to selec-
tively sw~ch the ATC 12 between aukomatic, manual, and live
~est modes~, The potential tr~nsformers 40 and l~2 supply
~oltage and frequency inputs ~rom the respective sources to
provide a signal through input ~erminals A9 throu~;h Al29 and
20 Bl ~hrough B4 to ~he ATC ko determlne i~ ~he source is at no~
mal ~oltage ~nd frequency and has proper phase rotationO Nor-
mal voltage is defined as the minimum operating voltage at
whlch the customer desire~ the system to operate7 as selected
on the ~oltage pickup rheostats 44.
The ATC include~ two identical sets o~ circuitry
~or ~o~tage~ ~requency~ and timing logic~ control power logic3
control power output, auxiliary ~ransf'er input, and generator
start lo,gic, with one set o~ circuitr~ for each source. I
addition7 it contains CLOSE and TRIP output signal capabilities
30 ~or each of two main breakers, and the tie breaker; e~en
3~
4~670 46,671 46,~72
though the tle breaker capabilities may not be used in each
appllcation. The means of adapting the ATC to operate from
either two-or-three-breaker systems wlll be described in
greater detail hereinafter.
2. Description o~ Operation:
2.1 Volta~e and Phase Sensor Inputs
Each source input includes two programming switches
to specify the voltag~e and wiring configuration of being con-
nected thereto. The programming switches PS-9 and PS-10
- 10 select either three-wire (three phase conductors) or four-
wire (three phase conductors and one neutral conductor)
systems; the programming switches PS-ll and PS-12 select
either 120 volt or 69 volt input voltage levels. I'hus, there
are four dif~erent ways to connect the voltage and ~requency
inputs A9-A12 and B1-B4: 1) For use with a system voltage of
480/277V~ using 3 potential transformers (PT's) with a 4-1
ratio connected to Y~Y. The input ~rom the secondary of the
PT's will be a 4-wire connection, with the voltage on the
secondary of the PT's being 69V~ phase to ground. The pro-
~ 20 gramming switches are then set for 4-wire, 69V operation.
; 2) For use with a system voltage of 480/277V, using 3-PTIs
with a 2.4-1 ratio connected Y-Y. The input from the secon-
dary of the PT's will be a 4 wlre connection with the voltage
of the PT's being 120V phase to ground. The programming
switches are then set for 4-wire, 120V operation.
3) For use with a system voltage o~ 208/120V with no PT's.
Connection from the sources will be 4-wire, with the voltage
belng 120V phase to neutral. The pro~ramming switches are
then set ~or 4-wire, 120V operation.
30 4) For use with a system voltage of 480V, using 2 PT's with
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~ 3~ 6,670 46~671 469672
a ~-1 ratio connected open delta. The inpu~ ~rom the secon-
dary o~ the PT~s will be a 3-wire connection9 with the vol-
tage on the secondar~ o~ the PT's being 120V phase ~o ground~
The progr~mning switches are then set ~or 3-wire" 120V opera-
~tion.
-Four L~E~D.'~ (Li~ht Emitting Diodes) are suppli0d
for each source. When lighted, one L~E~DD will indicate thak
the phase sequencing is correct~ The other thrae L~E.D~Is
are marked phase A9 phase B and phase G; a~d are lighted when
their respecti~e phase ~oltages are normal~ For instance; if
:a voltage loss occurred on ph~se A, with phase ~ and pha~e a
still at no~mal voltageg the phase A ~.E.D~ would extinguish,
i~dicating thak phase A was below normal. The pha~e B and
C L~E9D~ 9S w~uld remain li~htedO
1~ voltage-adjusting rheostats ~7~ and R577 are
provided ~or each source for ~oltage pic~up and volkage d~op-
outp:respecti~ely~ ~oltage pick-up i5 khe ~e~el to which a
phase voltage must rise for the ATC to racognlæe it as having
returned to normal~ The w lkage pic~-up r~eos~t 46 is
adjustable from 90% to 9~ o~ rated voltage~ The voltage
drop-~ut rheos~at is adjustable ~rom 65% to 90% o~ rated
voltag~
Z:~
Input to the frequency sensing logic i5 obtained
internall~ on the ATC ~rom the voltage inputs A9-~12 and
B1~4. I,ike the voltage inputst the ~requency sensing logic
will :~unctiorl at 120~,, 60 ~æ or 65lV~ 60 Hæ. It detects both
under.~requency and over~requency cond~tionsp ~kh a range of
50 to 70 H~. Both the over and under drop-out poin~s have
independent pick-up di~erentials within ~he range of the
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1~6~670 ~6 7 671 1,6,67
drop~out points. The pick-up and ~rop~ou~ points (unde.r~
~requency and o~er~requency) plus the ~i~ferentlals are
sel~cte~ for the specific applicatlons; and once selected,
cannot be changed~
The underfrequency drop-out point m~ be selected
anywhere withl~ ~he range of 50 Hz - 59 Hz~ The pick-up
dif~erential must khen be select~d at a point hi~her ~han
the:drop~out point and less than 61 H~ For example: i~
the u~der~requency drop-ou~ point selected is $4 Hz~ the
- 10 pick-up differen~ial selected mus~ be between 5~ Hz and
61 ~
The o~er~requency drop~out may b~ selected any-
where in ~he range of 61-70 Hz~ The pic~up dif~erential
must the~ be ~eleoted at a poin~ le~s than the ~rop-~out
point and higher than the 59 Hz~ For example, if ~he over-
frequQncy drop-out point selected is 65 Hz 5 the pick-up
di~erential selected must be 59 Hz ~n~ 64 Hz.
An L~E~Do i~ s~pplied7 which when lightedt
indicates that the ~reque~cy is within the predetermined
lim~ts o~ both the o~er and underfrequency drop-out pointsO
~ en frequency sensing is nok desired,, ~his logic
can ~e omitted and the ATC will assl3me no~nal ~requ~ncy~
The ~requency logic can per~orm two basic func
tions~ sel~cted ~or each source b~ programming ~witch~s PS-7
and PS-~ (Fig. 3a)~ respectively:
1) "Preve~ Closing Only" - With the mode ~elec~or switch
43 in the a~tomatic positio~ either ~ or khree breaker
operation specif~ed, and one source nonmal.ly deenQr~ized
(for example, an emergency genera~r), low ~oltage upon the
normal source will cause a signal to be sent to start tha
generator~ When the ~enera~or comes up to proper voltage
but the ~requency
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46~670 l~6~671 46,672
is nok wlthin the proper operating range as selected, the
generator source main breaker will be prevented from auto~
matically closing until the ~requency has reached proper
operat~ng range.
2~ "Automatic Trans~er Function" - With the mode selector
~3
switch/in automatic position~ two-or three-breaker operation
specified, and both sources or one source only normally
energized, if the ~requency on a source that i9 ~eeding a
load falls or rises beyond the limits of the normal operating
range and after a predetermined time delay (as selected on
the o~f delay timer, described hereinafter) the main breaker
on the faulted source will trip and a transfer operation to
the alternate source, as programmed, will occur.
2.3 Manual Breaker Closin~
Terminals A2 - Breaker 52-1
B10 - Breaker 52-2
C3 - Breaker 52-
~
These inputs provide ~or electrical closing of thebreakers by means of a control switch, pushbutton, or other
manually operated control device and`are operative only with
the mode selector switch 43 in the manual position. When
120V A.C. appears upon any of these terminals, the ATC will
generate a 120V A.C. output signal at the corresponding CLOSE
output A6, B7, or C5.
An L.E.D. is provided to indicate the logic slgnal
being supplied to the output signal generating circuitry.
The L.E.D. will be lighted when a "close breaker" logic sig-
nal is being supplled to the interface circuitry which gene-
c~.a~
rates the 120~ 4e~' command ~or the breaker. However,
there are times when the L.E.D. will be lit yet the breaker
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~'..2 ~ 46,670 46,671 46,672
remains open. For example, lf through a manual control
switch or an autotransf7er signal the ATC is being signalled
to close the breaker, and due to a malfunction, the breaker
does not close, the L.E.D. will be lit~ indicating that the
; ATC logic is calling for a closing operation.
2.4 Manual Breaker Trippin~ (In~uts)
~ .
Terminals A1 - Breaker 52-1
B9 - Breaker 52-2
Cl - Breaker 52 T
These inputs provide for electrical tripping of7 the
breakers by means of a control switch, pushbutton, or other
manually operated control devices, and are operatlve only
with the mode selector switch 43 in the manual position~ ~en
~ 120V A.C. appears on any of these terminals, the ATC w~ll
`~- operate 120V A.C. output sig7nal at the corresponding TRIP out-
put terminal A7, B8 3 or C6. An L.E.D. is provided to lndl-
cate the logic signal supplied to the output circultry which
generates the 120V ~ signal f70r the breaker trippin~
relay or trip coil. When the breaker is tripped, the L.E.D.
will be lighted. Again~ as described previously, it is pos-
sible f70r the L.E.D. to be lighted yet the breaker remains
closed.
2 5 Aux. Automatic Transfer
. _ __ __ _
A5 - Source #1 to Source #2
B9 - Source #2 to Source #l
These inputs are provided in the event that an
automatic transfer has to be initiated by means other than
the ATC device's built-in voltage and f7requency sensors,
such as external relaying on a complex system.
A 120V A.C. signal to this input causes an imme-
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46~670 46,671 46,672
diate trans~er (tlme delay ls bypassed from one source to
the other when the mode selector switch 43 is in the auto-
matic mode and the other source is within normal limits.
Once this signal is removed ~rom the input, an lmmediate
retrans~er (time-delay is bypassed) w:lll take place if:
1) The ATC device is programmed for automatic return~to
; normal, and
2) The source is within the other limi~ations of proper
voltage and frequency.
2.6 Auxiliary Lockout
-
A3 - Breaker 52-1
Bll - Breaker 52-2
C4 - Breaker 52-T
A 120V A.C. signal into this input can be ~rom
any ex~ernal device that requires that the breaker be blocked
from electrical closing. This input will not trip the breaker
i~ it is closed. It merely blocks electrical closing after
the breaker is tripped. These lockout inputs are not voided
by the selector switch 43 and will ~unction in any mode.
2.7 _Breaker Status Indicator
A4 - Breaker 52-1
B12 - Brealcer 52-2
C2 - Breaker 52-T
These inputs inform the ATC of' the status (closed
or trlpped) of the associated breakers, information whlch ls
required for electronic interlocking and breaker status indi-
cation. The signal to the lnput is supplied from a normally
closed (N.C.) breaker auxiliary switch.
2.8 Ground Fault Lockout
C~
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~ 3' 46,670 I~6,671 46,672
The signal to this input is generated by a normally
open (N.O.) contact which is acti~ated by a ground fault
detection sy~tem. When energized, thls input will prevent
electrical closing of all breakers. If a breaker is already
closed, this input will not trip the breaker. Also, unlike
Auxiliary I.ockout, a ~ signal ls sent to all breakers that
are open. This signal will trip the breaker lf the breaker
has been mechanically closed by the Manual Close button on
the front of the breaker. This is to prevent any open breaker
`~ 10 from being closed into a fault.
Removing the signal from the input will not void
the lockout; once the lockout is activated, it must be reset
by input C8 (Latch Reset).
An L.E.D. is supplied to indicate that ground ~ault
lockout has occurred.
2.9 Overcurrent Lockout
Cl~
The signal to this input will be ~rom an N.O con-
tact that is activated by an overcurrent tripping device asso-
ciated with the breaker. When energi~ed, thls input will
prevent closlng of all breakers (If the breaker is closed,
this will not trip the breaker). Also, unlike Auxiliary
-rl~l~
Lockout, a ~ signal is sent to all breakers that are open,
which signal will trip the breaker if it has been mechani-
cally closed by the Manual Close button on the front Or the
breaker.
Removing the signal ~rom the input will not void
the lockout; once the lockout is activated it must be reset
by input C8 (Latch Reset~. ~
An L.E.D. is supplied to indicate that overcurrent
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~ 46,670 46~671 46,672
lockout has occurred.
2.10 Latch Reset
~` C8
This input is used to reset the ATC logic a~ter a
lockout has occurred ~rom C9 or C10, and the fault has been
cleared.
The signal to the input will be from an NØ push~
button or an N.C. contact ~rom an electric or hand reset
relay that was used to energize C9 or C10.
Note: Signal to C~ or C10 must be removed be~ore
latch reset will function. -
If ~or some reason all control voltage is lost,
the latch will automatically reset.
:~ 2.11 Control Power
Dl - D2 Source #1 D4 - D3 Source #2
Input is 120V, 60 Hz power from the secondary
of a control power transformer. The control power trans
former primary is connected to phases A-and C o~ each source.
2.12 Auto Disable
Cll
The signal to this input is from a "Manual' (M)
contact of the mode selector switch 43. This input signals
the logic that all functions that are per~ormed in the auto-
matic mode should now be voided, except ~or the interlocking
and lockout.
2.13 _Test Input
C12
The signal to this input is from a '!Live Test" (LT)
contact on the mode selector switch 43. This input signals
the logic to perform all operations in the same manner as the
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~ 3~ 463670 ~6,671 46,672
automatic mode, except to disable the circuitry which gene-
rates the output sigrlals to the breakers~ thereby preventing
the breakers from being tripped or closed by the ATC.
2.14 Close_ ~
A6 - Breaker 52-1
B7 - Rreaker 52-2
C5 - Breaker 52-T
When a signal is received from the ATC logic to
electrically close a breaker, the output ~rom these termlnals
is 120V, 60 Hz. It should be noted that output remains at
120V as long as a closing logic signal is present. ~When
in the automatic mode, the closing signal is not removed
until a trip or lockout is called for.~
When these outputs are energized, the L.E.D.'s (as
described under Manual Breaker Closing) are lighted.
2.15
A7 - Breaker 52-1
B6 - Breaker 52-2
C6 - Breaker 52-T
When a signal is received ~rom the A~C logic to
electrically trip a breaker~ the output from these terminals
is 120V, 60 Hz. It should be noted that the output sta~s at
120V~ as long as the tripping logic signal is present. When
ln the automatic mode, the tripping signal is not removed
unti.l a close is called ~or.
When these outputs are energized, the L.E.D.'s (as
described under Manual Breaker Tripping) are lighted.
?.16 Control Power Output
D5
This is the output ~rom which control power is
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4G,670 46,671 46~672
obtained for the equipment remote from the device (indicating
lights, misc. relays, etc.). This output is under the influ-
ence of the control power transfer scheme~ which ls a part
of the ATC. The output is 120V, 60 Hz.
2.17 Generator Star_
A8 - Source #l controls Gen #2
B5 - Source #2 controls ~en #l
These outputs are energized whenever their corre~-
ponding source voltage is within the normal limits. The
outputs are connected to auxiliary relays which, under normal
; conditions, will be energized. lf a source falls below nor-
mal limi~s and the ATC logic calls ~or an automatic transfer,
the generator output will do one of the followlng:
the voltage falls to less than 55% of rated voltage
(control power threshold which is described ln 2.18), the
Generator Start output will be deenergized immediately~ and
the auxiliary relay will drop out, thus sending a signal
starting the generator.
2) I~ programming switch (PS-6) is closed, the generator
starting operation will be delayed. Otherwise, the operation
is begun as soon as the voltage sensors call for a transfer. ~ -
a. With programming switch PS~6 set for no time
delay, as soon as the voltage sensors ask ror a
trans~er, the ~enerator Start output w:lll drop out
(even if control power is still available), deener-
gizing the auxiliary relay, thereby sending a signal
to start the generator.
b. With programming switch set for time delay, when
the voltage sensors ask for a transfer, the gene-
rator start output will be delayed l/2 of the o~
-18-
46,670 I~6,671 46,672
delay timer setting before being deenergized
provided sufficient control power is still
avallable, i.e.~ ~ 55~)
The signal to shut down the generator is accom-
plished by reenergizing the Generator Start output. The out-
put is reenergized a~ter the normal source has returned, a
retransfer has occurred (if programmed ~or automatic return-
to-norma]), and the Generator Unloaded running timer has timed
out. The Generator Unloaded running timer is ad~ustable from
15 sec. to 30 min. When the ATC is programmed ~or manual
return-to-normal~ the Generator Unloaded running time begins
to time out as soon as the mode selector swltch 43 is placed
in the manual position, and the tripped breaker is reclosed.
An L.E.D. is supplied for each ~enerator Start out-
put. When the L.E.D. is llghted, this indicates that the
Generator Start output is energized and is not calling ~or a
generator start.
2.18 Control Power Selector Switch - Programmin~ Switch #l
(PS-l)
I'his switch is to designate which power source is
selected as the normal source of control power ~or the ATC
itself. When programming switch PS-l is open, source #l is
selected as the normal control power source. When switch
PS-l is closed~ source ~2 is deslgnated as normal. The above
statements apply only when both sources are at normal voltage.
The control power trans~er logic will seek out the
higher voltage source, regardless o~ the programming switch
PS-l settlng, if the level o~ khe designated source falls
below the drop-out setting of its assoclated voltage sensor.
Example: Programming switch PS-l set to select
--19--
~3-~ 3~ 46,670 ~,671 46,67
source ?$1 as normal control po~rer ~upply source. I~ the
volt~e on source ~1 ~alls below ~he drop~out ~etting of
the ~1 vvl~age s~nsor and ~he ~2 voltage sensor show~ ~or-
mal voltaget the control power trans~er logic wi~l signal
~or a transfer to sotarce ~ en the reskored voltage on
so~rce ~1 exceed~ the pick~up level o~ its voltage sensor,~
a return to source ~1 ~11 occur9 because th~ PS-l s~ti~g
desi.gna~ed source ~1 as normal cQntrol power ~u~ply.
If ~oth ~oltage sensors indicate ~oltages below
their respective drop-out levels~ the logic will ~hen seek
to select the source l~th the higher voltage level, pro~ided
~hat the source is higher than 55% o~ no~al volt ~e.
The 55~ criterion is chosen beGause a failure o~
a singl~ phase results i~ a phase~to~ph~se ~roltage o~ about
57% of no~al phase-to-phase roltage. Although th~s degree
o~ ~ailure would seriollsly a~ect the main load beir~g sup-
plied and requires tha~ t;he load be ~itched ko an alternate
source~ 57% o~ the normal voltage is still sati~ac~ory ~or
operation o~ the ATC~ Howe~er~ a vo~tage appreciably less
than thi~ would result in unreliable control action., There~
~ore~ 55% of normal voltage i~ ~elected as the poin~ at
; which a control power tran~fer ~hould occur~
~ no con~rol pow~r is available at an input be~
cause o~ a blown ~u~e or ~aulty c~ntrol power transformer7
r~gardless of the indication o~ it~ associated voltage
~ensor9 the ~ontrol logic (~ee 4.~) wi~l ~elect th~ other
source provided that the ~ourcs ~s highsr than 55% o~ normal
volkage.
I~ the voltage on both source~ fall~ below 55% of
normal~ all con~rol power will be disabled until o~e o~ ~he
sources retu~ns to a value greater than 55% o~ normal~
~20-
. ~; .
~ 46,670 46,671 ~6,~72
. - .
Two L.E.D.'s are supplied ~ one for source ~1, and
one for source #2. The one that is lighted indicates which
source is supplying the control power.
2.19 Tie Trip Inhlbit-
Programming Switch #2 ~PS~2)
This programming switch is to be used to selectmanual or automatic return-to-normal, on a 3~breaker system
(2 main breakers and a tie breaker).
When the programming swltch PS-2 is in the open
position and a transfer operation has taken place ~1 main
breaker tripped and the tie breaker closed), and when the
failed source returns to normal, and after a predetermined
~- time delay, the tie breaker will trip and the maln breaker
reclose (automatic return).
When the programming swltch PS-2 is in the closed
position, a retransfer back to the restored source will not
occur, and the tie breaker will remain closed. Retransfer
back to the restored source can be accomplished in either of
two ways:
1) If the failed source has returned to normal and failure
occurs on the source to which the load has been transferred,
then the main breaker on the failed source will tr:Lp, and the
main breaker on the restored source will reclosed ~the tie
breaker will remain closed during this operation).
2) After placing the mode selector switch 43 in the Manual
position, the breakers involved can be tripped and closed
using their respective manual control switches or pushbuttons~
2.20 Trip #2 if #1 is Normal
Trip #l if #2 ls Norma
.
Programming Switches #3 and #4 (PS-3, PS~4)
-2~-
l~6~670 46l671 46~672
These programming switches are to be used to select
manual or automatic return-to-normal on a two-breaker system
(2 main breakers and no tie breaker).
If both of these programmlng swltche~, are left open,
the first source energized will be se:lected as the normal
source that feeds the load. If an automatic transf'er opera-
tion takes place and the railed source then returns to nor-
mal, a retrans~er back to the restored source will not take
place as long as the source that ls feeding the load remains
at normal.
Retransfer back to the re~tored source will be per-
~ormed in either of' two situatlons:
1) The failed source has returned to normal and a f'ailure
occurs on the source to which the load has been transferred.
2) With the mode selector swltch 43 in the Manual position
and the breakers are tripped and closed using thel~ respec-
tive manual control switches or pushbuttons.
PS-3, when closed, designates maln breaker 52-l and
source #l as the normal power source that reeds the load.
When a trans~er operation ha,, occurred and transferre~ ~he
load to source ~2g a retransfer back to source #1 will occur
as soon as source #l returns to normal and the timers ha~e
timed out.
PS-4, when closed~ performs the same ~unction as
PS-3, except main breaker 52 2 and source #2 i~ designated
as the normal power source for the load.
Either PS-3 or PS-4 may be closed,, or neither one;
they may not both be closed. Note that PS-3 and PS-4 desig-
nate normal power source for the load, while PS-l designates
the normal source of' power for the ATC device and its control
-22-
~ ~ ?$~ 46,670 46,671 46,672
functions.
? .21 Ke~p Last Source
Programming Switch #5 (PS-5)
I'his switch, when closed, inhibits automatic trip-
ping of a main breaker if it receives a transfer signal from
its source and the load has been previously transferred to
this source. This inhibition is removed when the source from
which the load has been transferred returns to normal.
When ~ PS-5 is open and the load has been trans-
ferred to a source #2 due to a failure on source #l, and ifsource #2 (now feeding the load) has a failure, the main
breaker #2 of second failed source ~2 will see an automatic
transfer signal and will trip even though threre is no avail-
able source to transfer to. This will occur only ir the vol-
tage on the failed source #2 has dropped below the drop-out
setting of the voltage sensor and is above 55%, thereby provi-
ding control power.
In either case (both main breakers tripped, or one
tripped and one closed), if both sources are subnormal and
one source returns to normal, the normal source breaker will
close and the other main breaker, if closed, will trip regard-
less of how the system was programmed (manual or automatic
return to normal).
2.22 Delay Generator Start
Programming Switch ~Y6 (PS-6)
This programming switch, when closed, delays drop-
out of the Generator Start output approximately 1~2 of the
setting of the of~-delay timer when control power is available
(refer to Generator Start).
~en PS-6 is open, the Generator Start output ~ill
-23-
;3~ 69670 46,671 46,672
drop out as soon as an automatîc tran~r sigrlal is recei~ed~
Programming Swi~ch ~7 ~PS~7) - Source ~1
Progra~mning S~rîtch ~ (PS-~ ) Source ~2
l~ese progranmling ~ ches are provlded to
select the func~ion tha~ i~ to ~e per~Po~ed by the fre-
quency sensor~ ~as descr~bed under Freque~cy ~enslng Logic)3
Programming Switch #9 ~PS-9~ - Sourc~ r~l
Progra~ning ~itch j~10 ~PS- 10) Source ~2
These progr~iIIg switches are provided ~o
select the ~ype OI con~ection to be applied to ~he vol~age
~ensors9 3-~Jire (pha~e conductor~ onl~ o~ 4-~ire (phase
aonductQrs plu~ neutral ~ ~ as descr~ ~ed in ~oltage and Pha~e
Sensor ~puts 2.1,.
8:2~2~_
: Progra~ming S~ntch -~ll (PS~ll)
Progra~ml~g ~witch #12 (PS-12~
mes~ programming swi~ches are provlded to ~elect
the input ~ol~age sensors (as described u~der Voltage and
Phas~ Sequencing Inputs)v
2~e r ~
A total o~ ~iæ adjustable t~mers a~e ~urnLshed,
~hre~ for source ~1 and three ~or source ~2~
1) On-delay timlng ls supplied Por both sources to ensure
that when a failed source returns to normal~ the vo~tage is
~ta~llized before a retrans~or wflll occur~ The tim~ng range
is ad~usta~le ~rom 2 seconds to 10 minutes.
2~ Of~-de~ay timing i9 supplied ~or both sources to ensure
that momen~ary dip~ in voltage will not cause a trans~er
oparatlon~ The timing range is adjustable from 2 seconds
~o
2~-
~ 46~670 46S671 46l672
lO minutes.
3) A Generator Unloaded running timer ls provided for each
-~ source. These timers have a range o~ 15 seconds to 30
minutes.
Two L.~.D.'s are supplied, one for each set o~
on-and off-delay timers as described in l) and 2) above.
The L.E.D. will indicate when the timers are tlmlng and which
timer was last to operate.
L.E.D. Operation - ~ -
l. When either the on-or o~f-delay timer is timing, the
L.E.D. will be flashing.
2. If the on-delay timer was the last to operate~ the
I..E.D. will be continuously lighted.
If the o~f-delay timer was the last to operate, the
L.E.D will not be lighted.
3. Se~uence o~ Operation:
3.1 3-Breaker S~stem
3.1.1 Normal Operat~ion
Under these conditions, both sources are at normal
voltage and are ~eeding their respective loads. That ls,
both main breakers 52-l and 52-2 are closed, and tie breaker
52-~ ls open.
3.1.2 Automatic Mode
_,
1) With a loss o~ voltage on one of the sources, the ~ollowin~
will occur: Assuming a failure of source #1, the source #1
voltage sensors wlll generate a logic signal to start the of~-
delay timer. When the o~f-delay timer expires, the programmable
logic will generate activatlng logic signals to the output
signal generators causing breaker 52-l to trip and breaker 52 T
to close. The sa~e operation occurs should source #2 have
-25~
~ 3~ ~ 46,670 46,671 46,67~
failed, except breaker 52-2 would trip after a time delay and
the tie breaker (52 T) would close thereafter.
2) Should there be a simultaneous loss of voltage on both
~ sources, the following will occur:
- a. If both source voltages fall below 55%~ no control
power will be a~ailable. Thus~ both main breakers will
remain closed and the tie breaker open.
`~ b. If one (or both) of the sources is below the accept-
able limits o~ the voltage sensors, but greater than 55~,
control power will be available and the f`ollowing wlll occur:
(l) If programming switch PS-5 (Keep Last Source)
is open, both main breakers will trip after
their predetermined time delay. If` one main
breaker trips before the other due to a
shorter delay, the tie breaker will close,
whlch is acceptable at this point. This would
almost surely be the case since to set ?
timers (2 seconds - lO minutes) at the exact
same time would be nearly impossible. Which-
ever source first returns to normal will cause
the corresponding main breaker to close~ ~ol-
; lowed by the tie breaker (if not already
closed).
(2) If' programming switch PS~5 (Keep Last Source)
is closed~ the f`irst source for which khe of`f`-
delay time has expired will experience a main
breaker trip. Once that main breaker trips
it will be followed by tie breaker closure.
The other main breaker is prevented from trip-
ping (even though the corresponding off`-delay
-26-
46~670 46~671 469572
timer has expired). If the flrst source then
returns to normal a~ter a predetermined
time delay (on-delay) the main breaker on
the low source will trip, followed by clo
slng of the main on the returned source
(tie breaker remaining closed).
3) Should there be a loss of voltage at one source and ahnormal
voltage at the other, a transfer as described in (1) above
would have already occurred. Therefore, the following se-
quence is also true should voltage be lost on the source to
which the load has been transferred:
a. When the normal source fails and neither of the
; sources is above 55%, no control power will be available.
Thus, there will be no change in breaker status (one maln
breaker and tie breaker closed, other main breaker open).
~; b. When the normal source fails and one or both of the
sources are above 55~, control power will be available and
the following will occur:
(1) I~ programming PS-5 (Keep Last Source) is
open, after the predetermined time delay, the
main breaker of the source that was serving
the load ~ill trip resulting in a condition of
both maln breakers tripped and tie breaker
closed. Whichever source returns to normal
fir~t, after a predetermined time delay (on--
delay) its main breaker wlll close, thus leavlng
the condltion o.~ one maln breaker and the tle
breaker closed (tie breaker had never been
tripped) and the main breaker open.
(2) If programming PS-5 (Keep Last Source) is
-27-
.
3~ ~ 46,670 46,671 46,672
closed, the main breaker that is feedlng the
load will be blocked from tripping. One
main breaker and the tie is now closed, with
one main breaker open and both sources at
subnormal voltage. If normal voltage is re-
-~ stored to the source that was last fee~ding
the load, there will be no change in breaker
status. If voltage is restored to the source
~rom which the load was originally trans~erred
after a predetermined time delay (on-delay),
the main breaker on the subnormaI source will
; trip, followed by closing of the main on the
restored source which yields the condltion of
normal source maln breaker and tie breaker
closed (tle breaker had never been trlpped)
and subnormal main breaker tripped.
4) Return to normal after a trans~er operation can be accom-
plished in one of two ways.
a. When programming PS-2 (rrie Trip Inhibit) is ln the
open position and voltage on the source from which the 102d
had been transferred returns to normal after a predetermined
time delay (on-delay), the tie breaker will be tripped ~ol-
lowed by reclosing of the restored source's main breaker.
(Automatic return to normal)
b. When programming PS-2 (Tie Trip Inhibit) is in the
closed position and the volta~e on the source from which the
load had been transferred returrls to normal, no retransfer
will occur.
The mode selector switch 43 must be placed in the
manual position and khe tie breaker then tripped and the main
-28-
46,670 46,671 46,672
breaker reclosed by means of their respective ~anual control
swltches or pushbuttons.
3.1.3 Manual Mocle
With the mode selector switch 43 in the manual
` position~ control of the breakers is placed in the hands of
the operator. Breakers may be closed and tripped (a~ gov-
erned by lnterlocki.ng and lockout) by means of their respec-
tive manual control switches or pushbuttons.
3.1.4 Live I'est Mode
The purpose of the live test mode is to test the
operation of the ATC without changing the statuæ of the
breakers. This is accomplished through the breaker status
indicating L.E.D.'s as described in 2.3 and 2~4.
1) There are two test pushbuttons provided, one for each
source, connected to terminals A9 and B4 to stimulate loss
of incoming voltage to the source. With the mode selector
switch 43 in the "test" position and one of the pushbuttons
depressed and held, one of the phase-indicating L.E.D.'s and
the CLOSE L.E.D. of the main breaker will go out. After the
off-delay timer has timed out, the main breaker TRIP L.E.D.
will begin flashing~ followed by the tie breaker CLOSE L~E.D.
which will also begin flashing. These flashing L.E.D.'s indi-
cate the operation that would have occurred had there been a
voltage failure on the source (main breaker TRIP L.E.D.
flashlng to indicate a logic signal calling for a trip and tie
breaker CLOSE L.E.D. flashing to indicate a logic signal call-
ing for a close). When the pushbutton is released and the
on-delay timer has timed out~ the L.E.D. will revert back to
the actual status of the system.
It should be noted that during the entire sequence
-29-
''
~ ~ ~ 3~ 46,670 46,671 46,672
described above, all operations that the ATC per~orms to
lnitlate an automatic transfer are tested (~oltage sensing,
timing, interlocking~ etc.) except that in the li~e test
mode the inputs to the final output triacs (normally used
to generate 120V signals to the breakers) are shorted, thereby
preventing the breakers ~rom closing and tripping. Only the
tie breaker tripping output is not disabled during this opera-
tion. This is to maintain a positive interlock in the event
the mode selector switch 43 is left unattended ln the llve
test position and unauthorized personnel try to manually close
the tie breaker, causing two sources to be simultaneously
connected to the system. As a result of this interlock, the
; tie breaker TRIP L.E.D. will remain lighted durlng the test
operat ion .
3.1.5 Interlocking
The breakers are electronically interlocked to pre-
vent all three from being closed at the same time, thereby
paralleling the two sources. The interlock is operative
regardless of the position of the mode selector switch.
3.2 Sequence of Operation
Two-Breaker System
No modification of the ATC is required to change
from a three-breaker system to a two-breaker system. The
breaker status inputs are from N.C. breaker auxiliary con-
tact~ (contacts having a status opposite that of the mai.n
contacts). Thus, on a two-breaker system there will be no
input for a tie breaker and the A~C will interpret thi~ as a
tie breaker being closed. Therefore, only the two maln breakers
wlll react to the ATC's signals.
3.2.1 Automatic Mode
1) Assume source #1 and breaker 52-1 is the normal source and
-30-
.
~ f~ 6,670 46~671 46,672
source ~2 and breaker 52-2 is a generator source.
a. Upon voltage failure of source #l (but source #l
still has su~icient voltage to ho]d in control power, l.e.g
greater than 55%) a signal is sent to start source #2 generator
(signal is lnstantaneous or time delayed depending on selected
setting of programming swltch PS-6, Delay Generator Start).
A~ter the off-delay time has expired, breaker 52 1 will trip.
As soon as the generator is up to proper voltage and frequency
and the on-delay timer has expired, breaker 52-2 will close.
b. Should the same condition occur but source #l does
not have su~icient voltage to hold in control power~ the
generator will receive an instantaneous start signal. The
o~f-delay timer has enough capacitance to continue timing
; during the period of no control power (approximately 10 sec-
onds between loss of voltage and the time for the generator
to come up to 55% o~ rated voltage). After the o~f-delay
timer has expired and generator control power is available,
breaker 52-l wlll trip. After generator has reached proper
voltage and ~requency and the on-delay timer has explred,
breaker 52-2 will close.
2) For a return-to-normal a~ter a transrer operation re~er
to Section 2.20. After the normal breaker has reclosed, the
generator output will continue to call for the ~enerator to
run unloaded for a predetermined amount o~ tlme (as selected
on the unloaded runnlng timer, adJustable 15 seconds to 30
mlnutes).
3.'2.2. Manual Mode
l) Same as 3-breaker operation, see Section 3.1.
3.2 3 Interlockin~
Breakers are interlocked to prevent both from being
-31-
~ ~ ~,r~ 46,671 46,672
closed at the same time and paralleling the two sources.
The interlock ls operative re~ardless o~ the posltion o~ the
mode selector swltch 43.
3 2.4 Lockout
Same as three-breaker operation.
4. Circuit Descri~
Unless otherwise stated, the ATC device contains
two of each circuit, one ror each source, and the descrlption
- wlll refer to the source #1 clrcuit. Items ln parenthese~
refer to the corresponding ltem re~erence for source #2.
4.1_ Power Su~y
The Power Supply circuit, Flgure 4, contains iso-
lated bidirectional thyristor (triac) switches ~or control
power transfer and partially redundant low voltage DC sup-
plies. Figure 4 shows the entire power supply circuitry ~or
both sources. m e secondarie,s Or the two control power
trans~ormer~ are connected between terminal~ Dl and D2 and
between terminals D4 and D3. Terminal D5 carries the switched
control power o~ 120 volts AC, nominal3 with respect to
; 20 ground termlnals D2-D3. The power inputs are protected
against high voltage transients by metal oxide varistors
D47, D48. The Control Logic circuit (Fig. 11) determines
which transformer is to be the source of control power and
sinks current at elther terminal Co42 ~or source ttl or Co3
; for source t~2. Current into Co42 turns on optically coupled
thyristor isolator A4. The thyristor o~ ~4 short circu~ts
diode bridge DB4 to provide AC gate current for triac Q42
~rom its snubber network R41, C43 and C44. The snubber
limits the voltage across the thyrlstor of isolator A4 to
less than hal~ that across triac Q42 in addition to providing
~-32-
~ 3~ 6,671 46,672
dv/dt protection ~or both thyristors A4 and Q42.
Transformers T41 and T42 ~or low voltage DC supplie~
are also connected to the control power inputs. The center
tapped transformer TLIl and diode brldge CB4 provide po~itlve
and negative supplie~ smoothed by capacitors C47 and C49,
respectively. A redundant supply is associated with T42
consisting of bridge EB4 and capacitors C48 and C410. Both
unregulated negative supplies are connected at Ci8 and CilO
to Contro] Logic inputs in order to sense the presence of
control voltage ~rom the transformers T41 and T~2. Diodes
; D43 through D46 allow the greater magnitude DC voltages to
supply the positive and negative regulators. The posltive
regulator which only supplies low current to the two Voltage
~3 Sensor circuits is simply Zener ~i~e D41. The negatlve 1~
a series regulator using transistor Q41 and Zener dlode D42
as a reference. The negative supply powers all the ATC
logic circuitry with a Vss (logic 0) o~ -12.4 ~olts. For
each of the logic circuits a separate diode and capacitor
establishes Vdd (logic l), a diode drop below ground. High
current loads sink current directly ~rom ground to Vss so
that a logic supply Vdd to Vss is maintained during short
power outages.
4.2 Voltage Sensor
The Voltage Sensor circuits contain logic for
independently measuring each o~ the three phase voltages,
checking the phase sequence~ and monitorlng the phase-to-
phase voltage that powers the control power transformer.
Two identical voltage sensor circuits are provided, one ~or
each source. The voltage sensing circuitry is described
more completely in the a~orementioned ~en~l~g U.S. Patent
-33-
~3 ~ 3~ 6~671 ~6V672
~096J395~ en~itled "Au~omatic Transfer Control and
~oltage Sensor" issued June 20, 197~ to George F~ Bogel
and Rbbert M. Oatas4
The Voltage Sensors, one of T~hich is shown in
Figure 5, use ~12 volts ~or opera~ional ~mpli~iers, but
most clrcuitry uses -12 volts to ground~ The ~econdaries
o~ the input ~otent~al transfo~mers are referenced to
ground~ and voltage magnitude measurements are nega~ive
with respect to ground~ ~ig~ 5 shows the Voltage Sensor
circult con~igured for three~wire oper.ation and connected
to ~n open~delta potentl~l trans~ormer. ~on~ections to a
~our-wire Y-s~ondary potential transformer are sho~m in
dashed lines.
The reference voltage is selected by swi~ch PS-ll
(PS~12) $.1 ~olts or B.o volts ~or rated QC input~ o~ 69 or
120 volts, respecti~ely~ The DROP OUl' poten~iometer R577
determines the threshold voltage for the three inpu~ compar-
ators, correspo~din~ to 65~o- 90~ of ra~ed input ~oltage~ i~
the sen~o~ output indicate~ normal voltages on the bus~
~0 Transistor Q52 disables the PIC~ UP potenti~meter R57~ by
raising it to ground potential and re~erse biasing d~ode
: ~514~
I~ s~tch P~-9 (PS~10) is in the 4 WIRE position,
each o~ the phase~to-neutral vol*ages ~eed~ identical cir-
cuitsO Th~ phase A voltage of the potential ~rans~ormer
secondary connect,~d to terminal Va37 is divided b~ resistors
R570 and Rs56, wi~h diode D55 clamping ~uring the positive
hal~ cycle~ I~ the negati~e peak exceeds the ma~nitude of
the threshold voltage9 comparator output 5A2 goes hlgh to
trigger monostable multi~lbrator 5B. Output 5B~ goes high
blocking diode D5~ a~d outpu~ 5B7 goes lo~, turning on
~A NO~MAL
-3~o
.. ~
~ 6 3 671 46,672
light-emitting diode D519. The 44 millisecond pulse wldth
of the retrlggerable monostable multivibrator 5B requires
that two successive line cycles fall below the selected
threshold for a low voltage indication. If any of the phase
voltages (or the phase sequence) is abnormal, comparator
input 5E6 is pulled below its re~erence input 5E7 by diodes
D58, D59, D510 (or D517). The VOLTAGE NORMAL, Vl3 output at
terminal Vol4 goes low and its complement at terminal Yol2
goes high to signal abnormal bus voltage. Transistor Q51
turns on to disable the DROP OUT potentiometer R577. ~This
causes the comparator threshold voltage at 5A5, 5A9, and
5All to be raised (an increased negative magnitude) to that
determined by the PICK UP potentiometer R578, corresponding
to an input of 90~ to 98% rated voltage.
Phase A and C potential transformers are al~o con
nected to voltage dividers consisting of resistors R575 and
: R562 or R576 and ~560~ respectively. A signal proportional
to the phase-to-phase voltage Vca(t) is present at operB-
tional amplifier output 5C12. In a 3 WIRE system the two
open-delta potential transformers provide Vab(t) and Vcb(t)
to the phase A and C voltage sensors at VA37 and VA333
respectively. The operational amplifier-generated value
proportional to Vca(t) is provided to the third sensor at
5A8 via resistor R551 and switch PS-9A (PS-lOA).
The Vca(t) signal has three other uses. Switch
5S2B selects resistor R561 or R552 to connect Vca(t) to the
comparator input 5E8 in a circuit similar to the three
above. In this case monostable multivibrator output 5D6
drives terminal Vo20 high i~ phase-to-phase voltage Vca
powering the control power transformers is above 55% of
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~ ~rz 3~ 46,h71 46,672
rated (Pl - 1). The 55% threshold DC voltage ls derived
from resistors R563 and R567 in the reference circuit.
The Vca(t) signal is rectified and smoothed by
diode D518 and capacitor C510 to feed comparator input 5A6.
An identical circuit on the second Voltage Sensor clrcuit is
cross-coupled via external connectionl with comparator
negative input o~ Voltage Sensor Circult #l connected to
comparator positive input of Voltage Sensor circult #2 and
conversely. These comparators determine which of the two
1~ control power sources is greater in magnitude. Comparator
output 5Al of Voltage Sensor #1 drives terminal Vlo4 high if
Vca of #1 is greater (Pl~ P2 = 1). The double hysteresis
e~fect of the ~eedback resistors R536 in each comparator
ensures that a previously lower source must exceed the
; selected control power source by several volts be~ore causing
a control power transfer.
The phase sequence checking also uses the Vca(t)
signal with a 30 lag due to resistor R566 and capacitor
C53. In 4 WIRE systems of proper sequence switch PS-9C (PS-
lOC) connects a Vc(t) signal to operational amplifier input5C7 equal in magnitude and phase wlth the Vca(t-30) signal
at amp input 5C6. In 3 WIRE systems switch 5S2c connects
Vcb(t) via a 30 lead network (resistor R573, R574, R568 in
parallel with R569 and capacitor C51). With proper sequence
the Vcb(t~30) signal is equal ln rnagnitude and phase with
the Vca(t~30) signal.
Figure 6 s~lows a phasor diagram o~ the sequence
circuit operation. It can be seen that with norrnal sequence
on a 4-wire system the phase angle of phase-to-ground voltage
Vc (90) is equal to the phase angle of phase-to-phase vol-
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~ ~ 3~ 6,672
tage Vca (120~ shifted 30 ~n a lagging direction~ Siml-
larly, with normal ~equence on a 3-wire system the angle o~
Yoltage Vcb ~60) shi~ted 30 in a leading direction is
equal to the angle of voltage V~a (120~ shi~ted in a
lagging d~rection~ Resistors R57~ R573~ ~56~ and R566
are chosen to provide proper proporkionality cons~ant~ ~o
make ~he equa~ions of Fig~ 6 hold t~ue, Thus~ in either
3 or ~ wire positions~ the operat~o~al ampli.fier 5C10 out~
put vol~age is negli~ible and comparator po~iti~e input
5Ell is near ground potential due to resistor R52Bs cO~
para~or oukpu~ 5E13 is high9 block~n~ diode ~517 and ligh~ing
SEQUENCE CORRECT light-emit~ing diode D522 ria transistor
Q53~ ~or either 3 or 4 ~re) reYerse ~equence is equivalent
to 1~0 phase rever~al of ~ a phasor~ Thus, the large
~olta~e presen~ at ~he cperational a~plifier output due ~o
out-of-phase lnpu~s i~ rec~ified and smoothed by diode D~l~
and capacitor C59. Positive input 5E11 is dr~ren below the
-~ volt reference i~put a~d outpu~ 5E13 goes low~ Tra~-
~stor Q53 and L~E~D~ D522 are held o~. D~ode D517 pulls
comparator inpu~ 5E6 low to indicate a~ abnormal source ~t
the ~oltage sensor output ~ol40
The over/under frequency measuring circuit is
designed to digitally determine if an lnput voltage is
between present ~requency l~mlts. The fre~uency sen~or is
de~cribed more completely in the a~orementioned U"S. Patent
49090~090 entitled l'Automatic Trans~er Control Device ~th
Progra~mable ~requency Sensor" issued M~ 16, 197~ to
Paul M~, Johnston ~ The circuit, P~gure 7~ tests the in
coming signal during one
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`'~
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; cycle to see that it is ahove a lower frequency limit and
Oll the next cycle tests the input -to see that it is below
an upper limit. The process continues on alternate cycles
unless one of the limits has been exceeded.
If the lower frequency limit is passed, the circuit
is programmed to test the incoming signal and compare it to
a preset retllrn frequency higher than the trip point. In
other words, the input signal frequency is required to return
to a frequency that is higher, say 2 H~ typically, than the
dropout condition before the fault indication is cleared.
A similar procedure occurs when the upper frequency limit
is passed, except that the return point is set typically
2 H~ lower than the trip point. The four values, that is,
the overfrequency and underfrequency trip values along with
the two return values, are stored as eight bit binary num-
bers in a read-only memory, integrated circuit 7D.
The read-only memory (ROM) 7D requires a 5V DC
power supply at relatively high current. Thus, the fre-
quency sensor logic operates on a V~D to Vss supply of 5V
DC established by Zener diode D72. To conserve current the
ROM is turned on only briefly, ~ust before a half cycle
measurement period. The four comparators of 7A use the 12V
DC supply VGc to Vss at input and output.
Assume underfrequency testing is called for by a
logic 1 on pin l of flip-flop 7J. If no alarm condition had
been sensed before, the ROM is addressed with logic 0's on
pins 7D13 and 7D14. If the input voltage (69 or 120 volts
nominal) is in the negative half cycle, input sensing pins 8
and ll of the 7A comparator are more negative than the refe-
rence voltage established by resistors R77 and R79. Thusg
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~3~ 6,~72
the memory power supply switch Q71 is off as 7A13 is low,
and the clock oscil.lator 7C is held of~ via inverter output
7B6 and 7A14 is high. At the positive zero crossing of the
line, 7A13 goes high, turninQ; on Q71 to energize the memory
7D. Inverter Olltput 7~]5 resets counter 7~ and loads latches
7F and 7G wit~ t~le binary representation of the underfre-
quency trip level stored in the RQM. The input signal at
7A8 lags that at 7.~11 due to capacitor C72. This allows the
just-mentioned initializing by 7A13 be~ore 7A14 goes low
10 to start a measurement. :
: When 7A14 goes low at the delayed zero crossing,
7A13 is pulled low through diode D73 removing the reset on
counter 7H, latching 7F and 7G and turning off Q71. Capa-
citor C73 maintains power to memory 7D during the latching
of 7F and 7G. The cloc~ oscillator 7~ runs while 7All~ is
low. At the delayed negative zero crossing, 7A14 goes high
to shut off the clock and to toggle flip-flop 7J. The num-
ber of clock pulses counted by the 8-bit counter 7H repre-
sents the period of the input line voltage. This is compared
with the 8-bit binary representation of the underfrequency
trip level period from latches 7F and 7G. The underfrequenc~
output 7M12 of the 8-bit magnitude comparator consisting of
7E and 7M is high if the period counted is greater than the
trip level period stored :In the ROM (TinpUt > I~l~ trip implies
finput ~ fuf tri.p) ~he state of output 7M12 is latched by
flip~flop 7L at the end of the measurement half cycl.e when
flip-flop output 7J2 is toggled to a logic 1. The output
circuit translates the state of latch 7L to the 12 volt logic
level used by the other logic modules. If the frequency is
within normal limits, the output of the sensor is high and
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~ Ll 6,672
a light-emitting diode D71 is on.
T!le tog~ling of flip-flop 7J addresses the over-
frequency trip level in the memory 7D for the next positive
half cycle. When a limit is exceeded, the ROM addressing is
modified by feeding back the fault condition stored on latch
7L. The NAND gates 71~ selec-t the returrl condition during
its appropriate cycle whle the other normal limit is examined
during its alternate cycle.
4.4 ROM Programmin~ Procedure
Four locations out of the 32 locations available
in the P/ROM are utilized in this circuit. The information
stored and the particular addresses used are summarized in
~ the following table.
'~ Location Stored Data
7 Urlderfrequency Trip Point
Underfrequency Alarm Reset
, 23 Overfrequency Trip Point
; 31 Overfrequency Alarm Reset
For example, assume that the underfrequency trip
is desired to occur if the input frequency should go below
5~ Hz, and it should not rese-t the alarm until the input had
returned to a frequency of 60 Hz. Similarly, assume the
overfrequency trip to be se-t at 62 Hz with return at 60 ~z
also. Since the circuit is set up to divide a half cycle of
60 Hz inputs into 130 parts, this sets the binary number
required for locations 15 and 31 in the ROM at 1301o or
100000102. The under and overfrequency trip points are
calculated according to the following equation:
count = 2 x ~requencY x 64.1023~ sec 3 frequency
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~ 3~ 4~,672
where frequency is the upper or lower frequency limit in Hz~
In actual practice, the number arrived at for count will not
be an lnteger and should be rounded to the closest integer
number.
IJsing the above equation, the limits arrived at
~ for 58 Hz and 62 Hz are as follows:
; count [62] = 126 10 ~ 011111102
and
count [58~ = 134.48 = 1341o = 100001102
These numbers are then programmed into the ROM at locations
31 and 7, respectively.
4.5 Ma_n Breaker Lo~_c
Two identical Main Breaker Logic Circuitæ are
provided, one of which is shown in Figure 8. Each clrcult
contains bidirection thyristor (triac) switches for the
shunt tripping (Q8~) and closing (Q83) of the corresponding
main breaker and another ~or auxiliary generator engine
start~ng (Q85). These triacs remain gated on after breaker
operation for as long as the condition initiating turn on
remains.
There are four modes o~ shunt trlpping: manual~
interlock to prevent paralleling sources~ lockout from a
~aulted source, and automatic trans~er. The manual trip
input Mi41 directly causes a trip upon receipt of a logic 0
signal rrom its associated AC inter~ace circult. When the
interlock input Mil9 ~rom the Control Logic circuit goes
low, breaker closure is immedi.ately inhibited; and after an
approxlmately 20 msec delay from R814/C84, the trip output
is activated. The ground fault or overcurrent lockout lnput
Mi29 also inhibits closure when ].ow; and i~ the breaker 1
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open (such as by a ground fault or overcurrent trip), the
trip triac Q84 will be energized to override a mechanical
closure until the lockout latch ls reset. The automatic
transfer loglc has three trip request inputs and two in~
hibiting conditions. A logic 0 input from the off-delay
timer at Mi33, from the auxiliary transfer interface circuit
at Mi27, or from the retransfer to normal source logic at
Mi31 calls for an automatic trip (Mo7 goes high). Input
Mli31 is driven from the other Main Logic circuit's output
M2o6 which causes return to the designated normal source #2
of a two-breaker system (M2il7 = 1 via programming switch
PS-4) when its on-delay has timed out tM2ill = 1). The
automatic transfer by any of the three inputs is inhibited
if auto~atic enable is off (Mil5 = 0) or if the Keep Last
Source switch PS-5 is closed and the other main breaker
shows an automatic trip (Mi37 Mi39 - 1). Mi37 of one
circuit is cross-coupled to the other circuit's automatic
trip output Mo7. The aukomatic transfer output Mol3 goes to
the Tie Logic circuit requesting a tie breaker closure to
complete the three-breaker transfer.
There are two modes of closing a main breaker:
manual and automatic. Each has several inhibiting conditions.
For a manual CLOS~ attempt the output of the assoclated AC
inter~ace circuit drives Mi23 low. In the automatic mode
(Mil5 high) a closure is attempted i~ the normal voltage on
delay has timed out (Mill is high) and the ~requency sensor
indicates normal (Mi9 high). The closure is inhibited ir
there is a trlp output present, a source paralleling lnter-
lock (Mil9 low), an auxiliary lockout (M125 low) 3 or a
latched lockout from ground fault or overcurrent (Mi29
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?/3~Lf~ 116, 672
low). The automatlc transfer signal Mol3 provides a redundant
inhibit of closure at pin 11 of 8F during transfer conditions.
In the test mode (Mi21 - 0) the gates of the trip
and close triacs are short-circuited by saturated PNP tran-
sistors Q81 and Q82. Thus, the triacs are held off, and no
breaker transf'er operation occurs while testing the system.
The trip triac is al]owed to operate, however, for an inter-
lock or lockout trip. A logic O applied to pin 13 or pln
11~ respectively, of 8E turns of Q82 to allow the breaker to
trip. Also in the test mode the automatic enable Mil5 is
pulsed by the Con-trol Logic circuit to flash the trip or
close L.E.D. in the simulated automatic operation.
4.6 Delay Timer
The three independently ad~ustable timers: on-
delay, off-delay, and generator shutdown, utilize a common
14 stage digital counter. This is device 9H on Figure 9.
The oscillator associated with a particular timer is gated
on during its timing interval. If either input from the
Voltage Sensor Di5 or the ~requency Sensor Di9 shows an
abnormal condition (logic 0), the off-delay oscillator is
gated on at 9E12. The transition to off-delay timing causes
a counter reset pulse at EXCLUSIVE - OR output 9Fll via
R93/C91. The on-delay output latch NAND 9C is reset and
disabled which allows the timing status L.E.D. to go off and
removes the set signal at pin gA6 of the generator shutdown
latch. If programming switch PS-6, Delay Generator Start,
is open or lf the generator is already the source o~ control
power (Dil5 low), the latch is reset. Otherwise NAND output
9A10 must decode 211 off-delay oscillator periods before the
latch is reset which delays the generator by one-half of the
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off-delay t,i~e. ~fter 212 oscillator periods ~2 seconds to
10 minutes depending on the setting of potentiometer R914
pin All goes low to turn off the osclllator and drive the
off~delay output Do41 low. During timing the status L.E.D.
flashes at a rate of fO~ . 64 in response to counter stage
six, pin 9HLI. At of'f-dela~ time out 9HL~ stays low and the
L.E.D. is held off.
On-delay timing commences when both frequerlcy and
voltage inputs become norma]. The transition to normal
resets the counter via 9Fll. The off-delay and generator
start decoders are disa~led, the on-delay oscillator and
latch are enabled. During timing the L.E.D. ~lashes at
; fon T 64 similar to above. After 2l2 on-delay oscillator
periods (2 seconds to 10 minutes depending on R913) NAND
output 9C3 sets the on delay latch. Pin 9Cl0 goes low to
turn off the oscillator, drive the on-delay output Do26
high~ and hold the timing status L.E.D. on continuously.
When the on-delay latch is set at time out, a
logic 0 on 9Gl enables the generator shutdown decoder and
the logic 1 on pin 9B3 enables the generator oscillator.
The oscillator is held off until the position circuit Di31
senses that the normal source breaker has closed in res~onse
to the on-delay time out signal. At this time the counter
9H reads 2l2 or 010 ... 0. It requires 2l2 ~ 1213 periods
of the ~enerator oscillator (15 seconds to 30 mlnutes depend-
ing on R915) to reach the turnover to all zeroes at which
time 9G9 goes hlgh. Thls causes OlltpUt Do24 to slnk current
and turn on a trlac on the Main Logic circuit for generator
shutdown. Thus, a maximum generator unloaded cool-down time
three times longer than the maximum on/o~f delay time is
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~ ~ 3~ 46~672
possible using the same value capacitors and potentiometers
in the oscillators.
4.7 Tie Bre k~ ic
The Tle 10gic circuit, Figure lO, controls the
shunt tripping and closing of the tie breaker in three
breaker transfer schemes. It may be deleted in two breaker
schemes.
There are four modes of shunt tripping: manualg
interlock to prevent paralleling sources, lockout from a
~aulted bus, and automatic retransfer. The manual trip
input Ti2l directly causes a trip on a logic O signal from
its associated AC interface circuit. When the interlock
trip input Ti23 ~rom the Control Logic circuit goes low,
breaker closure is immediately inhibited; and after approxi-
mately 20 msec delay from RlOlO/Cl03, the TRIP output triac
Ql04 is activated. The ground fault or overcurrent lockout
input Ti33 also inhibits closure when low~ and if the breaker
is open (possibly a ground fault or overcurrent trip), the
TRIP triac QlO9 will be energized to override a mechanical
closure until the lockout latch is reset. The automatic
retransfer occurs if both on-delay timers indicate that the
sources are normal (Til5 and Til7 = l) and no automatic
transfer closures are requested (Ti9 and Till = l). The
retransfer is inhibited if the automatlc enable is off (Til9
= O) or if the "tie trip inhibit" programming swi.tch PS-2 is
closed (Ti29 = l).
In addltion to the tie breaker closure to complete
an automatic transfer (Ti9 or Till low), a manual CLOS~ via
an interface circuit is possible (Til3 low). Any closure is
inhibited if there is a trip output present, a source paral-
_L~5_
~ 46,672
,..~ ~
leling lnterlock (Ti23 low), an auxiliary loclcout (Ti31
low), or a latched lockout from ground fault or overcllrrent
(~i33 low).
In the test mode (T125 = 0) the gates of the TRIP
and CLOSE triacs Q10~ and Q103 are short-circuited by satu-
rated PNP transistors Q101 and Q102, respectively. No
breaker transfer operation occurs while testing the system.
The TRIP triac Q104 is allowed to operate, however, for an
interlock or lockout trip. A logic 0 applied to pin 2 or
10 pin 1, respectively~ of 10E turns of Q102 to allow the
breaker to trip. Also in the live test mode, the automatic
~- enable Til9 is pulsed by the Control Logic circuit to flash
the TRIP or CLOSE L.E.D.'s D102 or D103 in the simulated
automatic operation~
4.8 Control Logic
The Control Logic circuit, Flgure 11, contains
the control power transfer logic, the interlock circuits,
and the lockout latches. The control power transfer is
based on inputs from the Voltage Sensor circuits indicating
source voltage normal (Vl at Ci4, V2 at Cil7) or source
voltage above 55% ~Pl at Ci7, P2 at Cil3) and source ~1
greater than source #2 (Pl > P2 at Cill). Inputs from the
unregulated DC supplies (Sl at Ci8, S2 at Cil0) are propor-
tional to the control power transformer voltage and over-
ride the voltage sensor signals if no control power is pre-
sent because of a blown fuse or a faulty transformer. There
are three conditions for which control power transformer #l
is elected as source of control power:
1) Source #l and control power #l voltages are normal and
either programming switch PS-l is open designating #l as
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46,672
~ 3~
normal source or source #2 voltage is abnormal.
2) Source #2 voltage is abnormal, and source #1 voltage is
greater than 55%, and source #1 voltage is greater than
source #2~ and control power #1 voltage is adequate.
3) Control power #2 voltage is o~f tblown fuse, etc.) and
source #l voltage is greater than 55%.
Source #l i~
; [Vl Sl (PS1 + ~2)] ~ ~V2 Pl (Pl > P2) Sl]
[S2 Pl~ - CP1
When any o~ these conditions becomes true, capacitor Clll is
rapidly discharged by NAND llF3 through Dllll to turn off
trans~stor Q112 and the triac Q~3 (~ig. 4) ~or control power
source #2. Capacitor C112 is charged to a logic 1 by N~ND
llG3 through Rll9 in not less than one-half cycle of the
line to allow commutation of source #2 trlac Q43 before
transistor Qlll turns on to ~ire source #1 triac Q43
(Fig. 4). For condition 3 the unregulated DC supply con-
nected to Cil0 becomes less negative than Vss upon the
failure of its associated control power source. Transistor
Q114 turns on and overrides the source #2 normal signal.
For control power transfer purposes V2 = 0. Si~ilarly
NOR llC13, then inverter llA10, goes to logic 1 with resistor
R1120 providing positive feedback. This enables NAND llE10
to cause a turn-on o~ source #l triac if source #l voltage
is above 55%, Pl = 1.
The three conditions ~or which control power
trans~ormer ~2 is elected as source of control power are
similar to above.
1) Source #2 and control power #2 voltages are normal and
either programming switch PS-l is closed designating #2 as
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~ ,$ ~
normal source or source #1 voltage is ahnormal.
2) Source #1 voltage is abnormal and source #2 voltage is
~reater than 55~ and source ~2 voltage greater than ~ource
#1 and control power #2 is adequate.
3) Control power ~1 voltage is of`f, blown ~use, etc., and
source #2 voltage is greater than 55% and control power ~2
voltage is adequate.
Source #2 if
[V2 S2 (PS1 ~ Vl)] + [Vl P2 (Pl ~P2) S2] + S1
P2 S2~ = CP2
If the control power is on either CPl or CP2 is
low and NAND output llGll enables the interlock circuit NAND
llB. A low output to a Main or Tie Logic circuit causes an
interlock trip of the associated breaker if the other two
breakers are closed. The inputs Ci27, Ci25, and Ci23 of llB
are driven by AC inter~ace circuits using 120 volt control
power to sense the status of a normally closed auxiliary
contact of the tLe breaker, main breaker ~1, and main breaker
~2, respecti~ely. With the breaker main contacts open, the
AC interface is energized and a logic O is fed to the inputs
o~ the interlock NAND llB.
Ground fault Ci36 and overcurrent Ci38 lockout
inputs set the latches of llD on a logic O from inter~ace
circuits. The high output from a set latch drives Co40 low
via NOR llC10 and drives a buffer inverter to :Light the
ground fault or overcurrent L.E.D.'s D1113 or D1114. The
lockout reset AC input Ca35 is similar to the AC in-terface
circuit but has a longer time constant R116/C115 to insure a
reset condition on power-up.
~ The automatic enable output CO9 goes low to disable
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1l6~67~
2 ~Y` ~ ~
automatic operation on a low input from the interface clrcuit
connected to the MANUAL terminal of the mode selector switch
Ci31 or is pulsed low by the oscillator consisting of resistor
Rllll, capacitor C113, and a half of NOR llC. The oscillator
is gated on by a low input Ci41 from the live test mode
interface circuit. This pulsed enable signal causes the
TRIP and CLOSE L.E.D.'s of the Main and Tie circuits to
flash when the system is in the live test mode.
4.9 AC Interface Circuits
All connections to remote switches or breaker
auxillary contacts are made through interface circuits
operating on the 120V, AC control power. There are nine
~` circuits on each module, each using one-third of a hex
bu~fer. The description refers to the first circuit in
Figure 12. When AC input Ia5 is not energized, capacitor
; C121 is charged through resistor R129 to a logica1 1.
Hysteresis is provided by R121 and R1228. Output Io4 is
low, and Iol3 is high.
When 120V, AC control power is applied to Ia5 with
respect to ground, C1210 charges negatively through diode
D1210. Voltage divider R1237 and R129 pulls C121 down to
logic 0. Diode D121 clamps the signal at Vss. Output Io4
goes high, and output Iol3 goes low. Resistor R1210 provides
sufficient loading to prevent pilot contact leakage from
appearing as a closed contact. ~ delay in output switching
Or greater than 50 milliseconds is seen when the AC input is
; removed.
5. Mechanical
. . . _
As seen in Figure 13 the complete ~utomatic Transfer
30 Control 12 consists of a power supply circuit board 102, a
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~ 3~ ~ 46,672
rack 104 holding twelve plug-in printed circuit modules 106,
~our barrier terminal strips 108 (only two of which are
shown), a programming switch array (not shown), and the
interconnecting wiring. Two o~ the modules, the Tie Breaker
Logic and the Control Logic, are used singly. The Frequency
Sensor, Voltage Sensor, Main Brea~er Logic, Delay Timer, and
the AC Interface Circuit modules are used in pairs, one
associated with each of the main circuit brealcer. Figure 13
~-~ shows khe ATC with the full complement of rnodules. The
faceplate lenses with descriptive text are back-lighted by
previously described light-emitting diodes to indicate the
operating state of the ATC. For two-breaker transfer schemes~
the Tie Breaker Logic module is simply omitted or replaced
by a dummy module for front panel appearance. One or both
Frequency Sensor modules may be similarly omitted. The less
likely omission of other modules requires that the logic
outputs of the omitted module be replaced by ~umpers on the
backplane wiring or on a dummy module.
6. Summary
~ith the versatility offered by programming switches,
auxiliary inputs, and a wide range of frequency, voltage,
and time delay settings, the Automatic Transfer Control is
useful in a wide variety of transfer schemes. Sales personnel
can lead customers and their consulting engineers through
the "design" o~ transfer schemes by selection of the various
options available. More accurate estimates of the cost of
transfer schemes are possible, especially in the complex
transfer schemes, and considerable savings in engineering,
drafting, and wiring costs are obtained.
Specifically, by providing programmable electronic
~50-
3 l~6,672
digital logi.c means the invention provides a single device
applicable to a wide variety of transfer strategies while using
a minimum of power. Two- and three-breaker schemes are easily
implemented since breaker status information is sensed from
auxiliary contacts having a status opposite that of the main
contacts. A plurali-ty of` timing functions are economically
provided through the use of a plurality of oscillators coopera-
ting with a single di.gital counter. The use of 120V AC interface
circuitry provides high noise immunity while simplifying instal- -
lation. Additional flexibility is provided through the use of
-~ separate voltage sensors to determine which source to draw upon
for control power and by employin~ a control power criterion of
55% of rated normal voltage. The provision for auxiliary trans-
fer lockout, overcurrent lockout~ ground fault lockout, automatic
or manual return to either source~ a "Keep Last Source" mode,
and a live test mode in the present invention combine to provide
a significant increase in performance and versatility over prior
art automatic transfer control devices in an ef~icient and econo
mic manner.
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