Note: Descriptions are shown in the official language in which they were submitted.
112~;937
This invention relatës to an improved toll restrictor.
More particularly, it relates to a toll restrictor having infinite
input impedance during on-hook conditions and utilizes circuitry
features which prevent the making of long distance calls normally
allowed because of central office timeout and further prevent
improper restricting as well as providing standard toll restrict-
ing functions.
Toll restrictors and call divertors are provided to
overcome the problem of the use of telephones for unauthorized
long distance calls. These long distance calls, of course, re-
sult in tolls charged to that telephone number.
Some of the first toll restrictors merely utilized a
switch in series with either the tip or ring conductor of a tele-
phone. The switch could be placed in a lockbox with only author-
~ ized personnel having the key to the box. Of course, this would
;~ not permit even local calls when the switch was open. More
sophisticated electronic toll restrictors have also been provided.
One example of such a restrictor is shown in U.S. Patent 3,757,055.
This patent shows a means of restricting an outgoing call if the
digit zero is dialed on any of the first three dial pulls, aswell as a means for restricting the call if more than eight digits
are dialed. However, various techniques have been devised to de-
feat this type as well as other prior art electronic toll restric-
tors. For example, the subscriber may dial a digit and wait unt l
the central office times out the call which, in effect, restores
the dial tone. The prior art toll restrictor would have sensed
this digit and treated it as the digit of the first pull. By
using this slow dialing technique, a zero may be dialed, say on
the fourth pull, which is normally not restricted. The toll res-
trictor would see it as the fourth pull, however, the centraloffice would see it as a first dial pull and give access to the
operator, thus defeating the toll restrictor.
- 1 -
3 7
Also, there have been problems in digit counters giving
false indications of a digit to be restricted. For example, if
the digit three is to be restricted and the number four is
dialed, some counters will provide an output pulse as the counter
passes the three count en route to four, thus causing a false
indication of restriction.
Prior art toll restrictors and other devices which
sense telephone signals are normally attached ln parallel to the
telephone line, i.e., across the tip and ring co~ductors. These
devices have a finite input impedance. It has been alleged that
these can cause problems in the transmission characteristic in
the communication lines, such as wave reflections and other dis-
tortions.
It is, therefore, desirable to provide a toll restrictor
which overcomes these and other problems of prior art.
In the use of the term "restrictor", normally one thinks
of disconnecting the telephone handset from the central office
by a switch when a call is to be restricted. However, the device
set forth herein may also be used to divert outgoing calls from the
handset to some prerecorded message, so as to indicate to the
caller that he is trying to make a restricted call, or to some
other diversion. Furthermore, the restrictor may shunt or open
the line or provide other mechanisms for prohibiting the trans-
mission of an unauthorized long distance call. Therefore, the
term restrictor should be interpreted :Ln its broadest sense, which
would at least include all of the above.
It is one object of this invention to provide an im-
proved toll restrictor circuit.
It is another object of this invention to provide an
electrical circuit adapted to be connected in parallel with the
telephone line having substantially infinite input impedance
during the on-hook condition.
-- 2 --
l~Z~937
It is another object of this invention to provide an
improved toll restrictor having a circuit means to prevent un-
authorized calls by automatically restricting calls a predeter-
mined time after dial pull, but before the central office timeout.
It is another object of this invention to provide an
improved toll restrictor having circuit means to prevent the
restriction of an allowable digit.
In accordance with one form o~ this invention, there is
provided a circuit adapted to be connected to the conductors of a
telephone line. A current sensing means connected in a series of
one of the conductors. Voltage sensing means is adapted to be
connected across the conductor. Switch means is connected be-
tween said voltage sensing means and one of the conductors. The
circuit means responsive to said connect sensing means for open-
ing the switch during a first condition and closing the switch
during a second condition for providing substantially infinite ~
input impedance to the circuit during the first condition. ~;
According to another form of this invention, there is
provided a telephone toll restrictor circuit including means for
sensing dial pulses connected to a telephone line. A dial pull ~-
counter is responsive to the sensing means. Timing means are
further responsive to said sensing means. The circuit further
provides means to restrict outgoing telephone calls. A restric-
tion occurs after a predetermined time from the initiation of
said timing means which is less than the timeout cycle of the
particular telephone central office.
In accordance with another form of this invention, there
is provided a telephone toll restrictor circuit including tele-
phone digit pulse sensing means adapted to be connected to the
telephone line. A digit pulse counter is connected to said pulse
sensing means. Pulse generating means is connected to the sens-
ing means for generating a pulse after the telephone digit has
- 3 -
~ . , : , .. , . : ,,
~12S~37
been dialed. A coincidence gate is connected to the
pulse generating means and to the output of the pulse
counter for applying a signal to a telephone restrictor
upon simultaneous reception of signals from the pulse
generating means and the counter to prevent incorrect
restriction.
In accordance with the above-mentioned objects,
from a broad aspect, the present invention provides a
telephone toll restrictor circuit comprising ~irst and
second input terminals adapted to be connected to first
and second telephone leads. Means is provided for sens-
ing dial pulses connected to at least one of the input
terminals. A dial pulse counter is responsive to~the
sensing means. Means is provided to restrict an outgoing
- telephone call connected to one of the leads. Timing
means is responsive to the sensing means. The said
means to restrict an outgoing telephone call is respon-
sive to the timing means a~ter a predetermined time. The
predetermined time is less than the time out cycle of a
predetermined telephone central office, whereby the said
means to restrict an outgoing telephone call switches to
the restrict mode after t'ne occurrence of the said pre-
determined time so that a restrictable call is not
allowed to be made because of central office time out.
Means is also provided for resetting the timing cycle
of the timing means after each dial pulse. The means
for resetting includes a pulse generating means connected
to the means for sensing dial pulses and further connected
to the timing means. The pulse generating means generates
a reset pulse for each dial pulse.
Subject matter which is regarded as the
invention is set forth in the appended claim. The
invention itself, however, toyether with further objects
and advantages will be better understood by reference to
the following drawing.
; The Figure is a schematic circuit diagram of
one embodiment of the subject 1nvention.
Referring now to the Figure, current sensing
relay coil K2 is connected in series with a telephone
instrument tip terminal 1, and central office tip termi-
nal 2. Relay contacts 3 are further in series with the
telephone instrument tip terminal and relay coil K2 for
opening the tip line during the restriction of an
unauthorized telephone call. Operation of this set of
relay contacts will be explained later. Relay coil K2
is magnetically coupled to its relay contacts 4. Relay ~;~
contacts 4 are connected in series between resistor R16,
which is grounded, and node 5, which is connected to the
B~ power supply. Power is supplied for the toll restric-
tor at AC power input terminals 6 and 7, which may be
standard 60 cycle 24 volt power. Full wave rectifier
CRl is connected across terminals 6 and 7 for rectifying
an AC power. Capacitor Cl is connected to one side of
full wave rectifier CRl, to filter the rectified power
from the bridge and provide a smooth filtered DC supply.
The collector and emitter of transistor Ql is connected
in series with resistor Rl and this series circuit i5
connected across capacitor Cl. The base of transistor
Q1 is connected to its collector, thus, Ql acts as
a zener diode for providing a constant voltage drop
of 8 volts across Ql. Capacitor C2 is connected
across the emitter-base junction of transistor Ql for
- 4a -
;~
3~
further filtering the voltage. B+ voltage is thus established
at node 5. Resistors R2, R3, and R4 act as voltage dividers and
are connected in series and across the emitter-base junction of
transistor Ql for providing reference voltages for some of the
other circuit components.
Varistor V2 is connected across relay coil K2 for
maintaining longitudinal balance to reduce noise.
The junction between relay contacts 4 and resistor R16
is connected to one side of resistors R13, R14, R15, and R17, as
well as to the anode of diode CR15. Capacitor C4 is connected to
the cathode of diode CR14, and acts as a part of a timing circuit.
Capacitor C4 is further connected to the emitter of transistor
Q3. Transistor Q3 acts as a discharge path for timing capacitor
C4 and is turned on normally by ringing signals through resistor
R17 which is connected to its base. Comparator 8 has one input
terminal 9 connected to capacitor C4. The reference input
terminal 10 is connected to resistor Rl, which is in the power
supply section. Comparator 8 acts as a threshold detector for
capacitor C4. The output terminal 11 of comparator 8 is connec-
ted to resistor R10. Resistor R10 is further connected to thebase of transistor Q2.
Transistor Q2 acts as a switch to turn on the voltage
detecting circuitry. The collector of transistor Q2 is connected
to the parallel network including resistor R5, a serles combina-
tion of resistor R6 and LED12, and resistor R7. The other side
of this parallel resistive network ls connected to relay coil
K3. Relay coil K3 is also connected to resistor R43 in the power
supply section. Diode CR17 is connected across relay coil K3.
Relay coil K3 is rnagnetically coupled to relay contacts 13. Re-
lay contacts 13 are connected to resistor R8, which is furtherconnected, in this embodiment, to the telephone ring conductor.
The other side of relay contacts 13 is connected to full-wave
3~7
rectifier bridge CR2, which is further connected to the central
office tip terminal 2. Light-emitting diode 14 is connected
across bridge CR2 for sensing voltage across the tip and ring
conductors when relay contacts 13 are closed. The light-emitting
diode 14 is optically coupled to light-responsive transistor 15.
The combination of the light-emitting diode and light-responsive
transistor is called an optical coupler and is used here for
electrical isolation. The collector of light-response transistor
15 is connected to resistor R9, which is further connected to B+
power supply at node 5. The collector of light-emitting diode
15 is also conneeted to input terminal 16 of NOR gate 17~ The
other input terminal 18 of NOR 17 is connected to the cathode of -
diode CR15 and to resistor R12 which is further connected to
ground.
Referring again to the current-sensing portion of the
circuit, output 11 of comparator 8 is connected to the input of
inverter l9a The output 20 of inverter 19 is connected to diode
CR16, which is further connected to the input 18 of NOR gate 17.
Output 20 of inverter 19 also conneeted to the reset input 21 of
dial pull counter 22 and also to the reset input 23 of latch 24.
The output terminal 11 of comparator 8 is also connected to one
side of resistors R38, R39, R~0. Resistor R38 is connected to
the cathode of diode CR12. The anode of diode CR12 is connected
to the input terminal 25 of eomparator 26, as well as the output
terminal 27 of comparator 28. Input terminals 29 and 30 of com-
parators 26 and 28, respectively, act as reference inputs and
are connected to resistor R2 for their reference voltage. The
output 29 of comparator 26 is connected to resistor R35, which is
further connected to input 31 of NOR gate 32. Differential capa-
citor C6 is connected to the input terminal 33 of comparator 28
and also is connected to the parallel circuit including resistor
R36 and diode CR10. Input 31 of NOR gate 32 is also connected to
-- 6 --
'7
the output 34 of comparator 35. Input 36 of comparator 35 is
connected to a reference voltage at resistor R2. Input 37 is
connected to capacitor C12, which is further connected to ground.
Referring now again to the voltage detector portion
of the circuit, output terminal 38 of NOR gate 17 is connected
to capacitor C3, diode CR3, and resistor R18. Resistor R18 is
connected to input terminal 39 of comparator 40. Input terminal
41 of comparator 40 is connected to reference voltage resistor
R2. Resistor R18 is also connected to resistor Rl9, which is
further connected between the input terminal 39 and output ter-
minal 42 of comparator 40.
Output 42 is connected to the input terminal 43 of dial
pulse counter 44. Pulse counter 44 has ten output terminals which
correspond to a digit which may be programmed to be restricted.
The programming means includes dip switch 56 which are connected
to output of the pulse counter through a plurality of diodes and
a dip switch. The digit to be restricted corresponds to a closed
dip switch.
Output 42 of comparator 40 is also connected to resis-
tors R20 and R21. Resistor R21 is connected to diode CR4, ~hich
is further connected to capacitor C13. Capacitor C13 is con-
nected to input terminal 45 of comparator 46. The output of com-
parator 46 is connected to reset input 47 of pulse counter 44.
Capacitor C13 and resistor R20 are a:Lso connected to resistor R42,
which is further connected to input terminal 48 of comparator 49.
The output 50 of comparator 49 is connected to differential capa-
citor Cll~ Differential capacitor Cll is further connected to
input terminal 51 of comparator 52. Comparator 52 acts as pulse
generator for providing a negative strobe pulse at output 53 so
that there will not be restriction of a digit which should not
be restricted. This feature will be explained in more detail in
-- 7 --
1~L2~
the discussion of circuit operation.
Furthermore, this strobe pulse acts to reset an inter-
digital -timer by its connection to resistor R26, back to differ-
ential capacitor C6. Again, this feature will be explained in
the discussion of circuit operation.
Output 53 of comparator 52 is also connected to input
54 of NOR gate 55. The output terminals from the dip switches
56 which are closed are connected to resistor R27, which is fur-
ther connected to gate input 57 of nand gate 58. ~he output 59
of nand gate 58 is also connected to the input of logic gate 55.
Logic gate 55 acts as a coincidence gate such that there must
be a simultaneous occurrence of pulses on each input 5~ and 59
in order to provide an output pulse at 60. Gate 55 may be a
nand gate.
Output 60 of nand gate 55 is connected to diode CR8
which in turn is connected to the input terminal 61 of nor gate
62. The other input terminal 63 is connected to resistor R33.
Input terminal 61 is also connected to resistor 34, which is
further connected to the output terminal 64 of nor gate 32. In-
put terminal 61 of nor yate 62 is also connected to diode CR9.
Diode CR9 is further connected to the outputs of dial pull coun-
ter 22, which provides pulses upon dialing a predetermined num-
ber of pulls on the telephone which are to be restricted. In
this etnbodiment, the eighth pull is to be restricted. Therefore,
NOR gate 62 acts to gate through all restrict signals, includ-
ing the output signal of the digit rank or pulse counter 44,
the output of the dial pull counter 22, and the offhook inter-
digital timer which will be e~plained later.
Nor gate 62 is connected to the input terminal 65 of
flip-flop 66. Flip-flop 66 includes cross-coupled NOR gates 67
and 68, which operates as a latch. Another input terminal 69
is connected back to the output of comparator ~ which acts as a
reset for the flip-flop~ Output terminal 70 of flip-flop 66 is
connected through resistor R32 to transistor Q4. Capacitor C9
is connected across the base emitter junction of transistor Q4
to prevent false triggering and diode CR7 is connected between
the emitter of transistor Q4 and ground. The collector of trans- -
istor Q4 is connected to relay coil Kl. Relay coil Kl is magne-
tically coupled to relay contacts 3, which is connected in a ser-
ies with the telephone tip conductor, and acts to open circuit
or restrict telephone calls which are programmed to be restricted.
Diode CR6 is connected across coil Kl to provide transient pro-
tection.
The circuit operates in the following manner:
P~ONE ON HOOK
In the idle condition, when the phone is onhook, relay
coils Kl, K2, and K3 are deenergized and transistors Q2, Q3, and
Q4 are non-conducting. Since in the onhook condition, zero DC
current is flowing through coil K2, relay contacts 4 are open,
thus, there is no B+ supplied to the input terminal 9 of compara-
tor ~. Therefore, terminal 9 of comparator 8, is at ground.
Since terminal 9 is at ground, output terminal 11 of comparator
; 8 is also at ground, as well as input terminal of inverter 19.
The output terminal 20 of gate 19 is at a logic level 1. Also,
logic level 1 at reset terminal 21 of pull counter 22 as well as
the reset input terminal 23 of flip-flop 24. The pull counter
22 is a Johnson Decade counter. Output terminal 71 of flip-flop
24 is, therefore, logic level 1. So long as the output terminal
11 of cornparator 8 is at logic level æero, the transistor Q2 is
turned off, therefore, current does not flow through relay coil
K3, thus, relay contacts 13 remain open. Since relay contacts
13 are across the tip and ring conductors, the tip and ring con-
ductors and thus the central office would "see" infinite input
impedance to a sensing portion of the circuitry as well as the
remainder of the toll restrictor while the contacts 13 are open.
37
In this way, there is no possibility that telephone central office
equipment may be damaged nor can the transmission of telephone
conversations and signals be affected due to the fact that this
device is across the telephone lines. In fact, the only time
that the toll restrictor exhibits input impedance i9 during the
phone offhook condition.
P~ONE OFF~OOK
When telephone instrument comes offhook, D.C, current
flows through relay coil K2, which is also in series with the
~10 phone instrument. Contacts 4 are closed, thus allowing capacitor
C4 to begin charging from the power supply at node 5 through re- ;
sistor R13 and diode CR14. When the charge on capacitor C4 reaches ~;
the reference voltage on input terminal 10 of comparator 8, the
output terminal 11 changes to a logic level 1. Logic level 1 for-
ward biases the emitter base junction of transistor Q2 causing
collector current to flow through LED12 and resistors R5, R6 and
R7, as well as through relay coil K3. Relay coil K3 thus energi2es
and closes contacts 13, causing the voltage sensor or the optical
coupler including optical diode 14 and optical transistor 15 to be
placed across the telaphone line. The input impedance of the toll
restrictor is no longer infinite. As the LED comes on, transistor
15, which had previously been conducting, goes to its nonconduct-
ing state, there~ore, input terminal 16 of logic gate 17 becomes
positive, The logic level on output terminal 20 o~ inverter 19
becomes negative when the output on comparator 11 becomes positive,
thus removiny the reset from terminals 21 of pull counter 22 and
terminal 23 of flip-flop 24. The toll restrictor is thus powered
up and ready to begin counting digit pulses and dial pulls~
DIAL PULL COUNTING AND IDENTIFICATION
While the circuit described is particularly adapted
for use with a rotary-type telephone instrument, it may also be
used as a Touch-Tone type instrument by providing a Touch-Tone to
-- 10 -- ,
. . . .. .
~ ~.lZ~37
digital converter (not shown) across the optical coupler. The
circuit, however, will be described for use with a rotary-type
telephone instrument, but as such, is not limited to rotary.
When a digit is dialed on a rotary-type telephone
instrument, a number of breaks occur in the D.C.-output current
corresponding to a value of the digit dialed. A dial break re-
sults in the loss of loop current in the presence of full central
office battery voltage appears across the line. Consequently,
for each line break, relay coil K2 deenergizes, thus opening
relay contacts 4. Break time on the dial pulse is normally about
60 milliseconds. During each dial break, capacitor C4 begins
to discharge through resistors R14 and lS and through R16 to
ground~ As capacitor C4 discharges, input terminal 9 of compara-
tor 8 approaches the reference voltage of terminal 10. However,
capacitor C4 requires 300 milliseconds to obtain such reference
voltage when jumper HL is switched on. Since this time is great- -
er than the 60 millisecond dial pulse time, output terminal 11
remains at logic level 1 allowing current to continue to flow
through relay coil K3, thus keeping the relay contacts 13 closed
and the voltage sensor connected across the line. The junction
between CR15 and R16, however, will become logic level zero since
B+ is no longer available at that point. Diode CR15 will no
longer be forward biased. Input terminal 18 of nor gate 17 be-
comes logic zero. Since transistor 15 is on, input terminal 16
is logic level zero and the output 38 of gate 17 becomes logic
level 1, charging capacitor C3. When the voltage at the input
terminal 39 of comparator 40 exceeds its reference level on 41,
output terminal 42 becomes logic level 1. Logic level 1 is fed
back to input terminal 39 to obtain a fast switching transition.
A logic level 1 is applied at input terminal 45 of comparator 46.
Output terminal 72 becomes negative with the application of logic
level one at the input terminal 45, which causes a negative at
the reset input terminal 47 of digit pulse counter 44, as well
.
as the terminal 73 of dial pull counter 22. Resistors R23 and R22
provide a fast rise and fall edges during the transition time of
output terminal 72. The zero state at pulse counter reset 47
enables the digit pulse counter to commence counting on the
trailing edge of the dial pulse. As a result of the negative
transition on input terminal 73, due to the logic zero transition
of output 72, of pull counter 22 advances by one court, and
capacitor Cll discharges through diode CR5 to the logic l state.
The input terminal 48 of comparator 49 becomes logic l, resulting
in a logic l at output terminal 50. This logic 1 discharges
capacitor Cll through diode CR5. Upon the compIetion of dial
break, current again energizes relay coil K2, and thus closes
the contacts 4. The absence of voltage across the phone line
causes transistor 15 to stop conducting, placing logic level l
at input terminal 16 of nor gate 17. Output terminal 38 returns
to logic zero, discharging capacitor C3 and allowing output ter-
minal 39 of comparator 40 to become logic zero. Output terminal
42 also becomes logic zero. The transition to logic zero through
output ~2 of comparator 40 causes counter 44 to advance one
count.
Logic level zero at output terminal 42 resulting from
the dial switch closure starts capacitor Cl3 to discharge through
resistor R20. It requires Cll 150 milliseconds to discharge to
the voltage level where terminal 48 of comparator 49 becomes less
than the reference supply. If a digit being dialed is still
pulsing, the next dial break will occur before capacitor Cll has
an oportunity to discharge to this reference level. Consequently,
Cll will never discharge until the completion of the next dial
pull. However, after the last pulse, terminal 48 drops below
the reference level, resulting in output terminal 50 becoming
logic level zero. The negative transition of the output is
differentiated by capacitor ll causing logic level zero state at
- 12 -
the input terminal 51 of comparator 52. Logic level zero input
terminal 51 will persist until resistor R25 charges capacitor
Cll past the reference voltage applied at the reference ter~inal
of comparator 52, which is 10 milliseconds, in this embodiment.
Therefore, the comparator 52 will pulse logic zero, output
terminal 53 for 10 milliseconds. m e so-called strobe occurs
before reset has occurred on terminal 47 of counter 44.
RESTRICT CYCLE
Any call which is a candidate for restriction is indi-
cated by momentary logic level 1 at the input terminal 61 of norgate 62. A logic 0 is provided at output terminal 75, input
terminals 76 of inverter 77, and input terminal 65 of R-S latch
66. Output terminal 70 R-S latch 66 then goes to a logic level 1
state and emitter-base current f~ows in transistor Q4 through
resistor 32. Transistor Q4 saturates energizing relay coil Kl
which opens contacts 3 which is in series with the tip line. The
telephone instrument is disconnected from the central office so
long as coil Kl remains energized. In this embodiment, coil Kl
remains energized for 1.6 seconds which is sufficient time to
drop and reset all switching e~uipment in most centxal offices
so that when reconnection is established at the end of 1.6 seconds,
a new re~uest for service is detected by the central office and
a dial tone is re-established. The 1.6 seconds time constant is
established by capacitor C8 and resistor R33.
Logic, level æero at input terminal 76 of inverter 77
causes logic level 1 at the output terminal 78. This logic level
1 transition is differentiated by capacitor C8, which causes logic
level 1 at input terminal 63 of nor gate 62. For output terminal
of nor gate 62 and input terminal 65 of latch 66 to maintain the
logic zero state, it is necessary to maintain relay coil ener-
gized regardless of the condition of the terminal 61 of nor gate
62. Resistor 33 begins to charge capacitor C8, causing terminal
63 of nor gate 62 to return to the logic 0 state in 1.6 seconds.
- 13 -
1~2~ 37
When input terminal 63 becomes logic zero, output terminal 75 and
input terminal 65 of flip-flop 66 arelogic level 1, which causes
the latch to change state, providing that input terminal 69 Of latch
66 has returned to the logic 1 state, thus turning off the trans-
istor Q4 and deenergizing relay Kl, thereby closing contacts 3.
R~NK RESTRICTION
As explained previously, counter 44 identifies the
value of the digits dialed and maintains the information for
250 milliseconds after completing the dial pull. The digit is
10- identified by logic level 1 state at one of the ten outputs of
the counter. For example, if the digit 4 had been dialed in the
first dial pull, output terminal 4 will become a lo~ic level 1
and remain in this state for 250 milliseconds after completing
the dial pull. It is assumed that digit 4 is to be restricted
if dialed on the first pull. Output terminal 4 becomes logic 1
and, therefore, the associated output diode becomes forward
; biased. Current travels through jumper bridge Jl and through
resistor R28. The junction of resistor R28 and resistor R27
becomes logic level 1 allowing input terminal 57 of nand gate
58 to become logic level 1 causing æero logic level at output
terminal 59. This zero level is applied to input terminal 80
of nor gate 5S. As stated previously, a 10 millisecond nega-
tive strobe output from comparator 52 on output 53 is at logic
level zero 50 milliseconds after completing the dial pull. This
; 10 millisecond strobe pulse is applied to input terminal 54 of
nor gate 55. Output terminal 60 of nand gate 55 will become a
logic level 1 upon the coincidence of these two negative input
pulses. As a result CR8 is forward biased and applies a positive
pulse gate 62 at input terminal 61 of nor gate 62, causing a
restrict cycle as previously explained. Thus, by use of coinci-
dence gate 55 and the strobe pulse from output terminal 53, there
is provided assurance that only digits from counter 44 which are
programmed to be restricted will be restricted. For example, if
- 14 -
~5~
the digit 4 is to be restricted and digit 5 is dialed, an outputpulse will appear on the first five output terminals as the pulses
are counted in the pulse counter 44. Thus, even though the digit
five is pulled, a pulse will appear at the output of terminal 4
of the counter. ~owever, since the strobe does not occur until
the end of the dial train, there will be no coincidence of the
pulse on the output terminal 4 of counter 44 and the strobe out-
put of pulse generator 52 so that restrict cycle will not occur.
This negative strobe on output terminal 53 is also con-
nected to input terminal 79 of nor gate 80. Input terminal 81 of
nor gate 80' is groun~ed at level zeror Output terminal 82 of
nor gate 80'is, therefore, logic 1. Input terminal 83 of latch 24
is, therefore, level 1, Therefore, output terminal 71 becomes
logic zero for the duration of the offhook condition. Logic zero
on output terminal 71 is coupled to input terminal 84 of nand 5
Therefore, a signal will not pass to the output of nand gate 58
from pulse counter 44 because of the zero on input terminal 84
effectively disabling the pulse counter 44.
DIAL PULL COUNTER AND RESTRICTION
,, _
As explained earlier, the dial pull counter is counter 22,
In order to limit the number of dial pulls, the connector J2 must
be programmed appropriately. If it is desirable to restrict on
eight dial pulls, connector J2 must be connected to output P8.
The counter 22 advances on the leading edge of every dial pull.
At the beginning of the eight dial pull, the output terminal 9 of
counter 22 will obtain logic 1, therefore, diode CR9 will become
forward biased causlng output terminal 61 of nor gate 62 to become
the logic 1 state. The restrict cycle will occur as previously
described when the input of this nand gate 62 becomes positive.
DIALING TO0 SOON AFTER ONHOOK
When a telephone instrument is onhook, the output of
comparator 8 is at logic zero maintaining capacitor C12 in dis-
charged state, Input 37 of comparator 35 is also zero. Input
-- 15 --
`` 1~25~7
31 of nor gate 32 will also remain zero until C12 charges. Remov-
ing the phone instrument from onhook starts the charging of capa-
citor C12 through resistor R40. The time required for C12 to
charge above the reference level of 36 is one second. Should
dialing occur before C12 charges to logic one, a logic zero will
exist at input terminal 83 of nor gate 32 generated output 72
of comparator 46 going from one to logic zero from the leading
edge of the first dial break. Consequently, the output of nor
gate 32 will be logic one. This places a logic level one at the
input 61 of nor gate 62 eausing restriction whieh prevents fast
dialing immediately after the pick-up which has defeated some
toll restrictors in the past. ;
INTER-DIGITAL TIMING
As previously discussed, the output level of comparator
8 is logic state zero when phone is onhook. Removing the phone
from onhook causes the output 11 of comparator 8 to beeome a one,
therefore, capaeitor C5 starts charging to a logic 1 through
resistor R39. When capaeitor C5 has the opportunity to charge to
the voltage level equal to the reference voltage level applied to `
input terminal 29 of eomparator 26, output 29'beeomes logic zero.
Therefore, input terminal 31 of nor gate 32 is also zero. As
previously described on the leading edge of the dial pull, ter-
minal 83 of nor gate 32 becomes logic zero. Therefore, output
terminal 64 will become logic one along with input terminal 61 of
nor gate 62. Therefore, a restrict cycle will occur. The time
required for capacitor CS to charge is approximately 13 second~.
Therefore, dialing must occur before the 13 seconds time out
cycle of capacitor C5 or a restrict cyc]e shall follow. For
purpose of illustration, assume that capacitor C5 has started its
charging cycle but has not yet charged to the reference level of
comparator 26. Also, assume that dial break occurs in this time
period. The leading edge of the dial pull will cause the ter-
minal 53 from strobe output or pulse generator 52 to become logic
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:. ~ : . ,
. ~ .
zero, however, since capacitor ~S has not had the opportunity to
fully charge, the terminal 31 is at logic 1, the output 64 will
remain at zero, and the pull will not be restricted. Also, 150
milliseconds after the dial pull comparator 52 generates a negative
strobe on its output 53 for a period of 10 milliseconds.
The trailing edge of the negative strobe is differenti-
ated by capacitor C6 causing the terminal 33 of comparator 28 to
be logic zero and its output 27 to be logic zero. Therefore,
capacitor C5 is discharged to logic zero by way of output terminal
27 of comparator 28, As a result, capacitor C5 starts its time
out period over again following every dial pull.
Since the time out cycle of the central office is nor-
mally greater than 13 seconds, the toll restrictor cannot be fooled
by merely lifting the phone offhook and dialing a n~nber and leav-
ing the phone offhook for over 13 seconds before dialing a second
dial pull. The central office would have normally seena zero on
the first dial pull, thus giving operator access while the toll
restrictor would have seen zero on the second dial pull, which nor-
mally wouldnot berestricted, exceptfor this interdigital circuitryO
DIGITAL TIMING CIRCUITRY HANG UP
After completion of a call and the telephone instrument
is returned to onhook state, coil K2 deenergizes and starts the
discharge of capacitor C4 through resistors R14, R15, and R16.
The time required for C4 to discharge below the threshold refer-
ence of comparator 8 is approximately 300 milliseconds. This
time constitutes the onhook tirneout period. ~hen C4 is discharged
at the point below the reference of comparator 8, th~ output 11
of comparator 8 turns to logic zero. The transistor Q2 thus drops
out of saturation deenergizing relay K3, opening relay contacts
13, thus again providing infinite input impedance to the toll
restrictor as seen from the telephone line, With output 11 of
comparator 8 at logic zero, all the latches and counters return
to reset condition as previously described.
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37
RING-IN
Whenever a multiple ringer is placed on the line, the
tendency of capacitor C5 to charge is proportional to the number
of ringers on the line. The reason C4 starts to charge during
ring is because relay coil K2 becomes energized on every half
cycle of the ring current. Capacitor C4 has a tendency to in
tegrate to the logic level 1 on every positive and negative peak
of the ringing voltage. If this condition remained unchecked,
the toll restrictor logic will interpret the ring as an offhook
condition and thus breaking the ring would be considered as a
hangup. Consequently, the toll restrictor would be going from the
onhook to the offhook state, thus closing contacts 13 during ring-
ing. Therefore, the circuit would no longer provide infinite
impedance to the line which is undesirable. This condition is
prevented by way of transistor Q3. K2 energizes during ringing
and starts to charge C4. Thus, C4 after being charged to a
voltage equal to approximately .7 volts, causing the emitter-base
junction of Q3 to be forward biased between ringing voltage peaks.
Consequently, transistor Q3 saturates resulting in the removal
of the charge on C4. Capacitor C4 discharges through the emitter-
collector junction of Q3 and diode CR13 placing the logic "0" at
the output 11 of comparator 8. Therefore, capacitor C4 never has
the opportunity to become charged to the reference level of com-
parator 10 which would give a false onhook indication.
The circuit as heretofore described has been built and
operated with components having the following values:
CR1 W04M Full Wave Bridge Rectifier
CR2
CR14 IN4148 Diode
CR15 " "
CR13
CR20
CR12
CR3 ll "
CR4 ~ "
CR10 " "
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~3LZ~3~
CR9 IN4148 Diode
CR16 " 1~
CR8 " "
CR3 " "
CR30 "
CR31 "
CR32 "
CR33 " "
CR34 " "
CR35 " "
CR36
CR37 ~l .
CR38 1! 11
CR7 IN4004 Diode
CR6 ll .l
CR17 " "
CR5 ~l ,l
12 Light Emitting Diode (LED)
V2 Varistor (lOOF)
Ql Transistor NPN 2N2222
Q4 " ll
Q3 Darlington Transistor PND MPSA65
Q2 Transistor ~PN 2N2222
ICA 4001 2-Input Quad Nor Gate C-MOM
ICB 4011 C-Mo52-Input Quad Nand Gate
ICC 4001 C-Mo5 2 -Input Quad Nor Gate
44 4017 C-Mo5 Johnson Decade Counter
22 ~l ,l ll 1, ,
ICF 3403 Quad Op-Amp
ICG 3302 Quad Comparator
R16 10K Ohm Resistor
R17 1 Meg. Ohm " All Resi~stors
R15 330KOhm " are 1/2 Watt
R14 330KOhm
R13 47K
R12 100K
R40 1 Meg " "
R39 1.5 Meg " "
R38 1 K " "
R36 470K
R35 100K " "
R34 100K
R33 220K " "
37
R32 10K Ohm Resistor .
Rl lK " "
R43lK " "
R52.2K " " .
R62.2K " "
R72.2K " "
R210K " "
R34.7K " "
: R44.7K " "
R9100K " " :~
R1010K " " ~;
Rll100K " " ~ :
: R1847K
Rl9 1 Meg
R2247K " "
R20150K " " :
R2110K " "
R23 1 Meg " "
R41 1 Meg " "
R2447K " "
R25100K ": "
R30100K " " ~:
R29100K " "
R2847K " "
R27100K " "
R847K " "
Cl47 Micro Farad Capacitor
C210 " " "
C5065 " " " Non-Polarized
C42.2 " " "
C121 " " " ,
C510 " " "
C3.1 " " "
C131 " " "
Cll1 " " "
C810 " " "
C910 " " "
C6 1 " " "
Item 14 & 15 4N37 Optical Coupler
K2 1 Form A Reed Relay (Coil = 34 Ohm~
Kl 4 Pole Double Throw Cradle Relay
C10 1 Micro Farad Capacitor
R31 100K Ohm Resistor
'
- 20 -
. ' ! ~ ' .
~L~Z~3'7
So, it is seen that an infinite impedance toll restric-
tor (on hook) circuit is set forth which utilized a generated
strobe pulse for the dual purpose of providing interdigital tim-
ing and assurance of the restriction of only the intended digits.
From the foregoing description of the preferred embo-
diment of the invention, it will be apparent that many modifi-
cations may be made therein. It should be understood, however,
that this embodiment of the invention is intended as an exempli-
fication of the invention only and that the invention is not
limited thereto. It is to be understood, therefore, that it is
intended in the appended claims to cover all such modifications
as fall within the true scope of the invention.
This is a division of Canadian patent application
Serial No. 309,857 filed August 23, 1978.
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