Note: Descriptions are shown in the official language in which they were submitted.
s
DIGITAL SIGN~L PROCESSING SYSTEM
The present invention relates to a digital signal
processing system, and more particularly relates to a
digital signal processing system which is most preferably
utilized in a MODEM (Modulator - DEModulator).
The MODEM is used at each end of a telephone channel
to convert binary digital information to audio signals
suitable for transmission over the line, and vice versa.
It is the latest tendency to operate the MODEM with a very
high speed operation, for the purpose of dealing with a
very large amount of data for data communication or achieving
a high speed facsimile transmission. Accordingly, although
many kinds of digital processing techni~ues have been
provided, it is necessary to develop a digital processing
technique which is most suitable for such a high speed
operating MODEM. Further, such a digital processing
technique should preferably be realized by the aid of LSIs
(Large Scale Integratred Circuits).
Careful consideration is required in choosing the
LSI architecture in order to obtain efficient and economical
~0 LSI realization of the modem functions described. The LSI
architecture must be sufficiently flexible and expandable
so that it allows accornodation of various changes in the
specifications or adap'cation to other systems.
Designing different LSI's for each different ~unction
inevitably results in developing too many different kinds
of LST's andl moreover, although this approach may be very
, ,
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l~Z7~5
efficient, it often suffers from lack of flexibility.
There have been several reports describing successful
utilization of off-the-shelf microprocessors to data
modems. Although this approach seems to provide the
highest degree of flexibility, there is a slight problem
in that the current microprocessors cannot efficiently
perform the multiplication operations abundant in modem
functions.
The approach taken here is to develop an LSI processor
matched to the DSP (Digital Signal Processor) applications
and, when necessary, employ more than one of these LSI's
to manage the total required quantity of arithmetic ope-
rations. The processor will thus be equipped with a
powerful arithmetic unit and will have the ability to
operate in multiprocessor mode. It will also include as
many useful features of the common microprocessor as
possible; the most important one being the firmware program-
mability. It is possible to significantly reduce the
number of different ~SI's needed to be developed and also
achieve a high degree of flexibility using this approach.
Therefore, it is an object of the present invention
to provide a digital signal processing system which is
useful for fabricating the MODEM by using a few kinds of
LSIs. However, it should be understood that, as will be
apparent from the following explanation, the digital
signal processing system of the present invention may be
applied not only to the aforementioned MOD~M, but also to
other digital data processing apparatuses.
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The present invention will be more apparent from
the ensuring description with reference to the accompanying
drawings wherein:
Fig. 1 is a bloc~ diagram of MODE~ adopted quadature
amplitude modulation method;
Fig. 2 depicts timing charts used for schematically
explaining the basic processing sequence utilized in a -
~digital signal processing system according to the present
invention;
Fig. 3 illustrates one example of a data set which
is suitable for conducting the digital signal processing
system according to the present invention;
Fig. 4 is a block diagram illustrating an example
of the digital processing system according to the present
invention;
Fig. 5 depicts timing charts representing statuses
of the system shown in Fig. 4;
Fig. 6 depicts timing charts used for explaining
the operation for the starting program which runs in the
system shown in Fig. 4;
Fig. 7 schematically illustrates contents of the
control storage (ROM) 430 shown in Fig. 4;
Fig. 8 depicts timing charts used for explaining an
initial starting of the processing adapted to the digital
signal processing system according -to the present invention;
Fig. 9 is an example of a circuit diagram illustrating
hardware for executing an initial starting of the program
to be processed by the digital signal processing system;
3~S
Fig. 10A depicts timing charts used for explaining
the operation of the hardware shown in Fig. 9;
Fig. 10B depicts timing charts used for explaining
the hardware shown in Fig. 9, the scale of time is expanded
compared to that of Fig. 10A;
Fig. 11 depicts timing charts used for explaining a
unique method preferably employed in the digital processing
system shown in Fig. 4;
Fig. 12 schematically illustrates a flow of programs
stored in the control storage (ROM) 430 shown in Fig. 4,
according to the present invention;
Fig. 13 illustrates a circuit diagram of one example
of the hardware for carrying out the unique method, explained
with reference to Figs. 11 and 12, employed preferably in
the digital signal processing system;
Fig. 14 depicts timing charts used for explaining
the processes of the unique method, and;
Fig. 15 is a block diagram of improved MODEMs 110
and 150 shown in Fig. 1, which improved MODEMs are con-
structed by utilizing the digital signal processing systemaccording to the present invention.
Although, as previously mentioned, the digital
signal processing system of the present invention can be
applied to various kinds of digital data processing ap-
paratuses, the following explanation of the present inventionis effected by taking, for example, a digital signal
processing system utiliæed in the MODEM~
In Fig. 1, which is a block diagram of a MODEM, the
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reference numeral 110 represents a transmitter and the
reference numeral 150 represents a receiver. The transmitter
110 is comprised of a code converter (CODE CONT) 111, a
signal point generator ~SIGNAL POINT) 112, a roll-off
filter (ROF) 113, a roll-off filter (ROF) 114, a mixer
115, a mixer 116, a phase shifter (90) 117, an adder 118,
digital/analogue converter (D/A) 119, a low pass
filter 120, a sequence controller (SEQUENCER) 121 and a
digital phase-locked loop circuit (D.PLL) 122. The trans-
mitter 110 is connected to the receiver 150 over a telephoneline 130. The receiver 150 is comprised of a code converter
(CODE CONV) 151, a decision circuit (DEC) 152, a carrier
phase tracking circuit (CAPC) 153, an automatic equalizer
(AEQL) 154, a roll-off filter (ROF) 155, a roll-off filter
15 (ROF) 156, a mixer 157, a mixer 158, a phase shifter (90~) -
159, an analogue/digital converter (A/D) 160, an automatic
gain controller (AGC) 161, a band pass filter (BPF~ 162, a
sequence controller (SEQUENCER) 163, a digital phase-locked
loop circuit [D~PLL) 164, a timing signal extracting
circuit (TIr~ING) 165 and a carrier detector (DET) 166.
The reference symbols Din denotes an input digital data
signal, DoUt denotes an output digital data signal, W
denotes a carrier wave signal, and CLK denotes a clock
signal. Other symbols RS, CS, ST2 and CD are commonly
defined by the o-called C.C.I.T.T. Recommendation.
In the transmitter 110, the date to be transmitt~d
(Din) are scrambled and then grouped to ~ bits at a time
to form guad bits. The generator 112 determines a specified
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signal point among the sixteen signal points according to
the quad bits. Then the generator 112 applies both the
in-phase and quadrature components of the specified signal
point, respectively, to the filters 113 and 114. The
roll-off filters 113, 114 and also the roll-off filters
155, 156 are employed so as to achieve a proper spectram
shaping. The two outputs of filters 113 and 11~ modulate
the carrier wave signal W having the frequency of, for
example 1700 Hz by means of the mixers 115, 116 and a
shifter 117, and the modulated signals are added up together
,
by means of the adder 118 to form the final ~AM signal.
The output from the adder 118 is converted into an analogue
signal by means of the D/A converter 119 and transmitted
to the receiver over the line 130, 110 after filtering by
the filter 120.
- The sequence of the digital signal processing steps
in the transmitter 110 is determined by the sequence
controller 121. The synchronization of the digital signals
in the transmitter 110 is performed by the clock signal
CLK produced from the D.PLL circuit 122.
In the receiver 150, after eliminating out-of-band
noise with the band pass filter 162, the receiv~d modulated
signal is passed through AGC 161 to obtain constant signal
level. The output of the AGC 161 is fed into A/D con-
verter 160 and changed to digital form. The digitalizedsignal is demodulated by mixer 157, 158 and passed through
the roll,-off filters 155, 156 to eliminate unnecessary
components and complete (together with the roll-off rilter
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placed at the transmitter) the cosine roll-off spectrum
shaping. Both the in-phase and quadrature components
produced from the filters 155 and 156 are applied to the
automatic equalizer 154. The equalizer 154 compensates
the distortion of the transmitted data signal. The output
from the equalizer is then applied to the carrier phase
tracking circuit 153 which compensates both a frequency
offset and a phase jitter included in the transmitted data
signal. The equalized output from the circuit 153 is
applied to the decision circuit 152, and after proper code
conversion and descrambling by the circuit 151, the correct
received date (Dout) can be obtained. The circuit 152
also transfers the error signal between the equalized data
from the circuit 153 and the reference symbol point through
a feed back path F to accomodate with the adaptive equali-
zation and the carrier phase tracking. The detector 166
detects the arrival of a transmitted signal and activates
the sequence controller 1~3. The circuit 165 extracts the
timing signal included in the transmitted data signal and
activates the D PLL circuit 164 so as to generate the
reference clock signal CLK.
This MODEM which are constructed by utilizing the
digital processing system of the present invention, can be
fabricated by eight chips of LSIs which are classified
into only three different kinds of LSIs. The reason why
the number of kinds of LSIs could be reduced is as follows.
The circuit elements which construct the MODEM is divided
into 2 parts, namely those functions which can be realized
S
by digital signal processing operations and those whieh
are more random logic type in nature and cannot be
expressed by arithmetic operations. The latter part
includes code conversion, frequency dividers, sequence
controllers, and other miscellaneous functions. For
these functions, it is necessary to design random
logie LSIs dedieated to eaeh purposes. The former
part ean all be reduced to the AxB~C -~ D type operations
which includes! in the transmitter 110, the roll-off
filters 113, 114, and the modulation means comprised
of the mixers 115, 116, th~ adder 118 and the shifter
117 and, in the receiver 150, the roll-off filters 155,
156, the demodulation means eomprised of the mixers
157, 158 and the shifter 159, the automatie equalizer
154, the timing signal extracting circuit 165 and the
earrier phase tracking circuit 153. Thus, eaeh of the
above reeited circuit elements (113), (114) ...(165) can
be constructed by the identieal ehip o~ LSI. In eaeh
thereof, the above formula A x B ~ C is operated repeatedly.
20 For example, the transversal-type digital filter ean be
expressed by the following equation.
Yk = ~ cixk-i
25 The symbol Yk denotes the filtered output signal ~rom the
transversal-type digital filter and the symbols Ci is
coeffieient and Xk i is input data. The above reeited
equation may ke rewritten as follows.
~;273~5
Y = ClXk 1 + C2Xk-2 + C3Xk_3 + C4Xk_4 n k-n
The item ClXk 1 corresponds to the value C in the formula
A x B + C. The values C~ and Xk 2 correspond, respectively
to the values A and B in this formula A x B ~ C. That is,
C2Xk 2 corresponds to A x B. In the next stage, the items
(ClXk 1 + C2Xk 2) correspond to the value C. The values
C3 and Xk 3 correspond, respectively, to the values A and
B Thus, the value of ClXk_l ~ C2Xk_2 3 k-3
Then the resultant value Y~ may be obtained by executing
the identical formula A x B + C with respect to C4Xk 4
... CnXk n ~ repeatedlY-
The digital signal processing system of the presentinvention will be explained hereinafter. This digital
signal processing system can execute the above mentioned
arithmetic function (A x B + C) with a very high degree of
efficiency. It is important to note that the MODEMs should
be operated under a so-called real time processing mode,
and accordingly the digital signal processing system must
execute the desired function, such as the above mentioned
arithmetic function (A x B + C3, with a high degree
of efficiency.
Generally, the digital signal processing system of
the prior art is operated by the following steps,
(I)
a) decoding an instruction,
b) reading a data,
c) executing an arithmetic operation, and
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further
(II)
d) decoding an instruction to be transmitted
to an external device, and
S e) producing the resultant output data. As
will he apparent from the above recited steps a) through
e), all the individual operations are executed one by one ~ -
sequentially. Therefore, the digital signal processing
system of the prior art cannot execute the desired arithmetic
function with a high degree of efficiency. Further, the
processing system of the prior art has the following
shortcomings. Firstly, it is not easy to build up a
microprogram being subject to a sequence of a desired
function. Secondly, it requires much time and labour to
revise the microprogram. Thirdly, it is not easy to
simplify the construction of a clock means and a control
means in the processing system. The above mentioned three
shortcomings are derived from the fact that, in the pro-
cessing system of the prior art, the number of the machine
cycles are not the same with respect to the respective
kinds of instructions.
The digital signal processing system of the present
invention can execute the desired arithmetic function with
a hiyh degree of efficiency and also creates no shor-t-
comings similar to the above mentioned three shortcomingsof the prior art. Fig. 2 depicts timing charts used for
schematically explaining the basic processing sequence
utilized in the digital signal processing system according
:
;27~3~5
to the present invention. In Fig. 2, operation blocks
210, 220, 230, 240, 250, 260 ... are respectively performed
in (i)th, (i+l)th, (i~2)th, (i~3)th, (i+4)th, (i+5)th
processing steps. Each of the operation blocks, for
example the operation blocks 210 through 240, is operated
through a first cycle, a second cycle and a third cycle
sequentially, and the first cycles are data input cycles
(INPUT) 211, 221, 231 and 241, the second cycles are
arithmetic operatlon eycles (OPERATION) 212, 222, 232 and
242 and the third eycles are data output eyeles, if wanted,
(OUTPUT) 213, 223, 233 and 243. Further, all the eycles
are allotted so as to have the same constant duration.
Furthermore, every two adjacent operation blocks are
shifted from each other by a constant duration as the time t
elapsed. Consequently, the data input cycle 231, the
arithmetic operation cyele 222 and the data output cycle
213 overlap with each other and are exeeuted parallely.
When the above mentioned overlap proeessing is
eonducted, it is important to suitably determine the
number of steps to be eompleted in each cycle, in order to
eomplete the execution of eaeh eycle within a same constant
duration. In order to suitably determine the number of
steps, two factors must be taken into consideration. The
first faetor is an algorithm for operation and the second
factor is a format for transferring the input and output
data.
The number of steps to be eompleted in eaeh eyele
is determined, in the present invention to be, for example,
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five, when the aforesaid function A x B ~ C is operated.
Accordin~ly, the read operation of the instruction code
and also the feed operation of the inpu~ data, must be
completed with a high degree of efficiency within the five
steps. One example of a data set for completing each
cycle within the five steps, is illustrated in Fig. 3. In
Fig. 3, the data set 300 is composed of five data, that is
instructlon code 310, word "P" 320, word "Q" 330, word "R"
340 and word "S" 350. Each of the data 310 through 350
has 8 bits pattern (see the digits 1 through 8 on the top
of the data 310). The data 310 through 350 are all 1 byte
data. The five 1 byte data 310 through 350 are read from
a storage device in the respective five steps mentioned
above. Specifically, règarding the aforesaid function A x
B ~ C, the words "P" and "Q" are, respectively an upper 1
byte data and a lower 1 byte data of the multiplicand A
which is composed of 2 byte data, the words "R" and "S"
are, respectively an upper 1 byte data and a lower 1 byte
data of the multiplier B which is also composed of 2 byte
data. Since each arithmetic operation ~see 212, 222, 232
... in Fig. 2) is conducted by using 2 byte data, both the
multiplicand ~ and the multiplier B are composed of 2 byte
data.
Fig. 4 is a block diagram illustrating an example
of the digital signal processing system according to the
present invention, which system is operated according to
the overlap processing (refer to Fig. 2) and by using thP
data set 300 ~see Fig. 3). In Fig. 4, members 401 through
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409 constitute a microprocessor and members 420 and 430
constitute external devices with respect to the micro-
processor. The reference numeral 401 represents an arith-
metic unit which continuously performs the A x B ~ C - D
type operations, 402 represents an input data selector,
403 represents an input buffer data register, 404 represents
an instruction decoder, 405 represents a decoder buffer
register, 406 represents a RAM address selector, 407
represents a RAM (Random Access Memory3 address buffer
register, 408 represents an output data selector, 409
represents a program counter. The reference numeral 420
represents a storage device made of a RAM, the reference
numeral 430 represent program memories by ROMs (Read Only
Memory) and the reference numeral 440 represents a common
lS data bus. The programm`memories 430 store the data set
300 shown in Fia. 3. The instruction decoder 404 decodes
the data stored in the bu~fer 405 so as to control the
members 401, 402, 406, 408 and 409 via respective paths
indicated by dotted lines. The address buffer register
407 stores the words "P", "Q", 'IRi' and 'IS" (shown in Fig. 3)
sequentially. The storage device (RAM) 420 store
operand data. The data selector 402 selects the desired
one of the input data to be supplied to the arithmetic
unit 401. The arithmetic unit 401 achieves the operation
according to, for example, the aforesaid arithmetic function
A x B ~ C. The selector 408 selects the desired one of
the output data. The selector 406 is available to be used
as a means for a modifying RAM addressing.
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The operation of the system shown in Fig. 4 will be
explained with reference to Fig. 5 which depicts timing
charts representing the statuses of the system shown in
Fig. 4. The clock signals shown in a row a) are basic
clock signals for synchronizing the operations performed
in the system of Fig. 4. The aforementioned five steps
~ shown in a row g) are allotted sequentially
in synchronous wlth the clock signals. At first, the
program counter 409 executes an access to the control
storage 430 via a line 451 in synchronous with a clock
signal Cl in row a) of Fig. 5. Then a first one of the
data se-t 300 (see Fig. 3), that is the instruction code
310 tsee Fig. 3), is read from the storage 430. A first
data set is indicated by the reference symbol DS-l in a
row cJ of Fig. 5 and also the instruction code is indicated
by the xeference symbol INST-l in a row b) thereof. The
instruction code INST-l is applied, via a line ~52, to the
decoder buffer register 405, and then to the instruction
decoder 404 where the decoder 404 decodes the instruction
code INST-l in synchronous with the clock signal C2. A
duration in which the instruction code INST-l is effective
is defined by the time between the clock signals C2
through C6 (refer to "INST-l effective" in a row d) ).
All the operations during the INST-l effective" are subject
to the instruc~ion code INST-l. At the same time, the
word "P" shown in Fig. 3 (refer to the reference symbol
P-l in the row b) ) is read ~rom the control storage 430
in synchronous with the same clock signal C2. This word
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P-l which is read from the storage 430, is stored in the
RAM address buffer register 407, via lines 452 and 453 in
synchronous with the clock signal C3. The reference
symbol P-l in a row e) indicates the stored word P-l. At
the same time, the word "Q" shown in Fig. 3 (refer to the
reference sy~bol Q-l in the row b) ) is read from the
storage 430 in synchronous with the same clock signal C3. .
This word Q-l is also stored in the register 407 (refer to
the reference symbol Q-l in the row e) ), in synchronous
with the clock signal C4. In a similar way, the words "R"
and "S" shown in Fig. 3 are read from the storage 430
(refer to the re~erence symbols R-l and S-l in the row b) )
and stored in the register 407 (refer to the reference
symbols R-l and S-l in a row f) ), in synchronous with the
respective clock signals C4 , C5 and C6.
The words P-l and R-l are directly supplied to the
RAM address buffer register 407, via the lines 452 and 453
from the storage 430. The words Q-l and S-l are supplied
to the register 407, via lines 452, 453 and a line 454 and
the selector 406, from the storage 430. In a case where
the words P-l and ~-1 themselves are the operand data, as
a multiplicand, to be arithmetically operated in the
arithmetic unit 401, these words are directly supplied
~rom the register 407 to the unit 401, via a line 455 and
the input/output data selector 402. Contrary to this, in
a case where the words P-l and Q-l, as a multiplier, are
the access address information for the storage device
(RAM) 420, the register 407 executes an access to -the
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storage device 420 via a line 456. The operand data read
from the storage device 420 is supplied, as a multiplicand,
to the arithmetic unit 401 via a line 457 and the selector
402. Depending on whether the words P-l and Q-l are the
5 operand data itself or whether these words P-l and Q-l
are the access address information (in other words, depending
on whether the words P-l and Q-l are the data read from
the RAM 420 or the data read from the ROM 430), these
words P-l and Q-l can be supplied, via the lines 455 and
457, to the arithmetic unit 401 within a specified duration
until the rising edge of the clock signal C5 is generated,
due to the presence of the register 407. Similarly, the
words R-l and S-l can be supplied to the unit 401 within a
specified duration until the rising edge of the clock
15 signal C7 is genera~ed. It should be noted that, in the
digital signal processing system of the prior art, although
the data from the ROM can be directly supplied to the
arithmetic unit, the data from the RAM must be supplied
thereto through an addressing operation and a reading
20 operation in synchronous with the next coming clock signal.
However, in the present invention, since firstly the.
function of all the data to be supplied to the arithmetic
unit i5 determined, in advance, by the instruction code,
and secondly the five data 310 through 350 of each data
25 set are fixedly alloted the respective five steps ~ ,
~ ... ~ (see in row g) of Fig. 5), the above mentioned
addressing operation and all the reading operation to be
conducted in synchronous with the next coming clock signal
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- 17 -
can be eliminated.
At the time when the clock signal C7 is generated,
a second instruction code "INST-2" (see the row b) of
Fig. 5) of a second data set DS-2 (see the row c) of the
same) is decoded by the instruction decoder 404. Then the
operation A x B of the aforesaid function A x B ~ C is
carried out, in the unit 401, in accordance with the
second instruction code INST-2, by using the above mentioned
data P-l, Q-l, R-l and S-l which have already been supplied
to the unit 4010 This operation A x B, that is (P-l,
Q~l) x (R-l, S-1), is completed within a second time slot
TS-2 indicated in a row h) of Fig. 5. This time slot
TS-2 is also created along and within the five steps ~ ,
~ in a row gj of Fig. 5. The resulting data A x
B is added to the remained data C in the same time slot
TS-2, which resulting data C was obtained, in a first time
slot ST-l, as a result of the identical operation A x B +
C, and has b2en stored in an output data buffer register
(not shown) contained in the arithmetic unit 401. At the
same time, the words P-2, Q-2, R-2 and S-2 of a second
data set DS-2 are read from the control storage 430 and
supplied to the arithmetic unit 401 in the same manner as
described before with respect to the words P-l, Q-l,
R-l and S-l. Thus, the overlap processings are performed
sequentially. Whichever the data 320 through 350 (see Fig.
3) of the data set, read from ROM 430, represent the
operand data or the access address information, the operand
data to be supplied to the arithmetic unit ~01 can be
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transferred in synchronous with the specified clock signals,
due to the presence of the RAM access address buffer
register 407 which momentarily stores the data 320 through
350 therein.
Usually, the operand data to be supplied to the
arithmetic unit 401 are produced from the control storage
(ROM) 430 and the storage device (RAM) 420. However, the -~
data to be supplied to the unit 401 are not limited to the
above mentioned operand data. For example, following data
10 are also supplied to the unit 401. Firstly, the so-called
ROM data stored in the control storage 430; secondly, the
so-called RAM data stored in the storage device 420;
thirdly, the so-called EXT (external) data (see the reference
symbol EXT in Fig. 4) which is supplied from the data bus
15 440 which is connected to external devices such as the
séquence controller 121 in Fig. l; fourthly, the D data as
a result of operation kept in the output data buffer
register, which is supplied to the selector 408 via a line
458 and finally to the storage device 420 via a line 461;
20 and lastly, the E data supplied from the input buffer data
register 403. The above mentioned data EXT, D and E are
proyided to the arithmetic unit 401 by means of the selector
402. A line 462 transfers data to be operated repeatedly
in the unit 401. During the process of these EXT, D and E
25 data, it is not necessary to read the operand data from
the storage device 420. Therefore, by utilizing this
duration in which these EXT, D and E data are processed,
the output data from the selector 408 can be written in
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the storage device 420. The selector 408 receives the
data transferred on the line 458 and also the data trans-
ferred on a line 459.
In the above mentioned digital signal processing
5 system, the serial processing is achieved in accordance
with the series of the data sets (DS-l, DS-2 ...) which
are stored in the control storage 430. Accordingly, once
the series of the data sets are stored in the storage 430,
only the fixed serial processing is achieved. In other
10 words, it is impossible to carry out an optional processing
rather than the fixed serial processing. Consequently, it
is inconvenient to apply this system to, for example the
MODEM shown in Fig. 1. In the MODEM, it is often required
to change the parameters to maintain the MODEM at a high
15 level of guality, especially in the training period. In
such case, the selector 406 in Fig. 4 is available for
simply changing the address to the RAMS. The selector 406
produces either the data via the line 454 or a data via a
line 460. The data applied through the line 460 is an
2~ external control data ECD. Usually, on one hand, the
upper byte of the data from the ROM 430 is directly applied,
via the line 453, to the buffer register 407 and, on the
other hand, the lower byte of the data therefrom is applied,
via the line 454 and the selector 406. Thus, the selector
25 406 can produce either the lower byte of the data read
from the storage 430 or the external control data ECD as a
lower b~te of the data to be used as RAM address data. In
this case, it is not necessary for the processor to change
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- 20 -
the usual program in order to run the operation under the
changed addresses, but merely to provide the external
control data ECD instead of the data transferred through
the line 454. Thus, the operand data to be supplied to
5 the arithmetic unit 401 can be modified without changing
the contents of the data sets stored in the ROM 430, and
accordingly, the selector 406 together with the data ECD
is very useful for the real time processing apparatus such
as MODEM.
As mentioned above, the microprocessor is operated
in accordance with the predetermined program by using the
series of data sets (see Fig. 3). Since the digital
signal processing system o~ the present invention is
utilized preferably in the MODEM, it is further necessary
15 to provide a suitable method for starting the predetermined
program adapted to activate the MODEM. The suitable
method therefor will be explained hereinafter. The digital
processing system executes the processes in increments one
by one in the program counter 409. That is, the program
20 counter 409 executes the incremental access to the control
storage 430, and the respective instruction codes are read
from the storage 430. Then the system functions in accordance
with the decoded instruction codes. At this time, an idle
state of the system is established by executing an in-
25 struction code indicating a wait, that is a wait instruction.When the wait instruction is provided, the program counter
409 stops executing the access to the ROM ~30. In the
present invention, the system is designed to stop, once
- 21 -
the wait instruction is detected, the data processing
until a start pulse SP is supplied from an external device
(not shown in Fig. 4). The reason why the above mentioned
idle state must be established in the system, is as follows.
Generally, the MODEMs have various kinds of types, such as
9600 bit/s type MODEM, 7200 bit/s type MODEM, 4800 bit/s
type MODEM and so on. Which type of the MODEMs will be
employed, is decided by the user. Consequently, the system
of the present invention must be designed so as to be
adapted to any type of MODEMs. In order to comply with
such demand as mentioned above, it is necessary to establish
an idle state in the system, during which idle state
preparation for adapting the system to the specified type
of the MODEMs is effected. This preparation will be
clarified by the following explanation. Fig. 6 depicts
timing charts used ~or explaining the operation for starting
the program for the purpose of accomplishing preparation
mentioned above. In Fig. 6, the clock signals CLK are
shown in a row a). At first, the program counter 409 5see
Fig. 4) produces a ROM address data R~-l Ishown in a
row b) ) so as to execute an access to the control storage
430 (see Fig. 4). The data specified by the address RA-l,
that is an ROM output data RO 1 (shown in a row c) ) is
produced from the storage 430. This da~a RO-l represents
the wait lnstruction (see "WAIT" in a row d) ). When the
wait instruction ''WAIT'I is decoded by the instruction
decoder 40~ (see Fig. 4), a count enable signal C~ becomes
logic "O" as shown in a row f). As a result, the program
1~7~
counter 409 stops executing the incremental access to the
storage 430. At this time, the program counter 409 produces
a next ROM address data RA-2 as shown in the row b) and a
ROM output data RO-2 is produced from ROM 430 according to
the address data RA-2. Since the count enable signal CE
is now logic "O" subject to the wait instruction "WAIT",
the output data RO-2 is held as it is for a while. After-
wards`the start pulse SP having logic "l" is generated as
shown in a row g). The start pulse SP induces a counter
preset signal CP having logic "l" (see a row h) ) in
synchronous with, for example, a processing phase PH4
shown in a row Q). Processing phase PHl through PH5 shown
in rows i) through m) correspond to the respective five
steps ~ through ~ shown in the row g) of Fig. 5. The
signal CP may be induced by the signal SP in synchronous
with one of the processing phases other than PH4. However,
the phase PH4 is preferable for inducing the signal CP, if
a jitter included in the pulse SP is taken into con-
sideration. Thus, a counter preset processing is completed
by the signal CP. Then the output data RO-2 which has
been left as it is, is now loaded in the program counter
409. A~ter this, the program counter 409 starts executing
the incremental access to the control storage 430 according
to the sequence defined by the counter 409. In a row e~,
instruction decoder latch clock signals IL are illustrated.
The first latch clock signal IL latches the state of the
instruction decoder 404 so as not to decode the data RO-2
Isee the row c) ), by mistake, in accordance with the
7~S
- 23 -
forthcoming programs generated by the program counter 409.
The second latch clock signal IL also latches the instruction
decoder 404 so as to maintain an instruction "INST" (see
the row d) ) defined by a data RO-3 (see the row c) ).
The data RO-3 is specified by a data RA-(2~ see the row
b) ). The data RA-(2~1) is preset in the program counter
409, based on the data RO-2.
During the above mentioned initial starting of the
program, that is the aforesaid preparation for adapting
the system to the specified type of the MODEMs, following
four operations must be completed:
I) a first operation for determing one specified
processing program according to an external selection
5 ignal SYS;
II) a second operation for clearing all the contents
of the storage device (RAM) 420;
III) a third operation for storing, in the device
(RAM) 420, initial values adapted to the specified processing
program mentioned in the above paragraph I), and;
IV) a fourth operation for executing the specified
processing program.
Fig. 7 schematically illustrate contents of
the control storage (ROM~ 430 as an example. In Fig. 7, a
wait instruction "WAIT" is stored at, for example an
25 address "00". Following addresses "01", "02", "03" and
"04" are allotted for a system selection area 700. A part
of the area 700 is selected by the above mentioned selection
signal SYS. For example, the addresses "01", "02" and
s
- 24 -
"03" correspond, respectively to the previously mentioned
9600 bit/s type MODEM, 7200 bit/s type MODEM and 4800
bit/s type MODEM. In the system selection area, a jump
instruction is stored. This jump instruction indicates,
for example, a head address AD2 which specifies an initial
program for a selected system No. 2. (see the reference
numeral 702-0), which selected system corresponds to, for
example, the 7200 bit/s type MODEM system. Each last
instruction of an initial program for a system NoO 1 (see
the reference numeral 701-0), a usual program for the
system No. 1 (see 701-2), the initial program for the
system No. 2 (702-0) and an usual program for the system
No. 2 (see 702-2), must be the wait instruction IIWAIT"
(see the row d) in Fig. 6j. Each of the usual programs
701-2 and 702-2 instructs the execution the overlap pro-
cessing (refer to Fig. 2).
Since the last instruction of the program is,
as mentioned above, the wait instruction, when the wait
instruction is executed at the last of the initial program
702-0, for example, the digital signal processing system
is left in the idle state. During this idle state, a data
which has read from the control storage 430, is left as it
is, which data is an address "b" which designates a desti-
nation of the jump instruction. The data of address "b",
25 which is left as it is during the idle state, is identical
with the ROM output data RO-2 (see the row c~ in Fig. 6).
This address "b" designates a head address ADb (see 702-1)
of the usual program 702-2 of the system No. 2, and at the
g 3L5
- 25 -
time when the start pulse SP (see the row g) in Fig. 6) is
generated, the head address ADb is preset in the program
counter 409. After this, the processing system executes
the process in accorclance with the usual program 702-2.
The above mentioned initial starting of the
processing will be more apparent by the following description
with reference to Fig. 8 which depicts timing charts used
for explaining the initial starting of the processing. In
Fig. 8, the sequential start pulses SP-0, SP-l, SP-2
10 are shown in a row a). At the beginning of the supply of
power, a sequence signal SS-0 (see a row b) ) of the
processing system is caused to be logic "1", thereby the
signal SS-0 causes the contents of the program counter 409
to be clear (see a state "0" in a row c) and also a mode
"idle" in a row e) ). A little time after the beginning
of the supply of power, a sequence signal SS-l is caused
to be logic "1" and then, the digital signal processing
system initially starts the processing. During the time
between the start pulses SP-l and SP-2, it is determined
20 which of the systems (No. 1, No. 2 ...) is specified by
the aforesaid external selection signal SYS, by means of a
d~tecting circuit (explained hereinafter). The detecting
circuit causes the program counter 409 to execute the
incremental counting of the contents of the counter 409 so
25 that one of the addresses "01" through "04" of the system
selection area 700 (see Fig. 7) is selected according to
the information contained in the signal SYS. The operation
for executing the system selection is carried out in a
s
- 26 -
duration V shown in a row d). At the same time, the RAM
420 is operated under a write mode so as to clear all the
contents of the device (RAM) 420 ~see the mode "CLEAR RAM"
in the row e) ). In this case, since the input data to
the device (RA~) is maintained to be "0" all the contents
of the device (RAM) are cleared one by one, regardless of
the contents of the programs, every time each clock signal
is applied to the RAM address buffer register 407. Soon
after, all the contents of the device (RAM) are cleared.
The operation for clearing all the contents of the device
(RAM), is very important in the processing system utilized
in the MODEM. If the RAM is not cleared, when the automatic
equalizer 154 (Fig. 1) starts operating, it takes a rela-
tively long time to be in an stable state. During the
existence of the sequence signal SS-l when the start pulse
SP-2 is generated, a head address AD2 (see Fig. 7), for
example, is set in the program counter 409, then the
processing system starts processing in accordance with the
initial program 702-0 (see Fig. 7). The head address AD2
is determined by the aforementioned detecting circuit
based on the external selection signal SYS. The processing
system starts executing the initial program at the begining
of the duration W (see the row d) ) and finishes executing
when the wait instruction is detected. The beginning of
the duration W is in synchronous with the generation of
the start pulse SP-2. Thus, the mode for executing the
initial program 702-0 Isee Fig. 7) is established within
the mode "INITIAL PROGRAM" shown in the row e). This
- 27 -
initial program is available for loading initial values in
the device (RAM). The initial values are the constant like
0, 1 and so on which are used in the operation.
After executing the initial program, a mode of
"IDLE" state (see the row e) ) follows. At the beginning
of the start pulse SP-5, the sequence signal SS-2 appears
(see the row b) ). The sequence signals SS-2, SS-l and
SS-0 are provided from, for example, the aforesaid sequence
controller 121 (163) of the MODEMs shown in Fig. 1. Then
the processing system executes the usual program 702-2,
the head address of which program 702-2 is designated by
the head address ADb (see Fig. 7). The usual program
702-2 is executed in a duration ~ shown in the row d). In
the duration X, the usual program 702-2 is executed re-
peatedly so as to operate, for example, the aforesaidarithmetic function A x B + C cyclicly, in synchronous
with the start pulses, every time each five steps ~ ,
... ~ elapse. This is because, a head address ADb (see
702-3 in Fig. 7) existing at the end of the program 702-2,
designates the head of the same program 702-2.
Fig. 9 is a circuit diagram of a hardware for
executing the above mentioned initial starting o~ the
program to be processed by the processing system. In
Fig. 9, the program counter 409 and the RAM address buffer
register 407 have already been explained. Also, the
sequence signals SS-0 and SS-l, the wait instruction
"WAIT", the start pulse SP, the processing phases PHl
through PH5 and the external selection signal (SYSl,
- 28 -
SYS2), have already been explained. The reference numerals
905 through 910, respectively, represent flip-flops. The
reference numerals 911 through 915, respectively represent
NAND gates. The reference numerals 916 through 921,
respectively, represent AND gates. The reference numerals
922 through 926, respectively represent NOR gates. 927
represents a coincidence circuit (EXCLUSIVE NOR). The
numerals 928 through 933, respectively represent NOT
gates. 934 represents a kind of OR gates. Fig. 10A
depicts timing charts used for explaining the operation of
the hardware shown in Fig. 9. The waveforms of signals
~ through ~ appearing at respective portions in the
hardware of Fig. 9, are illustrated, respectively, in rows
a) through n) of Fig. 10A. In Fig. 9, when the sequence
signal SS-0 1 ~ ) is logic "1" (see a row a) ), the program
counter 409 is cleared (corresponding to the address "00"
(see Fig. 7) of the control storage 430). Therefore, the
wait instruction "WAIT" ( ~ ) which is logic "0", is
produced (see a row i) ) and the Q-output signal ~ of
the flip-flop 907 becomes logic "1" (see a row h) ).
Next, the sequence signal SS-l ( ~?) ) is provided (see a
row a') ~. A signal @ from the NAND gate 911 has logic
"3", after which the start pulse SP-3 ~ (see a row b~
is generated and also the sequence signal SS-l is logic
"1". In the duration when the signal ~) is logic "0"
~see a row c) ), the AND gate 91~ produces logic "0". A
signal (^d~ from the NAND gate 912 is created by differ-
entiating the sequence signal SS-l and becomes logic "0"
- 29 -
from the time when the start pulse SP-l is generated to
when the start pulse SP-2 is generated. Therefore, on one
hand, the output of the AND gate 916 is caused to be logic
"0" by a signal ~ . On the other hand, the signal ~ is
used as a start signal for clearing all the contents of
the RAM address buffer register 407 (refer to "CLEAR RAM"
in the row e) of Fig. 8). A signal ~ from the NOR gate
923 is created by differentiating the start pulse in
synchronous with the clock signal CLK generated at the
processing phase PH3 (see a row e) ). The clock signal
CLK, the start pulse SP, the processing phase, and also
the signals f~ , ~ are depicted in Fig. 10~.
However, Fig. 10B is depicted by using an expanded scale
of elapsed time compared to the scale used in Fig. lOA.
In Fig. 9, a signal ~ from the ~-output of the flip-flop
907 is used for determining the provision of the count -
enable signal CE (refer to the row f) of Fig. 6) for
activating the program counter 409. The signal (~ becomes
logic "0" in synchronous with the start pulses and the
clock signals, and the signal '~ has the waveforms as
shown in $he row h) in Fig. 10A. As a result, a signal
C~ that is the count enable signal CE is obtained, which
has the waveforms as shown in a row m). A signal ~ Isee
a row g) of Fig. lOA and Fig. 10B) from the AND gate 917
is used as a clock signal of the flip-flop 907, which
clock signal is generated after $he time when the count
enable signal is provided and also after the start pulse
is generated. Since the signal ~ has a relationship
7~
- 30 -
with the signal ~ by means of the AND gate 917, a clock
signal per each start pulse is produced. A signal ~
from the NAND gate 914 is logic "1" corresponding to the
external selection signals SYSl and SYS2 in the duration
(see a row Q) ). It is provided as an elongated clock
signal ~ for the syætem selection in the duration between
the start pulses SP-l and SP-2 when the sequence signal
SS-l is provided. This NAND gate 914 receives a signal
~ from the OR gate 934. The signal ~k~ is a clock
signal used for executing the system selection (refer to
the duration V in the row d) of Fig. 8 and the area 700 in
Fig. 7). This OR gate 934 produces sequential clock
signals generated in synchronous with the processing
phases PH3/ PH4, PH5 and PHl under the relationship with
the aforesaid external selection signals SYSl and SYS2.
The signals SYSl and SYS2 determine which system, for
example, 9600 ~it/s type MODEM, 7200 bit/s type MODEM or
4800 bit/s type MODEM, is to be slected. ~hen logics of
the signals SYSl and SYS2 are preset to be ("0""0"~,
("0""1"), ("1", '0'i) and ("1", "1"), the number of the
aforesaid sequential clock signals, generated in synchronous
with the processing phases PH3, PH4, PH5 and PHl are, for
example one, two, three and four, respectively. A signal
~ from the AND gate 916 is a load pulse of the program
counter which is made by differentiating the start pulses
except for SP-l, SP-3 and SP-4. A signal ~ from the
NAND gate 913 is caused to be a logic "1" signal so as to
count up the program counter in the duration except for
1~7~
D4. A signal ,~ from the NAND gate 915 (see a row n) )
is an inverted pulse signal of a signal i~ in synchronous
with PH4 signal. A row 0) indicates durations D1 through
D6. Dl corresponds to a duration for clearing the content
of the program counter 409, D2 to a duration for clearing
the device 420 and also carrying out the system
selection, D3 to a duration for executing the initial
program, D4 to a duration of the "IDLE" and D5 to a duration
for executing the usual program. D6 is identical with D5.
Since the system selection is carried out by
using the external selection signals SYS1 and SYS2, the
selection is achieved not by a software mode but by a
hardware mode. The hardware is the aforesaid detecting
circuit comprised of the gate members located at the input
stages of the signals SYSl and SYS2. Therefore, the
volume of the instructions ~hich must be loaded in the
control storage (ROM) 430 is considerably reduced.
The RAM address register 407 shown at the
bottom in Fig. 9 acts, on one hand, as a register for
storing the RAM addresses and, on the other hand, as a
scrambler by cooperating with the gates 925, 926, 927 and
the flip-flop 910. A line 951 acts as a serial input line
~or a first input stage and a line 952 acts as an output
line from a fifth output stage so that the scrambler
produces (29-1) random patterns. This scrambler is available
for clearing all the contents of the storage device IRAM)
420 (refer to "CLEAR RAM" in the row e) of Fig. 8). The
register 407 is utilized as the scrambler when the signal
7 ~ ~ ~
- 32 -
~ (see the row d) of Fig. 10A) having logic "0" is
applied to a control terminal 953 thereof. When the
signal ~ is logic "1", the register 407 is operated as
the RAM address register. It should be noted that the
register ~07 may also be comprised as a counter, instead
of a scrambler, for clearing all the contents of the
device ~RAM) 420.
Returning to Fig. 1, the ~IODEM must be operated
under the real time processing mode. For example, both
the automatic equalizer 154 and the carrier phase tracking
circuit 153 must process each respective input data one by
one intermittently with a frequency of, for example 2.4
KHz. The roll-off filters 113, 114, 155, 156, the modulating
means (115 through 118), the demodulating means (157
through 159) and the timing signal extracting circuit 165
must process each respective input data one by one inter-
mittently with a frequency of, for example 9.6 KHz.
Regarding the above mentioned real time operation mode,
one problem is raised that must be solved. The problem is
that the length of the duration in which the processing of
each input data is completed, is much shorter than the
length of the period at which these input data are supplied,
and, accordingly, undesired idling times are intermittently
created in the digital signal processing system shown in
Fig. 4. Therefore, the so-called NOP (No Operation) instruc-
tion must be executed during each idle time. However, the
control 430 should further store a great number of meaning-
less data in order to run the NOP instruction, and
~ t~
- 33 -
accordingly, the storage (ROM) 430 must be designed to be
a storage having a large capacity for accomodating the
great number of meaningless data therein. However, such a
large capacity storage (ROM) 430 is not desirable from an
economical viewpoint.
For the purpose of solving the abovementioned
problem in the present invention, unique method is further
employed. The method is comprised of the following
steps: -
a) holding the program counter 409 to be in
a non-incremetal accessing state after which a wait in-
struction is provided from the storage (ROM) 430;
b) creating sequential and divisional programs
in the storage (ROM) 430, which programs process for the
respective input data;
c) locating the above mentioned wait instructin
at each end of the above mentioned sequential and divisional
programs, and;
d) executing the divisional program for
processing the ne~t new input data by doing the incremental
accessing in the program counter 409 after which the wait
instruction is executed and also when a corresponding
restart pulse RSP is generated.
- The above mentioned method will become more
apparent from the following description. Fig. 11 depicts
timing charts used for explaining the above mentioned
unique method. In Fig. 11, sequential usual programs to
be execut~d are shown in a row b). These usual programs
- 34 -
correspond to the usual program 701-2 or 702-2 shown in
Fig. 7. Each usual program starts running every time the
aforesaid start pulse SP is generated (see SP in a row a) ).
The input data DTl, DT2, DT3 ... are intermittently
provided, as shown in a row c). As previously mentioned,
since the length of each duration in which the processing
of each input data is completed, is much shorter than the
length of the period at which these input data are supplied,
an undesired idling time is created in each period at
which the input data LS supplied. Fig. 12 illustrates a
flow of programs loaded in the ROM 430, according to the
present invention. The reference numerals 1201-1, 1201-2,
1201-3 ... represent a first divisional program (ptl), a
second divisional program (pt2), a third divisional program
(pt3) ... , respectively. The divisional programs (ptl,
pt2, pt3 ...) process, respectively, the intermittent
input data DTl, DT~, DT3 ... . These processes are indicated
by the reference symbols ptl, pt2, pt3 ... in a row d) of
Fig. 11. At each end of the divisional programs (tl, t2,
t3 ...), wait instructions "WAIT" 1202-1, 1202-2, 1202-3
... are located at the respective addresses Q, m, n ...
shown on a left side in Fig. 12. The wait instructions
"WAIT" stop the execution of program at each end of the
divisional programs ~refer to the reference symbol "W" in
the row d) of Fig. 11). Every time the wait instruction
is executed, the digital signal processing system is left
in an idle state (see the term "IDLE'I in the row d) of
Fig. 11. The idle state is released every time the aforesaid
~7~
- 35 -
restart pulse is generated (refer to the reference symbol
RSP in a row e) of Fig. 11) and at the same time the next
divisional program starts running. The reference numerals
1203-1, 1203-2, 1203-3 ... represent reset instructions
"RESET", located at addresses (Q+l), (m~l), (n~l) ... .
The reset instruction "RESET" is available only at the
time when the start pulse SP is generated. Accordingly,
the addresses (Q+l), ~m+l), (n+l) ... are dummy addresses,
as far as the reset pulse RSP is being generated. Thus,
when the start pulse SP is generated, the start address is
loaded in the program counter 409, which instruction
specifies predetermined one address "0~" in the counter
409 in this case. Thereafter, the usual program again
starts running from the initial step stored at the specified
address "08" (see 08 in Fig. 12). The processes for
dealing with wait instruction "WAIT", in connection with
the clock signals, the ROM address data (RA), the ROM
output data (RO), start pulses SP, the count enabling
signal CE, the counter preset signal CP, the processing
phase PHl through PH5 and so on, are identical with the
processes which have been already explained with reference
to Fig. 6.
The above mentioned wait instruction in each
divisional program and the start pulse SP are very use~ul,
respectively, for creating the idle state "IDLE" (see the
row d) of Fig. 11~ and for reseting the usual program
repeatedly to its initial step. However, the start pulse
SP cannot be used as a pulse for seguentially starting the
~2~
- 36
processes of the divisional programs tl, t2, t3 ... one by
one. This is the reason why the restart pulses RSP are
introduced into the processor. That is, the restart
pulses RSP can be used for sequentially starting the
processes of the divisional programs tl, t2, t3 ... . In
Fig. 12, the reset instructions "RESET" being located at
the addresses (Q+l), (m+l), (n+1) ... are available only
when the start pulses SP are generated in order to return
back to the initial step of the usual program repeatedly,
while program areas 1204-1, 1204-2, 1204-3 ... being
located, respectively, at addresses (Q+2), (m+2), (n+2)
... are available every time the restart pulse RSP is
generated so as to continue processing the next divisional
program after the lapse of the preceding idle state. The
addresses (Q+2), (m+2), (n~2) ... respectively specify the
head addresses of the divisional programs tl, t2, t3 ~.. .
Fig. 13 illustrates a circuit diagram of one
example of a hardware for carrying out the above e~plained
unique method employed preferably in the processor. This
20 hardware is mounted in the instruction decoder 404 shown
in Fig. 4. Fig. 14 depicts a timing chart used for ex-
plaining the processes of this unique method. In Fig. 14,
the contents of rows a) through d) are identical with the
contents of the rows a) through d) of Fig. 6, res-
25 pectively, and also the contents of rows e) through i) areidentical with the contents of the rows i) through m) of
Fig. 6. In Fig. 14, the ROM output data RO-l (see the row
c) ), which is specified by the RGM address data RA-m
?.lS
- 37 -
(see the row b) in Fig. 14 and also the address "m" in
Fig. 12) is the wait instruction. Thereafter, the in-
cremental access to the control storage (ROM) 430, by the
program counter 409, is stopped from being executed, as
has already been explained with reference to Fig. 6. At
this time, the ROM output data RO-2 (see the row c) )
specified by the ROM address data RA-(m+l) (see the row b),
has been produced from the control storage (ROM) 430.
In a case where the restart pulse RSP is generated, since
the address (m+l) act5 as the dummy address, the next
address (m+2) becomes effective. Consequently, the program
counter 409 further continues the execution of the in-
cremental access to storage (ROM) 430 again, in synchronous
with, for example, the processing phase PH4 (see the
row h) ). Then, the address (m+2) specifies the initial
step of the divisional program Pt3 (see Fig. 12). Although
the ROM output data RO-~ is loaded when the start pulse
is generated in the program counter 409 by executing the
preset operation to this counter 40~, this data RO-2 is
not loaded when the restart pulse RSP is generated in the
program counter 409, because the preset operation is not
executed by this restart pulse RSP.
In Fig. 13, the reference numerals 1302 through
1304 represent flip-flops~ 1305 represents an AND gate,
1306 represents a NAND gate, 1307 represents a NOT gate,
and 1308 and 1309 represent N~R gate. The reference
symbols 'IWAIT'', "CLK" (clock signal), "SP", "RSP", 'IPH3'',
"PH4ll, and "CE" have already explained. The reference
-- 38 --
symbol "PE" from the NAND gate 1306 indicates a preset
enable signal, which signal "PE" allows the program counter
409 to execute the above mentioned preset operation so as
to specify the initial step of the usual program repeatedly
5 in synchronous not with the restart pulse RSP, but with
the start pulse SP.
When the ROM output data RO-l specifies th~
wait instruction "WAIT", then the flip-flop 1302 is reset
by this instruction "WAIT". As a result, the count enable
10 signal CE, applied to the program counter 409, becomes
logic "0" (see the row m) of Fig. 14). Accordingly, the
incremental access ts~ the control storage (ROM) 430 by the
counter 409, is stopped from being executed, during the
existence of logic "0" of the count enable signal CE. In
15 this case, when the restart pulse RSP is generated (see a
row j) of Fig. 14), this restart pulse RSP from the NOR
gate 1308 is differentiated by a differentiating circuit
comprised of the flip-Elops 1303, 1304 and the NOR gate
1309 in synchrnous with the clock signal produced at the
20 generation processing phase PH3. The differentiated
restart pulse RSP' (see a row k) of Fig. 14) is produced
from the NOR gate 1309 and applied to the AND gate 1305.
The ANr) gate 1305 produces a clock signal to be applied to
the flip-flop 1302, in synchronous with both the processing
25 phase PH4 (see the row h) of Fig. 14) and the inverted
clock signal CLK (see the row a) of Fig. 14) by means of
the NOT gate 1307. Clock signal to be applied to the
flip-flop 1302, is shown in a row ~) of Fig. 14. As a
315
- 39 -
result, the pro~ram counter 409 continues the incremental
access to control storage (ROM) 430 again and executes the
next divisional program t3 (see Fig. 12). The program
counter 409 specifies the address (m-~l) at the time when
the wait instruction "WAIT" (see the reference nu~eral
1202-2 in Fig. 12) has been executed. Therefore, when the
program counter 409 continues the incremental access to
the control storage (ROM) ~30 again, the program counter
409 specifies the address (m+2). This address (m+2) specifies
the initial step of the divisional program t3 (see Fig. 12).
Contrary to the above, when the start pulse SP is generated,
the start pulse SP directly ac-tivates the NAND gate 1306,
which gate 1306 also receives the outputs from the Q
output of the flip-flop 1302, a differentiated start SP
from the NOR gate 1309 and the signal corresponding to the
processing phase PH4. As a result, the preset enable
signal PE is produced from the NAND gate 1306. The preset
enable signal PE causes the program counter 409 to preset
the ROM output data RO-2 (s~e the row c) of Fig. 143
therein. The count enable signal CE is created when
either the restart pulse RSP or the start pulse is generated;
however, the preset enable signal P~ is created only when
the start pulse SP is generated. Thus, the above described
unique method is very useful for operating each intermittent
input data in a very short time and for creating each idle
state for a little time imediately after the completion of
each operation of said intermittent input data, as occurs
in the MODEM, without increasing the capacity o~ the
3~
- 40 -
ROM 430.
Fig. 15 is a block diagram of improved MODEM
shown in Fig. 1, which improved MODEM is constructed by
utilizing the digital signal processing system according
to the present invention. In Fig. 15, the reference
numerals 1510 and 1550 respectively represent the improved
MODEM shown in Fig. 1. In Fig. 15, members which are
referenced by the same reference numerals and symbols as
those of Fig. 1, are identical members. It is important
to understand that the MODEM is fabricated by eight chips
of LSIs which are classified into only three different
kinds of LSIs. In Fig. 15, a first type of LSI (XMT) is
indicated by the reference numeral 1501, a second type of
LSI (REC) is indicated by the reference numeral 1502 and a
third type of LSI (ALU: Arithmetic and Logic Unit) is
indicated by the reference numerals 1503-1, 1503~2, 1503-3,
1503-4, 1503- 5 and 1503-6, which are also referenced by
the reference symbols ALUl, ALU2, ALU3, ALU4, ALU5 and
ALU6. Thus, the MODEM is fabricated by eight chips of
LSIs classified into only three kinds of LSIs (1501),
(1502) and (1503-1 through 1503-6). The LSIs 1503-1
through 1503-6 have the completely same construction.
Each of the LSIs ALUl through ALU6 is constructed by
members which are identical with the members shown in
Fig. 4 except for the members 420 and 430. Each of the
ROMs and RAMs which cooperate with the respective LSIs
ALUl through ALU6, is identical with the control storage
(ROM) 430 and the storage device (RAM) 420 shown in Fig. 4O
- 41 -
The ALUl of Fig. 15 is substituted for both the roll-off
filters 113, 114 and the modulating means ( 115 through
118) of Fig. 4. The AL~2 and ALU3 of Fig. 15 are substituted
for the combination of the roll-off filters 155, 156, the
demodulating means (158, 159) and the timing signal ex-
tracting circuit 16 5 of Fig. 1. The ALU4 and ALU5 of
Fig. 15 are substituted for the automatic equalizer 154 of
Fig. 1. The ALU6 of Fig. 15 is substituted for both the
carrier phase tracking circuit 153 and a part of the
automatic equalizer 154 of Fig. 1. The remaining members
of Fig. 1 are mounted on the LSI (XMT) 1501 or the LSI
(REC) 1502. The reference numerals 1521 and 1522 represent
ROMs being cooperated with the LSI (XMT) 1501 and the LSI
(REC) 1502, respectively. The re~erence numeral 44Q
represents the common bus as shown in Fig. 4. The reference
numerals 1523 and 1524 respectively represent a comparator
and a digital/analogue converter (D/A).
While the invention has been particularly
shown and described with reference to a preferred embodiment
20 thereof, it will be understood by those skilled in the art
that the foregoing and other changes in form and detail
may be made ~herein without departing from the spirit and
scope of the invention.
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