Note: Descriptions are shown in the official language in which they were submitted.
Background of the Invention
The present invention pertains to the electrical power
supply art and, more particularly, to improved power supply
shutdown apparatus.
Power supply shutdown circuits are well known, particularly
in the electronics art. Such shutdown circuits sense for
the condition of any defined fault, such as overcurrent,
overvoltage, undervoltage, extreme operation temperature and
so on and inhibit operation of the supply in response to the
fault occurring.
In a particular application, a power shutdown supply
which responds to a low voltage condition is required for
use in a mobile data terminal. There, proper functioning of
the terminal requires that a specified voltage be applied to
a central microprocessor. Should the power supply voltage
fall below a given value, the microprocessor is likely to
generate numerous errors.
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CM-78947
For the above mentioned mobile data terminal application,
a switching mode type power supply is used. In such supplies,
a controlled oscillator drives the primary of a transformer.
Power supply voltage is taken from the transformer's secondary, -
after suitable rectification and filtering. A feedback
signal from the supply's output is compared witn a stable DC
reference to generate an error signal which is coupled to
the controllable oscillator. The error signal causes either
the frequency or duty cycle, depending upon the oscillator's
design, to vary in such a manner that the output voltage is
maintained at a desired level.
In power supply low voltage shutdown circuits according
to the prior art, the output voltage from the supply is `
compared to a fixed stable reference and the supply inhibited
if the output voltage has a predetermined relationship to
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the reference. The problem with such prior art shutdown `
systems is not only do they require a temperature and time
stable voltage reference, but also they require temperature
and time stable associated components. This results in a ;
shutdown circuit of considerable cost. Thus, the prior art
has elt a need for a precise yet inexpensive low voltage
shutdown circuit, particularly suited for switching mode
type power supplies.
Summar~ of the Invention
It is an object of this invention, therefore, to
provide improved voltage shutdown apparatus which does not
require a stable voltage reference.
It is a further object of this invention to provide the
above described voltage shut down apparatus which is particu-
larly adapted for inhibiting operation of a switching type
supply.
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~ riefl~, accord~ng to the invention, an improved
shutdown means is provided ~or a s~itchin~ type power supply,
whIch supply produces an output voltage which is a function
of the output from a controlled oscillator. The improvement
comprises means which inhibits operation of the supply in
response to a predetermined output from the controlled
oscillator. As a feature of the invention, for applications
wherein the controlled oscillator varied its duty cycle to
maintain output voltage, the power supply is inhibited when
the controlled oscillator produces a predetermined duty cycle
output.
It is another feature of the invention that a
shutdown timer may be provided which inhibits operation of
the power supply for a predetermined interval in response to
the occurrence of the aforementioned predetermined controlled
oscillator output. Additionally, a restart timer may be
provided which deactivates the inhibiting circuitry for a pre-
determined interval thereby allowing the supply to reestablish
its output voltage.
Accordingly there is provided a shutdown circuit
for a switching type power supply having a fixed reference
oscillator with an output wherein the voltage produced by the
supply iB a function of the output from a controlled oscillator,
comprising:
low voltage sense means for comparing the output
of the controlled oscillator to the output of the fixed
reference oscillator, and generating an inhibit signal in
response to a predetermined relationship between the fixed
reference oscillator output and the output from the controlled
oscillator;
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1127711
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shutdown timer means coupled to the low voltage
sense means for inhibiting operation of the power supply for
a predetermined time interval in response to said inhibit
signal.
B ef Descri tion of the Drawin s
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Fig~l is a block diagram illustrating the topology
of a switching power supply in combination with the improved
shutdown apparatus;
Fig. 2 is a detailed schematic diagram of the
preferred embodiment of the improved shutdown apparatus; and
Fig. 3 is a series of waveforms illustrative of
operation of the improved shutdown apparatus shown in
Figs. 1 and 2.
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CM-78947
Detailed Description of the Preferred Embodiment of the Invention
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Fig. 1 illustrates, in block diagram form, the inventive
shutdown circuit in combination with a switching mode type
power supply used in a mobile data terminal. The data
terminal is located in an automotive vehicle, and, thus,
electrical power is supplied through an automotive battery
10. The function of the power supply is to provide an
output DC bias B+ suitable for powering a microprocessor
(not shown) which controls operation of the data terminal.
Due to the nature of computer equipment, any drop in applied
DC bias voltage below a given operating tolerance may cause
the digital memory components to lose their proper state and
result in a subtle or catastrophic equipment failure. Thus,
it is a function of the shutdown circuit to sense this
condition and inhibit operation of the power supply as long
as the eondition exists.
Power from the battery 10 couples through a provided
switch 12 to a logic supply voltage regulator 14. Logic
supply voltage regulator 14 is of conventional design and
produees an output DC bias V+ which is used to bias the
power supply and shutdown circuitry.
The power supply is of the switehing mode type and
ineludes a master oseillator 20 whieh produces a fixed
frequeney AC signal at its output 20a. The clock frequency
from master clock 20 is divided into equal amplitude but
180 out of phase signals in a conventional phase splitter
22. The out of phase signals appear at the phase splitter
outputs 22a, b. The out of phase clock signals from phase
splitter 22 couple to the transformer primary driver 24.
Transformer driver 24 is of conventional design in such
switehing type supplies and includes processing circuitry to
CM-78947 112~11
apply the phase signal splitters to output transistors which
couple to the primary winding 30a of the switching mode
transformer 30. Provided in transformer primary driver 24
is a shutdown input 24a which, upon receiving a suitable
shutdown signal, inhibits operation of the power supply.
Also provided is a duty cycle feedback input 24b which, as
is more fully described hereinbelow, responds to an error
signal input to vary the duty cycle of the phase split clock
signal to predeterminedly control the current conduction
time through the primary 30a of transformer 30.
The secondary 30b of transformer 30 couples to the
input of an output recitifier and filter circuit 32. This
circuit is of conventional design and rectifies and filters
the DC signal appearing at the transformer secondary 30b,
producing an output DC bias B+ used to power the afore-
mentioned microprocessor and related logic circuitry.
Regulation of the instant supply is provided by sensing
the output DC voltage B+ and comparing this voltage to the
voltage from a stable voltage reference source 40 in a
feedback error amplifier comparator 42. The signal appearing
at the feedback error amplifier's output 42a is, thus, a
function of the difference between the output produced DC
voltage B+ and the stable voltage reference 40 produced DC
voltage. The error voltage is coupled to the input 44a of a
pulse width modulator 44. The output 44b of pulse width
modulator 44 connects to the duty cycle input 24b of the
transformer primary driver 24. Acting in the conventional
manner, the pulse width modulator 44 responds to the magni-
tude of the error signal applied at its input 44a to produce
an output signal of duty cycle ranging between predetermined
limits, in the present application ranging between 20 to
90%. The duty cycle input at transformer primary driver
CM-78947
input 24b is gated with the master clock phase split signal
to thereby produce a fixed frequency, variable duty cycle
signal which controls the conduction time of the drivers to
the transformer primary 30a.
Thus, during turn on of the power supply, the output DC
voltage B+ is less than the voltage reference 40 whereby the
puIse width modulator maintains conduction of the transformer
primary 30a at a 90% rate. Once the produced output DC
voltage B+ reaches the reference voltage 40, the pulse width
modulator reduces the conduction time of primary 30a to
stabilize at the desired output voltage.
Thus, in summary, the instant power supply is seen to
be of the switch mode type wherein a feedback loop varies
the duty cycle of a controlled oscillator to control the
output produced DC voltage.
As mentioned hereinabove, the instant shutdown circuitry,
indicated generally at 50, shuts down or inhibits operation
of the power supply in the event that the output produced DC
voltage B+ falls below some preset limit. In the prior art,
analog shutdown schemes were applied, which analog schemes
required high stability components for precise operation.
In a device according to the instant invention, a aompletely
digital shutdown circuit is utilized, thus eliminating the
need for stable components.
Referring again to Fig. 1, the power shutdown circuit
50 includes a low voltage sense circuit 52 to which is
applied the master clock 20 signal at a first input signal
52a and the pulse width modulator 45 produced duty cycle
signal at its second input 52b. In a manner described more
fully with respect to Figs. 2 and 3, the low voltage sense
circuit 52 compares the ma~ter clock produced signal with
the duty cycle signal and activates its output 52c if the
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CM-78947 1 1 ~ 7~1
duty cycle increases to its maximum allowed level, i.e. 90%.
An activated output from voltage sense circuit 52 triggers a
shutdown timer 54 which produces a predetermined duration
time interval signal at its output 54a suitable for inhibit-
ing operation of the power supply via the shutdown input 24a
of the transformer primary driver 24. In this, the preferred
embodiment of the invention, the interval of shutdown timer
54 is approximately one second. As mentioned hereinabove,
during power turn-on the pulse width modulator operates the
transformer primary driver 24 at the 90~ duty cycle rate
until the output DC voltage B+ reaches its desired value.
To eliminate falsing of the shutdown circuit during the
turn-on condition, an initialize circuit 56, which is
powered by the logic supply produced voltage V+, produces a
signal at its output 56a suitable for inhibiting operation
of the shutdown timer 54 for a predetermined interval follow-
ing turn-on.
In addition, at the conclusion of the predetermined
inhibit interval, a restart timer 58 is activated. Restart
timer 58 produces a output signal at its output 58a which is
coupled back to an input 52c of the low voltage sense circuit
52. Upon receiving a restart timing signal at its input
52c, the low voltage sense circuit 52 is inhibited from
triggering the shutdown timer 54. Thus, by use of the
restart timer 58, the shutdown circuitry 50 is deactivated
for a predetermined time period following power supply
shutdown to allow the power supply produced DC output
voltage B+ to rise to its desired level by operating at a
90% duty cycle. In this, the preferred embodiment of the
invention, the restart timer 58 has a 100 millisecond restart
interval.
CM-78947 l~Z ~11
Fig. 2 is a detailed schematic diagram of the shutdown
circuit 50 illustrated in Fig. 1. Here, the low voltage
sense circuit 52 is comprised of a D flip flop 100. Applied
to the D input lOOa is the output of the pulse width modulator
44 (Fig. 1). Applied to the clock input lOOb of flip-flop
100 is the output from the master clock oscillator 20 (Fig.
1). The set input lOOc is connected to reference, or ground
potential and the Q output lOOd is left with no connection.
The output from the D flip-flop is taken at the Q output
lOOe.
The output from the D flip-flop 100 is applied to the
trigger input llOa of a timing circuit 110. In this, the
preferred embodiment of the invention, the timing circuit is
comprised of a standard 555 type timer integrated circuit,
commercially available from Motorola, Inc. Timing circuit
110 is connected in the monostable mode such that the time
duration of its output pulse is determined by the values of
a timing resistor 112 and timing capacitor 114. Resistor
112 and capacitor 114 are series connected between the logic
supply voltage +V and ground potential, with their common
node applied to the timing input llOb of timing circuit 110.
In response to receiving a negative transition pulse at its
trigger input llOa, timing circuit 110 drives its Q output
llOc high for the predetermined time interval. This level
is then coupled to the shutdown input of the power supply,
as is shown in Fig. 1.
Upon the conclusion of the shutdown timing signal, a
trigger pulse is coupled through a coupling capacitor 116 to
the toggle input 120a of the restart timing circuit 120. As
with the shutdown timer 110, the restart timer 120 is, in
this the preferred embodiment of the invention, comprised of
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CM-78947
a 555 timer integrated circuit. Upon receipt of a trigger
input, the restart timer 120 drives its Q output 120b high
for a predetermined time interval which is determined by the
values of timing resistor 122 and timing capacitor 124.
Resistor 122 and capacitor 124 connect between the logic
supply DC bias +V and ground potential, and their common
node connects to the timing input 120c of the restart timer
120. The Q output 120b of restart timer 120 is connected to
the reset input lOOf of D flip-flop 100. Thus, regardless
of the state of the input signals applied at its D and C
inputs lOOa, b, respectively, the D flip-flop 100 is pre-
vented from producing a trigger signal at its Q output lOOe .
for the duration of the restart timer interval. This, in
turn, prevents operation of the shutdown timing interval
until the power supply has had a time to rise to its desired
voltage.
To prevent activation of the shutdown timer 110 upon
turn-on of the power supply, the initialize circuit of Fig.
1 is realized by a timing circuit comprised of a series
capacitor 130 and resistor 132, connected between the logic
supply DC voltage +V and ground potential, and whose common
connection connects to the input of a standard inverter
stage 134. Thus, as is determined by the value of capacitor
130 and resistor 132, at power turn-on the output from
inverter 134 will be suitable for resetting the shutdown and
restart timers 110, 120 for a predetermined interval until
such time as the capacitor 130 is charged through resistor
132 to ground potential. Thus, the output from inverter 134
is coupled to the reset inputs llOd, 120d of the timers 110,
120, respectively.
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Precise operation of the shutdown apparatus is more
clearly understood with respect to the waveforms shown in
Fig. 3. Here, the first line labeled +V illustrates the
level of the logic supply voltage +V during turn-on at
portion 200; during proper operation at portion 202; and
during a voltage slump at portion 204.
Once the logic supply +V rises to a sufficient level
the power supply clock begins producing its fixed frequency
signal, as is shown in the second line of Fig. 3. For the
first few cycles of power supply operation, the pulse width
modulator 44 causes the transformer driver 24 to operate at
its maximum, i.e. 90~, duty cycle to thereby rapidly in-
crease the output voltage B+, as is shown in the last line
of Fig. 3.
Once the produced output voltage B+ rises to its desired
level, the feedback error amplifier activates the pulse
width modulator, and thus the transformer primary driver, to
a duty cycle of approximately 60~ as is shown at portion 206
of the pulse width modulator waveform.
To prevent the shutdown circuit from inhibiting power
supply operation during the initial turn-on period when a
90% duty cycle is required, the reset inputs 110d, 120d of
timers 110, 120 are kept low by the initialize signal, here
shown in the fourth line of Fig. 3, which deactivates the
timers until the instant at portion 208.
As long as the battery 10 output voltage remains above
a given level, the power supply will cQntinue to produce a
highly stabilized fixed output DC voltage B+ by suitably
varying the duty cycle of the transformer primary driver 24.
; 30 During normal operation, the D input 100a of flip-flop 100,
containing the pulse width modulator output signal, is set
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CM-78947
by the master clock signal at the beginning of each clock
cycle and is reset during a clock cycle. Thus, the Q output
lOOe of D flip-flop 100 assumes a constant high output level
during normal operation of the power supply.
Upon occurrence of a fault condition, such as an
instantaneous power drain on battery lO (Fig. l) causing it
to significantly reduce its output DC voltage, the power
supply may be unable to maintain its regulated output level
B+. Such a fault is indicated by portion 204 of the +V
waveform. During this period, the feedback error amplifier
42 activates the pulse width modulator 44 back to a 90% duty
cycle, as is illustrated by portion 210 of the pulse width
modulator waveform. Now, the D input lOOa of flip-flop 100
is not reset prior to conclusion of a clock interval and the
Q output lOOe produces an output trigger pulse, as is
illustrated at portion 212 of the fifth waveform of Fig. 3.
Upon the occurrence of the trigger pulse 212, the shutdown
timer llO is activated whereby it produces a one second
output pulse at its Q output llOc, as is shown at portion
214 of the sixth line in Fig. 3. This shuts down the power
supply for the one second interval.
Upon the negative transition of the shutdown timer
interval, the restart timer is triggered thereby producing
the predetermined restart interval, illustrated as portion
216 of the seventh waveform of Fig. 3. The restart signal
deactivates the shutdown circuit for the predetermined time
period thereby allowing the pulse width modulator to drive
the transformer primary driver 24 at the 90% duty cycle rate
in an attempt to bring the output voltage B+ to its desired
level. This is illustrated in the last line of Fig. 3. In
the instant example, the fault condition 204 continues
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during the restart interval whereby the output voltage B+
cannot rise to its desired level during the restart period.
Thus, upon conclusion of the restart period, indicated as
point 220 of the restart waveform, the D flip-flop lO0 again
triggers the shutdown timer 110 for its predetermined time
interval, as is illustrated at portion 222 of the shutdown
timer waveform. As before, upon conclusion of the shutdown
timer interval, the restart interval is again initiated and
the shutdown circuitry inactivated. At this point, the
fault has ceased and, during the restart time interval, the
power supply is able to return to its desired level B+.
Thus, at the conclusion of the restart interval the shutdown
circuitry is again activated and the system continues as
before.
In summary, an improved shutdown circuit, which finds
particular application in a switching mode supply for a
mobile data terminal, has been disclosed, which circuit is
totally digital in operation and does not require the use of
high stability, high cost components.
While a preferred embodiment of the invention has been
described in detail, it should be apparent that many modifi-
cations and variations thereto are possible, all of which
fall within the true spirit and scope of the invention.
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